PCB board and electrical appliance

Abstract

The application provides a PCB and an electric appliance. The PCB comprises a board body and a copper foil arranged in the board body, and a soldering via hole is arranged on the board body and electrically connected with the copper foil. The soldering via hole has a long axis and a short axis, and the long axis of the soldering via hole is parallel to the current direction in use. According to the technical scheme of the application, even if the tin resistivity in the via hole is larger than that of the copper foil, the thickness of the copper foil is very small and the resistance is large, and the volume of the tin conductor is relatively large and the resistance is small, so that the total loss is finally reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board, in particular to a PCB and an electric appliance. BACKGROUND

[0002] In the use of PCB, with the increase of load power and current, the resistance loss of the current-carrying conductor itself is also increasing. For the control system of medium power level, there are two choices for the electrical connection scheme: 1. When the current reaches a certain level, only external soft wire or hard conductor can be used; 2. When the current is relatively small, the copper foil on the PCB can be used for connection.

[0003] Using copper foil connection in PCB has the advantages of integration and miniaturization, but the thickness of copper foil is limited, the cross-sectional area is small, and the current-carrying capacity is limited. Generally, the via hole can be used on the PCB to connect the multiple layers of copper foil in parallel, and the copper foil is exposed and tinned on the PCB to increase the current-carrying capacity of the copper foil. Different via hole and exposed copper design schemes have a greater impact on the overall conductivity of the copper foil. The impact of conductivity mainly reflects the loss of unit area of copper foil. The overall resistivity is large, the conductivity is poor, and the loss is large.

[0004] For the scene of large current density, it is necessary to use via hole and exposed copper to improve the current-carrying capacity. The physical picture is as follows: considering the double-layer copper foil of the upper and lower layers, the via hole connects the upper and lower copper foils, but on the copper foil wiring path (only considering the straight path, not considering the bending), since there is no potential difference between the upper and lower copper foils, the current will not flow through the via hole axis, that is, the current will not shuttle between the upper and lower copper foils, as shown in Figure 1 The tin on the exposed copper is only used as a local current, and it will not pass through all the current in the line.

[0005] The scheme disclosed in the patent with the publication number CN202841682U is to use rectangular block exposed copper to tin, and the tin solidifies to form a small boss to enhance the current-carrying capacity and increase the cross-sectional area. In this patent, for the case where the current does not flow through the via hole axis, a large number of via holes are used in the large-area copper foil. The current will produce a high current density, that is, a high loss area before and after passing through each via hole, which weakens the effect of the via hole on enhancing the current-carrying capacity. Moreover, after the exposed copper is tinned, when high-frequency harmonic current flows through the copper foil, the current density in the tin line increases due to the skin effect. Since the impedance of tin is larger than that of copper, the loss will actually increase. SUMMARY

[0006] The embodiments of the present application provide a PCB and an electric appliance to solve the technical problem of large current loss in the use of the PCB in the prior art.

[0007] The embodiment of the present application provides a PCB, which comprises a board body and a copper foil arranged in the board body, and a soldering via hole is arranged on the board body and connected with the copper foil, the soldering via hole has a long axis and a short axis, and the long axis of the soldering via hole is parallel to the current direction in use of the copper foil.

[0008] In one embodiment, the soldering via hole is in an elliptical shape, a long hole or a waist-shaped hole.

[0009] In one embodiment, the soldering via hole is multiple, and the long axes of the multiple soldering via holes are located on the same straight line.

[0010] In one embodiment, the multiple soldering via holes are divided into multiple groups, each group comprises multiple soldering via holes, and the long axes of the soldering via holes in each group are located on the same straight line.

[0011] In one embodiment, the multiple soldering via holes are arranged in an array.

[0012] In one embodiment, the PCB further comprises exposed copper arranged on the surface of the board body.

[0013] In one embodiment, part of the edges of the soldering via hole are arranged to overlap with the exposed copper, or all the edges of the soldering via hole overlap with the exposed copper, or the soldering via hole is staggered with the exposed copper.

[0014] In one embodiment, the exposed copper is parallel or perpendicular to the current direction in use of the copper foil.

[0015] In one embodiment, the exposed copper is staggered with the soldering via hole, and the exposed copper is perpendicular to the current direction in use of the copper foil.

[0016] In one embodiment, a tin line is arranged on the exposed copper, and the width of the tin line is equal to the interval between two adjacent soldering via holes.

[0017] In one embodiment, a segmented part or a stamping part is arranged on the tin line.

[0018] The embodiment of the present application provides an electrical appliance comprising the above PCB.

[0019] In the above embodiments, the reason for making the long axis of the soldered via parallel to the current direction in use on the copper foil is that, on the one hand, it can make the volume or area of the conductor larger, and on the other hand, it adjusts the loss distribution in the copper foil. It can be determined from the different total losses of the long axis and the short axis of the soldered via that the adjustment of the loss distribution is the main reason for the decrease of the total loss. Specifically, when the long axis of the soldered via is along the current direction, the current can pass through the soldered via more and be diluted and shunted, and the filled solder is equivalent to a parallel conductor in the direction perpendicular to the current direction, i.e. the thickness direction of the copper foil or the PCB, thereby reducing the current density of the copper foil near the soldered via. In this case, even if the tin in the via has a larger resistivity than the copper foil, because the resistance of the copper foil is large due to the very thin thickness, and the resistance of the tin conductor is small due to the relatively large volume, the total loss is finally reduced. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which form a part of the present application, are used to provide further understanding of the present application, and the illustrative embodiments of the present application and their description serve the purpose of explaining the present application. The accompanying drawings should not be used to limit the present application without undue experimentation. In the drawings:

[0021] Figure 1 is a schematic diagram showing the current at the via of a PCB in the prior art

[0022] Figure 2 is a structural schematic diagram of embodiment 1 of a PCB according to the present application;

[0023] Figure 3 is a structural schematic diagram of embodiment 2 of a PCB according to the present application;

[0024] Figure 4 is a structural schematic diagram of embodiment 3 of a PCB according to the present application;

[0025] Figure 5 is a structural schematic diagram of embodiment 4 of a PCB according to the present application;

[0026] Figure 6 and Figure 7 is a schematic diagram of a PCB according to the present application with a tin wire laid on the exposed copper;

[0027] Figure 8 is a structural schematic diagram of embodiment 5 of a PCB according to the present application.

[0028] Among the above drawings, the following reference signs are included:

[0029] 10, board body; 11, soldered via; 12, exposed copper. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the embodiments and drawings. Herein, the illustrative embodiments of the present application and their descriptions are used to explain the present application but not as a limitation of the present application.

[0031] Figure 2 An embodiment 1 of the PCB board of the present application is shown, which comprises a board body 10 and a copper foil arranged in the board body 10, and a soldering via hole 11 is further formed on the board body 10 and connected with the copper foil, the soldering via hole 11 has a long axis and a short axis, and the long axis of the soldering via hole 11 is parallel to the current direction in use of the copper foil.

[0032] The reason why the long axis of the soldering via hole 11 is parallel to the current direction in use of the copper foil according to the technical solution of the present application is that, on one hand, it can make the volume or area of the conductor larger, and on the other hand, it adjusts the loss distribution in the copper foil. It can be determined from the different total losses of the long axis and the short axis of the soldering via hole 11 that the adjustment of the loss distribution is the main reason for the decrease of the total loss. Specifically, when the long axis of the soldering via hole 11 is along the current direction, the current can pass through the soldering via hole more and be diluted and shunted, the filled solder is equivalent to parallel conductors in the direction perpendicular to the current direction, i.e. the thickness direction of the copper foil or the PCB, thereby reducing the current density of the copper foil near the soldering via hole 11. In this case, even though the resistivity of the solder in the via hole is larger than that of the copper foil, because the thickness of the copper foil is very thin and the resistance is large, while the volume of the solder conductor is relatively large and the resistance is small, finally it still reflects the decrease of the total loss.

[0033] It should be noted that in the technical solution of the present application, the connection of the soldering via hole 11 with the copper foil can be electrical connection or thermal connection.

[0034] Preferably, in the technical solution of the embodiment 1, the soldering via hole 11 is elliptical. When the long axis of the elliptical soldering via hole 11 is along the current direction, the current can pass through the soldering elliptical via hole 11 more and be diluted and shunted, the filled solder is equivalent to parallel conductors in the direction perpendicular to the current direction, i.e. the thickness direction of the copper foil or the PCB, thereby reducing the current density of the copper foil near the elliptical soldering via hole 11. In this case, even though the resistivity of the solder in the elliptical soldering via hole 11 is larger than that of the copper foil, because the thickness of the copper foil is very thin and the resistance is large, while the volume of the solder conductor is relatively large and the resistance is small, finally it still reflects the decrease of the total loss. Similarly, the above principle is also applicable to the long hole or the waist hole, and all the soldering via holes 11 with long axis and short axis belong to the above technical solution to be protected.

[0035] The specific principle of the present application is that:

[0036] In the scenario of large current, the copper 12 flows through the direct current or low frequency alternating current, the electrons in the conductor collide with the atoms in the conductor, generating resistance and forming resistance heat, which is the loss of the conductor. In the copper 12 with a solder via 11, the current flows through the copper 12, and when it encounters the solder via 11, it may pass through or bypass, or flow through the hole wall of the solder via 11, so the current flow behavior is more complex. At this time, the conductivity of the copper 12 in the PCB can be evaluated by the overall electrical loss, and the larger the electrical loss, the poorer the conductivity, and vice versa. There is no uniform theory and formula to calculate the loss under these factors.

[0037] The following gives a numerical simulation-based loss calculation method of the current-carrying copper 12. When the shape of the solder via 11 and other factors change, they affect the distribution and flow path of the current in the conductor. For a constant steady current, when the charged system reaches electrostatic equilibrium, the potential distribution satisfies the steady-state source Poisson equation, and a region in three-dimensional space is taken as the research object, as shown in Figure 1 The following determines the boundary value and initial condition. Generally speaking, except in the bending or edge area, the current in the copper 12 has a certain flow direction, even if it is alternating current, the numerical value is reversed in the same line, not along the space flip direction, and we are considering the parallel current-carrying condition of the upper and lower two layers of copper 12, so the boundary condition can be specified: the current flows into the cross-sectional normal direction of the two copper 12, and the current flows out along the original coordinate axis direction after passing through the current-carrying copper 12 and the solder via 11, and the potential is defined as 0 on the cross section of the outflowing copper 12, thereby determining the inflow current and direction in the solution domain. In addition, an electrically insulating condition is applied at the interface between the FR4 substrate and the copper 12 and the solder via 11, and an electrically insulating condition is also applied to the outer surface of the solution domain in the other two directions parallel to the current inflow. Finally, the initial value of the potential in the solution domain is given as 0, thereby obtaining the definite problem of the electrostatic field Poisson equation as follows:

[0038]

[0039] Where σ is the electrical conductivity of the material, V is the potential function in the solution domain, Je is the externally applied volume current density, Q is the charge spatial distribution function of the charged system; J is the current density to be solved, Jn is the current density size of the boundary inflow, n is the normal vector of the boundary, Γ1 is the current injection boundary surface, Γ2 is the current outflow boundary surface, and Γ3 is the electrically insulating boundary surface; Ω is the entire solution domain.

[0040] After numerically solving the above three-dimensional space definite problem, the current density distribution in the solution domain is obtained, and the total loss of the region is obtained by volume integrating the current density:

[0041]

[0042] 2. Loss of circular and elliptical solder vias 11 when carrying current

[0043] Based on the above overall loss calculation method of the exposed copper 12, first, without considering the effect of the exposed copper tin wire, the input current is given as a direct current of 40 A, the circular solder via 11 and the elliptical solder via 11 are regularly placed in a square area of 16700 um x 16700 um, the center distance between the holes is 2000 um, the outer diameter of the circular hole is 0.7 mm, the hole wall thickness is set to 75 um, and the hole wall thickness is not considered, the size is uniform, the exposed copper 12 thickness is 75 um, the long axis of the elliptical hole is 0.8 mm, the short axis is 0.7 mm, the hole wall thickness, spacing and position are the same as the circular hole. Table 1 lists the total loss under four schemes, it can be seen that after adding the circular solder via 11, the total loss in the area decreases by 2.9%; when using the elliptical solder via 11, if the long axis is perpendicular to the current, the total loss is larger than that of the circular hole, if the long axis is parallel to the current, the total loss can be further reduced, therefore, the use of elliptical solder via 11 will have directionality, the long axis direction should be parallel to the current direction for alternating current, it is also on a line, the current in the exposed copper 12 bending area follows the curve, the solder via 11 can be rotated accordingly.

[0044] Table 1

[0045]

[0046] The reason why the elliptical solder via 11 with the long axis parallel to the current can reduce the total loss is that the volume or area of the conductor becomes larger, and on the other hand it adjusts the loss distribution in the exposed copper 12. From the different total losses of different elliptical axes, it can be determined that the adjustment of the loss distribution is the main reason for the reduction of the total loss. Specifically, when the long axis of the elliptical solder via 11 is along the current direction, the current can pass through the solder via 11 more and be diluted and shunted, the filled solder is equivalent to a parallel conductor in the direction perpendicular to the current direction, i.e. the thickness of the exposed copper 12 or the thickness of the PCB, thereby reducing the current density of the exposed copper 12 near the solder via 11. In this case, even if the resistivity of the tin in the solder via 11 is larger than that of the exposed copper 12, because the exposed copper 12 is very thin and the resistance is large, and the volume of the tin conductor is relatively large and the resistance is small, finally it still reflects the reduction of the total loss.

[0047] As Figure 2As shown, preferably, in the technical solution of Embodiment 1, there are multiple welding vias 11, and the major axes of the multiple welding vias 11 are located on the same straight line. This facilitates sequential connection for use. Optionally, the multiple welding vias 11 are divided into multiple groups, each group including multiple welding vias 11, and the major axes of the welding vias 11 in each group are located on the same straight line. This makes it easier to connect for use at multiple locations. As a preferred embodiment, in Embodiment 1, the multiple welding vias 11 are arranged in an array.

[0048] Optionally, in the technical solution of the present invention, the PCB board further includes exposed copper 12 disposed on the surface of the board body 10.

[0049] like Figure 2 As shown, in the technical solution of Embodiment 1, all edges of the welding via 11 overlap with the exposed copper 12, and the exposed copper 12 is perpendicular to the current direction when used on the copper foil.

[0050] like Figure 3 As shown, in the technical solution of embodiment 2, all edges of the welding via 11 overlap with the exposed copper 12, and the exposed copper 12 is parallel to the current direction when used on the copper foil.

[0051] like Figure 4 As shown, in the preferred embodiment, in the technical solution of Example 3, the welding via 11 is staggered from the exposed copper 12, and the exposed copper 12 is perpendicular to the current direction when used on the copper foil.

[0052] like Figure 5 As shown, in the technical solution of embodiment 4, the welding via 11 is staggered from the exposed copper 12, and the exposed copper 12 is parallel to the current direction when used on the copper foil.

[0053] like Figure 8 As shown, in the technical solution of embodiment 5, a portion of the edge of the welding via 11 overlaps with the exposed copper 12, and the exposed copper 12 is perpendicular to the current direction when used on the copper foil.

[0054] like Figure 6 and Figure 7 As shown, tin wires are provided on the exposed copper 12, and the width of the tin wires is equal to the spacing between two adjacent solder vias 11. This embodiment is the technical solution of Example 3 above. In this technical solution, the strip-shaped exposed copper 12 is laid vertically and staggered with respect to the solder vias 11, and the width of the tin wires is equal to the spacing between the solder vias 10. Through the combined action of the solder vias 10 and the exposed copper 12, the distribution of current-carrying cross-sectional area and loss density is further adjusted, and finally, the total loss of the copper foil itself is reduced by 6%.

[0055] More preferably, the tin wire is provided with a segment or an embossed part. With the tin wire provided with the segment or the embossed part, the continuity of the tin wire resistance can be inhibited, the loss can be reduced, and the total area of the tin wire laying can be substantially reduced. As shown in Fig. 7, the segment provided on the tin wire is shown in the circle; as shown in Fig. 8, the embossed part provided on the tin wire is shown in the circle and on the line. Figure 6 Figure 7

[0056] The losses of the copper 12 and the tin wire in different placement schemes of the elliptical solder via 11 are considered. Now, on the basis of the foregoing, the placement of the copper 12 is considered when the elliptical solder via 11 is placed with the long axis parallel to the current. Table 2 gives the calculation results of the losses in various different combinations, which are introduced as follows. The placement modes of the schemes 1-4 are shown in Fig. 9. Figures 2 to 5 As can be seen, only when the copper 12 overlaps the short axis and the copper 12 is perpendicular to the current, the loss is large, because in the current flow direction, the high loss density area is generated due to the impedance mutation before and after the solder via 11, as shown in Fig. 10. When the copper 12 overlaps the short axis, the loss density of the high loss area is further increased due to the same reason, thereby increasing the overall loss. The loss of the scheme in which the copper 12 is perpendicular to the current but the copper 12 is staggered with the solder via 11 is relatively small, because the copper 12 is placed in the high loss density area on both sides of the solder via 11 along the current direction, and the shunt effect of the tin wire reduces the overall loss. Figure 3

[0057] The total areas of the copper 12 in the foregoing four schemes are equal, and in the placement scheme in which the copper 12 is staggered with the solder via 11, the copper 12 can be opened in a larger area in the unit area of the copper 12, so schemes 3 and 4 should be selected in the four schemes. Scheme 5 is to further increase the area of the copper 12 when the copper 12 is perpendicular to the current and staggered with the hole, and it can be seen that the loss is further reduced.

[0058] ​​​As can be seen from Table 1 to Table 2, the total loss has a large decrease after the exposed copper 12 is coated with tin, and it can be determined that under certain conditions, the larger the area of the exposed copper 12, the smaller the total loss. For this reason, the calculation result of the case of full coverage of the exposed copper 12 is given in scheme 8 in Table 2, and the total loss indeed has a large decrease. However, this is not the optimal scheme, considering that the tin coating process is easy to cause local accumulation of tin paste when the exposed copper 12 is fully opened, causing local high temperature, and at the same time, it does not meet the basic requirements of the appearance process, and if the skin effect of the conductor is considered, when the high-frequency and large-amplitude harmonic current flows through the exposed copper 12, the current will be concentrated on the surface of the conductor, and the resistivity of tin is obviously larger than that of copper, so if a large area of tin is used for coverage, the loss will actually increase, so the full coverage scheme is not desirable. On the basis of scheme 5, the width of the exposed copper 12 can be further expanded to 1.2 mm, at which time the width of the tin line is basically equal to the spacing between the soldered vias 11, and the exposed copper 12 still has two directions, and the loss calculation results under the two conditions are given in schemes 6 and 7, and compared with scheme 5, the total loss further decreases, and the loss difference under the two conditions is not large, and since the exposed copper 12 is perpendicular to the current and reduces the loss density of the high-loss area on both sides of the soldered via 11 along the current direction, the loss is lower than that of scheme 7. At this time, the optimal scheme 6 reduces the loss by about 6% compared with the case of the circular soldered via 11 without the strip-shaped exposed copper 12 in Table 1, and the arrangement mode of the optimal scheme 6 is as shown in the accompanying drawings. Figure 8 .

[0059] Table 2

[0060]

[0061] The direction of the strip-shaped exposed copper 12 considering the skin effect.

[0062] The above-mentioned two edges refer to the distance between the exposed copper 12 to the edge of the soldered via 11 in Figure 4 or Figure 5 .

[0063] The above-mentioned hole edge refers to the distance between the exposed copper 12 to the edge of the soldered via 11 in Figure 2 or Figure 3 .

[0064] The skin effect is a phenomenon that when an alternating current flows through a conductor, the changing electromagnetic field affects the current density distribution inside the conductor, so that the current is concentrated on the surface of the conductor. In the foregoing discussion, the effects of scheme 6 and scheme 7 are close, but considering the skin effect, if the tin line is arranged parallel to the current direction, the loss caused by the skin effect will be larger because the flow path of the tin line is relatively smooth. Therefore, arranging the exposed copper 12 perpendicular to the current direction is the optimal comprehensive scheme.

[0065] If the processing or actual production is considered simple, the direction parallel to the current can also be adopted, and the tin wire is processed in segments or is processed by stamping in the middle of the continuous long strip of exposed copper 12, the continuity of the tin wire resistance is inhibited, and the purpose of reducing the loss can also be achieved, and the total area of the tin wire laying is not reduced.

[0066] The embodiment of the present application provides an electric appliance comprising the PCB described above. The electric appliance can be a household appliance, such as an air conditioner, a refrigerator, an electric rice cooker, etc. The electric appliance can also be a commercial electric appliance, such as a central air conditioner, etc.

[0067] In the patent with the patent publication number CN106714449A, a scheme similar to the present application but with a completely different principle is disclosed: the vias are arranged in a certain interval, or are arranged with a shrinking interval from the edge, or are staggered between the two rows of vias, which can realize reliable electrical connection and have a certain current-carrying capacity. In this scheme, the vias carry all the current in the circuit, and the current is switched between the upper and lower copper foils. When the direction in which the vias arranged in sequence and adjacent to each other is arranged is perpendicular to the current flow direction, these vias are collectively referred to as a row of vias. In the same group of multiple rows of vias, the arrangement direction of each row of vias is perpendicular to the corresponding current flow direction. Although the shape of the hole is limited to a circle, a triangle, an ellipse or a combination thereof, because only the arrangement direction of multiple vias is specified, the placement of a single via is not specified, such as: "the position of each row of vias is fitted to form a curve by linear fitting, the conductor layer has a current, and the tangent direction of the fitted curve is perpendicular to the current flow direction". In fact, single elliptical and triangular holes can have completely different placement methods. Since the current is switched between the upper and lower copper foils in this scenario, all the current flows through a small number of vias, so the shape and placement of a single via have little effect on the current-carrying capacity of the vias.

[0068] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A PCB board, comprising a board body (10) and copper foil disposed within the board body (10), wherein the board body (10) is further provided with soldering vias (11), the soldering vias (11) being connected to the copper foil, characterized in that, The welding via (11) has a major axis and a minor axis, and the major axis of the welding via (11) is parallel to the direction of the current when used on the copper foil; The PCB board also includes exposed copper (12) disposed on the surface of the board body (10), wherein a portion of the edge of the soldering via (11) overlaps with the exposed copper (12), or all the edges of the soldering via (11) overlap with the exposed copper (12), or the soldering via (11) is offset from the exposed copper (12).

2. The PCB board according to claim 1, characterized in that, The welding through hole (11) is elliptical, elongated, or oblong.

3. The PCB board according to claim 1, characterized in that, There are multiple welding vias (11), and the major axes of the multiple welding vias (11) are located on the same straight line.

4. The PCB board according to claim 3, characterized in that, The multiple welding vias (11) are divided into multiple groups, each group including multiple welding vias (11), and the major axes of the welding vias (11) in each group are located on the same straight line.

5. The PCB board according to claim 4, characterized in that, The multiple welding vias (11) are arranged in an array.

6. The PCB board according to claim 1, characterized in that, The exposed copper (12) is parallel or perpendicular to the direction of the current used on the copper foil.

7. The PCB board according to claim 6, characterized in that, The exposed copper (12) is offset from the welding via (11), and the exposed copper (12) is perpendicular to the direction of the current used on the copper foil.

8. The PCB board according to claim 7, characterized in that, A tin wire is provided on the exposed copper (12), and the width of the tin wire is equal to the distance between two adjacent welding vias (11).

9. The PCB board according to claim 8, characterized in that, The tin wire is provided with segmented sections or imprinted sections.

10. An electrical appliance, comprising a PCB board, characterized in that, The PCB board is the PCB board according to any one of claims 1 to 9.

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