Array substrate and display device

Abstract

An array substrate is provided. A first virtual line and a second virtual line pass through a first voltage supply line, a second voltage supply line, and a third voltage supply line, respectively. The first voltage supply line, the second voltage supply line, and the third voltage supply line respectively include a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion, respectively, between the first virtual line and the second virtual line. The orthographic projection of the third anode of the third light-emitting element on the base substrate completely covers the orthographic projection of the third voltage supply line portion on the base substrate. The third voltage supply line portion has a line width, which is greater than the line width of the first voltage supply line portion and greater than the line width of the second voltage supply line portion.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line of each row and a drain terminal connected to a data line of each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. The relevant parameters of the OLED display panel include energy consumption, brightness, color coordinates and color shift. Summary of the invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising: a first data line, a second data line, and a third data line, wherein the first data line, the second data line, and the third data line are configured to provide data signals to a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit, respectively; a first voltage supply line, a second voltage supply line, and a third voltage supply line, wherein the first voltage supply line, the second voltage supply line, and the third voltage supply line are configured to provide constant voltage signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; and a first light-emitting element, a second light-emitting element, and a third light-emitting element, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively. The second pixel driving circuit and the third pixel driving circuit; wherein the first virtual line and the second virtual line pass through the first voltage supply line, the second voltage supply line and the third voltage supply line respectively; the first voltage supply line, the second voltage supply line and the third voltage supply line respectively include a first voltage supply line portion, a second voltage supply line portion and a third voltage supply line portion respectively between the first virtual line and the second virtual line; the orthographic projection of the third anode of the third light-emitting element on the base substrate completely covers the orthographic projection of the third voltage supply line portion on the base substrate; and the third voltage supply line portion has a third line width, which is greater than the first line width of the first voltage supply line portion and greater than the second line width of the second voltage supply line portion.

[0004] Optionally, the first virtual line and the second virtual line also pass through the first data line, the second data line, and the third data line, respectively; the first data line, the second data line, and the third data line respectively include a first data line portion, a second data line portion, and a third data line portion, and the first data line portion, the second data line portion, and the third data line portion are respectively located between the first virtual line and the second virtual line; and the first data line portion, the second data line portion, and the third data line portion have substantially the same line width.

[0005] Optionally, an orthographic projection of the third anode on the base substrate at least partially overlaps with an orthographic projection of the third data line portion on the base substrate.

[0006] Optionally, the first data line, the second data line, the third data line, the first voltage supply line, the second voltage supply line and the third voltage supply line are substantially parallel to each other; and the data lines and the voltage supply lines are arranged alternately in the following order, wherein the first voltage supply line, the first data line, the second voltage supply line, the second data line, the third voltage supply line and the third data line are arranged in sequence.

[0007] Optionally, the third voltage supply line portion includes a main sub-portion and a widening sub-portion; the main sub-portion is located between the widening sub-portion and the third data line; and the main sub-portion, the first voltage supply line portion and the second voltage supply line portion have the same shape.

[0008] Optionally, the main sub-portion, the first voltage supply line portion and the second voltage supply line portion have the same shape and the same width.

[0009] Optionally, a first anode of the first light emitting element is located between the first voltage supply line and the second data line; and a second anode of the second light emitting element is between the first voltage supply line and the second data line.

[0010] Optionally, the orthographic projection of the first anode on the base substrate at least partially overlaps with the orthographic projection of the first data line on the base substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line on the base substrate; and the orthographic projection of the second anode on the base substrate at least partially overlaps with the orthographic projection of the first data line on the base substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line on the base substrate.

[0011] Optionally, the orthographic projection of the first anode on the base substrate also at least partially overlaps with the orthographic projection of the first voltage supply line on the base substrate; and the orthographic projection of the second anode on the base substrate at least partially overlaps with the orthographic projection of the first voltage supply line on the base substrate.

[0012] Optionally, the array substrate further includes: a first anode contact pad, a second anode contact pad, and a third anode contact pad; a planarization layer, which is located on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate; a first anode contact hole, a second anode contact hole, and a third anode contact hole, and the first anode contact hole, the second anode contact hole, and the third anode contact hole extend through the planarization layer respectively; a pixel defining layer, which is located on a side of the first anode, the second anode, and the third anode away from the planarization layer; a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, and the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening are respectively The first anode, the second anode and the third anode are respectively connected to the first anode contact pad, the second anode contact pad and the third anode contact pad through the first anode contact hole, the second anode contact hole and the third anode contact hole; and the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are respectively connected to the first anode, the second anode and the third anode through the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening.

[0013] Optionally, the first anode contact hole is outside the region having the first sub-pixel opening; the second anode contact hole is outside the region having the second sub-pixel opening; and the third anode contact hole is outside the region having the third sub-pixel opening.

[0014] Optionally, the array substrate also includes at least one insulating layer between the base substrate and the first anode contact pad, the second anode contact pad and the third anode contact pad; a first pad contact through hole, a second pad contact through hole and a third pad contact through hole, the first pad contact through hole, the second pad contact through hole and the third pad contact through hole respectively extending through the at least one insulating layer; and the first anode contact pad, the second anode contact pad and the third anode contact pad are respectively connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit through the first pad contact through hole, the second pad contact through hole and the third pad contact through hole.

[0015] Optionally, along the direction of the first virtual line or the second virtual line, the first anode contact hole is located between the first pad contact hole and the first voltage supply line; along the direction of the first virtual line or the second virtual line, the second anode contact hole is located between the second pad contact hole and the second voltage supply line; and the third pad contact hole and the third anode contact hole are arranged along a direction substantially parallel to the third data line and the third voltage supply line.

[0016] Optionally, the first anode includes a first main body portion and a first bridge portion; the second anode includes a second main body portion and a second bridge portion; the third anode includes a third main body portion and a third bridge portion; the first main body portion, the second main body portion and the third main body portion have a substantially rectangular shape; and the first bridge portion, the second bridge portion and the third bridge portion protrude outward from the first main body portion, the second main body portion and the third main body portion, respectively.

[0017] Optionally, the array substrate also includes: a first anode contact pad, a second anode contact pad and a third anode contact pad; a planarization layer, which is located on a side of the first anode contact pad, the second anode contact pad and the third anode contact pad away from the base substrate; a first anode contact hole, a second anode contact hole and a third anode contact hole, and the first anode contact hole, the second anode contact hole and the third anode contact hole extend through the planarization layer respectively; wherein the first bridge portion, the second bridge portion and the third bridge portion are respectively connected to the first anode contact pad, the second anode contact pad and the third anode contact pad through the first anode contact hole, the second anode contact hole and the third anode contact hole, respectively.

[0018] Optionally, the third bridge portion protrudes outward from the third main body portion along a direction substantially parallel to the first virtual line or the second virtual line; the second bridge portion protrudes outward from the second main body portion along a direction substantially parallel to the second data line or the second voltage supply line; and the first bridge portion protrudes outward from the first main body portion along a direction at an inclined angle to the first virtual line and the first data line.

[0019] Optionally, the first data line, the second data line and the third data line are also configured to provide the data signal to the fourth pixel driving circuit, the fifth pixel driving circuit and the sixth pixel driving circuit respectively; the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit are arranged sequentially along a direction substantially parallel to the first virtual line or the second virtual line; the fourth pixel driving circuit, the fifth pixel driving circuit and the sixth pixel driving circuit are arranged sequentially along the direction substantially parallel to the first virtual line or the second virtual line; the first pixel driving circuit and the fourth pixel driving circuit are arranged along a direction substantially parallel to the first data line or the first voltage supply line; the second pixel driving circuit and the fifth pixel driving circuit are arranged along a direction substantially parallel to the second data line or the second voltage supply line; and the third pixel driving circuit and the sixth pixel driving circuit are arranged along a direction substantially parallel to the third data line or the third voltage supply line.

[0020] Optionally, the first light-emitting element is driven by the first pixel driving circuit and is at least partially located in an area having the fifth pixel driving circuit; the second light-emitting element is driven by the second pixel driving circuit, is partially located in an area having the first pixel driving circuit, and is partially located in an area having the second pixel driving circuit; and the third light-emitting element is driven by the third pixel driving circuit, is partially in an area having the third pixel driving circuit, and is partially in an area having the sixth pixel driving circuit.

[0021] Optionally, the third line width is in the range of 8.0 μm to 10.0 μm, the first line width is in the range of 5.0 μm to 6.0 μm, and the second line width is in the range of 5.0 μm to 6.0 μm.

[0022] In another aspect, the present disclosure provides a display device, including an array substrate described herein or manufactured by the method described herein and an integrated circuit connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 3is a diagram showing the structure of multiple sub-pixels of an array substrate in some embodiments of the present disclosure.

[0027] Figure 4 is a diagram showing the structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 5 is a diagram showing the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 6 is a diagram showing the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 7 is a diagram showing the structure of a signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0031] Figure 8 is along Figure 3 Cross-sectional view along line A-A'.

[0032] Fig.9A is a diagram showing the structure of a planarization layer of an array substrate and an anode of a light emitting element according to some embodiments of the present disclosure.

[0033] Fig. 9B is along Fig.9A Cross-sectional view along line BB'.

[0034] Fig. 10A is a diagram showing the structure of a pixel defining layer of an array substrate and an anode of a light emitting element according to some embodiments of the present disclosure.

[0035] Fig. 10B is along Fig. 10A Cross-sectional view along line C-C'.

[0036] Fig.11 is a diagram showing the structure of a pixel defining layer, an anode of a light emitting element, and a light emitting layer of an array substrate according to some embodiments of the present disclosure.

[0037] Fig.12 is a diagram showing the structure of a cathode layer, an anode layer, and a light-emitting layer of a light-emitting element of an array substrate in some embodiments of the present disclosure.

[0038] Fig.13A is a diagram showing the structure of a signal line layer of an array substrate and an anode of a light emitting element according to some embodiments of the present disclosure.

[0039] Fig. 13B yes Fig.13AAn enlarged view of the area between the first virtual line and the second virtual line in FIG.

[0040] Fig. 13C is along Fig. 13B Cross-sectional view along line D-D'.

[0041] Fig.14 The structure of a voltage supply line portion in an array substrate according to some embodiments of the present disclosure is shown.

[0042] Fig.15 is a diagram showing the structure of a first pixel driving circuit of an array substrate in some embodiments of the present disclosure.

[0043] Fig.16 is along Fig.15 Cross-sectional view along line E-E'.

[0044] Fig.17 is along Fig.15 Cross-sectional view along line F-F'.

[0045] Fig.18 is a diagram showing the connection of anodes and anode contact pads in an array substrate according to some embodiments of the present disclosure.

[0046] Fig.19 is a diagram showing the structure of an anode of a light emitting element of an array substrate according to some embodiments of the present disclosure.

[0047] Fig. 20 The arrangement of light emitting elements in an array substrate according to some embodiments of the present disclosure is shown.

[0048] Fig.21 is a cross-sectional image of the array substrate.

[0049] Fig. 22 is a schematic diagram showing a cross-sectional image of an array substrate.

[0050] Fig.23 is a schematic diagram showing a cross-sectional image of an array substrate.

[0051] Fig.24 is a cross-sectional image of the array substrate.

[0052] Fig.25 is a diagram showing the structure of multiple sub-pixels of an array substrate in some embodiments of the present disclosure.

[0053] Fig.26 is a diagram showing the structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0054] Fig. 27is a diagram showing the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0055] Fig.28 is a diagram showing the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0056] Fig.29 is a diagram showing the structure of a signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0057] Fig.30 is along Fig.25 Cross-sectional view along line G-G'.

[0058] Fig.31 is a diagram showing a structure of a region in which a signal line crosses a second capacitor electrode in an array substrate according to some embodiments of the present disclosure.

[0059] Fig.32 is a further enlarged view of a region in which a signal line crosses a second capacitor electrode in an array substrate in some embodiments of the present disclosure.

[0060] Fig.33 is a diagram showing a structure of a region in which a portion of a semiconductor layer intersects a second capacitor electrode in an array substrate in some embodiments according to the present disclosure.

[0061] Fig.34 The structures of the first part and the second part of the second capacitor electrode in the array substrate in some embodiments of the present disclosure are shown.

[0062] Fig.35 is a diagram showing the structure of a sub-pixel of an array substrate in some embodiments of the present disclosure.

[0063] Fig.36 is along Fig.35 Cross-sectional view along line H-H'.

[0064] Fig.37 is along Fig.35 Cross-sectional view along line I-I'. DETAILED DESCRIPTION

[0065] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0066] The present disclosure particularly provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a first data line, a second data line, and a third data line, which are configured to provide data signals to a first pixel drive circuit, a second pixel drive circuit, and a third pixel drive circuit, respectively; a first voltage supply line, a second voltage supply line, and a third voltage supply line, which are configured to provide a high voltage signal to the first pixel drive circuit, the second pixel drive circuit, and the third pixel drive circuit, respectively; and a first light-emitting element, a second light-emitting element, and a third light-emitting element, which are connected to the first pixel drive circuit, the second pixel drive circuit, and the third pixel drive circuit, respectively. Optionally, the first virtual line and the second virtual line pass through the first voltage supply line, the second voltage supply line, and the third voltage supply line, respectively. Optionally, the first voltage supply line, the second voltage supply line, and the third voltage supply line respectively include a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion respectively between the first virtual line and the second virtual line. Optionally, the orthographic projection of the third anode of the third light-emitting element on the base substrate completely covers the orthographic projection of the third voltage supply line portion on the base substrate. Optionally, the third voltage supply line portion has a third line width, which is greater than the first line width of the first voltage supply line portion and greater than the second line width of the second voltage supply line portion.

[0067] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes a gate line GL, a data line DL, a voltage supply line (e.g., a high voltage supply line Vdd) and a second voltage supply line (e.g., a low voltage supply line Vss), each of which is electrically connected to the pixel driving circuit PDC. The light emission of each sub-pixel in the sub-pixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal in the range of 3V to 5V) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through the high voltage supply line Vdd; a low voltage signal (e.g., a VSS signal in the range of 0V to -5V) is input to the cathode of the light-emitting element through the low voltage supply line Vss. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0068] Various suitable pixel driving circuits can be used in the present array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 5T1C driving circuit. Various suitable light-emitting elements can be used in the present array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0069] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2 In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a reset control signal line rst of a current stage, a source connected to a reset signal line Vint of a current stage of a plurality of reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding one of a plurality of gate lines GL, a source connected to a corresponding one of a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the drain of the driving transistor Td; A fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a source connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 having a gate connected to a corresponding light emitting control signal line, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a reset control signal line rst(N+1) of the next stage, a source connected to a reset signal line Vint(N+1) of the next stage, and a drain connected to the drain of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0070] Figure 3 is a diagram showing the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 3In some embodiments, the array substrate includes a first data line DL1, a second data line DL2, and a third data line DL3, which are configured to provide data signals to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3, respectively; and a first voltage supply line Vdd1, a second voltage supply line Vdd2, and a third voltage supply line Vdd3, which are configured to provide a high voltage signal (constant voltage signal) to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3, respectively. In one example, the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 are configured to drive the image display in the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively. In one example, the first sub-pixel, the second sub-pixel, and the third sub-pixel are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0071] Figure 4 is a diagram showing the structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 5 is a diagram showing the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 6 is a diagram showing the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 7 is a diagram showing the structure of a signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 8 is along Figure 3 A cross-sectional view of the line A-A' in FIG. Figures 3 to 8 In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on a side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on a side of the second conductive layer away from the insulating layer IN, a signal line layer located on a side of the interlayer dielectric layer ILD away from the second conductive layer, and a planarization layer PLN located on a side of the signal line layer away from the interlayer dielectric layer ILD.

[0072] Reference Figure 3 Each of the first pixel driving circuit pdc1, the second pixel driving circuit pdc2 and the third pixel driving circuit pdc3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td.

[0073] Reference Figure 2 , Figure 3 and Figure 5 In some embodiments, the first conductive layer includes a gate line GL, a reset control signal line rst, a light emitting control signal line em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the gate line GL, the reset control signal line rst, the light emitting control signal line em and the first capacitor electrode Ce1 are located in the same layer.

[0074] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the gate line GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the gate line GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the step of forming the gate line GL and the step of forming the first capacitor electrode Ce1 at the same time, the gate line GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0075] Reference Figure 2 , Figure 3 and Figure 6 In some embodiments, the second conductive layer includes a reset signal line Vint and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the reset signal line Vint and the second capacitor electrode Ce2 are located in the same layer.

[0076] refer to Figure 2 , Figure 3 and Figure 7In some embodiments, the signal line layer includes a first voltage supply line Vdd1, a second voltage supply line Vdd2, a third voltage supply line Vdd3, a first data line DL1, a second data line DL2 and a third data line DL3, a first anode contact pad ACP1, a second anode contact pad ACP2, a third anode contact pad ACP3, a first connection line Cl1 and a second connection line Cl2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first voltage supply line Vdd1, the second voltage supply line Vdd2, the third voltage supply line Vdd3, the first data line DL1, the second data line DL2, the third data line DL3, the first anode contact pad ACP1, the second anode contact pad ACP2, the third anode contact pad ACP3, the first connection line Cl1 and the second connection line Cl2 are in the same layer. Figure 7 As shown, the data lines (eg, the first data line DL1 , the second data line DL2 , and the third data line DL3 ) are substantially straight lines.

[0077] refer to Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 8 In some embodiments, the storage capacitor Cst includes a first capacitor electrode Ce1, a second capacitor electrode Ce2, and an insulating layer IN between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. Figure 2 As shown, the second capacitor electrode Ce2 is electrically connected to the corresponding voltage supply line. For example, the second capacitor electrode Ce2 and the corresponding voltage supply line are configured to be always provided with the same voltage.

[0078] Reference Figure 2 , Figure 3 and Figure 4 In some embodiments, in each pixel driving circuit, the semiconductor material layer has an integral structure. Figure 4 In the figure, the pixel driving circuit on the left (first pixel driving circuit pdc1) is marked with a mark, which indicates the area corresponding to the multiple transistors in the pixel driving circuit (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td). Figure 4, the pixel driving circuit on the left (the third pixel driving circuit pdc3) is marked with a mark, which represents the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, S6, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of an integral structure in each sub-pixel. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0079] Reference Figure 2 , Figure 3 and Figure 8 In some embodiments, the signal line layer includes a first connection line Cl1 located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The first connection line Cl1 is in the same layer as the voltage supply line (e.g., the second voltage supply line Vdd2) and the data line (e.g., the second data line DL2). Optionally, the array substrate further includes a first through hole v1 located in the hole area H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first through hole v1.

[0080] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate further includes a first through hole v1 and a second through hole v2. The first through hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second through hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first through hole v1, and is connected to the semiconductor material layer SML through the second through hole v2.

[0081] Fig.9A is a diagram showing the structure of a planarization layer of an array substrate and an anode of a light emitting element according to some embodiments of the present disclosure. Fig. 9B is along Fig.9A Cross-sectional view of line BB' in FIG. Figure 2 , Figure 3 , Figure 7 , Fig.9A and Fig. 9B In some embodiments, the signal line layer includes a first anode contact pad ACP1, a second anode contact pad ACP2, and a third anode contact pad ACP3, respectively located on the interlayer dielectric layer ILD. The array substrate includes a planarization layer PLN, which is located on a side of the signal line layer away from the interlayer dielectric layer ILD; a first anode contact hole AH1, a second anode contact hole AH2, and a third anode contact hole AH3, respectively extending through the planarization layer PLN; and a first anode AD1, a second anode AD2, and a third anode AD3, respectively connected to the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 through the first anode contact hole AH1, the second anode contact hole AH2, and the third anode contact hole AH3. The first anode AD1, the second anode AD2, and the third anode AD3 are anodes of a first light emitting element, a second light emitting element, and a third light emitting element, respectively connected to a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit.

[0082] Fig. 10A is a diagram showing the structure of a pixel defining layer of an array substrate and an anode of a light emitting element according to some embodiments of the present disclosure. Fig. 10B is along Fig. 10A Cross-sectional view of line C-C' in FIG. Figure 2 , Figure 3 , Fig. 10A and Fig. 10B In some embodiments, the array substrate further includes a pixel defining layer PDL located on a side of the first anode AD1, the second anode AD2, and the third anode AD3 away from the planarization layer PLN. The array substrate further includes a first sub-pixel opening SA1, a second sub-pixel opening SA2, and a third sub-pixel opening SA3 extending through the pixel defining layer PDL, respectively.

[0083] Fig.11 1 is a diagram showing the structure of a pixel defining layer, an anode of a light emitting element, and a light emitting layer of an array substrate according to some embodiments of the present disclosure. Figure 2 , Figure 3 and Fig.11In some embodiments, the array substrate further includes a first light emitting layer EL1, a second light emitting layer EL2, and a third light emitting layer EL3 respectively located in the first sub-pixel opening SA1, the second sub-pixel opening SA2, and the third sub-pixel opening SA3. The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 are respectively connected to the first anode AD1, the second anode AD2, and the third anode AD3 through the first sub-pixel opening SA1, the second sub-pixel opening SA2, and the third sub-pixel opening SA3. The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 are respectively light emitting layers of the first light emitting element, the second light emitting element, and the third light emitting element are respectively connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit.

[0084] Fig.12 is a diagram showing the structure of a cathode layer, an anode layer, and a light-emitting layer of a light-emitting element of an array substrate in some embodiments of the present disclosure. Figure 2 , Figure 3 and Fig.12 In some embodiments, the array substrate further includes a cathode layer CD, which is located on a side of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 away from the first anode AD1, the second anode AD2, and the third anode AD3. Optionally, the cathode layer CD is an integral layer for all light-emitting elements in the array substrate.

[0085] Fig.13A is a diagram showing the structure of a signal line layer and an anode of a light emitting element of an array substrate according to some embodiments of the present disclosure. Fig.13A In some embodiments, the first virtual line Vl1 and the second virtual line Vl2 pass through the first voltage supply line Vdd1, the second voltage supply line Vdd2, and the third voltage supply line Vdd3, and the first data line DL1, the second data line DL2, and the third data line DL3, respectively. Fig. 13B yes Fig.13A An enlarged view of the area between the first imaginary line and the second imaginary line in FIG. Fig.13A and Fig. 13B In some embodiments, the first voltage supply line Vdd1, the second voltage supply line Vdd2 and the third voltage supply line Vdd3 respectively include a first voltage supply line portion vp1, a second voltage supply line portion vp2 and a third voltage supply line portion vp3, which are respectively located between the first virtual line Vl1 and the second virtual line Vl2.

[0086] Fig. 13C is along Fig. 13B Cross-sectional view of line D-D' in FIG. Fig.13A , Fig. 13B and Fig. 13C In some embodiments, the orthographic projection of the third anode AD3 of the third light emitting element on the base substrate (e.g., the interlayer dielectric layer ILD) completely covers the orthographic projection of the third voltage supply line portion vp3 on the base substrate. The third voltage supply line portion vp3 has a third line width w3 that is greater than the first line width w1 of the first voltage supply line portion vp1 and greater than the second line width w2 of the second voltage supply line portion vp2.

[0087] Optionally, w1 is in the range of 3 μm to 9 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm or 8 μm to 9 μm. Optionally, w1 is about 5.6 μm. Optionally, w2 is in the range of 3 μm to 9 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm or 8 μm to 9 μm. Optionally, w2 is about 5.6 μm. Optionally, w3 is in the range of 6 μm to 12 μm, for example, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, or 11 μm to 12 μm. Optionally, w3 is about 9 microns.

[0088] refer to Fig.13A , Fig. 13B and Fig. 13C In some embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 include a first data line portion dp1, a second data line portion dp2, and a third data line portion dp3, respectively, between the first virtual line Vl1 and the second virtual line Vl2. Optionally, the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3 have substantially the same line width w4. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not more than 8%, not more than 6%, not more than 4%, not more than 2%, not more than 1%, not more than 0.5%, not more than 0.1%, not more than 0.05%, and not more than 0.01% of the base value.

[0089] Optionally, w4 is in the range of 1 μm to 5 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm or 4 μm to 5 μm. Optionally, w4 is about 3 μm.

[0090] Optionally, the third line width w3 refers to the maximum line width of the third voltage supply line portion vp3, the first line width w1 refers to the maximum line width of the first voltage supply line portion vp1, the second line width w2 refers to the maximum line width of the second voltage supply line portion vp2, and the line width w4 refers to the maximum line width of the first data line portion dp1, the second data line portion dp2 and the third data line portion dp3 respectively.

[0091] Optionally, the third line width w3 refers to the average line width of the third voltage supply line portion vp3, the first line width w1 refers to the average line width of the first voltage supply line portion vp1, the second line width w2 refers to the average line width of the second voltage supply line portion vp2, and the line width w4 refers to the average line width of the first data line portion dp1, the second data line portion dp2 and the third data line portion dp3 respectively.

[0092] Optionally, the third line width w3 refers to the minimum line width of the third voltage supply line portion vp3, the first line width w1 refers to the minimum line width of the first voltage supply line portion vp1, the second line width w2 refers to the minimum line width of the second voltage supply line portion vp2, and the line width w4 refers to the minimum line width of the first data line portion dp1, the second data line portion dp2 and the third data line portion dp3 respectively.

[0093] Optionally, when line widths w1, w2 and w3 are measured along a line parallel to the first virtual line Vl1 and the second virtual line Vl2 and passing through the first voltage supply line portion vp1, the second voltage supply line portion vp2 and the third voltage supply line portion vp3, the third voltage supply line portion vp3 has a third line width w3 that is greater than the first line width w1 of the first voltage supply line portion vp1 and greater than the second line width w2 of the second voltage supply line portion vp2.

[0094] Reference Fig.13A , Fig. 13B and Fig. 13C In some embodiments, the orthographic projection of the third anode AD3 on the base substrate (e.g., the interlayer dielectric layer ILD) at least partially overlaps with the orthographic projection of the third data line portion dp3 on the base substrate. Optionally, the orthographic projection of the third anode AD3 on the base substrate (e.g., the interlayer dielectric layer ILD) completely covers the orthographic projection of the third data line portion dp3 on the base substrate.

[0095] refer to Fig.13A In some embodiments, the first data line DL1, the second data line DL2, the third data line DL3, the first voltage supply line Vdd1, the second voltage supply line Vdd2 and the third voltage supply line Vdd3 are substantially parallel to each other (see also Figure 1 , Figure 3 and Figure 7). Optionally, the data lines (e.g., the first data line DL1, the second data line DL2, and the third data line DL3) and the voltage supply lines (e.g., the first voltage supply line Vdd1, the second voltage supply line Vdd2, and the third voltage supply line Vdd3) are alternately arranged. Optionally, the first data line portion dp1, the second data line portion dp2, the third data line portion dp3, the first voltage supply line portion vp1, the second voltage supply line portion vp2, and the third voltage supply line portion vp3 are substantially parallel to each other. Optionally, the data line portions (e.g., the first data line portion dp1, the second data line portion dp2, and the third data line portion dp3) and the voltage supply line portions (e.g., the first voltage supply line portion vp1, the second voltage supply line portion vp2, and the third voltage supply line portion vp3) are alternately arranged. As used herein, the term “substantially parallel” means that the angle between two signal lines is in the range of 0 to about 25 degrees, such as 0 to about 5 degrees, 0 to about 10 degrees, 0 to about 15 degrees, or 0 to about 20 degrees.

[0096] Fig.14 The structure of the voltage supply line part in the array substrate in some embodiments of the present disclosure is shown. Fig.14 In some embodiments, the third voltage supply line portion vp3 includes a main sub-portion msp and a widening sub-portion wsp. The main sub-portion msp is located between the widening sub-portion wsp and the third data line portion dp3, so the main sub-portion msp is located between the widening sub-portion wsp and the third data line. Fig.14 As shown, in one example, the main sub-portion msp, the first voltage supply line portion vp1, and the second voltage supply line portion vp2 have the same shape and substantially the same size. The difference between the third voltage supply line portion vp3 and the first voltage supply line portion vp1 or the second voltage supply line portion vp2 is the widening sub-portion wsp, which makes the line width of the third voltage supply line portion vp3 greater than the line width of the first voltage supply line portion vp1 and the second voltage supply line portion vp2. The main sub-portion msp, the first voltage supply line portion vp1, and the second voltage supply line portion vp2 have the same line width. Reference Fig.14 , the main sub-portion msp has a line width w3m equal to w1 or w2.

[0097] Optionally, when the line width is measured along a line parallel to the first virtual line Vl1 and the second virtual line Vl2 and passing through the first voltage supply line portion vp1, the second voltage supply line portion vp2 and the main subportion msp, the main subportion msp, the first voltage supply line portion vp1, and the second voltage supply line portion vp2 have the same line width.

[0098] refer to Fig.13AIn some embodiments, the first anode AD1 of the first light emitting element is between the first voltage supply line Vdd1 and the second data line DL2; and the second anode AD2 of the second light emitting element is between the first voltage supply line Vdd1 and the second data line DL2. Fig. 13C , the orthographic projection of the first anode AD1 on the base substrate (e.g., the interlayer dielectric layer ILD) at least partially overlaps with the orthographic projection of the first data line DL1 (e.g., the first data line portion dp1) on the base substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line Vdd2 (e.g., the second voltage supply line portion vp2) on the base substrate. The orthographic projection of the second anode AD2 on the base substrate at least partially overlaps with the orthographic projection of the first data line DL1 (e.g., the first data line portion dp1) on the base substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line Vdd2 (e.g., the second voltage supply line portion vp2) on the base substrate.

[0099] Optionally, the orthographic projection of the first anode AD1 on the base substrate (e.g., the interlayer dielectric layer ILD) covers the orthographic projection of the first portion of the first data line DL1 (e.g., the first data line portion dp1) on the base substrate, and covers the orthographic projection of the second portion of the second voltage supply line Vdd2 (e.g., the second voltage supply line portion vp2) on the base substrate. Optionally, the orthographic projection of the second anode AD2 on the base substrate covers the orthographic projection of the third portion of the first data line DL1 (e.g., the first data line portion dp1) on the base substrate, and covers the orthographic projection of the fourth portion of the second voltage supply line Vdd2 (e.g., the second voltage supply line portion vp2) on the base substrate.

[0100] In some embodiments, the orthographic projection of the first anode AD1 on the base substrate also at least partially overlaps with the orthographic projection of the first voltage supply line Vdd1 (e.g., the first voltage supply line portion vp1) on the base substrate; and the orthographic projection of the second anode AD2 on the base substrate at least partially overlaps with the orthographic projection of the first voltage supply line Vdd1 (e.g., the first voltage supply line portion vp1) on the base substrate.

[0101] Optionally, the orthographic projection of the first anode AD1 on the base substrate also covers the orthographic projection of the fifth portion of the first voltage supply line Vdd1 (for example, the first voltage supply line portion vp1) on the base substrate; the orthographic projection of the second anode AD2 on the base substrate covers the orthographic projection of the sixth portion of the first voltage supply line Vdd1 (for example, the first voltage supply line portion vp1) on the base substrate.

[0102] See also Figure 3 , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11 and Fig.12 In some embodiments, the array substrate includes a first anode contact pad ACP1, a second anode contact pad ACP2, and a third anode contact pad ACP3; a planarization layer PLN, which is located on a side of the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 away from the base substrate (interlayer dielectric layer ILD); a first anode contact hole AH1, a second anode contact hole AH2, and a third anode contact hole AH3 extending through the planarization layer PLN respectively; a pixel defining layer PDL, which is located on a side of the first anode AD1, the second anode AD2, and the third anode AD3 away from the planarization layer PLN; a first sub-pixel opening SA1, a second sub-pixel opening SA2, and a third sub-pixel opening SA3 extending through the pixel defining layer PDL respectively; and a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 located on a side of the pixel defining layer PDL away from the base substrate. The first anode AD1, the second anode AD2 and the third anode AD3 are connected to the first anode contact pad ACP1, the second anode contact pad ACP2 and the third anode contact pad ACP3 through the first anode contact hole AH1, the second anode contact hole AH2 and the third anode contact hole AH3, respectively. The first light-emitting layer EL1, the second light-emitting layer EL2 and the third light-emitting layer EL3 are connected to the first anode AD1, the second anode AD2 and the third anode AD3 through the first sub-pixel opening SA1, the second sub-pixel opening SA2 and the third sub-pixel opening SA3, respectively.

[0103] Reference Fig.11 In some embodiments, the first anode contact hole AH1 is outside the region having the first sub-pixel opening SA1; the second anode contact hole AH2 is outside the region having the second sub-pixel opening SA2; and the third anode contact hole AH3 is outside the region having the third sub-pixel opening SA3.

[0104] Fig.15 is a diagram showing the structure of a first pixel driving circuit of an array substrate in some embodiments of the present disclosure. Fig.16 is along Fig.15 Cross-sectional view along line E-E'. Fig.17 for Fig.15 The cross-sectional view along the F-F' line. Figure 3 , Figure 7 , Fig.15 , Fig.16 and Fig.17In some embodiments, the array substrate further includes a connection through hole (e.g., a first connection through hole cv1 or a second connection through hole cv2) extending through the interlayer dielectric layer ILD. Optionally, a voltage supply line (e.g., a first voltage supply line Vdd1) is connected to a first portion Ce2-1 of the second capacitor electrode Ce2 through the connection through hole (e.g., through the first connection through hole cv1 and the second connection through hole cv2). In some embodiments, the second capacitor electrode Ce2 is configured to be provided with a high voltage signal through the voltage supply line (e.g., the first voltage supply line Vdd1), such as Figure 2 As shown in the circuit diagram.

[0105] Reference Figure 3 , Figure 7 , Fig.15 , Fig.16 and Fig.17 In some embodiments, the signal line layer further includes a first connection line Cl1 and a second connection line Cl2. Optionally, the second connection line Cl2 is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the second connection line Cl2 is in the same layer as the voltage supply line (e.g., the first voltage supply line Vdd1) and the data line (e.g., the first data line DL1). In some embodiments, the second conductive layer includes the second capacitor electrode Ce2 and the reset signal line Vint. Fig.15 , Fig.16 and Fig.17 In some embodiments, the array substrate includes a third through hole 3. The third through hole v3 extends through the interlayer dielectric layer ILD. The second connection line Cl2 is connected to the reset signal line Vint through the third through hole v3. Optionally, the array substrate further includes a fourth through hole v4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second connection line Cl2 is connected to the semiconductor material layer SML through the fourth through hole v4.

[0106] Reference Figure 3 , Figure 4 and Fig.16 In some embodiments, the source S1 of the first transistor T1 and the active layer ACT1 of the first transistor T1 are part of the integral structure in each sub-pixel. The second connection line Cl2 is connected to the source S1 of the first transistor T1 through the fourth through hole v4. Figure 2 and Fig.16 , a reset signal may be provided from the reset signal line Vint to the source S1 of the first transistor T1 through the second connection line Cl2.

[0107] Reference Figure 3 , Figure 7 Figure 9 Fig.15 and Fig.16In some embodiments, the array substrate includes a fifth through hole v5 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The data line (eg, the first data line DL1) is connected to the semiconductor material layer SML through the fifth through hole v5. Figure 3 , Figure 4 and Fig.16 In some embodiments, the source S2 of the second transistor T2, the active layer ACT2 of the second transistor T2, and the drain D2 of the second transistor T2 are part of the integral structure in each sub-pixel. The data line (e.g., the first data line DL1) is connected to the source S2 of the second transistor T2 through the fifth through hole v5. Figure 2 and Fig.16 , a data signal may be provided from a data line (eg, the first data line DL1 ) to the source electrode S2 of the second transistor T2 through the fifth through hole v5 .

[0108] Reference Figure 3 , Figure 7 , Fig.15 and Fig.17 In some embodiments, the array substrate includes a sixth through hole V6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The voltage supply line (eg, the first voltage supply line Vdd1) is connected to the semiconductor material layer SML through the sixth through hole v6. Figure 3 , Figure 4 and Fig.17 In some embodiments, the source S4 of the fourth transistor T4, the active layer ACT4 of the fourth transistor T4, and the drain D4 of the fourth transistor T4 are part of the integral structure in each sub-pixel. The voltage supply line (e.g., the first voltage supply line Vdd1) is connected to the source S4 of the fourth transistor T4 through the sixth through hole v6. Figure 2 and Fig.16 , a high voltage signal may be provided from a voltage supply line (eg, the first voltage supply line Vdd1 ) to the source S4 of the fourth transistor T4 through the sixth via v6 .

[0109] refer to Figure 3 , Figure 7 , Fig.15 and Fig.17 In some embodiments, the array substrate includes a pad contact via (e.g., a first pad contact via CNT1) extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The anode contact pad (e.g., the first anode contact pad ACP1) is connected to the semiconductor material layer SML through the pad contact via (e.g., the first pad contact via CNT1). Figure 3 , Figure 4 and Fig.17In some embodiments, the source S5 of the fifth transistor T5, the active layer ACT5 of the fifth transistor T5, and the drain D5 of the fifth transistor T5 are part of the integral structure in each sub-pixel. The anode contact pad (e.g., the first anode contact pad ACP1) is connected to the drain D5 of the fifth transistor T5 through a pad contact via (e.g., the first pad contact via CNT1). Figure 2 and Fig.16 A voltage signal is provided from the drain D5 of the fifth transistor T5 to the anode (eg, the first anode AD1) of the light emitting element through the anode contact pad (eg, the first anode contact pad ACP1) to drive the light emitting element to emit light.

[0110] In some embodiments, the array substrate further includes at least one insulating layer between the base substrate and the first anode contact pad, the second anode contact pad, and the third anode contact pad. Figure 3 , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11 , Fig.12 and Fig.17 In some embodiments, the array substrate includes a gate insulating layer GI, an insulating layer IN, and an interlayer dielectric layer ILD between the base substrate BS and the first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3.

[0111] Fig.18 is a diagram showing the connection of anodes and anode contact pads in an array substrate according to some embodiments of the present disclosure. Fig.18 and Fig.17 The array substrate includes a first pad contact through hole CNT1, a second pad contact through hole CNT2, and a third pad contact through hole CNT3 extending through the gate insulating layer GI, the insulating layer IN, and the interlayer dielectric layer ILD, respectively. The first anode contact pad ACP1, the second anode contact pad ACP2, and the third anode contact pad ACP3 are connected to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 through the first pad contact through hole CNT1, the second pad contact through hole CNT2, and the third pad contact through hole CNT3, respectively.

[0112] refer to Fig.18, along the direction of the first virtual line Vl1 or the second virtual line Vl2, the first anode contact hole AH1 is located between the first pad contact through hole CNT1 and the first voltage supply line Vdd1. Along the direction of the first virtual line Vl1 or the second virtual line Vl2, the second anode contact hole AH2 is located between the second pad contact through hole CNT2 and the second voltage supply line Vdd2. In an example, the third pad contact through hole CNT3 and the third anode contact hole AH3 are arranged in a direction substantially parallel to the third data line DL3 and the third voltage supply line Vdd3.

[0113] Fig.19 is a diagram showing the structure of an anode of a light emitting element of an array substrate according to some embodiments of the present disclosure. Fig.19 In some embodiments, the first anode AD1 includes a first main body portion MP1 and a first bridge portion P1; the second anode AD2 includes a second main body portion MP2 and a second bridge portion P2; and the third anode AD3 includes a third main body portion MP3 and a third bridge portion P3. In one example, the first main body portion MP1, the second main body portion MP2, and the third main body portion MP3 have a substantially rectangular shape. As used herein, the term "substantially rectangular" refers to a polygonal shape (e.g., a parallelogram) in which the opposite sides are substantially parallel and the vertex angle is substantially 90 degrees. As used herein, the term "opposite sides are substantially parallel" refers to two opposite sides forming an angle in the range of 0 degrees to about 15 degrees, for example, 0 degrees to about 1 degree, about 1 degree to about 2 degrees, about 2 degrees to about 5 degrees, about 5 degrees to about 10 degrees, and about 10 degrees to about 15 degrees. Optionally, the vertex angles of the substantially rectangular shape are in the range of about 75 degrees to about 105 degrees, for example, about 89 degrees to about 91 degrees, about 88 degrees to about 92 degrees, about 85 degrees to about 95 degrees, and about 80 degrees to about 100 degrees.

[0114] In some embodiments, the first bridge portion P1, the second bridge portion P2, and the third bridge portion P3 protrude outward from the first body portion MP1, the second body portion MP2, and the third body portion MP3, respectively. Fig.17 , Fig.18 and Fig. 10B , the first bridge portion P1, the second bridge portion P2 and the third bridge portion P3 are connected to the first anode contact pad ACP1, the second anode contact pad ACP2 and the third anode contact pad ACP3 respectively through the first anode contact hole AH1, the second anode contact hole AH2 and the third anode contact hole AH3. Fig.18 and Fig.19In one example shown, the third bridge portion P3 protrudes outward from the third body portion MP3 in a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The second bridge portion P2 protrudes outward from the second body portion MP2 in a direction substantially parallel to the second data line DL2 or the second voltage supply line Vdd2. The first bridge portion P1 protrudes outward from the first body portion MP1 in a direction inclined at an angle to the first virtual line Vl1 and the first data line DL1.

[0115] In some embodiments, each data line is configured to provide a data signal to a column of pixel driving circuits (or a column of sub-pixels), and each voltage supply line is configured to provide a high voltage signal to a column of pixel driving circuits (or a column of sub-pixels). Fig. 20 FIG. 4 shows the arrangement of light emitting elements in an array substrate according to some embodiments of the present disclosure. Fig. 20 In some embodiments, the array substrate includes a first pixel driving circuit pdc1, a second pixel driving circuit pdc2, a third pixel driving circuit pdc3, a fourth pixel driving circuit pdc4, a fifth pixel driving circuit pdc5 and a sixth pixel driving circuit pdc6. Fig.18 and Fig. 20 In some embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 are configured to provide data signals to the first pixel driving circuit pdc1, the second pixel driving circuit pdc2, the third pixel driving circuit pdc3, the fourth pixel driving circuit pdc4, the fifth pixel driving circuit pdc5, and the sixth pixel driving circuit pdc6, respectively. The first pixel driving circuit pdc1, the second pixel driving circuit pdc2, and the third pixel driving circuit pdc3 are sequentially arranged along a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The fourth pixel driving circuit pdc4, the fifth pixel driving circuit pdc5, and the sixth pixel driving circuit pdc6 are sequentially arranged along a direction substantially parallel to the first virtual line Vl1 or the second virtual line Vl2. The first pixel driving circuit pdc1 and the fourth pixel driving circuit pdc4 are arranged along a direction substantially parallel to the first data line DL1 or the first voltage supply line Vdd1. The second pixel driving circuit pdc2 and the fifth pixel driving circuit pdc5 are arranged in a direction substantially parallel to the second data line DL2 or the second voltage supply line Vdd2. The third pixel driving circuit pdc3 and the sixth pixel driving circuit pdc6 are arranged in a direction substantially parallel to the third data line DL3 or the third voltage supply line Vdd3.

[0116] Reference Fig. 20In some embodiments, the first light emitting element LE1 is driven by the first pixel driving circuit pdc1 and is at least partially located in the area with the fifth pixel driving circuit pdc5. The second light emitting element LE2 is driven by the second pixel driving circuit pdc2 and is partially located in the area with the first pixel driving circuit pdc1 and partially located in the area with the second pixel driving circuit pdc2. The third light emitting element LE3 is driven by the third pixel driving circuit pdc3 and is partially located in the area with the third pixel driving circuit pdc3 and partially located in the area with the sixth pixel driving circuit pdc6.

[0117] The present disclosure finds that the uniformity of the anode in the display panel may adversely affect the image display. For example, color shift can be caused by the tilt of the anode. It is found in the present disclosure that the signal line under the anode can significantly affect the degree of anode tilt. In one example, under the anode, a signal line is set on one side, while there is no signal line on the other side. This results in an uneven surface of the planarization layer on top of the signal line. The uneven surface of the planarization layer in turn causes the anode on top of the planarization layer to tilt. Fig.21 is a cross-sectional view of the array substrate. Fig.21 As shown, the presence of the signal line 1 under the left portion of the planarization layer 2 causes the planarized surface to be uneven, which in turn causes the anode 3 on the top of the planarization layer 2 to tilt to the right. The tilted anode reflects more light toward the right side of the display panel. In the display panel, the anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in the sub-pixels of different colors reflects light of different colors at different angles. The cumulative effect of this problem leads to color shift at large viewing angles.

[0118] Fig. 22 is a schematic diagram showing a cross-sectional view of an array substrate. Fig. 22 As shown, there is no signal line 1 under the third anode 3-3 which is not tilted. The signal line 1 is located below the anodes 3-1 and 3-2. However, the signal line is only located below the right part of the anode 3-1, and only located below the left part of the anode 3-2, which causes the two anodes to tilt. Anodes 3-1, 3-2 and 3-3 are respectively the anodes of the red sub-pixel, the anode of the green sub-pixel and the anode of the blue sub-pixel. Because the tilt angles of the anodes in the three sub-pixels of different colors are different from each other, color shift occurs at a large viewing angle.

[0119] Fig.23 is a schematic diagram showing a cross-sectional view of an array substrate. Fig.23 As shown, the signal line exists under the left and right portions of anode 3-1, and under the left and right portions of anode 3-2. All anodes are substantially non-tilted, thereby alleviating the color shift problem.

[0120] In the present array substrate, the third voltage supply line portion vp3 (under the third anode AD3) has an increased line width. Fig.13A and Fig.14 As shown, the main sub-portion msp and the third data line DL3 are mostly arranged below the right part of the third anode AD3. If not compensated, it will cause the anode tilting and color shifting in the display panel. By having a widening sub-portion wsp to increase the line width of the third voltage supply part vp3 below the third anode AD3, the signal line (third voltage supply part vp3 and data line DL3) is more evenly distributed below the left and right parts of the third anode AD3, preventing the third anode from tilting. Therefore, the color shift problem can be alleviated.

[0121] The presence of the anode contact hole in the array substrate may also affect the tilt angle of the related anode. In addition, the residual planarization layer material in the anode contact hole may cover a portion of the anode. It is found in the present disclosure that these problems also affect the performance of the display panel. Fig.24 is a cross-sectional image of the array substrate. Fig.24 The anode contact hole AH extends through the planarization layer PLN to expose the surface of the anode contact pad ACP. A portion of the anode AD is connected to the anode contact pad ACP through the anode contact hole AH. A pixel defining layer PDL is formed to define a sub-pixel opening SA. Fig.24 As shown, the anode AD includes a bridge portion BP connecting the main portion of the anode in the sub-pixel opening SA to the anode contact pad ACP. By making the bridge portion BP separate the anode contact hole AH from the sub-pixel opening SA, for example, making the anode contact hole AH outside the area with the sub-pixel opening SA, the adverse effects caused by the presence of the anode contact hole can be minimized or eliminated.

[0122] Fig.25 is a diagram showing the structure of a plurality of sub-pixels of an array substrate in some embodiments of the present disclosure. Fig.25 In some embodiments, the plurality of sub-pixels Sp include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0123] Fig.26 is a diagram showing the structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Fig. 27 is a diagram showing the structure of a first conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Fig.28 is a diagram showing the structure of a second conductive layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Fig.29 is a diagram showing the structure of a signal line layer in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Fig.30 is along Fig.25 Cross-sectional view of line G-G' in Fig. Figures 25 to 30 In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on a side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on a side of the second conductive layer away from the insulating layer IN, and a signal line layer located on a side of the interlayer dielectric layer ILD away from the second conductive layer.

[0124] Reference Figure 2 , Fig.25 and Fig. 27 In some embodiments, the first conductive layer includes a gate line GL, a reset control signal line rst, a light emitting control signal line em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Fig. 27 In the figure, the sub-pixel Sp on the left is marked with a mark, which represents the area corresponding to multiple transistors (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a driving transistor Td) in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the gate line GL, the reset control signal line rst, the light emitting control signal line em and the first capacitor electrode Ce1 are in the same layer.

[0125] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the gate line GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the gate line GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the step of forming the gate line GL and the step of forming the first capacitor electrode Ce1 at the same time, the gate line GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0126] Reference Figure 2 , Fig.25 and Fig.28In some embodiments, the second conductive layer includes a reset signal line Vint and a second capacitor electrode Ce2 of the storage capacitor Cst. Fig.28 In the figure, the sub-pixel Sp on the left is marked with a mark, which represents the area corresponding to multiple transistors (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a driving transistor Td) in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the reset signal line Vint and the second capacitor electrode Ce2 are located in the same layer.

[0127] Reference Figure 2 , Fig.25 and Fig.29 In some embodiments, the signal line layer includes a voltage supply line Vdd, a data line DL, a first connection line Cl1, and a second connection line Cl2. Fig.29 In the figure, the sub-pixel Sp on the left is marked with a mark, which represents the area corresponding to multiple transistors in the pixel driving circuit (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a driving transistor Td). Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the voltage supply line Vdd, the data line DL, the first connection line Cl1 and the second connection line Cl2 are located on the same layer. As Fig.29 As shown, the data line DL is not completely straight, but has a meandering portion to avoid overlapping with the semiconductor material layer.

[0128] refer to Figure 2 , Fig.25 , Fig. 27 , Fig.28 and Fig.30 In some embodiments, the storage capacitor Cst includes a first capacitor electrode Ce1, a second capacitor electrode Ce2, and an insulating layer IN between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. Figure 2As shown, the second capacitor electrode Ce2 is electrically connected to the voltage supply line Vdd. For example, the second capacitor electrode Ce2 and the voltage supply line Vdd are configured to be always supplied with the same voltage.

[0129] Reference Figure 2 , Fig.25 and Fig.26 In some embodiments, in each sub-pixel, the semiconductor material layer has an integral structure. Fig.26 In FIG. 1 , the sub-pixel Sp on the left is marked with a mark, which indicates the region corresponding to the plurality of transistors (including the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the driving transistor Td) in the pixel driving circuit. Fig.26 , the sub-pixel Sp on the right is marked with a mark, which represents the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd), source (S1, S2, S3, S4, S5, and Sd), and drain (D1, D2, D3, D4, D5, and Dd) of the transistor (T1, T2, T3, T4, T5, and Td) in each sub-pixel are part of an integral structure in each sub-pixel. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd), source (S1, S2, S3, S4, S5, and Sd), and drain (D1, D2, D3, D4, D5, and Dd) of the transistor (T1, T2, T3, T4, T5, and Td) are in the same layer.

[0130] Fig.31 is a diagram showing a structure of a region in which a signal line crosses a second capacitor electrode in an array substrate according to some embodiments of the present disclosure. Fig.32 FIG. 4 is a further enlarged view of a region in which a signal line crosses a second capacitor electrode in an array substrate according to some embodiments of the present disclosure. Fig.31 and Fig.32In some embodiments, the second capacitor electrode Ce2 includes a first portion Ce2-1 and a second portion Ce-2 as part of an overall structure in each sub-pixel. Optionally, the first portion Ce2-1 and the second portion Ce-2 are adjacent to each other. Optionally, the voltage supply line Vdd crosses the first portion Ce2-1 by a first crossing distance L1. Optionally, the data line DL crosses the second portion Ce2-2 by a second crossing distance L2. Optionally, the area of ​​the first portion Ce2-1 is greater than the area of ​​the second portion Ce-2.

[0131] In some embodiments, the first intersection distance L1 is greater than the second intersection distance L2. Optionally, the first intersection distance L1 is no greater than 30%, such as no greater than 25%, no greater than 20%, no greater than 15%, no greater than 10% or no greater than 5%.

[0132] In some embodiments, reference Fig.25 and Fig.31 , the voltage supply line Vdd and the data line DL are substantially parallel to each other. As used herein, the term "substantially parallel" means that the angle between the two signal lines is in the range of 0 to about 25 degrees, such as 0 to about 5 degrees, 0 to about 10 degrees, 0 to about 15 degrees, or 0 to about 20 degrees. Fig.32 , a section where the voltage supply line Vdd crosses the first portion Ce2 - 1 and a section where the data line DL crosses the second portion Ce2 - 2 are substantially parallel to each other.

[0133] In some embodiments, reference Fig.32 , a section of the voltage supply line Vdd intersects the first portion Ce2-1 to a first intersection area; and a section of the data line DL intersects the second portion Ce2-2 to a second intersection area. Optionally, the first intersection area is larger than the second intersection area, for example, by no more than 30%, no more than 25%, no more than 20%, no more than 15%, no more than 10%, or no more than 5%.

[0134] By making the second capacitor electrode Ce have a first part Ce2-1 and a second part Ce2-2, and the first crossing distance L1 is greater than the second crossing distance L2, the inventors of the present disclosure have found that unexpected advantages can be achieved compared with the capacitor electrode in which the first crossing distance L1 is equal to the second crossing distance L2. In the present array substrate, the data line DL crosses the second part Ce2-2 to form a parasitic capacitor. The data line DL is loaded before the transistor (e.g., the second transistor T2) of the pixel driving circuit is turned on. When the transistor is turned on (e.g., a gate scanning signal provided by the gate line), the presence of the parasitic capacitor can effectively prevent the degradation of the data signal in the data line DL. On the other hand, the overlap of the data line DL with the second capacitor electrode Ce2 can also cause a source load. A large source load may cause signal delay and higher power consumption. By making the second crossing distance L2 less than the first crossing distance L1, a balance can be unexpectedly achieved between the parasitic capacitance required to maintain the data signal and the relatively small source load when the transistor is turned on. In addition, since the array substrate can alleviate the source load problem, the total number of capacitance compensation circuits in the peripheral area of ​​the array substrate can be significantly reduced, so that more space can be used for image display.

[0135] In some embodiments, reference Fig.31 The section where the data line DL crosses the second portion Ce2-2 has a line width w, and optionally, the line width w is in the range of 2.0 μm to 4.0 μm, for example, 2.0 μm to 2.5 μm, 2.5 μm to 3.0 μm, 3.0 μm to 3.5 μm, or 3.5 μm to 4.0 μm. Optionally, the line width w is about 3.0 μm.

[0136] In some embodiments, reference Fig.31 The section of the data line DL intersects with the second portion Ce2-2 to a cross-sectional area of ​​50 μm. 2 Up to 90μm 2 In the range, for example, 50 μm 2 Up to 60μm 2 、60μm 2 Up to 70μm 2 、70μm 2 Up to 80μm 2 or 80μm 2 Up to 90μm 2 Optionally, the cross-sectional area is greater than or equal to 70 μm 2 .

[0137] refer to Figure 2 , Fig.25 , Fig. 27 , Fig.28 and Fig.30In some embodiments, the orthographic projection of the first portion Ce2-1 on the base substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS with a margin, except for a hole region H in which a portion of the first portion Ce2-1 of the second capacitor electrode Ce2 does not exist. The hole region H is in the middle of the first portion Ce2-1.

[0138] Reference Figure 2 , Fig.25 and Fig.30 In some embodiments, the signal line layer includes a first connection line Cl1 located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The first connection line Cl1 is located on the same layer as the voltage supply line Vdd and the data line DL. Optionally, the array substrate further includes a first through hole v1 located in the hole area H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first through hole v1.

[0139] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate further includes a first through hole v1 and a second through hole v2. The first through hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second through hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the first connection line Cl1 is connected to the first capacitor electrode Ce1 through the first through hole v1, and is connected to the semiconductor material layer SML through the second through hole v2.

[0140] Reference Figure 2 , Fig.25 and Fig.26 In some embodiments, the source S3 of the third transistor T3, the active layer ACT3 of the third transistor T3, the drain D3 of the third transistor, the source S1 of the first transistor T1, the active layer ACT1 of the first transistor T1, and the drain D1 of the first transistor T1 are part of the overall structure in each sub-pixel, and are optionally located in the same layer. Optionally, the first connection line Cl1 is connected to the source S3 of the third transistor T3 and the drain D1 of the first transistor T1 through the second through hole v2.

[0141] Fig.33 is a diagram showing a structure of a region in which a portion of a semiconductor layer intersects with a second capacitor electrode in an array substrate according to some embodiments of the present disclosure. Fig.31 , Fig.32 and Fig.33In some embodiments, the semiconductor material layer SML includes a cross portion COP that crosses at least one of the first portion Ce2-1 and the second portion Ce2-2 by a third cross distance L3. Optionally, the cross portion COP crosses the first portion Ce2-1. Optionally, the cross portion COP crosses the second portion Ce2-2. Optionally, the cross portion COP crosses both the first portion Ce2-1 and the second portion Ce2-2. Fig.32 and Fig.33 As shown, in one example, a left portion of the intersection portion COP intersects the first portion Ce2 - 1 , and a right portion of the intersection portion COP intersects the second portion Ce2 - 2 , and the left portion and the right portion are parallel to each other.

[0142] In one example, if Fig.33 As shown in FIG, the intersection portion COP, the voltage supply line Vdd and the data line DL are substantially parallel to each other. In another example, the intersection portion COP, the section where the voltage supply line Vdd crosses the first portion Ce2-1 and the section where the data line DL crosses the second portion Ce2-2 are substantially parallel to each other.

[0143] Reference Fig.30 , Fig.31 , Fig.32 and Fig.33 In some embodiments, the orthographic projection of the crossing portion COP on the base substrate BS, the orthographic projection of the voltage supply line Vdd on the base substrate BS, and the orthographic projection of the data line DL on the base substrate BS do not substantially overlap each other. As used herein, the term "substantially not overlapping" means that the two orthographic projections do not overlap by at least 90% (e.g., at least 92%, at least 94%, at least 96%, at least 98%, at least 99%, or 100%). By substantially overlapping the data line DL with the crossing portion COP, the source load on the data line DL can be further reduced.

[0144] In some embodiments, the orthographic projection of the semiconductor layer on the base substrate BS, the orthographic projection of the voltage supply line Vdd on the base substrate BS, and the orthographic projection of the data line DL on the base substrate BS do not substantially overlap with each other, which can further reduce the source load on the data line DL.

[0145] In some embodiments, the third crossing distance L3 is less than or equal to the first crossing distance L1, and greater than or equal to the second crossing distance L2. Fig.31 , Fig.32 and Fig.33 In one example, the third intersection distance L3 is smaller than the first intersection distance L1 and larger than the second intersection distance L2.

[0146] Reference Fig.33 and Fig.26In some embodiments, the drain D2 of the second transistor T2, the active layer ACT2 of the second transistor T2, the drain D4 of the fourth transistor T4, the active layer ACT4 of the fourth transistor T4, the source Sd of the driving transistor Td, and the active layer ACTd of the driving transistor Td are part of the overall structure in each sub-pixel. Optionally, at least a portion of the cross portion COP directly connects the drain D2 of the second transistor T2, the drain D4 of the fourth transistor T4, and the source Sd of the driving transistor Td to each other.

[0147] Fig.34 The structure of the first part and the second part of the second capacitor electrode in the array substrate in some embodiments of the present disclosure is shown. Fig.34 In some embodiments, the first portion Ce1 includes a main sub-portion Msp, a first side sub-portion Ssp1, and a second side sub-portion Ssp2. In one example, the main sub-portion Msp has a first side surface Ls1, a second side surface Ls2 opposite to the first side surface Ls1, a third side surface Ls3 connecting the first side surface Ls1 and the second side surface Ls2, and a fourth side surface Ls4 opposite to the third side surface Ls3. Optionally, the fourth side surface Ls4 connects the first side surface Ls1 and the second side surface Ls2. Fig.34 , the first side Ls1 is adjacent to the first side sub-portion Ssp1; the second side Ls2 is adjacent to the second side sub-portion Ssp2; the third side Ls3 is adjacent to the second portion Ce2-2. The main sub-portion Msp, the first side sub-portion Ssp1, the second side sub-portion Ssp2, and the second portion Ce2-2 are part of the overall structure in each sub-pixel. In an example, the first side Ls1 is a side where the main sub-portion Msp is directly connected to the first side sub-portion Ssp1; the second side Ls2 is a side where the main sub-portion Msp is directly connected to the second side sub-portion Ssp2; the third side Ls3 is a side where the main sub-portion Msp is directly connected to the second portion Ce2-2. Therefore, in some examples, the third side Ls3 is also a side of the second portion Ce2-2. Optionally, the length of the third side Ls3 is substantially the same as the second crossing distance L2. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as no more than 8%, no more than 6%, no more than 4%, no more than 2%, no more than 1%, no more than 0.5%, no more than 0.1%, no more than 0.05%, and no more than 0.01% of the base value.

[0148] In some embodiments, Fig.33As shown, the first side sub-portion Ssp1 has a substantially trapezoidal shape, and the second side sub-portion Ssp2 has a substantially inverted trapezoidal shape. As used herein, "substantially trapezoidal shape" or "substantially inverted trapezoidal shape" may include a shape or geometric shape having at least one pair of substantially parallel sides (regardless of whether the other two sides include straight lines, curves or other). As used herein, the term "substantially parallel sides" refers to two sides forming an angle in the range of 0 degrees to about 15 degrees, for example, 0 degrees to about 1 degree, about 1 degree to about 2 degrees, about 2 degrees to about 5 degrees, about 5 degrees to about 10 degrees, or about 10 degrees to about 15 degrees. Optionally, at least one pair of substantially parallel sides of the substantially trapezoidal shape includes a shorter side and a longer side, wherein the longer side is closer to the first side Ls1 of the main sub-portion Msp. Optionally, at least one pair of substantially parallel sides of the substantially inverted trapezoidal shape includes a shorter side and a longer side, wherein the longer side is closer to the second side Ls2 of the main sub-portion Msp.

[0149] Fig.35 is a diagram showing the structure of a sub-pixel of an array substrate in some embodiments of the present disclosure. Fig.36 is along Fig.35 Cross-sectional view along line H-H'. Fig.37 is along Fig.35 The cross-sectional view of the line I-I' in Fig. Fig.25 , Fig.31 , Fig.35 and Fig.37 In some embodiments, the array substrate further includes a connection through hole (e.g., a first connection through hole cv1 or a second connection through hole cv2) extending through the interlayer dielectric layer ILD. Optionally, the voltage supply line Vdd is connected to the first portion Ce2-1 of the second capacitor electrode Ce2 through the connection through hole (e.g., through the first connection through hole cv1 and the second connection through hole cv2). In some embodiments, the second capacitor electrode Ce2 is configured to be provided with a high voltage signal through the voltage supply line Vdd, such as Figure 2 As shown in the circuit diagram.

[0150] Reference Fig.25 , Fig.29 , Fig.31 , Fig.35 , Fig.36 and Fig.37 In some embodiments, the signal line layer includes a voltage supply line Vdd, a data line DL, a first connection line Cl1, and a second connection line Cl2. Optionally, the second connection line Cl2 is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the second connection line Cl2 is in the same layer as the voltage supply line Vdd and the data line DL. Fig.25 , Fig.28 , Fig.31 , Fig.35 , Fig.36 and Fig.37 In some embodiments, the second conductive layer includes a second capacitor electrode Ce2 and a reset signal line Vint. Fig.35 , Fig.36 and Fig.37 In some embodiments, the array substrate includes a third through hole v3. The third through hole v3 extends through the interlayer dielectric layer ILD. The second connection line Cl2 is connected to the reset signal line Vint through the third through hole v3. Optionally, the array substrate further includes a fourth through hole v4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second connection line Cl2 is connected to the semiconductor material layer SML through the fourth through hole v4.

[0151] Reference Fig.25 , Fig.26 and Fig.36 In some embodiments, the source S1 of the first transistor T1 and the active layer ACT1 of the first transistor T1 are part of the integral structure of each sub-pixel. The second connection line Cl2 is connected to the source S1 of the first transistor T1 through the fourth through hole v4. Figure 2 and Fig.36 , a reset signal may be provided from the reset signal line Vint to the source S1 of the first transistor T1 through the second connection line Cl2.

[0152] Reference Fig.25 , Fig.29 , Fig.31 , Fig.35 and Fig.36 In some embodiments, the array substrate includes a fifth through hole v5 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The data line DL is connected to the semiconductor material layer SML through the fifth through hole v5. Fig.25 , Fig.26 and Fig.36 In some embodiments, the source S2 of the second transistor T2, the active layer ACT2 of the second transistor T2, and the drain D2 of the second transistor T2 are part of the integral structure in each sub-pixel. The data line DL is connected to the source S2 of the second transistor T2 through the fifth through hole v5. Figure 2 and Fig.36 , the data signal may be provided from the data line DL to the source electrode S2 of the second transistor T2 through the fifth via v5.

[0153] Reference Fig.25 , Fig.29 , Fig.31 , Fig.35 and Fig.37In some embodiments, the array substrate includes a sixth through hole 6 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. The voltage supply line Vdd is connected to the semiconductor material layer SML through the sixth through hole v6. Fig.25 , Fig.26 and Fig.37 In some embodiments, the source S4 of the fourth transistor T4, the active layer ACT4 of the fourth transistor T4 and the drain D4 of the fourth transistor T4 are part of the integral structure in each sub-pixel. The voltage supply line Vdd is connected to the source S4 of the fourth transistor T4 through the sixth through hole v6. Figure 2 and Fig.36 , a high voltage signal may be provided from the voltage supply line Vdd to the source S4 of the fourth transistor T4 through the sixth via v6.

[0154] Reference Fig.25 , Fig.29 , Fig.31 , Fig.35 and Fig.37 In some embodiments, the array substrate includes a seventh through hole 7 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. The anode contact pad ACP is connected to the semiconductor material layer SML through the seventh through hole v7. Fig.25 , Fig.26 and Fig.37 In some embodiments, the source S5 of the fifth transistor T5, the active layer ACT5 of the fifth transistor T5 and the drain D5 of the fifth transistor T5 are part of the integral structure in each sub-pixel. The anode contact pad ACP is connected to the drain D5 of the fifth transistor T5 through the seventh through hole v7. Figure 2 and Fig.36 , a voltage signal is provided from the drain electrode D5 of the fifth transistor T5 to the anode of the light emitting element LE through the anode contact pad ACP to drive the light emitting element LE to emit light.

[0155] In some embodiments, reference Figure 25 to Figure 29 , the plurality of sub-pixels Sp include a first sub-pixel (eg, Fig.25 ), the second sub-pixel (eg, Fig.25 The middle sub-pixel in the figure) and the third sub-pixel (e.g., Fig.25In the first sub-pixel (e.g., the red sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML by a first overlapping area. In the second sub-pixel (e.g., the green sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML by a second overlapping area. In the third sub-pixel (e.g., the blue sub-pixel), the voltage signal line Vdd intersects the semiconductor material layer SML by a third overlapping area. Optionally, the third overlapping area is greater than the first overlapping area, and greater than the second overlapping area.

[0156] In some embodiments, in a first sub-pixel (e.g., a red sub-pixel), the voltage signal line Vdd intersects the second capacitor electrode Ce2 by a fourth overlapping area. In a second sub-pixel (e.g., a green sub-pixel), the voltage signal line Vdd intersects the second capacitor electrode Ce2 by a fifth overlapping area. In a third sub-pixel (e.g., a blue sub-pixel), the voltage signal line Vdd intersects the second capacitor electrode Ce2 by a sixth overlapping area. Optionally, the sixth overlapping area is greater than the fourth overlapping area, and greater than the fifth overlapping area.

[0157] In another aspect, the present disclosure provides a display panel, comprising an array substrate described herein or manufactured by a method described herein and an opposing substrate facing the array substrate. Optionally, the display panel is an organic light emitting diode display panel. Optionally, the display panel is a micro light emitting diode display panel.

[0158] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the method as described herein, and one or more integrated circuits connected to the array substrate.

[0159] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; forming a first data line, a second data line, and a third data line, which are configured to provide data signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; forming a first voltage supply line, a second voltage supply line, and a third voltage supply line, which are configured to provide high voltage signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; and forming a first light-emitting element, a second light-emitting element, and a third light-emitting element, which are connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively. Optionally, the first virtual line and the second virtual line pass through the first voltage supply line, the second voltage supply line, and the third voltage supply line, respectively. Optionally, the first voltage supply line, the second voltage supply line, and the third voltage supply line respectively include a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion respectively between the first virtual line and the second virtual line. Optionally, the orthographic projection of the third anode of the third light-emitting element on the base substrate completely covers the orthographic projection of the third voltage supply line portion on the base substrate. Optionally, the third voltage supply line portion has a third line width, which is greater than the first line width of the first voltage supply line portion and greater than the second line width of the second voltage supply line portion.

[0160] In some embodiments, the first virtual line and the second virtual line are formed to also pass through the first data line, the second data line, and the third data line, respectively. Optionally, forming the first data line, the second data line, and the third data line respectively includes forming a first data line portion, forming a second data line portion, and forming a third data line portion, and the first data line portion, the second data line portion, and the third data line portion are respectively located between the first virtual line and the second virtual line. Optionally, the first data line portion, the second data line portion, and the third data line portion are formed to have substantially the same line width. Optionally, the orthographic projection of the third anode on the base substrate at least partially overlaps with the orthographic projection of the third data line portion on the base substrate.

[0161] Optionally, the first data line, the second data line, the third data line, the first voltage supply line, the second voltage supply line and the third voltage supply line are formed substantially parallel to each other. Optionally, the data lines and the voltage supply lines are alternately arranged.

[0162] In some embodiments, forming the third voltage supply line portion includes forming a main sub-portion and forming a widened sub-portion. Optionally, the main sub-portion is located between the widened sub-portion and the third data line. Optionally, the main sub-portion, the first voltage supply line portion and the second voltage supply line portion have the same shape. Optionally, the main sub-portion, the first voltage supply line portion and the second voltage supply line portion have the same shape and the same width.

[0163] In some embodiments, a first anode of a first light emitting element is formed between a first voltage supply line and a second data line; and a second anode of a second light emitting element is formed between the first voltage supply line and the second data line. Optionally, an orthographic projection of the first anode on the base substrate at least partially overlaps with an orthographic projection of the first data line on the base substrate, and at least partially overlaps with an orthographic projection of the second voltage supply line on the base substrate. Optionally, an orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first data line on the base substrate, and at least partially overlaps with an orthographic projection of the second voltage supply line on the base substrate. Optionally, an orthographic projection of the first anode on the base substrate also at least partially overlaps with an orthographic projection of the first voltage supply line on the base substrate. Optionally, an orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first voltage supply line on the base substrate.

[0164] In some embodiments, the method further comprises forming a first anode contact pad, a second anode contact pad and a third anode contact pad; forming a planarization layer, which is located on the side of the first anode contact pad, the second anode contact pad and the third anode contact pad away from the base substrate; forming a first anode contact hole, a second anode contact hole and a third anode contact hole, which extend through the planarization layer respectively; forming a pixel defining layer, which is located on the side of the first anode, the second anode and the third anode away from the planarization layer; forming a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening, which extend through the pixel defining layer respectively; and forming a first light-emitting layer, a second light-emitting layer and a third light-emitting layer, the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are located on the side of the pixel defining layer away from the base substrate. Optionally, the first anode, the second anode and the third anode are formed to be connected to the first anode contact pad, the second anode contact pad and the third anode contact pad respectively through the first anode contact hole, the second anode contact hole and the third anode contact hole. Optionally, the first light emitting layer, the second light emitting layer and the third light emitting layer are formed to be connected to the first anode, the second anode and the third anode respectively through the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening respectively.

[0165] In some embodiments, a first anode contact hole is formed outside a region having a first sub-pixel opening; a second anode contact hole is formed outside a region having a second sub-pixel opening; and a third anode contact hole is formed outside a region having a third sub-pixel opening.

[0166] In some embodiments, the method further comprises at least one insulating layer formed between the base substrate and the first anode contact pad, the second anode contact pad and the third anode contact pad. Optionally, the method further comprises forming a first pad contact through hole, a second pad contact through hole and a third pad contact through hole, wherein the first pad contact through hole, the second pad contact through hole and the third pad contact through hole extend through the at least one insulating layer respectively. Optionally, the first anode contact pad, the second anode contact pad and the third anode contact pad are formed to be connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit respectively through the first pad contact through hole, the second pad contact through hole and the third pad contact through hole. Optionally, along the direction of the first virtual line or the second virtual line, the first anode contact hole is formed to be located between the first pad contact through hole and the first voltage supply line. Optionally, along the direction of the first virtual line or the second virtual line, the second anode contact hole is formed to be located between the second pad contact through hole and the second voltage supply line. Optionally, the third pad contact through hole and the third anode contact hole are arranged along a direction substantially parallel to the third data line and the third voltage supply line.

[0167] In some embodiments, forming the first anode includes forming a first main body portion and forming a first bridge portion; forming the second anode includes forming a second main body portion and forming a second bridge portion; forming the third anode includes forming a third main body portion and forming a third bridge portion. Optionally, the first main body portion, the second main body portion, and the third main body portion have a substantially rectangular shape. Optionally, the first bridge portion, the second bridge portion, and the third bridge portion protrude outward from the first main body portion, the second main body portion, and the third main body portion, respectively.

[0168] In some embodiments, the method further includes forming a first anode contact pad, a second anode contact pad, and a third anode contact pad; forming a planarization layer located on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate; forming a first anode contact hole, a second anode contact hole, and a third anode contact hole, wherein the first anode contact hole, the second anode contact hole, and the third anode contact hole extend through the planarization layer, respectively. Optionally, the first bridge portion, the second bridge portion, and the third bridge portion are formed to be connected to the first anode contact pad, the second anode contact pad, and the third anode contact pad, respectively, through the first anode contact hole, the second anode contact hole, and the third anode contact hole, respectively.

[0169] Optionally, the third bridge portion protrudes outward from the third body portion in a direction substantially parallel to the first virtual line or the second virtual line. Optionally, the second bridge portion protrudes outward from the second body portion in a direction substantially parallel to the second data line or the second voltage supply line. Optionally, the first bridge portion protrudes outward from the first body portion in a direction that is at an oblique angle to the first virtual line and the first data line.

[0170] In some embodiments, the first data line, the second data line and the third data line are also configured to provide the data signal to the fourth pixel driving circuit, the fifth pixel driving circuit and the sixth pixel driving circuit, respectively; the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit are arranged sequentially along a direction substantially parallel to the first virtual line or the second virtual line; the fourth pixel driving circuit, the fifth pixel driving circuit and the sixth pixel driving circuit are arranged sequentially along the direction substantially parallel to the first virtual line or the second virtual line; the first pixel driving circuit and the fourth pixel driving circuit are arranged along a direction substantially parallel to the first data line or the first voltage supply line; the second pixel driving circuit and the fifth pixel driving circuit are arranged along a direction substantially parallel to the second data line or the second voltage supply line; and the third pixel driving circuit and the sixth pixel driving circuit are arranged along a direction substantially parallel to the third data line or the third voltage supply line.

[0171] In some embodiments, a first light-emitting element is formed to be driven by the first pixel driving circuit and is formed to be at least partially located in a region having the fifth pixel driving circuit; the second light-emitting element is formed to be driven by the second pixel driving circuit and is formed to be partially located in a region having the first pixel driving circuit and partially located in a region having the second pixel driving circuit; and the third light-emitting element is formed to be driven by the third pixel driving circuit and is formed to be partially in a region having the third pixel driving circuit and partially in a region having the sixth pixel driving circuit.

[0172] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a gate line; forming a data line; forming a voltage supply line; and forming a pixel drive circuit. Optionally, forming the pixel drive circuit includes forming a plurality of transistors and forming a storage capacitor. Optionally, forming the storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode, and forming an insulating layer between the first capacitor electrode and the second capacitor electrode. Optionally, the second capacitor electrode is formed to be electrically connected to the voltage supply line. Optionally, forming the second capacitor electrode includes forming a first portion and a second portion as part of a first overall structure in each sub-pixel. Optionally, the voltage supply line crosses the first portion by a first crossing distance. Optionally, the data line crosses the second portion by a second crossing distance. Optionally, the first crossing distance is greater than the second crossing distance.

[0173] In some embodiments, the voltage supply line and the data line are substantially parallel to each other; and a section where the voltage supply line crosses the first portion and a section where the data line crosses the second portion are substantially parallel to each other.

[0174] In some embodiments, the method further comprises forming an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; and forming a connecting via extending through the interlayer dielectric layer. Optionally, the voltage supply line is formed to be connected to the first portion of the second capacitor electrode through the connecting via.

[0175] In some embodiments, the method further comprises forming a semiconductor material layer, wherein the intersection portion of the semiconductor material layer is formed to intersect at least one of the first portion and the second portion by a third intersection distance. Optionally, the third intersection distance is less than or equal to the first intersection distance and greater than or equal to the second intersection distance. Optionally, the intersection portion intersects both the first portion and the second portion.

[0176] In some embodiments, the intersection portion, the voltage supply line and the data line are substantially parallel to each other; and the intersection portion, the section where the voltage supply line intersects the first portion and the section where the data line intersects the second portion are substantially parallel to each other.

[0177] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, the drain of the second transistor, the active layer of the second transistor, the drain of the fourth transistor, the active layer of the fourth transistor, the source of the driving transistor, and the active layer of the driving transistor are formed as part of the second integral structure in each sub-pixel. Optionally, at least a portion of the intersection is formed to directly connect the drain of the second transistor, the drain of the fourth transistor, and the source of the driving transistor to each other.

[0178] In some embodiments, an orthographic projection of the crossing portion on the base substrate, an orthographic projection of the voltage supply line on the base substrate, and an orthographic projection of the data line on the base substrate do not substantially overlap with respect to each other.

[0179] In some embodiments, except for a hole region where a portion of the second capacitor electrode does not exist, an orthographic projection of the first portion on the base substrate completely covers an orthographic projection of the first capacitor electrode on the base substrate with a margin.

[0180] In some embodiments, the method further includes forming an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; forming a first connection line located on a side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; and forming a first through hole located in the hole region and extending through the interlayer dielectric layer and the insulating layer. Optionally, the first connection line is connected to the first capacitor electrode through the first through hole.

[0181] In some embodiments, the method further comprises forming a semiconductor material layer on the base substrate; and forming a gate insulating layer on a side of the semiconductor material layer away from the base substrate. Optionally, the first capacitor electrode is formed on a side of the gate insulating layer away from the base substrate. Optionally, the method further comprises forming a second through hole extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer. Optionally, the first connecting line is connected to the semiconductor material layer through the second through hole.

[0182] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, a source of the third transistor, an active layer of the third transistor, a drain of the third transistor, a source of the first transistor, an active layer of the first transistor, and a drain of the first transistor are part of the second integral structure in each sub-pixel. Optionally, the first connecting line is connected to the source of the third transistor and the drain of the first transistor through the second through hole.

[0183] In some embodiments, forming the first portion includes forming a main sub-portion, a first side sub-portion, and a second side sub-portion. Optionally, the main sub-portion is formed to have a first side, a second side opposite to the first side, a third side connecting the first side and the second side, and a fourth side opposite to the third side. Optionally, the first side is adjacent to the first side sub-portion. Optionally, the second side is adjacent to the second side sub-portion. Optionally, the third side is adjacent to the second portion. Optionally, the first side sub-portion has a substantially trapezoidal shape; and the second side sub-portion has a substantially inverted trapezoidal shape. Optionally, the third side is a side of the second portion; and the length of the third side is substantially the same as the second crossing distance.

[0184] In some embodiments, the method further includes forming an interlayer dielectric layer between the voltage supply line and the second capacitor electrode; forming a second connection line located on a side of the interlayer dielectric layer away from the second capacitor electrode and in the same layer as the voltage supply line and the data line; forming a reset signal line located on a side of the insulating layer away from the first capacitor electrode and in the same layer as the second capacitor electrode; and forming a third through hole extending through the interlayer dielectric layer. Optionally, the second connection line is connected to the reset signal line through the third through hole.

[0185] In some embodiments, the method further includes forming a semiconductor material layer on a base substrate; and forming a gate insulating layer, which is located on a side of the semiconductor material layer away from the base substrate. Optionally, the first capacitor electrode is formed to be located on a side of the gate insulating layer away from the base substrate. Optionally, the method further includes forming a fourth through hole extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer. Optionally, a second connecting line is formed to be connected to the semiconductor material layer through the fourth through hole.

[0186] In some embodiments, forming a plurality of transistors includes forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; and forming a fifth transistor. Optionally, the source of the first transistor and the active layer of the first transistor are part of the second integral structure in each sub-pixel. Optionally, the second connecting line is connected to the source of the first transistor through the fourth through hole.

[0187] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: a first data line, a second data line and a third data line, wherein the first data line, the second data line and the third data line are configured to provide data signals to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit respectively; a first voltage supply line, a second voltage supply line, and a third voltage supply line, wherein the first voltage supply line, the second voltage supply line, and the third voltage supply line are configured to provide constant voltage signals to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, respectively; as well as a first light emitting element, a second light emitting element and a third light emitting element, wherein the first light emitting element, the second light emitting element and the third light emitting element are connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit respectively; wherein the first virtual line and the second virtual line pass through the first voltage supply line, the second voltage supply line and the third voltage supply line respectively; the first voltage supply line, the second voltage supply line, and the third voltage supply line respectively including a first voltage supply line portion, a second voltage supply line portion, and a third voltage supply line portion respectively between the first virtual line and the second virtual line; The orthographic projection of the third anode of the third light emitting element on the base substrate completely covers the orthographic projection of the third voltage supply line portion on the base substrate; and the third voltage supply line portion having a third line width, the third line width being greater than the first line width of the first voltage supply line portion and greater than the second line width of the second voltage supply line portion; A first anode of the first light emitting element is located between the first voltage supply line and the second data line; and The second anode of the second light emitting element is between the first voltage supply line and the second data line.

2. The array substrate according to claim 1, wherein: The first virtual line and the second virtual line also pass through the first data line, the second data line, and the third data line respectively; The first data line, the second data line, and the third data line respectively include a first data line portion, a second data line portion, and a third data line portion, and the first data line portion, the second data line portion, and the third data line portion are respectively located between the first virtual line and the second virtual line; and The first data line portion, the second data line portion, and the third data line portion have substantially the same line width.

3. The array substrate according to claim 2, wherein: An orthographic projection of the third anode on the base substrate at least partially overlaps with an orthographic projection of the third data line portion on the base substrate.

4. The array substrate according to claim 1, wherein: The first data line, the second data line, the third data line, the first voltage supply line, the second voltage supply line and the third voltage supply line are substantially parallel to each other; and The data lines and the voltage supply lines are alternately arranged in the following order, wherein the first voltage supply line, the first data line, the second voltage supply line, the second data line, the third voltage supply line, and the third data line are arranged in sequence.

5. The array substrate according to claim 4, wherein: The third voltage supply line portion includes a main sub-portion and a widening sub-portion; The main sub-portion is located between the widening sub-portion and the third data line; and The main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have the same shape.

6. The array substrate according to claim 5, wherein: The main sub-portion, the first voltage supply line portion, and the second voltage supply line portion have the same shape and the same width.

7. The array substrate according to claim 1, wherein: The orthographic projection of the first anode on the base substrate at least partially overlaps with the orthographic projection of the first data line on the base substrate, and at least partially overlaps with the orthographic projection of the second voltage supply line on the base substrate; as well as An orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first data line on the base substrate, and at least partially overlaps with an orthographic projection of the second voltage supply line on the base substrate.

8. The array substrate according to claim 7, wherein: The orthographic projection of the first anode on the base substrate also at least partially overlaps with the orthographic projection of the first voltage supply line on the base substrate; as well as An orthographic projection of the second anode on the base substrate at least partially overlaps with an orthographic projection of the first voltage supply line on the base substrate.

9. The array substrate according to claim 8, further comprising: a first anode contact pad, a second anode contact pad, and a third anode contact pad; a planarization layer located on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate; a first anode contact hole, a second anode contact hole, and a third anode contact hole, wherein the first anode contact hole, the second anode contact hole, and the third anode contact hole extend through the planarization layer respectively; a pixel defining layer, which is located on a side of the first anode, the second anode and the third anode away from the planarization layer; a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, wherein the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening extend through the pixel defining layer, respectively; as well as A first light-emitting layer, a second light-emitting layer and a third light-emitting layer, wherein the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are located on a side of the pixel defining layer away from the base substrate; Wherein, the first anode, the second anode and the third anode are connected to the first anode contact pad, the second anode contact pad and the third anode contact pad respectively through the first anode contact hole, the second anode contact hole and the third anode contact hole; as well as The first light emitting layer, the second light emitting layer, and the third light emitting layer are connected to the first anode, the second anode, and the third anode through the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening, respectively.

10. The array substrate according to claim 9, wherein: The first anode contact hole is outside the region having the first sub-pixel opening; The second anode contact hole is outside the region having the second sub-pixel opening; as well as The third anode contact hole is outside the region having the third sub-pixel opening.

11. The array substrate according to claim 10, further comprising at least one insulating layer between the base substrate and the first anode contact pad, the second anode contact pad and the third anode contact pad; a first pad contact via, a second pad contact via, and a third pad contact via, the first pad contact via, the second pad contact via, and the third pad contact via, respectively, extending through the at least one insulating layer; and The first anode contact pad, the second anode contact pad and the third anode contact pad are respectively connected to the first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit through the first pad contact through hole, the second pad contact through hole and the third pad contact through hole.

12. The array substrate according to claim 11, wherein: Along the direction of the first virtual line or the second virtual line, the first anode contact hole is located between the first pad contact through hole and the first voltage supply line; Along the direction of the first virtual line or the second virtual line, the second anode contact hole is located between the second pad contact through hole and the second voltage supply line; as well as The third pad contact via hole and the third anode contact hole are arranged in a direction substantially parallel to the third data line and the third voltage supply line.

13. The array substrate according to claim 1, wherein: The first anode includes a first body portion and a first bridge portion; The second anode includes a second body portion and a second bridge portion; The third anode includes a third main body portion and a third bridge portion; the first body portion, the second body portion and the third body portion having a substantially rectangular shape; as well as The first bridge portion, the second bridge portion, and the third bridge portion protrude outward from the first body portion, the second body portion, and the third body portion, respectively.

14. The array substrate according to claim 13, further comprising: a first anode contact pad, a second anode contact pad, and a third anode contact pad; a planarization layer located on a side of the first anode contact pad, the second anode contact pad, and the third anode contact pad away from the base substrate; a first anode contact hole, a second anode contact hole, and a third anode contact hole, wherein the first anode contact hole, the second anode contact hole, and the third anode contact hole extend through the planarization layer respectively; The first bridge portion, the second bridge portion and the third bridge portion are connected to the first anode contact pad, the second anode contact pad and the third anode contact pad respectively through the first anode contact hole, the second anode contact hole and the third anode contact hole respectively.

15. The array substrate according to claim 14, wherein: The third bridge portion protrudes outward from the third body portion along a direction substantially parallel to the first virtual line or the second virtual line; the second bridge portion protruding outward from the second body portion in a direction substantially parallel to the second data line or the second voltage supply line; as well as The first bridge portion protrudes outward from the first body portion in a direction forming an oblique angle with the first virtual line and the first data line.

16. The array substrate according to any one of claims 1 to 15, wherein: The first data line, the second data line and the third data line are further configured to provide the data signal to a fourth pixel driving circuit, a fifth pixel driving circuit and a sixth pixel driving circuit respectively; The first pixel driving circuit, the second pixel driving circuit and the third pixel driving circuit are sequentially arranged along a direction substantially parallel to the first virtual line or the second virtual line; The fourth pixel driving circuit, the fifth pixel driving circuit and the sixth pixel driving circuit are sequentially arranged along the direction substantially parallel to the first virtual line or the second virtual line; The first pixel driving circuit and the fourth pixel driving circuit are arranged along a direction substantially parallel to the first data line or the first voltage supply line; The second pixel driving circuit and the fifth pixel driving circuit are arranged along a direction substantially parallel to the second data line or the second voltage supply line; as well as The third pixel driving circuit and the sixth pixel driving circuit are arranged along a direction substantially parallel to the third data line or the third voltage supply line.

17. The array substrate according to claim 16, wherein: The first light emitting element is driven by the first pixel driving circuit and is at least partially located in a region having the fifth pixel driving circuit; The second light emitting element is driven by the second pixel driving circuit, is partially located in the area having the first pixel driving circuit, and is partially located in the area having the second pixel driving circuit; as well as The third light emitting element is driven by the third pixel driving circuit, partially in a region having the third pixel driving circuit, and partially in a region having the sixth pixel driving circuit.

18. The array substrate according to any one of claims 1 to 15, wherein: The third line width is in the range of 8.0 μm to 10.0 μm, the first line width is in the range of 5.0 μm to 6.0 μm, and the second line width is in the range of 5.0 μm to 6.0 μm.

19. A display device comprising the array substrate according to any one of claims 1 to 18 and an integrated circuit connected to the array substrate.

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