Microelectromechanical Systems and Manufacturing Methods

Abstract

A microelectromechanical system (MEMS) includes: a circuit substrate containing an electronic circuit, a support substrate having a groove, a bonding layer disposed between the circuit substrate and the support substrate, a through-hole passing through the circuit substrate to the groove, a first conductive layer disposed on the front side of the circuit substrate, and a second conductive layer disposed on the inner wall of the groove. The first conductive layer extends into the through-hole, and the second conductive layer extends into the through-hole and is coupled to the first conductive layer. Embodiments of the present application also provide a method for manufacturing a microelectromechanical system.

Description

Technical Field

[0001] Embodiments of the present application relate to microelectromechanical systems and manufacturing methods. Background Art

[0002] Microelectromechanical systems (MEMS) devices have recently been developed. MEMS devices include devices manufactured using semiconductor technology to form mechanical and electrical components. MEMS devices are implemented in pressure sensors, microphones, actuators, mirrors, heaters, and / or printer nozzles. Although existing devices and methods for forming MEMS devices have generally been sufficient to meet their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0003] Embodiments of the present application provide a microelectromechanical system (MEMS), including: a circuit substrate including an electronic circuit; a support substrate having a groove; a bonding layer disposed between the circuit substrate and the support substrate; a through hole passing through the circuit substrate to the groove; a first conductive layer disposed on a front side of the circuit substrate; and a second conductive layer disposed on an inner wall of the groove, wherein the first conductive layer extends into the through hole, and the second conductive layer extends into the through hole and is coupled to the first conductive layer.

[0004] Embodiments of the present application provide a microelectromechanical system (MEMS), including: a circuit substrate including an electronic circuit; a passivation layer disposed above the circuit substrate; a support substrate having a groove; a through hole passing through the circuit substrate to the groove; and a conductive layer covering at least a portion of the passivation layer, an inner sidewall of the through hole, an inner wall of the groove, and a side surface of the microelectromechanical system.

[0005] Embodiments of the present application further provide a method of manufacturing a microelectromechanical system (MEMS), including: forming an electronic circuit on a front side of a first substrate; forming a hole penetrating the first substrate; forming a first conductive layer on at least a portion of the front side above the first substrate and an inner sidewall of the hole; filling the hole with a filling material; thinning a back side of the first substrate; bonding a second substrate to the back side of the first substrate through a bonding layer, the bonding layer being inserted between the second substrate and the first substrate; forming a groove in the second substrate to expose a bottom of the first substrate; forming a through hole by removing the filling material; and forming a second conductive layer on an inner wall of the groove and at least a portion of the inner sidewall of the through hole not covered by the first conductive layer. Brief Description of the Drawings

[0006] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be increased or decreased arbitrarily.

[0007] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I and Figure 1J show schematic cross-sectional views of the various stages of the sequential manufacturing operations for a MEMS device in accordance with an embodiment of the present invention.

[0008] Figure 1K 、 Figure 1L 、 Figure 1M 、 Figure 1N 、 Figure 1O and Figure 1P show schematic cross-sectional views of the various stages of the sequential manufacturing operations for a MEMS device in accordance with another embodiment of the present invention.

[0009] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D show a schematic cross-sectional view of a MEMS device in accordance with an embodiment of the present invention.

[0010] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D show schematic cross-sectional views of the various stages of the sequential manufacturing operations for a MEMS device in accordance with an embodiment of the present invention.

[0011] Figure 4A and Figure 4B show a schematic cross-sectional view of a MEMS device in accordance with an embodiment of the present invention.

[0012] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24A illustrate schematic cross-sectional views, and Figure 24B illustrate plan views of the respective stages of sequential manufacturing operations for a MEMS device in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0013] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or the desired performance of the device. Additionally, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. For simplicity and clarity, the various components may be arbitrarily drawn at different scales.

[0014] Furthermore, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of". In the present invention, at least one of A, B, and C means "A", "B", "C", "A and B", "A and C", "B and C", or "A, B, and C", unless otherwise specified, and does not mean one from A, one from B, and one from C. The materials, configurations, dimensions, and processes described with respect to one embodiment may be applied to other embodiments, and their detailed descriptions may be omitted.

[0015] A MEMS device according to the present invention may be any one of a semiconductor device, an accelerometer, a gyroscope, a pressure sensor, a microphone, an RF resonator, an RF switch, or an ultrasonic transducer.

[0016] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E ,Figure 1F , Figure 1G , Figure 1H , Figure 1I and FIG. 1J shows schematic cross-sectional views of various stages of a manufacturing operation for a MEMS device according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the process shown in Figures 1A to 1J , and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged.

[0017] As Figure 1A shown, an electronic circuit 25 is formed in a block surface region of a circuit substrate 20. The electronic circuit 25 includes transistors, and the transistors include semiconductor field effect transistors such as complementary metal oxide semiconductor (CMOS) devices. In some embodiments, the circuit substrate 20 is made of crystalline silicon or any other suitable semiconductor material.

[0018] After forming the electronic circuit 25, one or more passivation films 28 are formed over a front surface of the circuit substrate 20. In some embodiments, the one or more passivation films 28 include silicon oxide, silicon nitride, or an organic film. Then, as Figure 1B shown, one or more holes 60 (e.g., through-silicon vias (TSVs)) are formed in the circuit substrate 20 using a mask pattern 29. In some embodiments, the holes 60 are formed such that no metal pattern is exposed inside the holes.

[0019] Then, as Figure 1C shown, a first conductive layer 50 is formed over a front side of the circuit substrate 20. In some embodiments, the first conductive layer 50 is formed over the passivation film 28. In some embodiments, as Figure 1C shown, the first conductive layer 50 is also formed on at least a portion of an inner wall of each hole 60. In some embodiments, the first conductive layer 50 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the first conductive layer 50 is a gold (Au) layer formed over a Ti layer. In other embodiments, the first conductive layer 50 is composed of one, two, three, four, or five layers of materials different from each other. For example, in some embodiments, the first conductive layer 50 has A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (where A / B means B is over A), where each of A, B, C, D, and E represents a metal or a metallic material. In other embodiments, the first conductive layer 50 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other.

[0020] In some embodiments, the first conductive layer 50 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), plating, or any other suitable film deposition method. In certain embodiments, a sputtering method is used. In some embodiments, the thickness of each metal layer or metal - made layer of the first conductive layer 50 ranges from about 2 nm to about 100 nm.

[0021] In some embodiments, the first conductive layer 50 is conformally formed inside the hole 60 such that the inner sidewalls and the bottom of the hole 60 are completely covered by the first conductive layer 50. In other embodiments, only the bottom and the inner sidewalls of the hole 60 are partially covered by the first conductive layer 50, and a portion of the circuit substrate (Si substrate) is exposed in the hole 60. In particular, in some embodiments, the lower part of the inner sidewall of the hole 60 is not covered by the first conductive layer 50.

[0022] In some embodiments, as Figure 1D shown, a filling layer 140 is formed to fill the hole 60. In some embodiments, the filling layer 140 includes silicon oxide, silicon nitride, or any other suitable insulating material. In certain embodiments, silicon oxide is used. In some embodiments, a blanket layer of the filling material is formed over the first conductive layer 50, and then a planarization operation such as a chemical - mechanical polishing process or a back - etching process is performed to leave the filling material only inside the hole 60, as Figure 1D shown. In other embodiments, no filling material is formed.

[0023] Then, as Figure 1E shown, the back side of the circuit substrate 20 is thinned by a grinding or polishing process. In some embodiments, the remaining thickness of the thinned circuit substrate 20 ranges from about 100 μm to about 500 μm.

[0024] Next, as Figure 1F shown, the thinned circuit substrate 20 is bonded to the support substrate 30 via the bonding layer 40. In some embodiments, as Figure 1C shown, the bonding layer 40 is silicon oxide formed on the surface of the support substrate 30 by, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process. In other embodiments, the bonding layer 40 is formed on the back side of the circuit substrate 20 by, for example, a CVD process. In some embodiments, the thickness of the bonding layer 40 ranges from about 500 nm to about 5 μm, and in other embodiments, from about 1 μm to about 2 μm.

[0025] Then, as Figure 1GAs shown, the back side of the support substrate 30 is recessed by using one or more photolithography and etching operations. In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the wet etching utilizes a tetramethylammonium hydroxide (TMAH) or KOH solution. In some embodiments, the bonding layer 40 serves as an etch stop layer for forming the groove 35 as shown in Figure 1G shown.

[0026] Subsequently, the bonding layer 40 is removed by a suitable etching operation. Then, the back side of the circuit substrate 25 is etched to expose the filling material 140 filled in the hole 60, and the filling material 140 is removed, thereby forming a through hole 65, as shown in Figure 1H shown.

[0027] In some embodiments, multiple MEMS devices are formed on a single wafer, and the wafer is cut into individual MEMS devices (chips) by sawing (a cutting operation), as shown by the arrow in Figure 1I In some embodiments, the cutting operation is performed before the groove etching for forming the groove 35.

[0028] After the cutting operation, as shown in Figure 1J shown, a second conductive layer 55 is formed inside the groove, at the bottom of the support substrate 30, and on the side surface of the chip. In some embodiments, the second conductive layer 55 includes one or more layers of Au, Ti, Cu, Ag, and Ni or their alloys. In some embodiments, the second conductive layer 55 is a gold (Au) layer formed on a Ti layer. In other embodiments, the second conductive layer 55 is composed of one, two, three, four, or five layers of materials different from each other. For example, the second conductive layer 55 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (A / B means B is on A), where each of A, B, C, D, and E represents a metal or a metallic material. In other embodiments, the second conductive layer 55 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. For example, the second conductive layer 55 has a layered structure of A / B / A / B, A / B / B / A, A / B, or A / A. In some embodiments, the film structure of the second conductive layer 55 is the same as that of the first conductive layer, and in other embodiments, the film structure of the second conductive layer 55 is different from that of the first conductive layer. In some embodiments, at least one metal layer of the first conductive layer 50 is the same as the metal layer of the second conductive layer 55.

[0029] In some embodiments, the second conductive layer 55 is formed by CVD, PVD including sputtering, ALD, plating, or any other suitable film deposition method. In certain embodiments, a sputtering method is used. In some embodiments, the thickness of each metal layer or metal-made layer of the second conductive layer 55 ranges from about 2 nm to about 100 nm.

[0030] In some embodiments, the second conductive layer 55 is conformally formed inside the vias 65 such that the inner sidewalls of the vias 65 on which the first conductive layer 50 is at least partially formed are completely covered by the second conductive layer 55. In other embodiments, the inner sidewalls of the vias 65 are only partially covered by the second conductive layer 55, and a portion of the first conductive layer 50 is exposed in the vias 65. Since the second conductive layer 55 is formed after the dicing operation, the second conductive layer is formed on the side surface of the chip.

[0031] In other embodiments, during the backside thinning operation described with respect to Figure 1E , the bottom of the exposed hole 60, particularly the filling material 140, is exposed as shown in Figure 1K . In this case, as shown in Figure 1L , the bonding layer 40 is in contact with the filling material 140. Then, similar to Figure 1G , the backside of the support substrate 30 is recessed by using one or more photolithography and etching operations as shown in Figure 1M . In some embodiments, the bonding layer 40 serves as an etch stop layer for forming the groove 35 as shown in Figure 1G . Further, the bonding layer 40 and the filling material 140 are removed by a suitable etching process as shown in Figure 1N . When the filling material 140 and the bonding layer 40 are made of the same material (e.g., silicon oxide), both the filling material 140 and the bonding layer 40 are removed in the same processing step. In some embodiments, a wet etching process using HF or buffered HF is performed to remove the bonding layer 40 and the filling material 140, thereby forming the vias 65. Then, as shown in Figure 1O , a dicing operation is performed, and the second conductive layer 55 is formed as shown in Figure 1P .

[0032] Figure 2A , Figure 2B , Figure 2C and Figure 2D show schematic cross-sectional views of manufacturing a MEMS device according to one or more of the foregoing embodiments. The detailed descriptions of the materials, configurations, dimensions, and processes described with respect to Figures 1A to 1P may be omitted.

[0033] As shown in Figure 2AAs shown, the MEMS device 10A includes a circuit substrate 20 in which an electronic circuit 25 is formed and a support substrate 30 having a groove 35. In some embodiments, an insulating layer 40 (bonding layer) is disposed between the circuit substrate 20 and the support substrate 30. In some embodiments, the insulating layer 40 is one or more of a silicon oxide layer, a silicon nitride layer, or any other metal oxide or nitride layer. In some embodiments, one or more vias 65 are provided to pass through the circuit substrate 20. In some embodiments, in a plan view, the vias 65 are rearranged in an n×m matrix, where n and m are integers of 2 or greater and equal to or less than, for example, 128.

[0034] In some embodiments, the thickness of the circuit substrate 20 is in the range of about 100 μm to about 500 μm. In some embodiments, the thickness of the support substrate 30 is in the range of about 300 μm to about 1500 μm. In some embodiments, the thickness of the insulating layer 40 is in the range of about 500 nm to about 5 μm, and in other embodiments, in the range of about 1 μm to about 2 μm. In some embodiments, the total thickness of the MEMS device is in the range of about 500 μm to about 2 mm, and in other embodiments, in the range of about 600 μm to about 1200 μm.

[0035] In some embodiments, as Figure 2A shown, a first conductive layer 50 is formed on the front surface of the circuit substrate 20, and a second conductive layer 55 is formed on the back surface of the support substrate 30. In some embodiments, the first conductive layer 50 is also formed on at least part of the inner wall of the via 65 and the passivation film 28, and the second conductive layer 55 is also formed on at least part of the inner wall of the via 65.

[0036] In some embodiments, as Figure 2A shown, the insulating layer 40 contacts the second conductive layer 55 and contacts the circuit substrate 20. In other embodiments, the insulating layer 40 remains at the bottom of the cavity 35 and the second conductive layer 55 does not contact the circuit substrate 20.

[0037] In some embodiments, the circuit substrate 20 includes an electronic circuit 25 such as a signal processing circuit and / or an amplifier circuit formed by an electronic circuit. In some embodiments, the groove 35 has a rectangular (e.g., square) shape in a plan view. In some embodiments, at least one of the circuit substrate 20 and the support substrate 30 is made of crystalline silicon.

[0038] Figures 2B to 2D is Figure 2AAn enlarged view of region A1. In some embodiments, the inner sidewall of the through-hole 65 is completely covered by the first conductive layer 50 and the second conductive layer 55. In some embodiments, when the first and second conductive layers are formed using a sputtering method, depending on the aspect ratio T1 / T3, the conductive layers are unevenly formed on the inner sidewall of the through-hole 65. T1 is the depth of the through-hole 65 from the upper surface of the passivation film 28 to the bottom of the circuit substrate 20, and T3 is the diameter of the through-hole 65. In some embodiments, the first and / or second conductive layer has a tapered shape. In other embodiments, the thickness of the first and / or second conductive layer is substantially uniform inside the through-hole 65, as Figure 2C and Figure 2D shown. In Figure 2C , the first conductive layer 50 partially covers the inner sidewall of the through-hole 65, and in Figure 2D , the first conductive layer 50 completely covers the inner sidewall of the through-hole 65. Since the second conductive layer 55 is formed from the back side of the circuit substrate 20, even if the first conductive layer 50 does not completely cover the inner sidewall of the through-hole 65, the inner sidewall of the through-hole 65 is completely covered by the conductive material. Since the first conductive layer and the second conductive layer are coupled to each other and completely cover the inner sidewall of the through-hole, it can improve the heat dissipation of the MEMS device.

[0039] In some embodiments, the coverage amount D1 of the first conductive layer 50 including the thickness of the first conductive layer 50 above the inner sidewall is equal to or greater than the coverage amount D2 of the second conductive layer 55 including the thickness of the second conductive layer 55 above the inner sidewall. In some embodiments, D1 and D3 are greater than about 50% of T3. In some embodiments, the second conductive layer 55 overlaps with the first conductive layer 50, and the overlap amount D3 is about 10% to 90% of the depth T1. In some embodiments, the total thickness of the conductive layer on the inner sidewall of the through-hole 65 is uneven. In some embodiments, the thickness of the conductive layer on the inner sidewall of the through-hole 65 at the overlapping region is greater than the thickness of each single layer of the first conductive layer 50 and the second conductive layer 55.

[0040] In some embodiments, the angle θ1 at the bottom of the groove 35 is greater than 0 degrees to less than 180 degrees, and is greater than 60 degrees to equal to or less than 90 degrees.

[0041] In some embodiments, the second conductive layer 55 covers a portion of the outer side surface of the MEMS device 10A while no first conductive layer 50 is provided on the outer side surface, as Figure 2BAs shown. In some embodiments, the distance D4 from the bottom to the top of the second conductive layer 55 is equal to or less than the total thickness T2 of the MEMS device 10A from the top of the first conductive layer 50 to the bottom of the second conductive layer 55. In some embodiments, the distance D5 from the interface between the insulating layer 40 and the circuit substrate 20 to the top end of the second conductive layer 55 is greater than zero. In other words, the second conductive layer 55 completely covers the side surface of the insulating layer 40. In some embodiments, the second conductive layer 55 on the outer side does not contact the first conductive layer 50 formed on the passivation layer 28. In other embodiments, the second conductive layer 55 on the outer side contacts the first conductive layer 50 formed on the passivation layer 28. The heat dissipation is improved by the coverage of the second conductive layer 55 on the outer side of the MEMS device 10A.

[0042] In some embodiments, the MEMS device can be manufactured by the operations shown below. After forming an electronic circuit above the circuit substrate, one or more planar electrodes are formed, and one or more layers of passivation layer are formed. The electrodes are electrically connected to the electronic circuit formed in the circuit substrate. In some embodiments, the circuit substrate includes a crystalline silicon substrate. In some embodiments, one or more openings are formed above the electrodes located in one or more layers of passivation layer. In some embodiments, the electrodes are made of one or more layers of Cu, Al, Au, Ni, Ag, or other suitable conductive materials. The passivation layer includes silicon nitride, SiON, silicon oxide, aluminum nitride, or an organic material.

[0043] Then, one or more holes for through-silicon vias (TSVs) are formed in the regions other than the electrodes. The TSV holes are formed by one or more photolithography and etching operations. In some embodiments, in the plan view, the TSV holes are arranged in an n×m matrix, where n and m are integers of 2 or greater and equal to or less than, for example, 128. In some embodiments, starting from the top of the passivation layer, the depth of the TSV is in the range of about 20 μm to about 100 μm. In some embodiments, the depth is determined such that after performing a thinning process on the back side of the circuit substrate subsequently, the bottom of the TSV hole is exposed. In some embodiments, the shape of the TSV hole in the plan view is circular or rectangular (e.g., square). In some embodiments, the TSV hole is a cone with an opening larger than the bottom. In some embodiments, the diameter (or the length of the side) of the TSV hole at the opening is in the range of about 100 nm to about 10,000 nm.

[0044] Then, a first conductive layer is formed above the electrodes, the passivation layer, and inside the TSV holes. Then, a filling layer is formed to fill the TSV holes. The first conductive layer has Figures 1A to 1DThe first conductive layer 50 shown has the same or similar functions. In some embodiments, the first conductive layer includes one or more layers of Au, Ti, Cu, Ag, and Ni. In certain embodiments, a gold layer formed over the Ti layer is used as the first conductive layer. In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 200 nm, and in other embodiments, from about 80 nm to about 120 nm. In some embodiments, the thickness of the gold (Au) layer ranges from about 10 nm to about 400 nm, and in other embodiments, from about 150 nm to about 250 nm. In some embodiments, the filling layer includes silicon oxide or any other suitable insulating material. In some embodiments, a blanket layer of the filling material is formed over the first conductive layer, and then a planarization operation such as a chemical mechanical polishing process or a back etching process is performed to leave the filling material only inside the TSV holes. In other embodiments, the filling material also remains on the recessed portions above the electrodes.

[0045] Next, the conductive layer is patterned to form one or more openings over the passivation layer near the TSV holes to partially expose the passivation layer. Then, an insulating layer is formed and patterned to form island-shaped insulating patterns to cover the openings. In some embodiments, the insulating pattern includes silicon nitride.

[0046] In addition, a first carrier bonding layer is formed over the front surface of the circuit substrate on which the conductive layer and the pattern are formed, and then the first carrier substrate is attached. In some embodiments, the first carrier substrate is a glass substrate, a ceramic substrate, a semiconductor substrate, or a resin substrate. In some embodiments, the first carrier bonding layer includes an organic material, silicon oxide, or any other suitable material.

[0047] Then, the back side of the circuit substrate is thinned by a grinding or polishing (e.g., CMP) operation. In some embodiments, after thinning, the remaining thickness of the circuit substrate ranges from about 20 μm to about 100 μm, and in other embodiments, the remaining thickness ranges from about 40 μm to about 60 μm. The bottom of the filling material layer filled in the TSV holes is exposed. In other embodiments, after the thinning operation, the first carrier substrate is attached to the front surface of the circuit substrate.

[0048] In addition, a bonding layer is formed on the thinned back surface of the circuit substrate. The bonding layer has the same or similar functions as Figure 1A the bonding layer 40 shown in FIGS. 2D. In some embodiments, the bonding layer includes silicon oxide formed by, for example, a CVD process.

[0049] Then, a support substrate is prepared and the support substrate is bonded to the circuit substrate through a bonding layer (oxide fusion bonding). In some embodiments, the support substrate is made of single crystal silicon. After the oxide fusion bonding, the first carrier substrate and the first carrier bonding layer are removed. When the first carrier bonding layer is made of an organic material, the first carrier substrate and the first carrier bonding layer are removed by a wet process. The bonding layer is connected to the filling material layer located in the TSV holes. In some embodiments, the bonding layer and the filling material layer are made of the same material.

[0050] In other embodiments, the bonding layer is formed on the support substrate or on both the support substrate and the circuit substrate. In some embodiments, the thickness of the support substrate without the bonding layer is in the range of about 200 μm to about 1.8 mm, and in other embodiments, in the range of about 500 μm to about 750 μm.

[0051] Next, a first hard mask layer is formed, and then a second hard mask layer is formed above the front end surface of the circuit substrate. In some embodiments, the first hard mask layer includes silicon oxide, and the second hard mask layer includes polysilicon or amorphous silicon. In some embodiments, the silicon oxide hard mask layer is formed by a CVD process, and then a planarization operation such as a CMP operation is performed. Similarly, in some embodiments, the polysilicon hard mask layer is formed by chemical vapor deposition (CVD), and then optionally a CMP operation is performed. In some embodiments, the thickness of the polysilicon hard mask layer is in the range of about 30 μm to about 70 μm.

[0052] Then, by using one or more lithography and etching operations, the second hard mask layer and the first hard mask layer are patterned to form one or more openings above the electrodes. In some embodiments, the size of the openings is larger than the size of the openings in the passivation layer formed above the electrodes. Further, in some embodiments, the insulating pattern is partially exposed in the openings.

[0053] Next, one or more conductive layers are formed in the openings. In some embodiments, the conductive layer includes gold or a gold alloy (e.g., AuCu and AuNi) formed by a plating operation (electroplating or electroless plating). In some embodiments, the thickness of the plated conductive layer is in the range of about 20 μm to about 50 μm. In some embodiments, the thickness (height) of the plated conductive layer is less than the top of the second hard mask layer.

[0054] In addition, a portion of the plating layer located above one or more electrodes is covered by a mask pattern. In some embodiments, the mask pattern includes a photoresist pattern. Then, an additional conductive layer is formed over the conductive plating layer. In some embodiments, the additional conductive layer is formed by a plating operation (electroplating or electroless plating). In some embodiments, the additional conductive layer is made of the same material as the plated conductive layer and includes gold or a gold alloy (e.g., AuCu, AuNi). In other embodiments, the additional conductive layer is made of a material different from the plated conductive layer. Then, the photoresist pattern is removed.

[0055] In some embodiments, the thickness of the additional conductive layer ranges from about 10 μm to about 30 μm. In some embodiments, the total thickness (height) of the plated conductive layer and the additional conductive layer is less than the top of the second hard mask layer.

[0056] Then, a second carrier bonding layer is formed over the front side of the circuit substrate, and then, the second carrier substrate is attached to the front side of the circuit substrate via the second carrier bonding layer. In some embodiments, the second carrier substrate is a glass substrate, a ceramic substrate, a semiconductor substrate, or a resin substrate. In some embodiments, the second carrier bonding layer includes an organic material, silicon oxide, or any other suitable material.

[0057] Then, the entire substrate is vertically flipped, and then the back side of the support substrate is patterned to form a groove. In some embodiments, the groove is formed by one or more lithography and etching operations using a mask pattern. In some embodiments, the mask pattern is made of photoresist.

[0058] In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the bonding layer is used as an etch stop layer for forming the groove. When the groove is formed using a plasma dry etching process, the plasma etching substantially stops at the bonding layer, and thus plasma damage to the electronic circuits formed in the circuit substrate can be prevented.

[0059] In some embodiments, after the groove etching stops at the bonding layer, the bonding layer is further etched by one or more dry etching or wet etching operations. In some embodiments, the etching of the bonding layer has a high selectivity with respect to the circuit substrate (e.g., Si). For example, the etching rate of the bonding layer is 10 times or more the etching rate of the circuit substrate. In some embodiments, when the bonding layer is made of silicon oxide, a wet etching process using HF or buffered HF is performed to inhibit damage to the electronic circuits formed in the circuit substrate. When the bonding layer is removed, when the filling material layer is made of the same material as the bonding layer (e.g., silicon oxide), the filling material layer in the TSV holes is also removed. When the filling material layer is made of a material different from the bonding layer (e.g., silicon nitride), additional etching operations such as wet etching operations are performed to remove the filling material layer.

[0060] After removing the filler material layer from the TSV holes, a second conductive layer is formed inside the grooves.

[0061] In some embodiments, the second conductive layer is formed to contact the first conductive layer formed on the inner wall of each TSV hole. In some embodiments, the second conductive layer is also formed on the inner wall of the TSV holes where the first conductive layer has been formed. In some embodiments, the second conductive layer is made of the same or different material as the first conductive layer and includes one or more layers of Au, Ti, Cu, Ag, and Ni. In certain embodiments, the gold layer formed above the Ti layer is used as the second conductive layer. In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 200 nm, and in other embodiments, from about 80 nm to about 120 nm. In some embodiments, the thickness of the gold (Au) layer ranges from about 10 nm to about 400 nm, and in other embodiments, from about 150 nm to about 250 nm.

[0062] In some embodiments, a plurality of MEMS devices are formed on an Si wafer, and the wafer is cut into individual MEMS devices (chips) by sawing (cutting operation) at the scribe lines. In some embodiments, the cutting operation does not completely cut the support for the second carrier bonding layer. By removing the second carrier bonding layer and thus the second carrier substrate, the individual MEMS devices are released. In some embodiments, the cutting operation is performed before forming the second conductive layer, and the second conductive layer is also formed at the sides of the MEMS devices.

[0063] In some embodiments, after removing the second carrier substrate and the second carrier bonding layer, the individual MEMS devices are attached to a frame. By removing the second carrier substrate and the second carrier bonding layer, the TSV holes are exposed.

[0064] In other embodiments, a silicon-on-insulator (SOI) wafer is used. In this case, the fusion bonding process is omitted, and the oxide layer of the SOI wafer serves as an etch stop layer in the recess etching. Figures 3A, Figure 3B , Figure 3C and Figure 3D show schematic cross-sectional views of the various stages of the manufacturing operations for MEMS devices according to embodiments of the present invention. It should be understood that additional operations can be provided before, during, and after the process shown in Figures 3A to 3D , and for additional embodiments of the method, some of the operations described below can be substituted or eliminated. The order of the operations / processes can be interchanged. The materials, configurations, dimensions, and processes described with respect to Figure 1A to Figure 2 can be applied to the following embodiments, and their detailed descriptions can be omitted.

[0065] As Figure 3A shown, the SOI substrate includes a device layer (semiconductor layer) 20', an oxide layer 40', and a bulk layer (semiconductor substrate) 30'.

[0066] As Figure 3A shown, a CMOS circuit 25 is formed in the front surface region of the device layer 20'. One or more passivation films 28 are formed above the front surface of the device layer 20'. In some embodiments, the one or more passivation films 28 include silicon oxide, silicon nitride, or an organic film. In some embodiments, holes 60 filled with a filling material 140 are formed to penetrate the device layer 20'. Further, as Figure 3A shown, one or more first conductive layers 50 are formed on the front side of the device layer and in the holes 60.

[0067] Then, as Figure 3B shown, the back side of the bulk layer 30' is recessed by using one or more lithography and etching operations. In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the wet etching utilizes tetramethylammonium hydroxide (TMAH) or a KOH solution.

[0068] In some embodiments, the oxide layer 40' serves as an etch stop layer for forming a groove 35 as Figure 3B shown.

[0069] After the groove etching stops at the oxide layer 40', the oxide layer 40' is further etched by one or more dry etching or wet etching operations. During the etching of the oxide layer 40', the filling material layer 140 is also removed from the holes 60, thereby forming vias 65, as Figure 3C shown.

[0070] In some embodiments, one or more second conductive layers 55 are formed on the back side of the bulk layer 30', as Figure 3D shown.

[0071] Figure 4A And Figure 4B shows a schematic cross-sectional view of a MEMS device according to an embodiment of the present invention. Regarding Figures 1A to 3D the materials, configurations, dimensions, and processes described above can be applied to the following embodiments, and their detailed descriptions can be omitted.

[0072] In some embodiments, as Figure 4A shown, no insulating layer (bonding layer) 40 is provided, and a single substrate 22 (e.g., a bulk silicon substrate) is used.

[0073] In some embodiments, as Figure 4BAs shown, the first conductive layer 50 and the second conductive layer 55 are made of the same material (e.g., a layer of the same metal or metallic material), and thus, at the overlapping region inside the via 65, no observable interface exists between the first conductive layer 50 and the second conductive layer 55.

[0074] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15, Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24A show schematic cross-sectional views and Figure 24B show plan views of the respective stages of the sequential manufacturing operations for a MEMS device according to an embodiment of the present invention. It should be understood that additional operations may be provided before, during, and after the process shown in Figures 5 to 24B , and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged. Regarding Figures 1A to 4B the materials, configurations, dimensions, and processes described may be applied to the following embodiments, and their detailed descriptions may be omitted.

[0075] Similar to Figure 1A , one or more electronic circuits 1025 are formed in the front surface region of the circuit substrate 1020, as Figure 5 shown. The electronic circuits 1025 include transistors, and the transistors include semiconductor field effect transistors such as complementary metal oxide semiconductor (CMOS) devices. In some embodiments, the circuit substrate 1020 is made of crystalline silicon or any other suitable semiconductor material.

[0076] As Figure 5 shown, after forming the electronic circuits 1025, one or more passivation films 1028 are formed over the front surface of the circuit substrate 1020. In some embodiments, the one or more passivation films 1028 include silicon oxide, silicon nitride, or an organic film. Then, similar to Figure 1B , one or more holes 1060 (e.g., TSVs) are formed in the circuit substrate 1020, as Figure 6As shown. In some embodiments, the hole 1060 is formed such that no metal pattern is exposed inside the hole. In some embodiments, the hole 1060 includes one or more first holes 1061 for TSV electrodes and one or more second holes 1062 for heat dissipation vias.

[0077] Then, similar to Figure 1C , a first conductive layer 1050 is formed above the front side of the circuit substrate 1020, as Figure 7 shown. In some embodiments, the first conductive layer 1050 is formed on the passivation film 1028. In some embodiments, the first conductive layer 1050 is also formed on at least a portion of the inner wall of each hole 1060, as Figure 7 shown. In some embodiments, the first conductive layer 1050 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the first conductive layer 1050 is a gold (Au) layer formed on a Ti layer. In other embodiments, the first conductive layer 1050 is composed of one, two, three, four, or five layers of materials different from each other. For example, in some embodiments, the first conductive layer 50 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (where A / B means B is on A), where each of A, B, C, D, and E represents a metal or a metallic material. In other embodiments, the first conductive layer 1050 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. In certain embodiments, the first conductive layer is a three-layer structure of Ti / Au / Ti.

[0078] In some embodiments, the first conductive layer 1050 is formed by CVD, PVD, ALD, plating, or any other suitable film deposition method. In certain embodiments, a sputtering method is used. In some embodiments, the thickness of each metal layer or metallic layer of the first conductive layer 1050 is in the range of about 2 nm to about 100 nm.

[0079] In some embodiments, the first conductive layer 1050 is conformally formed inside the hole 1060 such that the inner sidewall and the bottom of the hole 1060 are completely covered by the first conductive layer 1050. In other embodiments, only a portion of the inner sidewall and the bottom of the hole 1060 are covered by the first conductive layer 1050, and a portion of the circuit substrate (Si substrate) is exposed in the hole 1060. In particular, in some embodiments, the lower portion of the inner sidewall of the hole 1060 is not covered by the first conductive layer 1050. In some embodiments, the first conductive layer 1050 serves as a seed layer for electroplating in subsequent processes.

[0080] In some embodiments, as Figure 8As shown, a first mask layer 1110 is formed above the front side of the circuit substrate 1020. The first hard mask layer 1110 has one or more openings 1101 located above the first hole 1061. In some embodiments, the first mask layer 1110 is a photoresist layer.

[0081] Then, as Figure 9 shown, a third conductive layer 1200 is formed to fill the first hole 1061. In some embodiments, the third conductive layer 1200 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the third conductive layer 1200 is a copper (Cu) or Cu alloy layer. In other embodiments, the third conductive layer 1200 is composed of one, two, three, four, or five layers of materials different from each other. For example, in some embodiments, the third conductive layer 1200 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (where A / B means B is on A), where each of A, B, C, D, and E represents a metal or metallic material. In other embodiments, the third conductive layer 1200 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. In some embodiments, the third conductive layer 1200 is formed by electroplating using the first conductive layer 1050 as a seed layer. In some embodiments, as Figure 9 shown, the top of the third conductive layer 1200 is above the upper surface of the passivation layer 1028. In some embodiments, the third conductive layer 1200 serves as a TSV electrode. After forming the third conductive layer 1200, the first mask layer 1100 is removed.

[0082] Next, as Figure 10 shown, a second mask layer 1120 having one or more openings 1104 is formed above the front side of the circuit substrate 1020. In some embodiments, the second mask layer 1120 is a photoresist layer.

[0083] Then, as Figure 10As shown, a fourth conductive layer 1210 is formed to fill the first hole 1061. In some embodiments, the fourth conductive layer 1210 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the fourth conductive layer 1210 is a copper (Cu) or Cu alloy layer. In other embodiments, the fourth conductive layer 1210 is composed of one, two, three, four, or five layers of materials different from each other. For example, in some embodiments, the fourth conductive layer 1210 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (where A / B means B is on A), where each of A, B, C, D, and E represents a metal or metallic material. In other embodiments, the fourth conductive layer 1210 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. In some embodiments, the fourth conductive layer 1210 is formed by electroplating using the first conductive layer 1050 as a seed layer. In some embodiments, as Figure 10 shown, the fourth conductive layer 1210 is electrically connected to the electronic circuit 1025. In some embodiments, the fourth conductive layer 1210 serves as an under bump metal (UBM) layer. After the fourth conductive layer 1210 is formed, the second mask layer 1120 is removed.

[0084] Next, as Figure 11 shown, a third mask layer 1130 having one or more openings 1106 is formed over the front side of the circuit substrate 1020. In some embodiments, the third mask layer 1130 is a photoresist layer. As Figure 11 shown, the third mask layer 1130 covers the third conductive layer and the fourth conductive layer as well as the second hole, and unnecessary portions of the first conductive layer, the third conductive layer, and / or the fourth conductive layer are removed by one or more dry etching and / or wet etching operations. Through this etching operation, the conductive layers are appropriately isolated from each other. After the etching operation, the third mask layer 1130 is removed, as Figure 12 shown.

[0085] In some embodiments, as Figure 13 shown, a first bonding layer 1042 is formed over the front side of the circuit substrate 1020, and the dummy substrate 1032 is bonded to the circuit substrate 1020 via the first bonding layer 1042. In some embodiments, the first bonding layer 1042 is silicon oxide formed by, for example, CVD, PVD, or ALD processes. In some embodiments, the dummy substrate 1032 is a silicon substrate, a glass substrate, or a ceramic substrate. In some embodiments, after the dummy substrate 1032 is attached, the dummy substrate 1032 is thinned by appropriate etching and / or polishing processes.

[0086] Furthermore, as Figure 14As shown, the circuit substrate 20 is bonded to the support substrate 1030 via the second bonding layer 1040. In some embodiments, the second bonding layer 1040 is silicon oxide formed on the surface of the support substrate by, for example, a thermal oxidation process or a CVD process. In other embodiments, the second bonding layer 1040 is formed on the back side of the circuit substrate 1020 by, for example, a CVD process. In some embodiments, the thickness of the second bonding layer 1040 ranges from about 500 nm to about 5 μm, and in other embodiments, ranges from about 1 μm to about 2 μm.

[0087] In some embodiments, prior to attaching the support substrate 1030, similar to Figure 1E , the back side of the circuit substrate 1020 is thinned by a grinding or polishing process. In some embodiments, the remaining thickness of the thinned circuit substrate 1020 ranges from about 100 μm to about 500 μm. In some embodiments, the support substrate 1030 is attached to the back side of the circuit substrate 1020, and then the dummy substrate 1032 is attached to the front side of the circuit substrate 1020.

[0088] Then, the back side of the support substrate 30 is recessed to form a groove 1035 by using one or more lithography and etching operations, as Figure 15 shown. In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the wet etching utilizes a tetramethylammonium hydroxide (TMAH) or KOH solution.

[0089] In some embodiments, similar to Figure 1G , the second bonding layer 1040 serves as an etch stop layer for forming the groove 1035. Subsequently, the second bonding layer 1040 is removed by a suitable etching operation. Then, the back side of the circuit substrate 1020 is etched to expose the first and / or third conductive layers and the first bonding layer 1042, as shown in FIG. 15. In some embodiments, the etching of the circuit substrate 1020 stops at the first conductive layer 1050, and then the exposed first conductive layer 1050 is further etched to expose the third conductive layer 1200 and the first bonding layer 1042.

[0090] In addition, in some embodiments, as Figure 16 shown, the exposed first bonding layer 1042 is recessed upward by one or more dry and / or wet etching operations. In some embodiments, the recess amount D12 is the same as the coverage amount D2 shown in Figure 2B .

[0091] In some embodiments, similar to Figure 1I, a plurality of MEMS devices are formed on a wafer, and the wafer is diced (cutting operation) into individual MEMS devices (chips). In some embodiments, the cutting operation is performed before the trench etching for forming the trench 1035.

[0092] After the cutting operation, as Figure 17 shown, a second conductive layer 1055 is formed inside the trench 1035, at the bottom of the support substrate 1030, on the side surface of the chip, and inside the first hole 1061. In some embodiments, the second conductive layer 1055 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the second conductive layer 1055 is a gold (Au) layer formed on a Ti layer. In other embodiments, the second conductive layer 1055 is composed of one, two, three, four, or five layers of materials different from each other. For example, the second conductive layer 1055 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (A / B means B is on A), where each of A, B, C, D, and E represents a metal or a metallic material. In other embodiments, the second conductive layer 1055 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. For example, the second conductive layer 1055 has a layered structure of A / B / A / B, A / B / B / A, A / B, or A / A. In some embodiments, the film structure of the second conductive layer 1055 is the same as that of the first conductive layer 1050, and in other embodiments, the film structure of the second conductive layer 1055 is different from that of the first conductive layer 1050. In some embodiments, at least one metal layer of the first conductive layer 1050 is the same as at least one metal layer of the second conductive layer 1055.

[0093] In some embodiments, the second conductive layer 1055 is formed by CVD, PVD including sputtering, ALD, plating, or any other suitable film deposition method. In certain embodiments, the sputtering method is used. In some embodiments, the thickness of each metal layer or metallic layer of the second conductive layer 1055 is in the range of about 2 nm to about 100 nm. In some embodiments, the second conductive layer 1055 is conformally formed inside the first hole 1061, such that the inner sidewall of the first hole 1061, on which at least part of the first conductive layer 1050 is formed and exposed, is completely covered by the second conductive layer 1055. In other embodiments, the inner sidewall of the exposed first hole 1061 is only partially covered by the second conductive layer 1055, and part of the first conductive layer 1050 is exposed in the first hole 1061. Since the second conductive layer 1055 is formed after the cutting operation, the second conductive layer 1055 is formed on the side surface of the chip. In some embodiments, the second conductive layer 1055 serves as a seed layer for electroplating in subsequent processes.

[0094] Next, as Figure 18 shown, a fourth mask layer 1140 is formed over the back side of the circuit substrate 1020 in the recess, the fourth mask layer 1140 having one or more openings 1107 located over the second holes 1062 filled with the third conductive layer 1200. In some embodiments, the fourth mask layer 1140 is a photoresist layer. Then, as Figure 18 shown, a fifth conductive layer 1220 is formed at the bottom of the openings 1107 over the second conductive layer 1055. In some embodiments, the fifth conductive layer 1220 includes one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the fifth conductive layer 1220 is a copper (Cu) or Cu alloy layer. In other embodiments, the fifth conductive layer 1220 is composed of one, two, three, four, or five layers of materials different from each other. For example, in some embodiments, the fifth conductive layer 1220 has a layered structure of A / B / C / D / E, A / B / C / D, A / B / C, A / B, or A (where A / B means B is on A), where each of A, B, C, D, and E represents a metal or metallic material. In other embodiments, the fifth conductive layer 1220 is composed of two, three, four, or five layers, where adjacent layers are made of materials different from each other. In some embodiments, the fifth conductive layer 1220 is formed by electroplating using the second conductive layer 1055 as a seed layer. After forming the fifth conductive layer 1220, the fourth mask layer 1140 is removed.

[0095] Next, as Figure 19 shown, a fifth mask layer 1150 having one or more openings 1108 is formed over the back side of the circuit substrate 1020. In some embodiments, the fifth mask layer 1150 is a photoresist layer. As Figure 19 shown, the fifth mask layer 1150 covers the fifth conductive layer 1220 and the second holes, and unnecessary portions of the second and / or fifth conductive layers are removed by one or more dry etching operations and / or wet etching operations. By this etching operation, the conductive layers are appropriately isolated from each other. After the etching operation, as shown in FIG. 20, the fifth mask layer 1150 is removed.

[0096] In addition, in some embodiments, as Figure 21As shown, one or more semiconductor integrated circuits (ICs) are attached to the TSV electrodes 1200 via the bonding electrodes 1230 in the recess 1035. In some embodiments, the semiconductor IC includes a substrate, and one or more memory chips disposed laterally or vertically stacked on the substrate together with a control circuit. In other embodiments, the semiconductor IC includes a substrate, and various circuits such as driver circuits, logic circuits, or any other electronic circuits disposed laterally or vertically stacked on the substrate. In some embodiments, the semiconductor IC is entirely disposed in the recess 1035. In some embodiments, the IC is encapsulated, and in other embodiments, the IC is a bare chip without resin molding.

[0097] Then, as Figure 22 shown, the dummy substrate 1032 and the first bonding layer 1042 are removed. Further, in some embodiments, as Figure 23 shown, one or more semiconductor integrated circuits (ICs) are attached to the TSV electrodes 1200 via the bonding electrodes 1240 located at the front side of the circuit substrate 1020. In some embodiments, the semiconductor IC includes a substrate, and one or more processors (e.g., central processing unit, microprocessor unit, graphics processing unit (GPU), etc.) are disposed laterally or vertically stacked on the substrate. In other embodiments, the semiconductor IC includes a substrate, and various circuits such as driver circuits (e.g., power management IC (PMIC), logic circuits, or any other electronic circuits) are disposed laterally or vertically stacked on the substrate. In some embodiments, the IC is encapsulated, and in other embodiments, the IC is a bare chip without resin molding.

[0098] Further, in some embodiments, as Figure 24A shown, one or more heat sinks 1300 are disposed on the front side of the circuit substrate 1020. In some embodiments, the heat sink 1030 is in direct contact with the semiconductor IC or in contact with the semiconductor IC via one or more layers of heat transfer material and / or bonding material. In some embodiments, the heat sink 1300 is connected to the third conductive layer (UBM layer) 1210 via the bump electrodes 1250, as Figure 24A shown.

[0099] Figure 24B is not shown Figure 24A is a plan view (top view) of some layers / components of the MEMS device not shown. As Figure 24B shown, the heat dissipation holes 1061 (first holes) covered by the first conductive layer and the second conductive layer inside surround the semiconductor IC (IC-1 and IC-2, one or both of the ICs above the front side or the back side of the circuit substrate 1020).

[0100] In some embodiments, Figure 24Athe first conductive layer 1050 at region A2, the structure and configuration of the second conductive layer 1055 are the same as those of the first conductive layer 50 and the second conductive layer 55 shown in Figure 2B , Figure 2C and Figure 2D and the detailed description as described above is incorporated herein.

[0101] In other embodiments, the operations explained with respect to Figures 1K to 1P are also applied to Figures 5 to 24B embodiments.

[0102] In an embodiment of the present invention, in a MEMS device, since the first conductive layer and the second conductive layer are coupled to each other and partially or completely cover the inner sidewall of the through hole, it is possible to improve heat dissipation. In some embodiments, since the inner wall of the heat dissipation hole is continuously and completely covered by one or more conductive layers, the heat dissipation efficiency of the MEMS device can be improved.

[0103] As described above, the various embodiments or examples described herein provide several advantages over the prior art. It will be understood that not all advantages need to be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0104] According to one aspect of the present invention, a microelectromechanical system (MEMS) includes: a circuit substrate including an electronic circuit, a support substrate having a groove, a bonding layer disposed between the circuit substrate and the support substrate, a through hole passing through the circuit substrate to the groove, a first conductive layer disposed on the front side of the circuit substrate, and a second conductive layer disposed on the inner wall of the groove. The first conductive layer extends into the through hole, and the second conductive layer extends into the through hole and is coupled to the first conductive layer. In one or more of the foregoing and following embodiments, the bonding layer includes silicon oxide. In one or more of the foregoing and following embodiments, in the groove, no bonding layer is provided, and the bottom of the circuit substrate contacts the second conductive layer. In one or more of the foregoing and following embodiments, in the through hole, the second conductive layer overlaps the first conductive layer. In one or more of the foregoing and following embodiments, the second conductive layer continuously covers the bottom of the support substrate and at least partially covers the outer surface of the MEMS. In one or more of the foregoing and following embodiments, the second conductive layer completely covers the side surface of the bonding layer. In one or more of the foregoing and following embodiments, each of the first conductive layer and the second conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu or an alloy thereof. In one or more of the foregoing and following embodiments, the configuration of one or more layers of the first conductive layer is different from that of one or more layers of the second conductive layer. In one or more of the foregoing and following embodiments, the configuration of one or more layers of the first conductive layer is the same as that of one or more layers of the second conductive layer.

[0105] According to another aspect of the present invention, a MEMS includes: a circuit substrate including an electronic circuit, a passivation layer disposed above the circuit substrate, a support substrate having a groove, a through hole passing through the circuit substrate to the groove, and a conductive layer covering at least a part of the passivation layer, the inner sidewall of the through hole, the inner wall of the groove, and the side surface of the MEMS. In one or more of the foregoing and following embodiments, a part of the side surface of the MEMS is not covered by the conductive layer. In one or more of the foregoing and following embodiments, the conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu. In one or more of the foregoing and following embodiments, the entire conductive layer is made of one material. In one or more of the foregoing and following embodiments, the thickness of the conductive layer on the inner sidewall of the through hole is non-uniform. In one or more of the foregoing and following embodiments, the MEMS further includes an insulating layer disposed between the circuit substrate and the support substrate. In one or more of the foregoing and following embodiments, the circuit substrate and the support substrate are parts of a single substrate.

[0106] According to another aspect of the present invention, in a method of manufacturing a MEMS, an electronic circuit is formed above the front side of a first substrate, a hole is formed through the first substrate, a first conductive layer is formed above the front side of the first substrate and at least a part of the inner sidewall of the hole, the hole is filled with a filling material, the back side of the first substrate is thinned, a second substrate is bonded to the back side of the first substrate with a bonding layer inserted therebetween, a groove is formed in the second substrate to expose the bottom of the first substrate, a through hole is formed by removing the filling material, and a second conductive layer is formed on the inner wall of the groove and at least a part of the inner sidewall of the through hole not covered by the first conductive layer. In one or more of the foregoing and following embodiments, before forming the second conductive layer, a cutting process is performed to cut out the MEMS. In one or more of the foregoing and following embodiments, the second conductive layer is also formed on the cut side surface of the MEMS. In one or more of the foregoing and following embodiments, at least one of the first conductive layer and the second conductive layer is made by a sputtering process.

[0107] According to another aspect of the present invention, a semiconductor device includes: a circuit substrate including an electronic circuit, a support substrate having a groove, a bonding layer disposed between the circuit substrate and the support substrate, a through hole passing through the circuit substrate to the groove, the through hole being made of a conductive material and passing through the circuit substrate, a first conductive layer disposed on the front side of the circuit substrate, a second conductive layer disposed on the inner wall of the groove, a first semiconductor integrated circuit (IC) disposed on the front side of the circuit substrate and coupled to at least one through hole, and a second semiconductor IC disposed on the back side of the circuit substrate within the groove and coupled to at least one through hole. In one or more of the foregoing and following embodiments, the first conductive layer extends into the through hole, and the second conductive layer extends into the through hole and is coupled to the first conductive layer. In one or more of the foregoing and following embodiments, the bonding layer includes silicon oxide, and in the groove, no bonding layer is provided, and the bottom of the circuit substrate is in contact with the second conductive layer. In one or more of the foregoing and following embodiments, the second conductive layer overlaps the first conductive layer in the through hole. In one or more of the foregoing and following embodiments, the second conductive layer continuously covers the bottom of the support substrate and at least partially covers the outer side surface of the semiconductor device. In one or more of the foregoing and following embodiments, the second conductive layer completely covers the side surface of the bonding layer. In one or more of the foregoing and following embodiments, each of the first conductive layer and the second conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu or an alloy thereof. In one or more of the foregoing and following embodiments, the configuration of one or more layers of the first conductive layer is different from that of one or more layers of the second conductive layer. In one or more of the foregoing and following embodiments, the configuration of one or more layers of the first conductive layer is the same as that of one or more layers of the second conductive layer.

[0108] According to another aspect of the present invention, a semiconductor device includes: a circuit substrate including an electronic circuit, a passivation layer disposed above the circuit substrate, a support substrate having a groove, a through hole passing through the circuit substrate to the groove, the through hole being made of a conductive material and passing through the circuit substrate, a first semiconductor integrated circuit (IC) disposed on a front side of the circuit substrate and coupled to at least one through hole, a second semiconductor IC disposed on a back side of the circuit substrate within the groove and coupled to at least one through hole, and a conductive layer covering at least a portion of the passivation layer, an inner sidewall of the through hole, an inner wall of the groove, and a side surface of the semiconductor device. In one or more of the foregoing and following embodiments, a portion of the side surface of the semiconductor device is not covered by the conductive layer. In one or more of the foregoing and following embodiments, the conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu. In one or more of the foregoing and following embodiments, the entire conductive layer is made of one material. In one or more of the foregoing and following embodiments, the thickness of the conductive layer on the inner sidewall of the through hole is non-uniform. In one or more of the foregoing and following embodiments, the semiconductor device further includes an insulating layer disposed between the circuit substrate and the support substrate. In one or more of the foregoing and following embodiments, in a plan view, the through hole surrounds the first semiconductor IC.

[0109] According to another aspect of the present invention, a semiconductor device includes: a circuit substrate including an electronic circuit, a passivation layer disposed above the circuit substrate, a support substrate having a groove, a through hole passing through the circuit substrate to the groove, the through hole being made of a conductive material and passing through the circuit substrate, a first semiconductor integrated circuit (IC) disposed on a front side of the circuit substrate and coupled to at least one through hole, a heat sink coupled to the first semiconductor IC, and a conductive layer covering at least a portion of the passivation layer, an inner sidewall of the through hole, an inner wall of the recess, and a side surface of the semiconductor device. In one or more of the foregoing and following embodiments, when no semiconductor IC is inserted, the heat sink is coupled to the circuit substrate via one or more layers of a conductive layer. In one or more of the foregoing and following embodiments, the conductive material of the through hole includes one or more layers of copper or a copper alloy. In one or more of the foregoing and following embodiments, the through hole protrudes from an upper surface of the passivation layer.

[0110] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, an electronic circuit is formed on a front side of a first substrate, a first hole and a second hole are formed through the first substrate, a conductive layer is formed above the front side of the first substrate and on at least a part of inner walls of the first hole and the second hole, a through hole is formed by filling the second hole with a conductive material while covering the first hole, a second substrate is bonded to the front side of the first substrate with a first bonding layer interposed therebetween, a third substrate is bonded to the back side of the first substrate with a second bonding layer interposed therebetween, a groove is formed in the third substrate to expose a part of the first substrate, a first bonding material is recessed in the first hole, and a second conductive layer is formed on an inner wall of the groove and at least a part of an inner wall of the first hole. In one or more of the foregoing and following embodiments, a bottom electrode is formed on a bottom of the through hole in the groove, and one or more semiconductor integrated circuits (ICs) are attached to the bottom electrode. In one or more of the foregoing and following embodiments, an upper electrode is formed on a top of the through hole at the front side of the first substrate, and one or more first semiconductor integrated circuits (ICs) are attached to the upper electrode. In one or more of the foregoing and following embodiments, a heat sink is attached to one or more first semiconductor ICs and the first substrate.

[0111] Embodiments of the present application provide a microelectromechanical system (MEMS), including: a circuit substrate including an electronic circuit; a support substrate having a groove; a bonding layer disposed between the circuit substrate and the support substrate; a through hole passing through the circuit substrate to the groove; a first conductive layer disposed on a front side of the circuit substrate; and a second conductive layer disposed on an inner wall of the groove, wherein the first conductive layer extends into the through hole, and the second conductive layer extends into the through hole and is coupled to the first conductive layer. In some embodiments, the bonding layer includes silicon oxide. In some embodiments, in the groove, no bonding layer is provided, and a bottom of the circuit substrate contacts the second conductive layer. In some embodiments, in the through hole, the second conductive layer overlaps the first conductive layer. In some embodiments, the second conductive layer continuously covers a bottom of the support substrate and at least partially covers an outer surface of the microelectromechanical system. In some embodiments, the second conductive layer completely covers a side surface of the bonding layer. In some embodiments, each of the first conductive layer and the second conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu or an alloy thereof. In some embodiments, a configuration of one or more layers of the first conductive layer is different from a configuration of one or more layers of the second conductive layer. In some embodiments, a configuration of one or more layers of the first conductive layer is the same as a configuration of one or more layers of the second conductive layer.

[0112] Embodiments of the present application provide a microelectromechanical system (MEMS), including: a circuit substrate including an electronic circuit; a passivation layer disposed above the circuit substrate; a support substrate having a groove; a through-hole passing through the circuit substrate to the groove; and a conductive layer covering at least a portion of the passivation layer, the inner sidewall of the through-hole, the inner wall of the groove, and the side surface of the MEMS. In some embodiments, a portion of the side surface of the MEMS is not covered by the conductive layer. In some embodiments, the conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu. In some embodiments, the entire conductive layer is made of one material. In some embodiments, the thickness of the conductive layer on the inner sidewall of the through-hole is non-uniform. In some embodiments, an insulating layer is further disposed between the circuit substrate and the support substrate. In some embodiments, the circuit substrate and the support substrate are parts of a single substrate.

[0113] Embodiments of the present application further provide a method for manufacturing a microelectromechanical system (MEMS), including: forming an electronic circuit on the front side of a first substrate; forming a hole passing through the first substrate; forming a first conductive layer on at least a portion of the front side of the first substrate and the inner sidewall of the hole; filling the hole with a filling material; thinning the back side of the first substrate; bonding a second substrate to the back side of the first substrate through a bonding layer, the bonding layer being inserted between the second substrate and the first substrate; forming a groove in the second substrate to expose the bottom of the first substrate; forming a through-hole by removing the filling material; and forming a second conductive layer on the inner wall of the groove and at least a portion of the inner sidewall of the through-hole not covered by the first conductive layer. In some embodiments, the substrate has a plurality of MEMS formed thereon, and further includes, before forming the second conductive layer, performing a cutting process to separate the plurality of MEMS. In some embodiments, the second conductive layer is further formed on the side surface of one of the MEMS. In some embodiments, at least one of the first conductive layer and the second conductive layer is made by a sputtering process.

[0114] The features of several embodiments or examples are outlined above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A microelectromechanical system (MEMS), comprising: A circuit substrate including an electronic circuit; A support substrate having a groove; An adhesive layer disposed between the circuit substrate and the support substrate; A through-hole passing through the circuit substrate to the groove; A first conductive layer disposed on the front side of the circuit substrate and physically contacting the inner sidewall of the through-hole; And A second conductive layer disposed on the inner wall of the groove, Wherein the first conductive layer extends into the through-hole, and the second conductive layer extends into the through-hole and is coupled to the first conductive layer.

2. The microelectromechanical system according to claim 1, wherein, The adhesive layer includes silicon oxide.

3. The microelectromechanical system according to claim 2, wherein, In the groove, no adhesive layer is provided, and the bottom of the circuit substrate contacts the second conductive layer.

4. The microelectromechanical system according to claim 1, wherein, In the through-hole, the second conductive layer overlaps with the first conductive layer.

5. The microelectromechanical system according to claim 1, wherein, The second conductive layer continuously covers the bottom of the support substrate and at least partially covers the outer surface of the microelectromechanical system.

6. The microelectromechanical system according to claim 5, wherein, The second conductive layer completely covers the side surface of the adhesive layer.

7. The microelectromechanical system according to claim 1, wherein, Each of the first conductive layer and the second conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu or their alloys.

8. The microelectromechanical system according to claim 7, wherein, The configuration of one or more layers of the first conductive layer is different from that of one or more layers of the second conductive layer.

9. The microelectromechanical system according to claim 7, wherein, The configuration of one or more layers of the first conductive layer is the same as that of one or more layers of the second conductive layer.

10. A microelectromechanical system (MEMS), comprising: A circuit substrate including an electronic circuit; A passivation layer disposed above the circuit substrate; A support substrate having a groove; A through-hole passing through the circuit substrate to the groove; And A conductive layer covering at least part of the passivation layer, the inner sidewall of the through-hole, the inner wall of the groove, and the side surface of the microelectromechanical system, Wherein the conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer covers at least part of the passivation layer and the inner sidewall of the through-hole and physically contacts the inner sidewall of the through-hole, the second conductive layer covers part of the inner sidewall of the through-hole, the inner wall of the groove, and at least part of the side surface of the microelectromechanical system, and the second conductive layer is coupled to the first conductive layer.

11. The microelectromechanical system according to claim 10, wherein, The part of the side surface of the microelectromechanical system is not covered by the conductive layer.

12. The microelectromechanical system according to claim 10, wherein, The conductive layer includes one or more layers of Au, Ti, Ni, Ag, and Cu.

13. The microelectromechanical system according to claim 12, wherein, The entire conductive layer is made of one material.

14. The microelectromechanical system according to claim 10, wherein, The thickness of the conductive layer on the inner sidewall of the through-hole is not uniform.

15. The microelectromechanical system according to claim 10, further comprising an insulating layer disposed between the circuit substrate and the support substrate.

16. The microelectromechanical system according to claim 10, wherein, The circuit substrate and the support substrate are parts of a single substrate.

17. A method of manufacturing a microelectromechanical system (MEMS), comprising: Forming an electronic circuit on the front side of a first substrate; Forming a hole passing through the first substrate; Forming a first conductive layer on the front side of the first substrate above and at least part of the inner sidewall of the hole, the first conductive layer physically contacting the inner sidewall of the through-hole; Filling the hole with a filling material; Thinning the back side of the first substrate; Bond a second substrate to the back side of the first substrate through a bonding layer, the bonding layer being inserted between the second substrate and the first substrate; Form a groove in the second substrate to expose the bottom of the first substrate; Form a through hole by removing the filling material; And Form a second conductive layer on at least a portion of the inner wall of the groove and the inner side wall of the through hole that is not covered by the first conductive layer.

18. The method according to claim 17, wherein, The first substrate has a plurality of microelectromechanical systems formed thereon, and further includes, before forming the second conductive layer, performing a cutting process to space apart the plurality of microelectromechanical systems.

19. The method according to claim 18, wherein, The second conductive layer is also formed on a side surface of one of the microelectromechanical systems.

20. The method according to claim 18, wherein At least one of the first conductive layer and the second conductive layer is made by a sputtering process.

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