Startup method for network device and network device

Abstract

The embodiments of the present application relate to the field of computer network technologies and disclose a startup method for a network device and a network device. The specific solution is as follows: the main processor performs hardware initialization; the main processor obtains the status value of the coprocessor from the status register; when the status value indicates that the coprocessor is in the first state, the main processor executes a non-fast startup process, and the first state includes the state of not being started; when the status value indicates that the coprocessor is in the second state, after the main processor delays for a certain time, it obtains the status value of the coprocessor from the status register again; the second state includes the states during initialization, during the process of configuring the switching chip, or during abnormal operation; when the status value indicates that the coprocessor is in the third state, the main processor executes a fast startup process; the third state includes the state of having configured the switching chip. The embodiments of the present application can achieve the compatibility between the fast startup of the main processor software version and the non-fast startup hardware platform, facilitating system maintenance and management.

Description

Technical Field

[0001] The present invention relates to the technical field of computer networks, and particularly to a method for starting a network device and a network device. Background Art

[0002] The existing method for quickly starting a network device is implemented by a coprocessor responsible for configuring a switching chip, and after the main processor completes hardware initialization, synchronizing the switching chip configuration from the coprocessor. The coprocessor notifies the main processor that the switching chip configuration is completed by setting the pins of the general-purpose input / output port (GPIO, General Purpose Input Output) reserved between the main processor to pre-defined fixed values. The main processor queries that the GPIO is the pre-defined fixed value to determine that the coprocessor has finished execution and starts to synchronize the switching chip configuration from the coprocessor. The hardware initialization of the network device and the switching chip configuration adopt a fast startup method of parallel execution by two processors, which shortens the startup time of the switch. However, the software version of the main processor in this fast startup is not compatible with the non-fast startup hardware platform, which brings inconvenience to system maintenance and management. Summary of the Invention

[0003] In view of the above problems in the prior art, embodiments of the present application provide a method for starting a network device and a network device, which can achieve the compatibility between the software version of the main processor in fast startup and the non-fast startup hardware platform, and facilitate system maintenance and management.

[0004] To achieve the above object, a first aspect of the present application provides a method for starting a network device, including:

[0005] Performing hardware initialization by a main processor;

[0006] The main processor obtains the status value of the coprocessor recorded in the status register from the status register;

[0007] When the status value indicates that the coprocessor is in a first state, the main processor executes a non-fast startup process, and the first state includes a state of not being started;

[0008] When the status value indicates that the coprocessor is in a second state, after the main processor delays for a certain time, it obtains the status value of the coprocessor recorded in the status register from the status register again; the second state includes a state during initialization, a state during configuring a switching chip, or a state of running abnormally;

[0009] When the status value indicates that the coprocessor is in a third state, the main processor executes a fast startup process; the third state includes a state in which the switching chip has been configured.

[0010] As a possible implementation of the first aspect, the non - fast - start process includes: configuring the switching chip by the main processor.

[0011] As a possible implementation of the first aspect, the fast - start process includes: synchronizing the configuration of the switching chip from the coprocessor by the main processor.

[0012] As a possible implementation of the first aspect, the initial status value recorded by the status register is a status value indicating that the coprocessor is in the first state;

[0013] After the status register receives the signal indicating power - on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state;

[0014] After the status register receives the signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

[0015] As a possible implementation of the first aspect, the status register receiving the signal indicating power - on startup output by the coprocessor includes: the status register receiving a periodic square - wave signal indicating power - on startup output by the coprocessor through GPIO1; or

[0016] The status register receiving the signal indicating that the switching chip has been configured output by the coprocessor includes: the status register receiving a high - level signal indicating that the switching chip has been configured output by the coprocessor through GPIO2.

[0017] As a possible implementation of the first aspect, the implementation steps for the coprocessor to be in the third state include:

[0018] The coprocessor outputs a signal indicating power - on startup;

[0019] The coprocessor acquires the access right to the switching chip;

[0020] The coprocessor configures the switching chip according to the pre - stored configuration parameters;

[0021] The coprocessor releases the access right to the switching chip;

[0022] The coprocessor outputs a high - level signal indicating that the switching chip has been configured.

[0023] As a possible implementation of the first aspect, the above - mentioned method further includes:

[0024] When the status value of the coprocessor recorded in the status register is obtained again from the status register and the number of acquisition times exceeds a predetermined number, the main processor executes a non-fast startup process.

[0025] As a possible implementation manner of the first aspect, the above method further includes:

[0026] When the status value indicates that the coprocessor is in the first state, marking the version information of the startup program implementing the startup method of the network device as a non-fast startup version, or

[0027] When the status value indicates that the coprocessor is in the third state, marking the version information of the startup program implementing the startup method of the network device as a fast startup version.

[0028] As a possible implementation manner of the first aspect, the status register is the status register of the CPLD.

[0029] A second aspect of the present application provides a network device, including: a main processor, a coprocessor, a CPLD, and a switching chip, where the CPLD includes a status register;

[0030] The status register is used to record a status value, and the status value is used to represent the first state, the second state, or the third state of the coprocessor. The first state includes an unstarted state, the second state includes a state during startup, a state during configuring the switching chip, or a state of running abnormally, and the third state includes a state where the switching chip has been configured;

[0031] When the network device starts up, the main processor is used to perform hardware initialization and to obtain the status value of the coprocessor recorded in the status register from the status register;

[0032] When the status value indicates that the coprocessor is in the first state, the main processor is used to execute a non-fast startup process;

[0033] When the status value indicates that the coprocessor is in the second state, the main processor is used to delay for a certain time and then obtain the status value of the coprocessor recorded in the status register from the status register again;

[0034] When the status value indicates that the coprocessor is in the third state, the main processor is used to execute a fast startup process.

[0035] A third aspect of the present application provides a startup device for a network device, including:

[0036] An initialization unit, configured to perform hardware initialization by the main processor;

[0037] An acquisition unit for the main processor to acquire the status value of the coprocessor recorded in the status register from the status register;

[0038] An execution unit for the main processor to execute a non-fast startup process when the status value indicates that the coprocessor is in a first state, where the first state includes a non-started state;

[0039] The execution unit is further configured to: when the status value indicates that the coprocessor is in a second state, after the main processor delays for a certain time, acquire again from the status register the status value of the coprocessor recorded in the status register; the second state includes a state during initialization, a state during the process of configuring the switching chip, or a state of running exception;

[0040] The execution unit is further configured to: when the status value indicates that the coprocessor is in a third state, the main processor executes a fast startup process; the third state includes a state where the switching chip has been configured.

[0041] As a possible implementation manner of the third aspect, the non-fast startup process includes: the main processor configures the switching chip.

[0042] As a possible implementation manner of the third aspect, the fast startup process includes: the main processor synchronizes the configuration of the switching chip from the coprocessor.

[0043] As a possible implementation manner of the third aspect, the initial status value recorded in the status register is a status value indicating that the coprocessor is in the first state; the device further includes a recording unit, and the recording unit is configured to:

[0044] After the status register receives a signal indicating power-on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state;

[0045] After the status register receives a signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

[0046] As a possible implementation manner of the third aspect, the status register receiving a signal indicating power-on startup output by the coprocessor includes: the status register receiving a periodic square wave signal indicating power-on startup output by the coprocessor through GPIO1; or

[0047] The status register receiving a signal indicating that the switching chip has been configured output by the coprocessor includes: the status register receiving a high-level signal indicating that the switching chip has been configured output by the coprocessor through GPIO2.

[0048] As a possible implementation of the third aspect, the device further includes a configuration unit, and the configuration unit is used to configure the switching chip so that the coprocessor is in a third state, specifically used for:

[0049] The coprocessor outputs a signal indicating power-on startup;

[0050] The coprocessor obtains the access right to the switching chip;

[0051] The coprocessor configures the switching chip according to the pre-stored configuration parameters;

[0052] The coprocessor releases the access right to the switching chip;

[0053] The coprocessor outputs a high-level signal indicating that the switching chip is configured.

[0054] As a possible implementation of the third aspect, the execution unit is further used for:

[0055] The coprocessor state value recorded in the status register is obtained again from the status register. When the predetermined acquisition times are exceeded, the main processor executes a non-fast startup process.

[0056] As a possible implementation of the third aspect, the execution unit is further used for:

[0057] When the status value indicates that the coprocessor is in the first state, mark the version information of the startup program for implementing the startup method of the network device as a non-fast startup version, or

[0058] When the status value indicates that the coprocessor is in the third state, mark the version information of the startup program for implementing the startup method of the network device as a fast startup version.

[0059] As a possible implementation of the third aspect, the status register is the status register of the CPLD.

[0060] A fourth aspect of the present application provides a computing device, including:

[0061] A communication interface;

[0062] At least one processor, which is connected to the communication interface; and

[0063] At least one memory, which is connected to the processor and stores program instructions, and when the program instructions are executed by the at least one processor, the at least one processor is caused to execute the method according to any one of the first aspects above.

[0064] The fifth aspect of the present application provides a computer-readable storage medium, on which program instructions are stored, and when the program instructions are executed by a computer, the computer is caused to execute the method according to any one of the above first aspects.

[0065] These and other aspects of the present invention will become more apparent and understandable in the following description of the (one or more) embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The following further describes each feature of the present invention and the relationship between each feature with reference to the drawings. The drawings are all exemplary. Some features are not shown in actual proportions, and in some drawings, the features that are customary in the field related to the present application and are not necessary for the present application may be omitted, or features that are not necessary for the present application may be shown additionally. The combination of the features shown in the drawings is not used to limit the present application. In addition, throughout the present specification, the content referred to by the same reference numerals is also the same. The specific description of the drawings is as follows:

[0067] Figure 1 A schematic diagram of an embodiment of a method for starting a network device in the prior art;

[0068] Figure 2 A schematic diagram of an embodiment of a method for starting a network device provided by an embodiment of the present application;

[0069] Figure 3 A schematic diagram of a hardware principle of an embodiment of a method for starting a network device provided by an embodiment of the present application;

[0070] Figure 4 A processing flowchart of an embodiment of a method for starting a network device provided by an embodiment of the present application;

[0071] Figure 5 A schematic diagram of an embodiment of a device for starting a network device provided by an embodiment of the present application;

[0072] Figure 6 A schematic diagram of an embodiment of a device for starting a network device provided by an embodiment of the present application;

[0073] Figure 7 A schematic diagram of a computing device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0074] The terms "first", "second", "third", etc. or module A, module B, module C, etc. in the description and claims are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that, where permitted, the specific order or sequence can be interchanged so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0075] In the following description, the reference numerals of the steps involved, such as S110, S120... etc., do not necessarily mean that the steps will be executed in this order. The order of the steps before and after can be interchanged, or they can be executed simultaneously, if permitted.

[0076] The term "comprising" as used in the specification and claims should not be construed as being limited to the content listed thereafter; it does not exclude other elements or steps. Therefore, it should be construed as specifying the presence of the stated features, wholes, steps or components, but not excluding the presence or addition of one or more other features, wholes, steps or components and their groups. Thus, the expression "a device comprising device A and B" should not be limited to a device consisting only of components A and B.

[0077] As used herein, the term "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the various specific features, structures, or characteristics can be combined in any suitable manner, as will be apparent to those of ordinary skill in the art from this disclosure.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. In case of inconsistency, the meaning set forth in this specification or the meaning derived from the content recorded in this specification shall prevail. Additionally, the terms used herein are for the purpose of describing embodiments of this application only and are not intended to limit this application. For the purpose of accurately describing the technical content in this application and for accurately understanding the present invention, the following explanations or definitions of the terms used in this specification are given before describing the specific embodiments:

[0079] 1) General Purpose Input Output (GPIO): Each GPIO pin can be individually configured as an input or output through software. For an input, the potential level of the pin can be determined by reading a certain register; for an output, the pin can be made to output a high or low potential by writing to a certain register.

[0080] 2) Complex Programmable Logic Device (CPLD): A CPLD is a digital integrated circuit that allows users to construct logic functions according to their respective needs. Its basic design method is to generate corresponding target files by means of an integrated development software platform, using schematic diagrams, hardware description languages, etc., and then transfer the code to the target chip through a download cable ("in-system" programming) to implement the designed digital system. A CPLD mainly consists of three parts: logic blocks, programmable interconnect channels, and input / output (I / O) blocks.

[0081] 3) Coprocessor: A chip used to relieve the system microprocessor of specific processing tasks. A coprocessor is a processor developed and applied to assist the central processing unit in completing processing tasks that it cannot execute or can execute with low efficiency or poor effectiveness.

[0082] 4) Universal Asynchronous Receiver / Transmitter (UART): A UART is a general-purpose serial data bus used for asynchronous communication. This bus enables two-way communication and can achieve full-duplex transmission and reception. The UART converts the data to be transmitted between serial communication and parallel communication. As a chip that converts parallel input signals into serial output signals, the UART is usually integrated into other communication interfaces. Or the physical entity of the UART can also be represented as an independent modular chip or as a peripheral device integrated into a microprocessor.

[0083] 5) Serial Peripheral Interface (SPI): SPI is a high-speed and efficient serial interface technology, usually consisting of a master module and one or more slave modules. The master module selects a slave module for synchronous communication to complete data exchange. Usually, SPI is a ring structure and requires at least four wires for communication. SPI is a synchronous serial data link operating in full-duplex mode. It can be used to transfer data between a single master controller and one or more slave devices.

[0084] First, the existing methods will be introduced below, and then the technical solutions of this application will be introduced in detail.

[0085] The existing method for rapid startup of network devices is achieved by having a coprocessor responsible for configuring the switching chip and the main processor synchronizing the switching chip configuration from the coprocessor after completing hardware initialization. For example Figure 1As shown in the figure, the coprocessor notifies the main processor that the configuration of the switching chip is completed by setting the pins of the General Purpose Input Output (GPIO) reserved between the coprocessor and the main processor to predefined fixed values. The main processor queries that the GPIO is the predefined fixed value to determine that the coprocessor has finished execution, and then starts to synchronize the switching chip configuration from the coprocessor. The hardware initialization of the network device and the configuration of the switching chip are executed in parallel by the two processors in a fast startup mode, which shortens the startup time of the switch.

[0086] The prior art has the following defects: The existing fast startup method is that the main processor synchronizes the switching chip configuration from the coprocessor. For products without the fast startup function, the coprocessor can be not soldered on the hardware board. Then the above existing fast startup main processor software version is not applicable to products without the fast startup function. This fast startup main processor software version is not compatible with the non-fast startup hardware platform, which brings inconvenience to system maintenance and management.

[0087] Based on the technical problems existing in the above prior art, the present application provides a method for starting up a network device. In this method, the main processor first obtains the status value of the coprocessor recorded in the status register, and determines whether to execute the fast startup process or the non-fast startup process according to the status value of the coprocessor. For products without the fast startup function, the non-fast startup process can be determined according to the default status value of the coprocessor, thus solving the technical problem that the fast startup main processor software version in the prior art is not compatible with the non-fast startup hardware platform.

[0088] Figure 2 It is a schematic diagram of an embodiment of the method for starting up a network device provided by an embodiment of the present application. As Figure 2 shown, the method for starting up the network device may include:

[0089] Step S110, the main processor performs hardware initialization;

[0090] Step S120, the main processor obtains the status value of the coprocessor recorded in the status register from the status register;

[0091] Step S130, when the status value indicates that the coprocessor is in the first state, the main processor executes the non-fast startup process, and the first state includes the unstarted state;

[0092] Step S140, when the status value indicates that the coprocessor is in the second state, after the main processor delays for a certain time, it obtains the status value of the coprocessor recorded in the status register from the status register again; the second state includes the state during initialization, the state during configuring the switching chip, or the state of abnormal operation;

[0093] In step S150, when the status value indicates that the coprocessor is in the third state, the main processor executes a fast startup process; the third state includes the state where the switching chip has been configured.

[0094] A network device is a physical entity connected to a network. Basic network devices may include: switches, hubs, bridges, computers (personal computers or servers), etc. With the development of Internet and communication device software and hardware technologies, the startup time of network devices is getting shorter and shorter. Especially for core network devices such as switches, after the device is powered on, it starts up in a short time and enters normal data communication, enabling data services to be quickly restored and forwarded, and a network with high real-time performance and high stability can be achieved. The embodiments of the present application can implement a fast startup method for the main processor to synchronize the switching chip configuration from the coprocessor in products with a fast startup function, and at the same time have good compatibility with products without a fast startup function.

[0095] In step S110, first, the main processor performs board-level hardware initialization of the network device. In step S120, after the main processor of the network device starts up, it obtains the status value of the coprocessor by querying the status register. Among them, the initial status value recorded in the status register is the status value indicating that the coprocessor is in the first state; after the coprocessor starts up and outputs a signal indicating power-on startup to the status register, the status value recorded in the status register is updated to the status value indicating that the coprocessor is in the second state; after the coprocessor has configured the switching chip and outputs a signal indicating that the switching chip has been configured to the status register, the status value recorded in the status register is updated to the status value indicating that the coprocessor is in the third state.

[0096] The first state may include the state where the coprocessor is not started, and its corresponding status value is also the default status value of the status register. If the coprocessor is in the state of not being powered on and started, or the coprocessor is not soldered on the hardware board, the status value of the status register is the default status value, that is, the status value indicating that the coprocessor is in the first state. In step S130, when the status value indicates that the coprocessor is in the first state, in this case, the coprocessor is not started or does not exist, and the main processor executes a non-fast startup process.

[0097] The second state may include the state during the co - processor initialization process, the process of configuring the switching chip, or the state of running abnormally. After the co - processor is powered on and started, and before the co - processor has finished configuring the switching chip, the status value of the status register is the status value indicating that the co - processor is in the second state. In step S140, when the status value indicates that the co - processor is in the second state, it can wait for a certain period of time and then turn to execute step S120 to obtain again the status value of the co - processor recorded in the status register from the status register. Subsequent steps are executed according to the status value obtained again. When the number of times of obtaining the status value exceeds the predetermined number of acquisitions, the main processor can execute the non - fast - startup process.

[0098] The third state may include the state where the co - processor has finished configuring the switching chip. In step S150, when the status value indicates that the co - processor is in the third state, the main processor executes the fast - startup process.

[0099] Using the startup method of the network device provided by the embodiments of the present application, in a non - fast - startup hardware platform, the co - processor may not be soldered on the hardware board. In this case, the non - fast - startup process can be executed. On the other hand, the fast - startup process can be executed when the co - processor is powered on and started and has finished configuring the switching chip. The embodiments of the present application can achieve the compatibility between the fast - startup main - processor software version and the non - fast - startup hardware platform, which is convenient for system maintenance and management.

[0100] In one implementation, the non - fast - startup process includes: configuring the switching chip by the main processor.

[0101] In one implementation, the fast - startup process includes: synchronizing the configuration of the switching chip from the co - processor by the main processor.

[0102] Figure 3 This is the hardware schematic diagram of an embodiment of the startup method of the network device provided by the embodiments of the present application. As Figure 3 shown, the non - fast - startup process includes: the main processor reads the configuration parameters of the switching chip from its own flash memory FLASH, and configures the switching chip through the CPLD using the configuration parameters. The fast - startup process includes: the co - processor reads the configuration parameters of the switching chip from its own flash memory, and configures the switching chip through the CPLD using the configuration parameters. Then the main processor synchronizes the configuration of the switching chip from the co - processor.

[0103] In one implementation, the status register is the status register of the CPLD.

[0104] See Figure 3, a Complex Programmable Logic Device (CPLD) is connected to a main processor, a coprocessor, and a switching chip respectively through a Serial Peripheral Interface (SPI). The main processor and the coprocessor are connected through a Universal Asynchronous Receiver / Transmitter (UART). A status register is set in the CPLD.

[0105] In one example, the non-fast startup process may include: after the UART is powered on, through a human-computer interaction method, configure parameters of the switching chip in the command line of the switch, and store the configure parameters of the switching chip in the flash memory of the main processor. The main processor reads the configure parameters of the switching chip from the flash memory and configures the switching chip through the CPLD using the configure parameters.

[0106] In one implementation, the initial status value recorded by the status register is a status value indicating that the coprocessor is in a first state;

[0107] After the status register receives a signal indicating power-on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in a second state;

[0108] After the status register receives a signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in a third state.

[0109] In one implementation, the signal indicating power-on startup received by the status register from the coprocessor includes: the status register receives a periodic square wave signal indicating power-on startup output by the coprocessor through GPIO1; or

[0110] The signal indicating that the switching chip has been configured received by the status register from the coprocessor includes: the status register receives a high-level signal indicating that the switching chip has been configured output by the coprocessor through GPIO2.

[0111] See Figure 3, the current state of the coprocessor can be mapped to the coprocessor status register of the CPLD. In one example, the status value of the default coprocessor status register is 0. The status value of 0 is used to identify that the coprocessor is in an unstarted state. After the coprocessor is started, a periodic pulse square wave signal is output to the CPLD through the GPIO1 pin to notify the CPLD of the powered-on and started state of the coprocessor. After receiving this pulse, the CPLD sets the status value of the coprocessor status register to 1. The status value of 1 is used to identify that the coprocessor is in a powered-on and started state. After the coprocessor is powered on and started, it performs the operations of initializing and configuring the switching chip. From the time when the coprocessor is powered on and started until the process of configuring the switching chip has not been completed, the status value of the coprocessor status register is always 1. After the coprocessor configures the switching chip, it outputs a high-level signal indicating that the switching chip has been configured through GPIO2, and notifies the CPLD that the coprocessor has configured the switching chip through the high-level signal. After receiving this signal, the CPLD sets the status value of the coprocessor status register to 2. The status value of 2 is used to identify the state that the coprocessor has configured the switching chip.

[0112] In the embodiments of the present application, the CPLD chip is used to implement the state interaction between the coprocessor and the main processor, so as to achieve the compatibility between the main processor software version with fast startup and the non-fast startup hardware platform. For products without the fast startup function, the coprocessor can be not soldered on the hardware board; for products with the fast startup function, only the coprocessor software version needs to be soldered and burned on the hardware board. The embodiments of the present application achieve the compatibility between the main processor software version with fast startup and the non-fast startup hardware platform, which is convenient for the maintenance of software code and the unified management of software and hardware platforms.

[0113] The main processor determines the current state of the coprocessor by reading the coprocessor status register of the CPLD. If the status value of the coprocessor status register is 0 and the coprocessor is in an unstarted state, the non-fast startup process is executed; if the status value of the coprocessor status register is 1 and the coprocessor is in a powered-on and started state and has not configured the switching chip, indicating that the coprocessor is not initialized or operates abnormally, the main processor delays for a certain time and then queries the status value of the coprocessor status register again; if the status value of the coprocessor status register is 2 and the coprocessor is in a state where the switching chip has been configured, the fast startup process is executed.

[0114] In the embodiments of the present application, the coprocessor feeds back the current state to the coprocessor status register in the CPLD, and the main processor obtains the current state of the coprocessor by querying the status value of the coprocessor recorded in the CPLD, which enhances the compatibility of the software and hardware platforms.

[0115] In one implementation manner, the implementation steps for the coprocessor to be in the third state include:

[0116] The coprocessor outputs a signal indicating power-on startup;

[0117] The coprocessor obtains access rights to the switching chip;

[0118] The coprocessor configures the switching chip according to pre-stored configuration parameters;

[0119] The coprocessor releases the access rights to the switching chip;

[0120] The coprocessor outputs a high-level signal indicating that the switching chip has been configured.

[0121] See Figure 3 , usually the access rights to the switching chip belong to the main processor by default. In the fast startup process, the coprocessor applies to the CPLD to obtain access rights to the switching chip. After obtaining the access rights, the coprocessor configures the switching chip according to the configuration parameters pre-stored in the flash memory. After the configuration is completed, the coprocessor releases the access rights to the switching chip. The access rights to the switching chip belong to the main processor again. After the coprocessor configures the switching chip, it outputs a high-level signal indicating that the switching chip has been configured to the CPLD. After receiving this signal, the CPLD sets the status value of the coprocessor status register to the status value indicating that the coprocessor is in the third state.

[0122] In one embodiment, the above method further includes:

[0123] When the status value of the coprocessor recorded in the status register is obtained again, and when the predetermined number of acquisition times is exceeded, the main processor executes a non-fast startup process.

[0124] When the coprocessor is in the second state, the main processor delays for a certain time and then obtains the status value of the coprocessor again. If the coprocessor is still in the second state after the status value of the coprocessor has been obtained from the status register multiple times, in this case, the coprocessor may be operating abnormally, and the main processor executes a non-fast startup process.

[0125] In one embodiment, the above method further includes:

[0126] When the status value indicates that the coprocessor is in the first state, mark the version information of the startup program that implements the startup method of the network device as a non-fast startup version, or

[0127] When the status value indicates that the coprocessor is in the third state, mark the version information of the startup program that implements the startup method of the network device as a fast startup version.

[0128] As described above, in the non-fast startup process, the main processor configures the switching chip, and in the fast startup process, the main processor synchronizes the configuration of the switching chip from the coprocessor. In comparison, when the above two different startup processes are executed, the relevant configuration parameters are stored in different memories after startup. Therefore, after startup, it is necessary to mark the version information of the startup program so that in the subsequent execution of various service-related programs and data interaction processes, the relevant configuration parameters can be obtained from the corresponding memory according to the version information mark of the startup program.

[0129] When the status value of the coprocessor indicates that the coprocessor is in the first state, the main processor executes the non-fast startup process; or, when the status value of the coprocessor recorded in the status register is obtained again from the status register and exceeds the predetermined acquisition times, the main processor executes the non-fast startup process. When the main processor executes the non-fast startup process, the version information of the startup program implementing the startup method of the network device is marked as the non-fast startup version.

[0130] When the status value of the coprocessor indicates that the coprocessor is in the third state, the main processor executes the fast startup process. When the main processor executes the fast startup process, the version information of the startup program implementing the startup method of the network device is marked as the fast startup version.

[0131] Figure 4 This is a processing flowchart of an embodiment of the startup method of the network device provided by the embodiment of the present application. Figure 4 The processing flows of each processor during the startup process of the switch are shown in the example. As Figure 4 shown, according to the operating conditions of the coprocessor, three coprocessor states are defined to identify different operating stages of the coprocessor. The three coprocessor states are: the unstarted state, the startup state, and the state where the switching chip has been configured. Among them, the startup state includes the state where the coprocessor is in the initialization process, the switching chip configuration process, or the abnormal operation state, that is, the coprocessor is in the powered-on startup state and the switching chip has not been configured completely.

[0132] As Figure 4As shown, the processing flow of the CPLD during startup is shown in steps S210 to S230, and the processing flow of the coprocessor during startup is shown in steps S410 to S460. In step S210, when the CPLD starts up, the status register in the CPLD is default set to the state where the coprocessor has not started. In step S410, after the coprocessor starts up, it outputs a periodic square wave signal through the GPIO1 pin. In step S220, after the CPLD detects the square wave signal of the coprocessor, it sets the status register of the coprocessor to the startup state. In steps S420 to S450, the coprocessor acquires the access right to the switching chip, and then after configuring the switching chip according to the pre-saved switch startup parameters, it releases the access right to the switching chip. In step S460, the coprocessor outputs a high level through the GPIO2 pin to notify the CPLD that the switching chip has been configured. In step S230, the CPLD receives the signal that the switching chip has been configured output from the GPIO2 pin, and sets the status register of the coprocessor to the state where the switching chip has been configured.

[0133] As Figure 4 shown, the processing flow of the main processor during startup is shown in steps S310 to S350. In step S310, after the main processor starts up, it first performs board-level hardware initialization. Since the CPLD and the coprocessor start up relatively fast, when the main processor completes the board-level hardware initialization, the CPLD and the coprocessor usually have already started up. In step S320, the main processor queries the status register of the coprocessor in the CPLD. In step S330, if the coprocessor is in the state of not started, the non-fast startup process is executed. In step S340, if the coprocessor is in the startup state, it delays for a certain time and then queries the status of the coprocessor again. If it is still in the startup state after the second query, the access right ownership of the switching chip is forcibly switched to the main processor by writing the CPLD register, and the non-fast startup process is executed, and the main processor configures the switching chip; otherwise, if the coprocessor is not in the startup state but in the state where the switching chip has been configured when queried again, the fast startup process is executed. In step S350, if the coprocessor is in the state where the switching chip has been configured, the fast startup process is executed.

[0134] In the embodiment of the present application, for products with non-fast startup, there is no need to solder the coprocessor. In this case, the status register of the coprocessor maintains the default value when powered on, that is, it remains in the default state of not started. When the main processor queries that the status of the coprocessor is not started, the non-fast startup process is executed. By adopting the startup method of the network device provided by the embodiment of the present application, the main processor software version is applicable to both fast startup products and non-fast startup products, so as to achieve the compatibility between the fast startup main processor software version and the non-fast startup hardware platform.

[0135] See Figures 2 to 4 , on the other hand, this application provides a network device, including: a main processor, a coprocessor, a CPLD, and a switching chip, and the CPLD includes a status register;

[0136] The status register is used to record a status value, and the status value is used to represent a first status, a second status, or a third status of the coprocessor. The first status includes a non-started status, the second status includes a status during startup, a status during configuring the switching chip, or a status of abnormal operation, and the third status includes a status of having configured the switching chip;

[0137] When the network device starts up, the main processor is used to perform hardware initialization and to obtain the status value of the coprocessor recorded in the status register from the status register;

[0138] When the status value represents that the coprocessor is in the first status, the main processor is used to execute a non-fast startup process;

[0139] When the status value represents that the coprocessor is in the second status, the main processor is used to delay for a certain time and then obtain the status value of the coprocessor recorded in the status register from the status register again;

[0140] When the status value represents that the coprocessor is in the third status, the main processor is used to execute a fast startup process.

[0141] Regarding the beneficial effects or technical problems solved by this network device, reference can be made to the description in the above-mentioned startup method of the network device or the description in the summary of the invention, and details will not be repeated here.

[0142] As Figure 5 shown, this application also provides an embodiment of a startup device for a corresponding network device. Regarding the beneficial effects or technical problems solved by this device, reference can be made to the description in the methods corresponding to each device or the description in the summary of the invention, and details will not be repeated here.

[0143] In the embodiment of the startup device for this network device, the device includes:

[0144] An initialization unit 100, configured to perform hardware initialization by the main processor;

[0145] An acquisition unit 200, configured to obtain, by the main processor, the status value of the coprocessor recorded in the status register from the status register;

[0146] The execution unit 300 is configured to, when the status value indicates that the coprocessor is in the first state, the main processor executes a non-fast startup process, where the first state includes a state of not being started;

[0147] The execution unit 300 is further configured to: when the status value indicates that the coprocessor is in the second state, after the main processor delays for a certain time, the main processor obtains again the status value of the coprocessor recorded in the status register; the second state includes a state during initialization, a state during the process of configuring the switching chip, or a state of running abnormally;

[0148] The execution unit 300 is further configured to: when the status value indicates that the coprocessor is in the third state, the main processor executes a fast startup process; the third state includes a state where the switching chip has been configured.

[0149] In one embodiment, the non-fast startup process includes: the main processor configures the switching chip.

[0150] In one embodiment, the fast startup process includes: the main processor synchronizes the configuration of the switching chip from the coprocessor.

[0151] As Figure 6 shown, in one embodiment, the initial status value recorded in the status register is a status value indicating that the coprocessor is in the first state; the device further includes a recording unit 400, and the recording unit 400 is configured to:

[0152] After the status register receives a signal indicating power-on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state;

[0153] After the status register receives a signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

[0154] In one embodiment, the status register receiving a signal indicating power-on startup output by the coprocessor includes: the status register receiving a periodic square wave signal indicating power-on startup output by the coprocessor through GPIO1; or

[0155] The status register receiving a signal indicating that the switching chip has been configured output by the coprocessor includes: the status register receiving a high-level signal indicating that the switching chip has been configured output by the coprocessor through GPIO2.

[0156] In one embodiment, the device further includes a configuration unit 500, which is configured to configure the switching chip so that the coprocessor is in the third state. Specifically, it is used for:

[0157] The coprocessor outputs a signal indicating power-on startup;

[0158] The coprocessor obtains the access right to the switching chip;

[0159] The coprocessor configures the switching chip according to pre-stored configuration parameters;

[0160] The coprocessor releases the access right to the switching chip;

[0161] The coprocessor outputs a high-level signal indicating that the switching chip has been configured.

[0162] In one embodiment, the execution unit 300 is further configured to:

[0163] The coprocessor state value recorded in the status register is obtained again from the status register. When the predetermined number of acquisition times is exceeded, the main processor executes a non-fast startup process.

[0164] In one embodiment, the execution unit 300 is further configured to:

[0165] When the status value indicates that the coprocessor is in the first state, mark the version information of the startup program implementing the startup method of the network device as a non-fast startup version, or

[0166] When the status value indicates that the coprocessor is in the third state, mark the version information of the startup program implementing the startup method of the network device as a fast startup version.

[0167] In one embodiment, the status register is the status register of the CPLD.

[0168] Figure 7 It is a structural schematic diagram of a computing device 900 provided by an embodiment of the present application. The computing device 900 includes: a processor 910, a memory 920, and a communication interface 930.

[0169] It should be understood that Figure 7 The communication interface 930 in the computing device 900 shown in can be used for communication with other devices.

[0170] Among them, the processor 910 can be connected to the memory 920. The memory 920 can be used to store the program code and data. Therefore, the memory 920 can be a storage unit inside the processor 910, an external storage unit independent of the processor 910, or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910.

[0171] Optionally, the computing device 900 may further include a bus. Among them, the memory 920 and the communication interface 930 can be connected to the processor 910 through the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0172] It should be understood that in the embodiments of the present application, the processor 910 can adopt a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Or the processor 910 adopts one or more integrated circuits to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0173] The memory 920 can include a read-only memory and a random access memory, and provide instructions and data to the processor 910. A part of the processor 910 can also include a non-volatile random access memory. For example, the processor 910 can also store information about the device type.

[0174] When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform the operation steps of the above method.

[0175] It should be understood that the computing device 900 according to the embodiments of the present application may correspond to the corresponding entity that executes the methods according to the embodiments of the present application, and the above and other operations and / or functions of each module in the computing device 900 respectively implement the corresponding processes of the methods in each of the present embodiments. For the sake of brevity, they will not be described in detail here.

[0176] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0177] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be described in detail here.

[0178] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0179] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

[0180] In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0181] When the above functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0182] The embodiments of this application also provide a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it is used to execute a diversified problem generation method, and this method includes at least one of the solutions described in the above various embodiments.

[0183] The computer storage medium of the embodiments of this application can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device.

[0184] The computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0185] The program code contained on a computer-readable medium can be transmitted with any appropriate medium, including but not limited to wireless, wire, optical fiber cable, RF, etc., or any suitable combination of the above.

[0186] The computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0187] Note that the above is only the preferred embodiment of this application and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although this application has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, all of which fall within the protection scope of the present invention.

Claims

1. A method for starting a network device, characterized in that, Including: The main processor performs hardware initialization; The main processor obtains the status value of the coprocessor recorded in the status register from the status register; When the status value indicates that the coprocessor is in the first state, the main processor executes a non - fast startup process, and the first state includes a state of not started or non - existent; When the status value indicates that the coprocessor is in the second state, after a certain delay by the main processor, the main processor obtains again the status value of the coprocessor recorded in the status register; the second state includes a state during initialization, during the process of configuring the switching chip, or a state of running abnormally; When the status value indicates that the coprocessor is in the third state, the main processor executes a fast startup process; the third state includes a state where the switching chip has been configured; Among them, the initial status value recorded in the status register is a status value indicating that the coprocessor is in the first state; After the status register receives a signal indicating power - on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state; After the status register receives a signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

2. The method according to claim 1, wherein The non - fast startup process includes: the main processor configures the switching chip; The fast startup process includes: the main processor synchronizes the configuration of the switching chip from the coprocessor.

3. The method according to claim 1, wherein The status register receiving a signal indicating power - on startup output by the coprocessor includes: the status register receiving a periodic square - wave signal indicating power - on startup output by the coprocessor through GPIO1; or The status register receiving a signal indicating that the switching chip has been configured output by the coprocessor includes: the status register receiving a high - level signal indicating that the switching chip has been configured output by the coprocessor through GPIO2.

4. The method according to claim 1 or 3, characterized in that, The implementation steps for the coprocessor to be in the third state include: The coprocessor outputs a signal indicating power - on startup; The coprocessor obtains the access right to the switching chip; The coprocessor configures the switching chip according to pre - stored configuration parameters; The coprocessor releases the access right to the switching chip; The coprocessor outputs a high - level signal indicating that the switching chip has been configured.

5. The method according to claim 1, characterized in that The method further includes: When obtaining again the status value of the coprocessor recorded in the status register exceeds a predetermined number of acquisition times, the main processor executes a non - fast startup process.

6. The method according to claim 1, wherein The method further includes: When the status value indicates that the coprocessor is in the first state, marking the version information of the startup program for implementing the startup method of the network device as a non - fast startup version, or When the status value indicates that the coprocessor is in the third state, marking the version information of the startup program for implementing the startup method of the network device as a fast startup version.

7. The method according to claim 1, characterized in that The status register is the status register of the CPLD.

8. A startup device for a network device, the device comprising: An initialization unit for performing hardware initialization by a main processor; An acquisition unit for the main processor to acquire the status value of a coprocessor recorded in the status register from the status register; An execution unit for the main processor to execute a non-fast startup process when the status value indicates that the coprocessor is in a first state, the first state including a state of not started or non-existent; The execution unit is further configured to: when the status value indicates that the coprocessor is in a second state, after the main processor delays for a certain time, acquire again the status value of the coprocessor recorded in the status register; the second state includes a state during initialization, a state during configuring a switching chip, or a state of abnormal operation; The execution unit is further configured to: when the status value indicates that the coprocessor is in a third state, the main processor executes a fast startup process; the third state includes a state where the switching chip has been configured; Wherein, the initial status value recorded in the status register is a status value indicating that the coprocessor is in the first state; After the status register receives a signal indicating power-on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state; After the status register receives a signal indicating that the switching chip has been configured output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

9. A network device, characterized in that, Comprising: A main processor, a coprocessor, a CPLD, and a switching chip, the CPLD includes a status register; The status register is used to record a status value, and the status value is used to represent the first state, the second state, or the third state of the coprocessor. The first state includes a state of not started or non-existent, the second state includes a state during startup, a state during configuring a switching chip, or a state of abnormal operation, and the third state includes a state where the switching chip has been configured; When the network device starts up, the main processor is used to perform hardware initialization and to acquire the status value of the coprocessor recorded in the status register from the status register; When the status value indicates that the coprocessor is in the first state, the main processor is used to execute a non-fast startup process; When the status value indicates that the coprocessor is in the second state, the main processor is used to delay for a certain time and then acquire again the status value of the coprocessor recorded in the status register; When the status value indicates that the coprocessor is in the third state, the main processor is used to execute a fast startup process; Wherein, the initial status value recorded in the status register is a status value indicating that the coprocessor is in the first state; After the status register receives a signal indicating power-on startup output by the coprocessor, the recorded status value is updated to a status value indicating that the coprocessor is in the second state; After the status register receives the signal output by the coprocessor indicating that the switching chip has been configured, the recorded status value is updated to a status value indicating that the coprocessor is in the third state.

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