Gate Driver and Electroluminescent Display Device Using the Same

Abstract

Provided is a gate driver and an electroluminescent display device using the gate driver. The electroluminescent display device includes: a light emitting line (EL); a sub-pixel connected to the EL; and a light emitting driver that provides a light emitting signal to the EL and includes a plurality of stages, wherein the k-th stage of the plurality of stages includes: a first output node (O1) connected to the EL; a second output node (O2); a Q node; a pull-down circuit and a pull-up circuit that are controlled by the Q node and the O2 node respectively and provide a voltage to the O1 node; a first controller that receives the voltage of the O1 node of the (k-1)-th stage or a first start signal; a second controller that receives the voltage of the O2 node of the (k-1)-th stage or a second start signal; a third controller that controls the voltage of the O2 node; and a fourth controller that is controlled by the O2 node, where k is a natural number greater than or equal to 1.

Description

[0001] This application is a divisional application of the invention patent application with the application date of July 23, 2019, the application number of 201910665667.6, and the invention title of "Gate Driver and Electroluminescent Display Device Using the Same". Technical Field

[0002] The present invention relates to a gate driver and an electroluminescent display device using the gate driver, and more particularly, to a gate driver having improved driving ability and an electroluminescent display device using the gate driver. Background Art

[0003] With the progress of information technology, the market for display devices as a connection medium between users and information has increased. Accordingly, the use of various types of display devices such as electroluminescent display devices, liquid crystal display (LCD) devices, organic light emitting diode (OLED) devices, and quantum dot light emitting diode (QLED) devices has increased.

[0004] In a display device, an electroluminescent display device has advantages of fast response speed, high luminous efficiency, and wide viewing angle. Generally, an electroluminescent display device applies a data voltage to the gate of a driving transistor by using a transistor turned on by a scanning signal, and charges the data voltage supplied to the driving transistor into a storage capacitor. The electroluminescent display device causes a light emitting diode to emit light by using a light emission control signal to output the data voltage charged in the storage capacitor. The light emitting diode may include an organic light emitting diode and an inorganic light emitting diode.

[0005] A gate signal and a data signal are supplied to the electroluminescent display device, and the gate signal includes a scanning signal and a light emission signal. The electroluminescent display device is driven by using the light emission signal and one or more scanning signals. Generally, a gate driver that generates a scanning signal may include a shift register for sequentially outputting gate signals.

[0006] A display panel as a basic device for displaying an image may be divided into a display area where a pixel array is arranged and an image is displayed, and a non-display area where an image is not displayed. The gate driver is attached to the display panel in the form of a chip on film (COF) or a chip on glass (COG), or is implemented in the form of an in-panel gate (GIP) formed by combining thin film transistors in a border area that is a non-display area of the display panel. The GIP type gate driver includes stages corresponding to the number of gate lines, and each stage outputs a gate pulse supplied to the gate line, and the stages correspond to the gate lines one-to-one. The gate lines supply gate signals to the pixel array arranged in the display area to cause the light emitting diodes to emit light. Accordingly, a method for improving the driving ability and reliability of the gate driver to transmit accurate signals to the pixel array has been studied.

[0007] As described above, a light emission signal and one or more scan signals are used to drive an electroluminescent display device. To drive the electroluminescent display device, a scan signal for scanning data signals and a light emission signal for pausing light emission of light emitting diodes are required.

[0008] The operation margin (e.g., operation range) is reduced due to an increase in the load of a clock signal and a light emission signal corresponding to a high resolution of a display panel, and defects in a light emission driving circuit may occur. Moreover, a GIP type gate driver increases the size of a border area of the electroluminescent display device. SUMMARY OF THE INVENTION

[0009] Accordingly, an aspect of the present invention is to provide a gate driver and an electroluminescent display device using the gate driver, which substantially overcome one or more problems caused by limitations and disadvantages of the related art.

[0010] An aspect of the present invention is to provide a gate driver and a display device using the gate driver, in which a size of a border area of a display panel may be reduced.

[0011] Additional features and aspects of the present invention will be set forth in the description below, will be apparent in part from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of the structures specifically pointed out in the written description or derivatives thereof and claims and the drawings.

[0012] To achieve these and other aspects of the inventive concept, as embodied and generally described herein, there is provided an electroluminescent display device including: a light emission line; sub-pixels connected to the light emission line; and a light emission driver configured to provide a light emission signal to the light emission line and including a plurality of stages, wherein a k-th stage of the plurality of stages includes: a first output node connected to the light emission line; a second output node; a Q node; a pull-down circuit and a pull-up circuit controlled by the Q node and the second output node, respectively, and configured to provide a voltage to the first output node; a first controller configured to receive a voltage of the first output node of the (k-1)-th stage of the plurality of stages or a first start signal; a second controller configured to receive a voltage of the second output node of the (k-1)-th stage of the plurality of stages or a second start signal; a third controller configured to control a voltage of the second output node; and a fourth controller controlled by the second output node, where k is a natural number of 1 or greater. Accordingly, an operation margin of elements constituting a stage may be increased, and reliability of the gate driver may be improved. In addition, an area reserved by a stage may be reduced, thereby reducing the size of the border area.

[0013] According to another aspect of the present invention, there is provided a gate driver, comprising: a plurality of stages, wherein the k-th stage of the plurality of stages includes: a first output node; a second output node; a pull-down transistor and a pull-up transistor configured to control the first output node; a controller configured to control the second output node; and an output signal stabilizer, wherein k is a natural number of 1 or greater, wherein the controller includes: a T3 transistor configured to be controlled by a Q node; a T4 transistor configured to be controlled by a first clock signal; a T5 transistor configured to be controlled by a QB node; and a first capacitor, the first capacitor including a first electrode connected to the QB node and a second electrode connected to the second output node, wherein the output signal stabilizer is connected to the Q node and the second output node, and wherein voltages applied to the first output node and the second output node are applied as start signals of the (k + 1)-th stage. Accordingly, the operation margin of elements constituting the stages can be increased, and the reliability of the gate driver can be improved. In addition, the area reserved by the stages can be reduced, thereby reducing the border area.

[0014] According to another aspect of the present invention, there is provided an electroluminescent display device, comprising: a display panel including a display area and a non-display area; scan lines in the display area and the non-display area; a scan driver configured to provide scan signals to the scan lines in the non-display area; light-emitting lines in the display area and the non-display area; sub-pixels that are connected in a row direction in the display area to a light-emitting line connected to a gate of a light-emitting transistor that is turned on during a light-emitting period and to a scan line connected to a gate of a scan transistor that is turned off during the light-emitting period; a light-emitting driver configured to provide light-emitting signals to the light-emitting lines adjacent to the scan driver in the non-display area, the light-emitting driver including a plurality of stages, wherein the k-th stage of the plurality of stages includes: a first output node connected to the light-emitting line; a Q node, an O2 node, and a QB node in the non-display area; a pull-down circuit controlled by the Q node and configured to provide a conduction voltage to the first output node, the (k + 1)-th stage, and the light-emitting lines in the display area; a pull-up circuit controlled by the O2 node and configured to provide a cut-off voltage to the first output node, the (k + 1)-th stage, and the light-emitting lines in the display area; a first controller controlled by a first clock signal and configured to provide a voltage of the first output node of the (k - 1)-th stage to the Q node; a second controller controlled by a second clock signal and configured to control the QB node; a third controller configured to charge or discharge the O2 node and control the pull-up circuit by using the QB node; and a fourth controller configured to stabilize the voltage of the Q node, wherein k is a natural number of 1 or greater.

[0015] After studying the accompanying drawings and the detailed description, other systems, methods, features and advantages will be or will become apparent to those of ordinary skill in the art. All such additional systems, methods, features and advantages are intended to be covered in this specification, fall within the scope of the present invention, and are protected by the appended claims. Nothing in this section shall be construed as a limitation on the claims. Further aspects and advantages will be discussed below in connection with embodiments of the present invention. It will be understood that the foregoing general description of the present invention and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings, which are included to provide a further understanding of the present invention and constitute a part of this application, illustrate embodiments of the present invention and, together with the description, serve to explain the various principles of the present invention, wherein:

[0017] Figure 1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention;

[0018] Figure 2 is a block diagram showing a gate driver according to an exemplary embodiment of the present invention;

[0019] Figure 3 is a block diagram showing a stage according to an exemplary embodiment of the present invention;

[0020] Figure 4 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention;

[0021] Figure 5 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention;

[0022] Figure 6 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention;

[0023] Figure 7 is a waveform diagram showing the driving of a stage according to an exemplary embodiment of the present invention.

[0024] Throughout the drawings and the detailed description, unless otherwise indicated, the same reference numerals should be understood to refer to the same elements, features and structures. For clarity, illustration and convenience purposes, the relative dimensions and illustrations of these elements may be exaggerated. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Reference will now be made in detail to embodiments of the present invention, some examples of which are illustrated in the accompanying drawings. In the following description, when it is determined that a detailed description of a well-known function or configuration involved herein will unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted. The processes of processing steps and / or operations are described as examples, but the order of the steps and / or operations is not limited to that described herein and may be changed as known in the art, unless the steps and / or operations must occur in a specific order. Like reference numerals throughout the drawings denote like elements. The names of the respective elements used in the following description are merely selected for convenience in writing the specification and may thus be different from the names in actual products.

[0026] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0027] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" refers to all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0028] When describing an embodiment, when a structure is described as being "on or above" or "under or below" another structure, such a description should be interpreted to include the case where these structures are in contact with each other and the case where a third structure is provided therebetween. The dimensions and thicknesses of each element shown in the drawings are only given for convenience of description, and the embodiments of the present invention are not limited thereto.

[0029] The terms "first horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted only based on the set relationship in which the corresponding directions are strictly perpendicular to each other, but may refer to directions having a wider directivity within the range in which the components of the present invention are functionally operable.

[0030] The features of the various embodiments of the present invention can be partially or wholly combined or combined with each other and can be operated with each other in various ways and be technically driven, as can be fully understood by those skilled in the art. The embodiments of the present invention can be executed independently of each other or can be executed together in a mutually dependent relationship.

[0031] In the present invention, the gate driver on the substrate of the display panel can be implemented with n-type or p-type transistors. For example, the transistor can be implemented with a transistor having a metal oxide semiconductor field effect transistor (MOSFET) structure. The transistor can be a three-electrode device including a gate, a source, and a drain. The source can supply carriers to the transistor. In the transistor, the carriers can start to move from the source. The drain can be the electrode through which the carriers move from the transistor to the outside.

[0032] For example, in the transistor, the carriers can move from the source to the drain. In an n-type transistor, since the carriers are electrons, the voltage of the source is lower than the voltage of the drain, causing the electrons to move from the source to the drain. In an n-type transistor, since the electrons move from the source to the drain, the current moves from the drain to the source. In a p-type transistor, since the carriers are holes, the voltage of the source is higher than the voltage of the drain, causing the holes to move from the source to the drain. In a p-type transistor, since the holes move from the source to the drain, the current moves from the source to the drain. The source and drain of the transistor can be not fixed and can be switched according to the applied voltage. Therefore, the source and drain can be respectively referred to as the "first electrode" and the "second electrode" or the "second electrode" and the "first electrode".

[0033] Hereinafter, the gate-on voltage can be the voltage of the gate signal for turning on the transistor. The gate-off voltage can be the voltage for turning off the transistor. For example, in a p-type transistor, the gate-on voltage can be a logic low voltage VL, and the gate-off voltage can be a logic high voltage VH. In an n-type transistor, the gate-on voltage can be a logic high voltage, and the gate-off voltage can be a logic low voltage. Hereinafter, the gate driver according to the present invention and the electroluminescent display device using the gate driver will be described with reference to the drawings.

[0034] The inventors of the present invention recognized the above problems and invented a gate driver and an electroluminescent display device using the gate driver, in which the gate driver can be arranged in a small area and the operation margin (e.g., the operation range) and reliability are improved.

[0035] Hereinafter, the gate driver according to an embodiment of the present invention and the electroluminescent display device using the gate driver will be described in detail with reference to the drawings.

[0036] Figure 1 is a block diagram showing an electroluminescent display device according to an exemplary embodiment of the present invention.

[0037] Refer to Figure 1, the electroluminescent display device 100 may include an image processor 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply unit 180. The image processor 110 may output drive signals for driving various devices together with externally provided image data. The drive signals output from the image processor 110 may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0038] The timing controller 120 may receive image data, drive signals, etc. from the image processor 110. The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and a data signal DATA having luminance information of an image to be displayed on the display panel 150 based on the drive signals.

[0039] The gate driver 130 may output scan signals in response to the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may output gate signals through gate lines GL1 to GLn. The gate driver 130 may be provided in the form of an IC (integrated circuit), or may be provided in the form of a gate-in-panel (GIP) built in the display panel 150. The gate driver 130 may be arranged on each of the left and right sides of the display panel 150, or may be arranged on one of the left and right sides, but the embodiments are not limited to these arrangements. The gate driver 130 may include a plurality of stages. For example, the first stage of the gate driver 130 may output a first gate signal to be applied to the first gate line of the display panel 150.

[0040] The data driver 140 may output data voltages in response to the data timing control signal DDC provided from the timing controller 120. The data driver 140 may sample and latch the digital data signal DATA provided from the timing controller 120, and may convert the digital data signal DATA into an analog data signal based on a gamma reference voltage. The data driver 140 may output data signals through data lines DL1 to DLm. The data driver 140 may be provided on the display panel 150 in the form of an IC (integrated circuit), or may be provided on the display panel 150 in the form of a chip-on-film (COF).

[0041] The power supply unit 180 can output a high-potential power supply voltage VDD and a low-potential power supply voltage VSS. The high-potential power supply voltage VDD and the low-potential power supply voltage VSS output from the power supply unit 180 can be supplied to the display panel 150. The high-potential power supply voltage VDD can be supplied to the display panel 150 through a high-potential power line, and the low-potential power supply voltage VSS can be supplied to the display panel 150 through a low-potential power line. The voltage output from the power supply unit 180 can be used by the gate driver 130 or the data driver 140.

[0042] The display panel 150 can display an image in response to a gate signal and a data signal respectively provided from the gate driver 130 and the data driver 140 and a power supply voltage provided from the power supply unit 180. The display panel 150 can include a pixel array for displaying an image, and the pixel array can include a plurality of sub-pixels SP.

[0043] The display panel 150 can include: a display area DA in which the sub-pixels SP can be arranged; and a non-display area in which various signal lines or pads can be formed outside the display area DA. Since the display area DA is the area for displaying an image, the sub-pixels SP can be in the display area. Since the non-display area is the area where no image is displayed, the sub-pixels SP can not be in the non-display area, but virtual pixels can be arranged therein. Moreover, the gate driver 130 and the data driver 140 can be in the non-display area.

[0044] The display area DA can include a plurality of sub-pixels SP, and can display an image based on the gray scale displayed by each sub-pixel SP. Each sub-pixel SP can be connected to a data line DL arranged along a column line, and can be connected to a gate line arranged along a pixel row or a row line. The sub-pixels SP on the same pixel row can be simultaneously driven while sharing the same gate line. When the sub-pixel SP connected to the first gate line is defined as the first sub-pixel and the sub-pixel SP connected to the nth gate line is defined as the nth sub-pixel, the first sub-pixel to the nth sub-pixel can be sequentially driven.

[0045] The sub-pixels SP can be arranged in a matrix form to constitute a pixel array, but the implementation is not limited to this case. For example, in addition to the matrix form, the sub-pixels SP can be arranged in various forms, such as the form of shared sub-pixels SP, the stripe form, and the diamond form.

[0046] The sub-pixels SP can include red sub-pixels, green sub-pixels, and blue sub-pixels, or can include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels. According to the light-emitting characteristics, the sub-pixels SP can have one or more different light-emitting regions.

[0047] Figure 2It is a block diagram showing a gate driver according to an exemplary embodiment of the present invention.

[0048] For example, Figure 2 A gate driver according to an exemplary embodiment of the present invention and a pixel row to which a signal output from the gate driver can be applied are shown. As described above, the display panel 150 may include: a display area DA where an image can be displayed based on sub-pixels SP; and a non-display area NDA where signal lines or drivers can be provided and no image can be displayed.

[0049] The sub-pixel may include a light-emitting diode and a pixel driving circuit for controlling the amount of current applied to the anode of the light-emitting diode. The pixel driving circuit may include a driving transistor for controlling the amount of current so that a certain current flows to the light-emitting diode. The light-emitting diode may emit light during a light-emitting period and may not emit light during another period. For periods other than the light-emitting period, the pixel driving circuit may be activated, a scan signal may be input to the pixel driving circuit, and a programming and pixel driving circuit compensation period may be executed. For example, the compensation of the pixel driving circuit may be the compensation of the threshold voltage of the driving transistor. Since the current that allows the light-emitting diode to emit light at a specific brightness is not uniformly provided during periods other than the light-emitting period, the light-emitting diode may not emit light. For example, as a method of not allowing the light-emitting diode to emit light, a light-emitting transistor may be connected between the anode of the light-emitting diode and the driving transistor. The light-emitting transistor may be connected to a light-emitting line and may be controlled by a light-emitting signal output from a light-emitting driver. For the light-emitting period, the light-emitting signal may be a conduction voltage, and for periods other than the light-emitting period, the light-emitting signal may be a cut-off voltage.

[0050] The gate signal for driving the sub-pixels SP included in the display panel 150 may include a scan signal and a light-emitting signal. Therefore, the gate driver 130 may separately include a driving part for applying the scan signal and a driving part for applying the light-emitting signal. The scan signal may be applied to the sub-pixels SP through scan lines, and the light-emitting signal may be applied to the sub-pixels through light-emitting lines.

[0051] Figure 2 The gate driver 130 may only show the driving part for applying the light-emitting signal. The gate driver 130 according to the present invention may include a first stage EM(1) to an nth stage EM(n). In Figure 2 this, the kth stage EM(k) will be described as an example. In this case, k is a natural number and 1 < k ≤ n.

[0052] The gate driver 130 may include a plurality of lines, and a first clock signal CLK1, a second clock signal CLK2, a low voltage VL, a high voltage VH, and a start voltage VST input to the k-th stage EM(k) may be applied to the plurality of lines respectively. For example, the low voltage VL may be -8V to -7V, and the light-emitting high voltage VH may be 7V to 8V. The k-th stage EM(k) may provide a light-emitting signal to the k-th pixel row H(k), while shifting the start voltage VST to correspond to the first clock signal CLK1 and the second clock signal CLK2. For example, the start voltage VST may be input to the first stage EM(1), and the second stage EM(2) to the n-th stage EM(n) may operate by receiving the light-emitting signal output from their respective previous stages as a start signal. For example, the first output signal OUT1 of the k-th stage EM(k) may be input to the start signal of the (k + 1)-th stage EM(k + 1) and the k-th pixel row H(k). The (k + 1)-th stage EM(k + 1) may provide a light-emitting signal to the (k + 1)-th pixel row H(k + 1). The second output signal OUT2 of the k-th stage EM(k) may be input to the start signal of the (k + 1)-th stage EM(k + 1). The (k + 1)-th stage EM(k + 1) may use the two signals output from the k-th stage EM(k) as start signals, may reduce the area reserved by the stage to reduce the border area, and may increase the operation margin (e.g., operation range) of the elements included in the stage. Similarly, the (k + 2)-th stage EM(k + 2) may use the two signals output from the (k + 1)-th stage EM(k + 1) as start signals. The (k + 2)-th stage EM(k + 2) may provide a light-emitting signal to the (k + 2)-th pixel row H(k + 2).

[0053] The first clock signal CLK1 and the second clock signal CLK2 may swing between a high voltage and a low voltage, and may have opposite phases to each other. For example, although the first clock signal CLK1 and the second clock signal CLK2 may have opposite phases to each other, there may be a difference in the clock periods between them. For example, the clock period of the first clock signal CLK1 may be longer than the clock period of the second clock signal CLK2. Figure 2 It shows (but the embodiment is not limited thereto) a two-phase circuit of the first clock signal CLK1 and the second clock signal CLK2 input to the gate driver 130.

[0054] Figure 3 is a block diagram showing a stage according to an exemplary embodiment of the present invention.

[0055] In Figure 3 it, the k-th stage EM(k) constituting the gate driver 130 will be described as an example. In this case, the stage may be a light-emitting stage. Refer to Figure 3, the k-th stage EM(k) may include a pull-down unit (e.g., a circuit) 11, a pull-up unit (e.g., a circuit) 12, a Q-node controller 13, a QB-node controller 14, an O2-node controller 15, and an output signal stabilizer 16.

[0056] The pull-down unit 11 may output a first output signal OUT1 in response to the voltage of the Q-node Q. The pull-up unit 12 may control the first output signal OUT1 through a cut-off voltage in response to the voltage of the O2-node O2. The first output signal OUT1 may be applied to the O1-node O1 and the k-th pixel row. The O2-node will be described later. The Q-node may be referred to as the "first node", the O2-node may be referred to as the "second node", and the O1-node may be referred to as the "third node".

[0057] The Q-node controller 13 may be an element for charging or discharging the Q-node Q, and may apply a conduction voltage to the Q-node Q by using the first output signal OUT1(k - 1) of the (k - 1)-th stage EM(k - 1) as a starting signal. The (k - 1)-th stage EM(k - 1) may provide a light-emitting signal to the (k - 1)-th pixel row H(k - 1). The Q-node controller 13 may be referred to as the "first controller".

[0058] The QB-node controller 14 may be an element for charging or discharging the QB-node QB, and may apply a conduction voltage to the QB-node QB by using the second output signal OUT2(k - 1) of the (k - 1)-th stage EM(k - 1) as a starting signal. The QB-node controller 14 may be referred to as the "second controller".

[0059] The O2-node controller 15 may be an element for charging or discharging the O2-node O2, and may receive the signal applied to the QB-node QB and output the signal to the O2-node O2. The O2-node controller 15 may output a conduction voltage to the O2-node O2 when the Q-node Q is at a cut-off voltage, and may output a cut-off voltage to the O2-node O2 when the Q-node Q is at a conduction voltage. If the voltage of the Q-node Q is a low voltage, the O2-node controller 15 may keep the voltage of the O2-node O2 at a high voltage. The O2-node controller 15 may be referred to as the "third controller".

[0060] The output signal stabilizer 16 may stabilize the first output signal OUT1 by keeping the voltage of the Q-node Q at a high voltage according to the voltage of the O2-node O2. The output signal stabilizer 16 may be referred to as the "fourth controller".

[0061] As described above, the cut-off voltage may vary depending on the type of transistor to which the cut-off voltage can be applied. In the case of a p-type transistor, the cut-off voltage may be a high voltage; while in the case of an n-type transistor, the cut-off voltage may be a low voltage. In the case of a p-type transistor, the turn-on voltage is a low voltage; while in the case of an n-type transistor, the turn-on voltage is a high voltage. Hereinafter, the k-th stage EM(k) included in a p-type transistor will be described as an example.

[0062] Figure 4 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention.

[0063] Figure 4 is Figure 3 a detailed circuit diagram of an example of a block diagram of, and will be described with reference to Figure 4 the k-th stage EM(k) constituting the gate driver 130 as an example. Referring to Figure 4 , the k-th stage EM(k) may include a pull-down unit 11, a pull-up unit 12, a Q node controller 13, a QB node controller 14, an O2 node controller 15, and an output signal stabilizer 16.

[0064] The Q node controller 13 may include a first transistor T1. The gate of the first transistor T1 may be connected to a first clock signal line to which a first clock signal CLK1 can be input, the source of the first transistor T1 may be connected to the first output node of the (k-1)-th stage, and the drain of the first transistor T1 may be connected to the Q node Q. The first transistor T1 may be turned on by the turn-on voltage of the first clock signal CLK1 to provide the first output signal OUT1(k-1) of the (k-1)-th stage to the Q node Q.

[0065] The QB node controller 14 may include a second transistor T2. The gate of the second transistor T2 may be connected to a second clock signal line to which a second clock signal CLK2 is input, the source of the second transistor T2 may be connected to the second output node of the (k-1)-th stage, and the drain of the second transistor T2 may be connected to the QB node QB. The second transistor T2 may be turned on by the turn-on voltage of the second clock signal CLK2 to provide the second output signal OUT2(k-1) of the (k-1)-th stage to the QB node QB.

[0066] The O2 node controller 15 may include a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be connected in series with each other. The drain of the third transistor T3 may be connected to the drain of the fourth transistor T4, and the source of the fourth transistor T4 may be connected to the source of the fifth transistor T5. The gate of the third transistor T3 may be connected to the gate of the first transistor T1, the gate of the fourth transistor T4 may be connected to the first clock signal line, and the gate of the fifth transistor T5 may be connected to the QB node QB. The source of the third transistor T3 may be connected to the high voltage line to which the high voltage VH is input, and the source of the fifth transistor T5 is connected to the low voltage line to which the low voltage VL may be input.

[0067] When the voltage of the first clock signal CLK1 and the QB node QB is the conduction voltage, the low voltage VL may be applied to the O2 node O2. The voltage applied to the O2 node O2 may become the start signal of the (k + 1)th stage. For example, the fifth transistor T5, which may be subjected to higher stress than other transistors, may be connected to the first capacitor and may be a double-gate transistor, which can improve the reliability of the fifth transistor T5.

[0068] The O2 node controller 15 may further include a first capacitor C1. The first electrode of the first capacitor C1 may be connected to the O2 node O2, and the second electrode of the first capacitor C1 may be connected to the QB node QB. When the low voltage VL is applied to the O2 node O2, the first capacitor C1 may cause the voltage of the QB node QB to be lower than the low voltage VL through bootstrap, and the fifth transistor T5 may be stably maintained in the on state. When the low voltage is supplied to the Q node Q, the third transistor T3 may be turned on, so that the high voltage VH may be applied to the O2 node O2.

[0069] The output signal stabilizer 16 may include a sixth transistor T6. The gate of the sixth transistor T6 may be connected to the O2 node O2, the source of the sixth transistor T6 may be connected to the high voltage line to which the high voltage VH is input, and the drain of the sixth transistor T6 may be connected to the Q node Q. When the low voltage is applied to the O2 node O2, the sixth transistor T6 may be turned on and thus the sixth transistor T6 may apply the high voltage to the Q node Q. The sixth transistor T6 may turn off the pull-down unit 11 and may allow the cut-off voltage to be stably maintained at the O1 node O1. The sixth transistor T6, which may be subjected to higher stress than other transistors, may be connected to the first capacitor and may be a double-gate transistor, which can improve the reliability of the sixth transistor T6.

[0070] The output signal stabilizer 16 may further include a second capacitor C2. A first electrode of the second capacitor C2 may be connected to the Q node Q, and a second electrode of the second capacitor C2 is connected to the second clock signal line. When the Q node Q is at a low voltage, the second capacitor C2 may hold the voltage of the Q node Q at a low voltage through a charge pumping operation.

[0071] The pull - down unit 11 may include a seventh transistor T7. A gate of the seventh transistor T7 may be connected to the Q node Q, a source of the seventh transistor T7 may be connected to the low - voltage line, and a drain of the seventh transistor T7 may be connected to the O1 node O1. If a low voltage is applied to the O1 node O1, the seventh transistor T7 may be turned on, so that a low voltage VL may be applied to the O1 node O1. The voltage applied to the O1 node O1 may be transmitted as a first output signal of the k - th stage to the k - th pixel row. The pull - down unit 11 may further include a third capacitor C3. A first electrode of the third capacitor C3 may be connected to the Q node Q, and a second electrode of the third capacitor C3 may be connected to the O1 node O1. When a low voltage VL is applied to the O1 node O1, the third capacitor C3 may cause the voltage of the Q node Q to be lower than the low voltage VL through bootstrapping, and the seventh transistor T7 may be stably held in the on state.

[0072] The pull - up unit 12 may include an eighth transistor T8. A gate of the eighth transistor T8 may be connected to the O2 node O2, a source of the eighth transistor T8 may be connected to the high - voltage line, and a drain of the eighth transistor T8 may be connected to the O1 node O1. If a low voltage is applied to the O2 node O2, the eighth transistor T8 may be turned on, so that a high voltage VH may be applied to the O1 node O1.

[0073] Except for the fifth transistor T5 and the sixth transistor T6 shown as double - gate transistors among the transistors included in the k - th stage in an exemplary manner according to the present invention, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may all be implemented as double - gate transistors, and the reliability of the gate driver may be improved.

[0074] According to Figure 4 The k - th stage according to the example may have a relatively simple circuit that may include 8 transistors, and may use two output signals of the (k - 1) - th stage as input signals. Thereby, the area occupied by the stage may be reduced to reduce the border area, and the operation margin of the elements included in the stage may be increased.

[0075] Figure 5 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention.

[0076] Figure 5 is Figure 3 a detailed circuit diagram of an example of a block diagram of. Reference will be made to Figure 5Describe the k-th stage EM(k) that constitutes the gate driver 130 as an example.

[0077] In Figure 5 the ninth transistor T9 is added to Figure 4 the exemplary circuit diagram of, the reliability of the circuit can be improved. Therefore, the description of the elements that are repeated with those of Figure 4 can be omitted or briefly given.

[0078] Referring to Figure 5 , the k-th stage EM(k) may include a pull-down unit 11', a pull-up unit 12, a Q-node controller 13, a QB-node controller 14, an O2-node controller 15, and an output signal stabilizer 16'. The pull-up unit 12, the Q-node controller 13, the QB-node controller 14, and the O2-node controller 15 are substantially similar to those described above.

[0079] The output signal stabilizer 16' may include a sixth transistor T6' and a ninth transistor T9. The ninth transistor T9 may be connected to the Q-node Q and may divide the Q-node into a Q-node Q and a Q'-node Q'. Since the gate of the ninth transistor T9 is connected to the low voltage line, the ninth transistor T9 may remain in the on state. The source and drain of the ninth transistor T9 may be connected to the Q-node Q and the Q'-node Q', respectively. When the Q-node Q is separated, the drain of the sixth transistor T6' may be connected to the Q'-node Q'. For example, the ninth transistor T9 may be referred to as a Q-node stabilizer.

[0080] The threshold voltage of the third transistor T3 included in the O2-node controller 15 and connected to the Q-node Q may degrade, and the degradation of the threshold voltage of the sixth transistor T6' included in the output signal stabilizer 16' is more severe than that of other transistors. To solve this problem, the ninth transistor T9 may be added to separate the Q-node Q. Thereby, the degradation level of the threshold voltages of the third transistor T3 and the sixth transistor T6' can be alleviated, and the reliability of the gate driver can be improved.

[0081] Figure 4 The third capacitor in the example of Figure 5 can be omitted from the pull-down unit 11' in the example of

[0082] Except in Figure 5In addition to the fifth transistor T5 and the sixth transistor T6' shown as double-gate transistors among the transistors included in the k-th stage in the example of, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can all be implemented as double-gate transistors, and the reliability of the gate driver can be improved. According to Figure 5 The k-th stage of the example of uses two output signals of the (k - 1)-th stage as input signals. The area occupied by the stage can be reduced to reduce the frame area, and the operating margin of the elements constituting the stage can be increased.

[0083] Figure 6 is a circuit diagram showing a stage according to an exemplary embodiment of the present invention.

[0084] Figure 6 is Figure 3 a detailed circuit diagram of an example of a block diagram of. The k-th stage EM(k) constituting the gate driver 130 will be described as an example with reference to Figure 6 In

[0085] In Figure 6 the tenth transistor T10 can be added to the Figure 5 circuit diagram, whereby the operating margin of the transistor can be increased, and the inoperable problem caused by the threshold voltage shift can be solved. Moreover, a fourth capacitor C4 can be additionally provided, and the distortion problem of the voltage applied to the O1 node O1 can be solved. Hereinafter, the description of the elements that are repeated with those of Figure 4 or Figure 5 can be omitted or briefly described.

[0086] Referring to Figure 6 , the k-th stage EM(k) may include a pull-down unit 11', a pull-up unit 12, a Q node controller 13, a QB node controller 14, an O2 node controller 15, and an output signal stabilizer 16”. The pull-down unit 11', the pull-up unit 12, the Q node controller 13, the QB node controller 14, and the O2 node controller 15 are substantially similar to those in the example of according to Figure 5 Output signal stabilizer 16” may include a sixth transistor T6”, a ninth transistor T9, a tenth transistor T10, a second capacitor C2, and a fourth capacitor C4. Since the ninth transistor T9 and the second capacitor C2 are substantially similar to those in

[0087] the description thereof will be omitted. Figure 5 In

[0088] The gate of the tenth transistor 10 may be connected to the second clock signal line, the source of the tenth transistor 10 may be connected to the drain of the sixth transistor T6”, and the drain of the tenth transistor 10 may be connected to the Q’ node Q’. The gate of the sixth transistor T6” may be connected to the O2 node O2, the source of the sixth transistor T6” may be connected to the high voltage line, and the drain of the sixth transistor T6” may be connected to the source of the tenth transistor T10. If the first clock signal CLK is at the conduction voltage, the tenth transistor T10 may reduce or prevent a conflict between the conduction voltage transmitted through the first transistor T1 and the high voltage transmitted through the sixth transistor T6”. Thus, even if the threshold voltage of the third transistor T3 may shift due to degradation of the third transistor T3, the first output signal of the (k-1)th stage may be normally transmitted through the first transistor T1.

[0089] The first electrode of the fourth capacitor C4 may be connected to the O2 node O2, and the second electrode of the fourth capacitor C4 is connected to the high voltage line. When the voltage at the QB node QB shifts from low voltage to high voltage before the voltage at the O1 node OQ shifts from high voltage to low voltage, the fourth capacitor C4 may reduce or prevent the voltage at the O2 node O2 from being shifted to high voltage by the first capacitor C1, and may hold the O2 node in a low voltage state and hold the O1 node O1 in a high voltage state. For example, the tenth transistor T10 and the fourth capacitor C4 may be referred to as an operation margin increasing portion.

[0090] Except for the fifth transistor T5 and the sixth transistor T6’ shown as double-gate transistors among the transistors included in the kth stage in the example according to Figure 6 , the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6” may be applied as double-gate transistors. Thus, the reliability of the gate driver may be improved.

[0091] According to Figure 6 's example, the kth stage may use two output signals of the (k-1)th stage as input signals. Thus, the area reserved by the stage may be reduced to reduce the border area and the operation margin of the components constituting the stage may be increased.

[0092] Figure 7 is a waveform diagram showing stage driving according to an exemplary embodiment of the present invention.

[0093] Figure 7 's waveform may equally be applied to Figures 4 - 6 any of the examples in Figures 4 - 7, when the second output signal OUT2(k - 1) of the (k - 1)-th stage EM(k - 1) and the second clock signal CLK2 correspond to the low voltage in the first time period ①, the second transistor T2 can be turned on, and the low voltage can be applied to the QB node QB. Due to the low voltage applied to the QB node QB, the fifth transistor T5 can be turned on, and thus the low voltage VL can be applied to the drain of the fifth transistor.

[0094] When the first clock signal CLK1 corresponds to the low voltage in the second time period ②, the first transistor T1 and the fourth transistor T4 can be turned on, the high voltage of the first output signal OUT1(k - 1) of the (k - 1)-th stage can be applied to the Q node Q, and the low voltage of the drain of the fifth transistor T5 can be applied to the O2 node O2. Due to the bootstrap of the first capacitor C1, the QB node QB can have a voltage lower than the low voltage, so the fifth transistor T5 can be stably maintained in the on state. When the eighth transistor T8 is turned on by the low voltage applied to the O2 node O2, the high voltage can be applied to the O1 node O1. Therefore, the first output signal OUT1 of the k-th stage can be the high voltage in the second time period ②.

[0095] The high voltage and the low voltage can maintain 4 horizontal time periods relative to the first output signal OUT1(k - 1) and the second output signal OUT2(k - 1) of the (k - 1)-th stage. Therefore, the high voltage and the low voltage can maintain 4 horizontal time periods relative to the first output signal OUT1 and the second output signal OUT2 of the k-th stage.

[0096] In addition, in Figure 4 and 5 example, the sixth transistors T6 and T6' can be turned on in 3 horizontal time periods including the second time period ② due to the low voltage applied to the O2 node O2, and the high voltage can be applied to the Q node Q and the Q' node Q'. Therefore, the first output signal OUT1 can stably output the high voltage. In Figure 6 example, the sixth transistor T6” can be turned on in 3 horizontal time periods including the second time period ② due to the low voltage applied to the O2 node O2, but the tenth transistor T10 can be turned on only when the second clock signal CLK2 corresponds to the low voltage. The high voltage can be intermittently applied to the Q' node Q'.

[0097] For the third time period ③, when the second output signal OUT2(k - 1) of the (k - 1)-th stage is shifted to the high voltage and the second clock signal CLK2 corresponds to the low voltage, thus the high voltage can be applied to the QB node QB. The fifth transistor T5 can be turned off.

[0098] For the fourth period ④, when the first output signal OUT1(k-1) and the first clock signal CLK1 of the (k-1)th stage correspond to a low voltage, the first transistor T1 can be turned on so that a low voltage can be applied to the Q node Q. Accordingly, the third transistor T3 can be turned on so that a high voltage can be applied to the O2 node O2. The high voltage can turn off the eighth transistor T8 and the high voltage can be input to the (k+1)th stage as the second output signal OUT2 of the kth stage. Also, when the seventh transistor T7 is turned on by the low voltage applied to the Q node Q, a low voltage can be applied to the O1 node O1. For example, due to the threshold voltage value of the seventh transistor T7, a complete low voltage may not be applied to the O1 node O1. This can be compensated by the second capacitor C2 in the fifth period ⑤.

[0099] For the fifth period ⑤, the second clock signal CLK2 can be shifted to a low voltage, and the voltage of the Q node Q can be stably shifted to a low voltage due to the bootstrap of the second capacitor C2, the second transistor T7 can be kept in an on state, and a low voltage can be applied to the O1 node O1. The voltage applied to the O1 node O1 can be applied to the kth pixel row as the first output signal OUT1 of the kth stage.

[0100] According to an exemplary embodiment of the present invention, one stage can use two signals output from a previous stage as starting signals, the area reserved by the stage can be reduced thereby reducing the border area, and the operation margin of the elements constituting the stage can be increased. According to an exemplary embodiment of the present invention, a transistor connected to both ends of a capacitor can form a double-gate type transistor, and the reliability of the circuit constituting the stage can be improved.

[0101] According to an exemplary embodiment of the present invention, the Q node for controlling a pull-down transistor can be separated using a transistor, and the parasitic capacitance formed in the Q node can be reduced. Accordingly, the capacitor formed in the pull-down unit can be omitted.

[0102] According to an exemplary embodiment of the present invention, the tenth transistor can be disposed between the Q' node and the sixth transistor to avoid a conflict between the on-voltage transmitted through the first transistor and the high voltage transmitted through the sixth transistor when the first clock signal is an on-voltage. Accordingly, even if the threshold voltage is shifted due to the degradation of the third transistor, the signal input through the first transistor can be normally transmitted.

[0103] According to an exemplary embodiment of the present invention, the fourth capacitor connected between the second output signal line and the high voltage line can prevent: when the QB node is changed from a low voltage to a high voltage before the first output signal is changed from a high voltage to a low voltage, the voltage of the second output signal is shifted to a high voltage through the first capacitor, and can keep the second output signal in a low voltage state to keep the first output signal in a high voltage state.

[0104] A gate driver and an electroluminescent display device according to an exemplary embodiment of the present invention can be described as follows.

[0105] According to an embodiment of the present invention, an electroluminescent display device includes: a light-emitting line; sub-pixels connected to the light-emitting line; and a light-emitting driver configured to provide a light-emitting signal to the light-emitting line and including a plurality of stages, wherein the k-th stage of the plurality of stages includes: a first output node connected to the light-emitting line; a second output node; a Q node; a pull-down circuit and a pull-up circuit, controlled by the Q node and the second output node respectively and configured to provide a voltage to the first output node; a first controller configured to receive a voltage of the first output node of the (k-1)-th stage of the plurality of stages or a first start signal; a second controller configured to receive a voltage of the second output node of the (k-1)-th stage of the plurality of stages or a second start signal; a third controller configured to control a voltage of the second output node; and a fourth controller controlled by the second output node, where k is a natural number of 1 or greater. Accordingly, an operation margin of elements constituting a stage can be increased, and reliability of the gate driver can be improved. In addition, an area reserved by a stage can be reduced, thereby reducing a bezel area.

[0106] For example, in the electroluminescent display device according to an embodiment of the present invention, the fourth controller may further include a Q node stabilizer configured to divide the Q node into a main Q node and a Q' node. For example, in the electroluminescent display device according to an embodiment of the present invention, the fourth controller may further include an operation margin increasing part configured to reduce or prevent a conflict between voltages from occurring in the fourth controller.

[0107] For example, in the electroluminescent display device according to an embodiment of the present invention, the third controller may further include a capacitor, and at least one transistor connected to the capacitor may be a dual-gate type transistor in each of the third controller and the fourth controller. For example, in the electroluminescent display device according to an embodiment of the present invention, the pull-down circuit may include a capacitor connected to the Q node and the first output node. For example, in the electroluminescent display device according to an embodiment of the present invention, the first controller may further be configured to be controlled by a first clock signal, the second controller may further be configured to be controlled by a second clock signal, the first clock signal and the second clock signal swing between a low voltage and a high voltage in a cycle of 1 horizontal period, and their respective phases are opposite to each other.

[0108] For example, in the electroluminescent display device according to an embodiment of the present invention, the fourth controller may include: a T6 transistor configured to be controlled by the second output node and connected to the Q node; a T9 transistor connected to the Q node and configured to divide the Q node into a main Q node and a Q' node; and a C2 capacitor connected to the Q node and the second clock signal line. For example, in the electroluminescent display device according to an embodiment of the present invention, the fourth controller may further include: a T10 transistor configured to be controlled by a second clock signal and connected to the Q node and the T6 transistor; a C4 capacitor connected to the second output node and the high voltage line.

[0109] According to an embodiment of the present invention, a gate driver may include: a plurality of stages, wherein the k-th stage of the plurality of stages includes: a first output node; a second output node; a pull-down transistor and a pull-up transistor configured to control the first output node; a controller configured to control the second output node; and an output signal stabilizer, where k may be a natural number of 1 or greater, wherein the controller includes: a T3 transistor configured to be controlled by the Q node; a T4 transistor configured to be controlled by a first clock signal; a T5 transistor configured to be controlled by the QB node; and a first capacitor, the first capacitor including a first electrode connected to the QB node and a second electrode connected to the second output node, wherein the output signal stabilizer is connected to the Q node and the second output node, and the voltages applied to the first output node and the second output node may be applied as start signals for the (k + 1)-th stage.

[0110] For example, in the gate driver according to an embodiment of the present invention, the T5 transistor may be a dual-gate transistor. For example, in the gate driver according to an embodiment of the present invention, the k-th stage may further include: a T1 transistor configured to control the voltage of the Q node and a T2 transistor configured to control the voltage of the QB node, the T1 transistor may be connected to the first output node of the (k - 1)-th stage, and the T2 transistor may be connected to the second output node of the (k - 1)-th stage.

[0111] For example, in the gate driver according to an embodiment of the present invention, the k-th stage may include: a T6 transistor connected to the Q node in the output signal stabilizer and configured to be controlled by the second output node; and a second capacitor connected to the Q node and the second clock signal line. For example, in the gate driver according to an embodiment of the present invention, the pull-down transistor and the T5 transistor may be connected to the low voltage line, and the pull-up transistor, the T3 transistor, and the T6 transistor may be connected to the high voltage line. For example, in the gate driver according to an embodiment of the present invention, the T6 transistor may be a dual-gate transistor.

[0112] For example, in the gate driver according to an embodiment of the present invention, the k-th stage may include a third capacitor connected to the Q node and the first output node. For example, in the gate driver according to an embodiment of the present invention, the k-th stage may include: a T6 transistor in the output signal stabilizer, configured to be controlled by the second output node and connected to the Q node; a T9 transistor, connected to the Q node and configured to divide the Q node into a main Q node and a Q' node; and a second capacitor, connected to the Q node and the second clock signal line.

[0113] For example, in the gate driver according to an embodiment of the present invention, the pull-down transistor, the T5 transistor, and the T9 transistor may be connected to the gate low voltage line, and the pull-up transistor, the T3 transistor, and the T6 transistor may be connected to the gate high voltage line. For example, in the gate driver according to an embodiment of the present invention, the T6 transistor may be a dual-gate type transistor.

[0114] For example, in the gate driver according to an embodiment of the present invention, the k-th stage in the output signal stabilizer may include: a T9 transistor, connected to the Q node and configured to divide the Q node into a Q node and a Q' node; a T6 transistor, configured to be controlled by the second output node; a T10 transistor, configured to be controlled by a second clock signal and connected to the Q node and the T6 transistor; a second capacitor, connected to the second clock signal line, configured to receive the Q node and the second clock signal; and a fourth capacitor, connected to the second output node and the high voltage line. For example, in the gate driver according to an embodiment of the present invention, the pull-down transistor, the T5 transistor, and the T9 transistor may be connected to the gate low voltage line, and the pull-up transistor, the T3 transistor, and the T6 transistor may be connected to the gate high voltage line. For example, in the gate driver according to an embodiment of the present invention, the T6 transistor may be a dual-gate type transistor.

[0115] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the technical concept or scope of the present invention. Therefore, the embodiments of the present invention are intended to cover all modifications and variations of the present invention falling within the scope of the appended claims and their equivalents.

Claims

1. An electroluminescent display device, comprising: A display panel, the display panel including a display area and a non-display area; Scan lines in the display area and the non-display area; A scan driver configured to provide a scan signal to the scan lines in the non-display area; Light-emitting lines in the display area and the non-display area; Sub-pixels, the sub-pixels being connected in a row direction in the display area to a light-emitting line connected to the gate of a light-emitting transistor that conducts during a light-emitting period and to a scan line connected to the gate of a scan transistor that is cut off during the light-emitting period; A light-emitting driver configured to provide a light-emitting signal to a light-emitting line adjacent to the scan driver in the non-display area, the light-emitting driver including a plurality of stages, wherein the k-th stage of the plurality of stages includes: A first output node connected to the light-emitting line; A Q node, an O2 node, and a QB node in the non-display area; A pull-down circuit controlled by the Q node and configured to provide a conduction voltage to the first output node, the (k + 1)-th stage, and the light-emitting lines in the display area; A pull-up circuit controlled by the O2 node and configured to provide a cut-off voltage to the first output node, the (k + 1)-th stage, and the light-emitting lines in the display area; A first controller controlled by a first clock signal and configured to provide the voltage of the first output node of the (k - 1)-th stage to the Q node; A second controller controlled by a second clock signal and configured to control the QB node; A third controller configured to charge or discharge the O2 node and control the pull-up circuit by using the QB node; and A fourth controller configured to stabilize the voltage of the Q node, wherein the fourth controller holds the voltage of the Q node at a cut-off voltage for turning off the pull-down circuit according to the voltage of the O2 node, where k is a natural number of 1 or greater.

2. The electroluminescent display device according to claim 1, wherein, The first clock signal and the second clock signal swing between a low voltage and a high voltage in a cycle of 1 horizontal period, and their respective phases are opposite to each other.

3. The electroluminescent display device according to claim 1, wherein, The fourth controller includes a second capacitor, the second capacitor including a first electrode connected to the Q node and a second electrode connected to a second clock signal line that provides the second clock signal.

4. The electroluminescent display device according to claim 3, wherein, The pull-down circuit includes a seventh transistor, the seventh transistor including a gate connected to the Q node, a first electrode connected to a low voltage line that provides the conduction voltage, and a second electrode connected to the first output node, wherein the pull-up circuit includes an eighth transistor, the eighth transistor including a gate connected to the O2 node, a first electrode connected to a high voltage line that provides the cut-off voltage, and a second electrode connected to the first output node.

5. The electroluminescent display device according to claim 4, wherein, The pull-down circuit further includes a third capacitor, the third capacitor including a first electrode connected to the Q node and a second electrode connected to the first output node.

6. The electroluminescent display device according to claim 1, wherein, The first controller includes a first transistor, and the first transistor includes a gate connected to a first clock signal line to which the first clock signal is input, a first electrode connected to a first output node of the (k - 1)th stage, and a second electrode connected to the Q node.

7. The electroluminescent display device according to claim 6, wherein, The first clock signal line is connected to the third controller.

8. The electroluminescent display device according to claim 7, wherein, A second clock signal line to which the second clock signal is input is connected to the Q node via the fourth controller.

9. The electroluminescent display device according to claim 1, Among them, The fourth controller includes a Q node stabilizer, and the Q node stabilizer reduces parasitic capacitance formed in the Q node. Wherein, the Q node stabilizer is a transistor, a first electrode of the Q node stabilizer is connected to the pull - down circuit via the Q node, and a second electrode of the Q node stabilizer is connected to the first controller via the Q' node.

10. The electroluminescent display device according to claim 9, wherein, The fourth controller further includes an operation margin increasing part, and the operation margin increasing part is configured to reduce or prevent conflicts between multiple voltages in the fourth controller.

11. The electroluminescent display device according to claim 1, wherein, The third controller further includes a capacitor. Wherein, at least one transistor connected to the capacitor is in the third controller, and the at least one transistor (T5, T6) is a double - gate transistor. Wherein, a first connection end of the capacitor is connected to a gate of a transistor in the fourth controller and a first electrode of a transistor (T4) in the third controller. Wherein, a second connection end of the capacitor is connected to the second controller.

12. The electroluminescent display device according to claim 1, wherein, The third controller includes: A third transistor (T3); A fourth transistor (T4); and A fifth transistor (T5). The third transistor, the fourth transistor, and the fifth transistor are connected in series with each other. The third transistor is controlled by a voltage of a first output node of the (k - 1)th stage.

13. The electroluminescent display device according to claim 12, wherein, A first electrode of the third transistor is connected to a high - voltage line to which a high voltage is provided, a second electrode of the third transistor is connected to the fourth transistor, and a gate of the third transistor is connected to the first controller. A first electrode of the fourth transistor is connected to the third transistor, a second electrode of the fourth transistor is connected to the fifth transistor, and a gate of the fourth transistor is connected to a first clock signal line to which the first clock signal is input. A first electrode of the fifth transistor is connected to the fourth transistor, a second electrode of the fifth transistor is connected to a low - voltage line to which a low voltage is provided, and a gate of the fifth transistor is connected to a second clock signal line to which the second clock signal is input.

14. The electroluminescent display device according to claim 12, wherein, The third controller further includes a capacitor, and the capacitor includes a first electrode and a second electrode. The first electrode of the capacitor is connected to the second electrode of the third transistor and the first electrode of the fourth transistor. The second electrode of the capacitor is connected to the second controller.

15. The electroluminescent display device according to claim 14, wherein the first electrode of the capacitor is connected to the fourth controller.

16. The electroluminescent display device according to claim 1, wherein the fourth controller includes a sixth transistor, the sixth transistor including a first electrode and a second electrode, the first electrode of the sixth transistor is connected to the Q node, the second electrode of the sixth transistor is connected to a high voltage line provided with the cut-off voltage.

17. The electroluminescent display device according to claim 1, wherein the sub-pixel connected to the light-emitting line has at least two different light-emitting regions.

18. The electroluminescent display device according to claim 1, wherein the scan transistor, the light-emitting transistor, and the transistors included in the light-emitting driver are p-type transistors, and the light-emitting transistor conducts when the conduction voltage is a low-level voltage.

19. The electroluminescent display device according to claim 1, wherein the O2 node is a second output node, and the O2 node is connected to the second controller of the (k + 1)th stage.

20. The electroluminescent display device according to claim 1, wherein the scan driver and the light-emitting driver are separated from each other.

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