Memory device and method of manufacturing a memory device

Abstract

The embodiments relate to a memory device and a method of manufacturing the same. The memory device (20) includes a memory cell array (30), a first read circuit (32A), a second read circuit (32B), a first write circuit (33A), and a second write circuit (33B). The memory cell array includes a plurality of first subarrays (SAa) and a plurality of second subarrays (SAb). Each of the plurality of first subarrays includes a plurality of first memory cells. Each of the plurality of second subarrays includes a plurality of second memory cells. The first read circuit reads data from the plurality of first memory cells. The second read circuit, unlike the first read circuit, reads data from the plurality of second memory cells. The first write circuit writes data to the plurality of first memory cells. The second write circuit writes data to the plurality of second memory cells. The first subarray and the second subarray have different areas. Thus, a semiconductor device and a method of manufacturing the same are provided to improve the performance of the memory device.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-032332 (filed on March 2, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation methods relate to memory devices and methods of manufacturing memory devices. Background Technology

[0003] There are known memory devices that use magnetoresistive elements as storage elements (MRAM: Magnetoresistive Random Access Memory). Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same to improve the performance of memory devices.

[0005] The storage device of this embodiment includes a memory cell array, a first read circuit, a second read circuit, a first write circuit, and a second write circuit. The memory cell array includes multiple first sub-arrays and multiple second sub-arrays. Each of the multiple first sub-arrays includes multiple first memory cells. Each of the multiple second sub-arrays includes multiple second memory cells. The first read circuit reads data from the multiple first memory cells. The second read circuit, unlike the first read circuit, reads data from the multiple second memory cells. The first write circuit writes data to the multiple first memory cells. The second write circuit writes data to the multiple second memory cells. The areas of the first sub-arrays and the second sub-arrays are different. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example of the configuration of the memory system according to the first embodiment.

[0007] Figure 2 This is a block diagram illustrating an example of the configuration of the storage system according to the first embodiment.

[0008] Figure 3 This is a circuit diagram illustrating an example of the structure of the core circuitry of the storage device according to the first embodiment.

[0009] Figure 4 This is a circuit diagram illustrating an example of the circuit structure of a plurality of subarrays included in the first storage area of ​​the core circuit of the storage device according to the first embodiment.

[0010] Figure 5 This is a circuit diagram illustrating an example of the circuit structure of a memory matrix included in the first storage area of ​​the core circuit of the storage device according to the first embodiment.

[0011] Figure 6 This is a circuit diagram illustrating an example of the circuit structure of multiple subarrays included in the second storage area of ​​the core circuit of the storage device according to the first embodiment.

[0012] Figure 7 This is a circuit diagram illustrating an example of the circuit structure of a storage matrix included in the second storage region of the core circuit of the storage device according to the first embodiment.

[0013] Figure 8 This is a perspective view showing an example of the three-dimensional structure of the storage matrix in the storage device according to the first embodiment.

[0014] Figure 9 This is a cross-sectional view showing an example of the cross-sectional structure of the first storage cell in the storage device according to the first embodiment.

[0015] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the second storage cell in the storage device according to the first embodiment.

[0016] Figure 11 This is a schematic diagram illustrating an example of the read operation of the storage device according to the first embodiment.

[0017] Figure 12 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the first embodiment.

[0018] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0019] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0020] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0021] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0022] Figure 17This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0023] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the first embodiment.

[0024] Figure 19 This is a graph showing the correlation between the selector film thickness and the dose between the first and second storage cells in the storage device according to the first embodiment.

[0025] Figure 20 This is a graph showing the correlation between the selector's threshold voltage and the leakage current of the half-select memory cell.

[0026] Figure 21 This is a schematic diagram illustrating an example of how the storage system according to the first embodiment is used.

[0027] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the first storage cell in the storage device according to the second embodiment.

[0028] Figure 23 This is a flowchart illustrating an example of a method for manufacturing a storage device according to the second embodiment.

[0029] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0030] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0031] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0032] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0033] Figure 28 This is a cross-sectional view showing an example of the cross-sectional structure during the manufacturing process of the storage device according to the second embodiment.

[0034] Symbol Explanation

[0035] 1. Storage system; 2. Host device; 10. Memory controller; 11. Host interface; 12. CPU (Central Processing Unit); 13. RAM; 14. ECC circuit; 15. Buffer memory; 16. Device interface; 20. Storage device; 21. Core circuit; 22. Input / output circuit; 23. Control circuit; 24. Driver circuit; 25. Decode circuit; 26. Page buffer. Buffer; 30 Memory cell array; 31 Sink circuit; 32A, 32B Read circuit; 33A, 33B Write circuit; 40, 41 Conductor layer; 50 Lower electrode; 51, 51a, 51b, 51c Silicon oxide film; 52 Upper electrode; 60 Ferromagnetic layer; 61 Nonmagnetic layer; 62 Ferromagnetic layer; RG1 First memory region; RG2 Second memory region; SA, SAa, SAb subarray; GBL, GBLa, GBLb global bit lines; GSL, GSLa, GSLb global source lines; LBL, LBLa, LBLb local bit lines; LSL, LSLa, LSLb local source lines; BL bit line; SL source line. Detailed Implementation

[0036] The embodiments will now be described with reference to the accompanying drawings. The drawings are schematic or conceptual. The dimensions and proportions of the drawings may not be identical to those in reality. In the following description, constituent elements having substantially the same function and structure are labeled with the same symbols (reference numerals). Numbers following the characters in the reference symbols are used to distinguish between elements that are referenced by reference symbols containing the same characters and have the same structure. Where it is not necessary to distinguish between elements represented by reference symbols containing the same characters, these elements are referred to by reference symbols containing only characters. Where elements represented by reference symbols containing the same characters or numbers differ, these differences will be described.

[0037] [1] First Embodiment

[0038] The storage system 1 according to the first embodiment will be described below.

[0039] [1-1] Composition

[0040] [1-1-1] Overall Structure of Storage System 1

[0041] Figure 1 This is a block diagram illustrating an example of the configuration of the storage system 1 according to the first embodiment. For example... Figure 1As shown, the storage system 1 is configured to connect to an external host device 2, and includes, for example, a storage controller 10 and a storage device 20.

[0042] The storage controller 10 is configured to control the storage device 20. The storage controller 10 can respond to requests (commands) from the host device 2, commanding the storage device 20 to perform read operations, write operations, etc. Furthermore, the storage controller 10 manages the storage space of the storage device 20.

[0043] The storage device 20 has multiple storage cells and stores data non-volatilely. The storage device 20 uses resistive switching elements to store data. For example, a device with a magnetoresistance effect based on a magnetic tunnel junction (MTJ element) is used as the resistive switching element. MTJ elements are also called magnetoresistance effect elements. The storage device 20 using MTJ elements can also be referred to as a magnetic storage device.

[0044] [1-1-2] Configuration of storage controller 10

[0045] Figure 1 This also shows the detailed configuration of the storage controller 10. For example... Figure 1 As shown, the storage controller 10 includes, for example, a host interface (I / F) 11, a CPU (Central Processing Unit) 12, RAM (Random Access Memory) 13, an ECC (Error Correcting Code) circuit 14, a buffer memory 15, and a device interface (I / F) 16.

[0046] Host interface 11 is connected to host device 2 and manages communication between storage controller 10 and host device 2. Host interface 11 transmits requests and data received from host device 2 to CPU 12 and buffer memory 15, respectively. Host interface 11 responds to commands from CPU 12 and transmits data in buffer memory 15 to host device 2.

[0047] CPU 12 controls the overall operation of memory controller 10. For example, CPU 12 responds to a write request received from host device 2 by issuing a write command containing instructions, addresses, etc. The issued write command is transmitted to memory device 20, and memory device 20 performs a write operation based on the write command. For read operations, CPU 12 can also perform them in the same way as write operations.

[0048] RAM13 is used as the working area of ​​CPU12. RAM13 holds firmware, various management tables, etc., used to manage storage device 20. As RAM13, semiconductor memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) is used, for example.

[0049] ECC circuit 14 performs error correction-related processing. During a write operation, ECC circuit 14 generates a parity bit based on the write data received from host device 2 and appends the generated parity bit to the write data. During a read operation, ECC circuit 14 generates a syndrome based on the read data received from storage device 20 and detects and corrects errors in the read data based on the generated syndrome.

[0050] The buffer memory 15 temporarily holds read data received by the storage controller 10 from the storage device 20, write data received by the storage controller 10 from the host device 2, etc. The buffer memory 15 can be a volatile memory or a non-volatile semiconductor memory. Furthermore, the buffer memory 15 can be externally connected to the storage controller 10 or integrated with the RAM 13.

[0051] Device interface 16 is connected to storage device 20 and manages communication between storage controller 10 and storage device 20. Device interface 16 transmits commands issued by CPU 12 to storage device 20. During a write operation, device interface 16 transmits the write data held in buffer memory 15 to storage device 20. During a read operation, device interface 16 transmits the read data received from storage device 20 to buffer memory 15.

[0052] [1-1-3] Configuration of storage device 20

[0053] Figure 2 This is a block diagram illustrating an example of the configuration of the storage system 1 according to the first embodiment, showing the detailed configuration of the storage device 20. For example... Figure 2 As shown, the storage device 20 includes, for example, a core circuit 21, an input / output circuit 22, a control circuit 23, a drive circuit 24, a decoding circuit 25, and a page buffer 26.

[0054] The core circuit 21 includes multiple memory cells MC for storing data and peripheral circuitry for accessing each memory cell MC. Each memory cell MC is connected between a source line SL and a bit line BL, and is associated with a group of rows and columns. A row address is assigned to the source line SL, and a column address is assigned to the bit line BL. Details of the core circuit 21 will be described later.

[0055] Input / output circuit 22 is connected to memory controller 10 and manages communication between memory device 20 and memory controller 10. Input / output circuit 22 transmits the instruction CMD, address ADD, and data DAT received from memory controller 10 to control circuit 23, decoding circuit 25, and page buffer 26, respectively. Additionally, input / output circuit 22 transmits the data DAT received from page buffer 26 to memory controller 10.

[0056] The control circuit 23 controls the overall operation of the storage device 20. Specifically, the control circuit 23 can control the input / output circuit 22, the core circuit 21, the drive circuit 24, the decoding circuit 25, and the page buffer 26. Moreover, the control circuit 23 can perform write operations, read operations, etc., according to the instruction CMD transmitted from the input / output circuit 22.

[0057] The driving circuit 24 generates the voltage used in read operations, write operations, etc., and transmits the generated voltage to the peripheral circuits within the core circuit 21. For example, when the control circuit 23 receives a command CMD associated with a write operation, the driving circuit 24 generates the voltage used in the write operation based on the instruction from the control circuit 23.

[0058] The decoding circuit 25 decodes the address ADD transmitted from the input / output circuit 22. The address ADD contains a group specifying the row address and column address of the memory unit MC to be acted upon. Furthermore, the decoding circuit 25 controls the peripheral circuits within the core circuit 21 based on the decoding result of the address ADD.

[0059] Page buffer 26 includes multiple latching circuits. These latching circuits are capable of holding write data, read data, etc. During a write operation, page buffer 26 temporarily holds the write data received from input / output circuit 22 and transmits the write data to core circuit 21. During a read operation, page buffer 26 temporarily holds the read data received from core circuit 21 and transmits the read data to input / output circuit 22.

[0060] [1-1-4] Composition of core circuit 21

[0061] Figure 3This is a circuit diagram illustrating an example of the configuration of the core circuitry 21 included in the storage device 20 according to the first embodiment, and also showing the page buffer 26. (As...) Figure 3 As shown, the core circuit 21 includes, for example, a memory cell array 30, a sink circuit 31, read circuits 32A and 32B, and write circuits 33A and 33B.

[0062] The memory cell array 30 includes a first memory region RG1 and a second memory region RG2. The first memory region RG1 includes multiple subarrays SAa. The second memory region RG2 includes multiple subarrays SAb. Each of the subarrays SAa and SAb includes multiple memory cells MC. The area of ​​one subarray SAa is smaller than the area of ​​one subarray SAb. The multiple subarrays SAa and SAb are formed on the same substrate, and the total area of ​​the multiple subarrays SAb is greater than the total area of ​​the multiple subarrays SAa. Furthermore, the number of subarrays SAa included in the first memory region RG1 and the number of subarrays SAb included in the second memory region RG2 can be designed to be arbitrary. The shapes of the first memory region RG1 and the second memory region RG2 are not limited to rectangles and can be appropriately designed.

[0063] The sinking circuit 31 is connected to the local source line LSL via the global source line GSL disposed on the memory cell array 30. Furthermore, the sinking circuit 31 can ground the local source line LSL based on the control of the control circuit 23. Details of the global source line GSL and the local source line LSL will be explained later.

[0064] The read circuit 32 is used to read data stored in the memory cell MC, and includes, for example, a sense amplifier. The read circuit 32 determines the data stored in the memory cell MC by detecting the current flowing through it. Furthermore, the read circuit 32 transmits the determination result as read data to the page buffer 26. Read circuits 32A and 32B are associated with the first memory region RG1 and the second memory region RG2, respectively. For example, read circuits 32A and 32B are optimized for read operations relative to subarrays SAa and SAb, respectively. Furthermore, if optimal settings can be utilized for each of the subarrays SAa and SAb, the memory device 20 can also use a single read circuit to perform read operations for each of the subarrays SAa and SAb.

[0065] Write circuit 33 is used to write data to memory cell MC, and includes, for example, a write driver. Write circuit 33 writes the desired data to memory cell MC by, for example, by allowing current to flow through memory cell MC based on write data transferred from page buffer 26. Write circuits 33A and 33B are associated with first memory region RG1 and second memory region RG2, respectively. For example, write circuits 33A and 33B are optimized for write operations relative to subarrays SAa and SAb, respectively. Furthermore, if optimal settings can be utilized in each of subarrays SAa and SAb, memory device 20 can also use a single write circuit to perform write operations for each of subarrays SAa and SAb.

[0066] [1-1-5] Circuit structure of memory cell array 30

[0067] The circuit structure of the memory cell array 30 will now be described in the order of elements associated with the first memory region RG1 and elements associated with the second memory region RG2.

[0068] (Circuit structure in memory region RG1)

[0069] Figure 4 This is a circuit diagram illustrating an example of the circuit structure of a plurality of subarrays SAa included in the first storage region RG1 of the core circuit 21 of the storage device 20 according to the first embodiment. Multiple wirings connected to the plurality of subarrays SAa are also shown. Figure 4 As shown, multiple subarrays SAa are configured, for example, in a matrix configuration. Multiple wirings connecting the multiple subarrays SAa include multiple global source lines GSLa (GSLa0, GSLa1, ...) and multiple global bit lines GBLa (GBLa0, GBLa1, ...). Each subarray SAa includes a storage matrix MATa, row selection circuit RSCa, column selection circuit CSCa, multiple local source lines LSLa (source lines SL), and multiple local bit lines LBLa (bit lines BL).

[0070] Multiple global source lines GSLa and multiple global bit lines GBLa are configured to be connected to each of the sink circuit 31, the read circuit 32A, and the write circuit 33A. A subarray SAa is located at the intersection of the global source line GSLa and the global bit line GBLa. That is, each subarray SAa is associated with one global source line GSLa and one global bit line GBLa. The following description focuses on a single subarray SAa and explains its components.

[0071] The storage matrix MATa comprises multiple first storage cells MCa configured in a matrix shape. Each first storage cell MCa is connected between a local source line LSLa and a local bit line LBLa. Furthermore, each first storage cell MCa is assigned a group of row addresses and column addresses.

[0072] The row selection circuit RSCa is connected to the storage matrix MATa via multiple local source lines LSLa. RSCa controls the connection between the global source line GSLa and the multiple local source lines LSLa. For RSCa, the decoding result (row address) of address ADD is supplied from the decoding circuit 25. Furthermore, RSCa electrically connects a local source line LSLa selected based on the row address to the associated global source line GSLa.

[0073] The column selection circuit CSCa is connected to the storage matrix MATa via multiple local bit lines LBLa. The column selection circuit CSCa controls the connection between the global bit line GBLa and the multiple local bit lines LBLa. For the column selection circuit CSCa, the decoding result (column address) of address ADD is supplied from the decoding circuit 25. Furthermore, the column selection circuit CSCa electrically connects a local bit line LBLa selected based on the column address received from the decoding circuit 25 to the associated global bit line GBLa.

[0074] (Circuit structure of storage matrix MATa)

[0075] Figure 5 This is a circuit diagram illustrating an example of the circuit structure of the storage matrix MATa included in the first storage region RG1 of the core circuit 21 of the storage device 20 according to the first embodiment. For example... Figure 5 As shown, memory cells MCa are connected between local source line LSLa0 and local bit line LBLa0, between local source line LSLa0 and local bit line LBLa1, between local source line LSLa1 and local bit line LBLa0, and between local source line LSLa1 and local bit line LBLa1.

[0076] Multiple memory cells MCa arranged in the same row are connected to any one local source line LSLa. Multiple memory cells MCa arranged in the same column are connected to any one local bit line LBLa. Furthermore, each first memory cell MCa includes a resistive switching element MTJ and a selector SELa connected in series. For example, one end of the resistive switching element MTJ is connected to the local bit line LBLa. The other end of the resistive switching element MTJ is connected to one end of the selector SELa. The other end of the selector SELa is connected to the local source line LSLa. Alternatively, the connection relationship between the resistive switching element MTJ and the selector SELa between the local source line LSLa and the local bit line LBLa can be reversed.

[0077] The resistive variable element MTJ is, for example, an MTJ element. The resistive variable element MTJ stores data based on its resistance value. For example, the storage cell MC stores "1" data when the resistive variable element MTJ is in a high-resistance state (resistance state) and "0" data when the resistive variable element MTJ is in a low-resistance state. The allocation of data associated with the resistance value of the resistive variable element MTJ can also be otherwise configured. The resistance state of the resistive variable element MTJ may vary depending on the current generated by the write circuit 33A.

[0078] The selector SELa is, for example, a bidirectional diode. The selector SELa functions as a switching element controlling the current supply to the associated resistive switching element MTJ in both write and read operations. Specifically, the selector SELa included in a memory cell MCa is in an off state when the voltage applied to the memory cell MCa is below a threshold voltage Vtha, and in an on state when the voltage applied to the memory cell MCa is above the threshold voltage Vtha. In the off state, the selector SELa functions as an insulator with high resistance. When the selector SELa is in the off state, no current flows between the local source line LSLa and the local bit line LBLa connected to the memory cell MCa. In the on state, the selector SELa functions as a conductor with low resistance. When the selector SELa is in the on state, current flows between the local source line LSLa and the local bit line LBLa connected to the memory cell MCa. That is, the selector SELa can switch whether to allow current to flow, regardless of the direction of current flow, based on the magnitude of the voltage applied to the storage cell MCa.

[0079] (Circuit structure in memory region RG2)

[0080] Figure 6 This is a circuit diagram illustrating an example of the circuit structure of a plurality of subarrays SAb included in the second storage region RG2 of the core circuit 21 of the storage device 20 according to the first embodiment. Multiple wirings connected to the plurality of subarrays SAb are also shown. Figure 6 As shown, multiple subarrays SAb are configured, for example, in a matrix configuration. Multiple wirings connecting the multiple subarrays SAb include multiple global source lines GSLb (GSLb0, GSLb1, ...) and multiple global bit lines GBLb (GBLb0, GBLb1, ...). Each subarray SAb includes a storage matrix MATb, a row select circuit RSCb, a column select circuit CSCb, multiple local source lines LSLb (source lines SL), and multiple local bit lines LBLb (bit lines BL).

[0081] Multiple global source lines GSLb and multiple global bit lines GBLb are configured to connect to each of the sink circuit 31, read circuit 32B, and write circuit 33B. A subarray SAb is located at the intersection of the global source lines GSLb and the global bit lines GBLb. That is, each subarray SAb is associated with one global source line GSLb and one global bit line GBLb. The following description focuses on a single subarray SAb and explains its components.

[0082] The storage matrix MATb comprises multiple second storage cells MCb configured in a matrix. Each second storage cell MCb is connected between a local source line LSLb and a local bit line LBLb. Furthermore, each second storage cell MCb is assigned a group of row and column addresses. The size (area) of the storage matrix MATb is larger than the size (area) of the storage matrix MATa. The wiring length of the local source line LSLb is longer than that of the local source line LSLa. The number of second storage cells MCb connected to a local source line LSLb is greater than the number of first storage cells MCa connected to a local source line LSLa. The wiring length of the local bit line LBLb is longer than that of the local bit line LBLa. The number of second storage cells MCb connected to a local bit line LBLb is greater than the number of first storage cells MCa connected to a local bit line LBLa. The storage capacity of the storage matrix MATb is greater than the storage capacity of the storage matrix MATa.

[0083] The row selection circuit RSCb is connected to the storage matrix MATb via multiple local source lines LSLb. The row selection circuit RSCb controls the connection between the global source line GSLb and the multiple local source lines LSLb. For the row selection circuit RSCb, the decoding result (row address) of address ADD is supplied from the decoding circuit 25. Furthermore, the row selection circuit RSCb electrically connects a local source line LSLb selected based on the row address to the associated global source line GSLb.

[0084] The column select circuit CSCb is connected to the storage matrix MATb via multiple local bit lines LBLb. The column select circuit CSCb controls the connection between the global bit line GBLb and the multiple local bit lines LBLb. For the column select circuit CSCb, the decoding result (column address) of address ADD is supplied from the decoding circuit 25. Furthermore, the column select circuit CSCb electrically connects a local bit line LBLb selected based on the column address received from the decoding circuit 25 to the associated global bit line GBLb.

[0085] (Circuit structure of storage matrix MATb)

[0086] Figure 7This is a circuit diagram illustrating an example of the circuit structure of the storage matrix MATb included in the second storage region RG2 of the core circuit 21 of the storage device 20 according to the first embodiment. For example... Figure 7 As shown, a second memory cell MCb is connected between local source line LSLb0 and local bit line LBLb0, between local source line LSLb0 and local bit line LBLb1, between local source line LSLb1 and local bit line LBLb0, and between local source line LSLb1 and local bit line LBLb1.

[0087] Multiple second memory cells MCb configured in the same row are connected to any one local source line LSLb. Multiple second memory cells MCb configured in the same column are connected to any one local bit line LBLb. Each second memory cell MCb includes a resistive switching element MTJ and a selector SELb connected in series. For example, one end of the resistive switching element MTJ is connected to the local bit line LBLb. The other end of the resistive switching element MTJ is connected to one end of the selector SELb. The other end of the selector SELb is connected to the local source line LSLb. Furthermore, the connection relationship between the resistive switching element MTJ and the selector SELb between the local source line LSLb and the local bit line LBLb can also be reversed. The resistive switching element MTJ included in the second memory cell MCb is the same as the resistive switching element MTJ included in the first memory cell MCa.

[0088] The selector SELb is, for example, a bidirectional diode. The selector SELb has the same function as the selector SELa. Specifically, the selector SELb included in a memory cell MCb is in a cutoff state when the voltage applied to the memory cell MCb is below the threshold voltage Vthb, and in a conduction state when the voltage applied to the memory cell MCb is above the threshold voltage Vthb. In the cutoff state, the selector SELb functions as a high-resistance insulator. When the selector SELb is in the cutoff state, no current flows between the local source line LSLb and the local bit line LBLb connected to the memory cell MCb. In the conduction state, the selector SELb functions as a low-resistance conductor. When the selector SELb is in the conduction state, current flows between the local source line LSLb and the local bit line LBLb connected to the memory cell MCb. The threshold voltage Vthb of the selector SELb is designed to be higher than the threshold voltage Vtha of the selector SELa.

[0089] [1-1-6] Construction of the memory cell array 30

[0090] Hereinafter, an example of the construction of the memory cell array 30 in the first embodiment will be described. In the following drawings, the X direction corresponds to the extension direction of the source line SL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction opposite to the surface of the semiconductor substrate used to form the memory device 20. In the perspective view, shading lines have been appropriately added to make the view easier to read. The shading lines added to the perspective view are not necessarily related to the material or characteristics of the constituent elements to which the shading lines are added. In the perspective view and sectional view, each constituent element has been appropriately simplified or omitted to make the view easier to read.

[0091] (The three-dimensional structure of the storage matrix MAT)

[0092] Figure 8 This is a perspective view showing an example of the three-dimensional structure of the storage matrix MAT in the storage device 20 according to the first embodiment. The structure of the storage matrix MAT is similar between the first storage region RG1 and the second storage region RG2. In this project, an example of a similar three-dimensional structure between the storage matrices MAT1 and MAT2b will be described. Figure 8 As shown, the storage matrix MAT includes multiple conductive layers 40 and multiple conductive layers 41.

[0093] Each of the plurality of conductive layers 40 has a portion extending in the X direction. The plurality of conductive layers 40 are arranged and separated from each other along the Y direction. Each conductive layer 40 is used as a local source line (LSL).

[0094] Each of the plurality of conductive layers 41 has a portion extending in the Y direction. The plurality of conductive layers 41 are arranged and separated from each other along the X direction. Each conductive layer 41 is used as a local bit line LBL.

[0095] Furthermore, multiple conductive layers 41 are disposed above multiple conductive layers 40. Moreover, a memory cell MC is disposed at the intersection of the multiple conductive layers 40 and the multiple conductive layers 41. Specifically, a selector SEL is disposed above the conductive layer 40. A resistive switching element MTJ is disposed above the selector SEL. The conductive layer 41 is disposed above the resistive switching element MTJ.

[0096] Between storage matrices MATa and MATb, the cross-sectional structure of the first storage cell MCa is different from that of the second storage cell MCb. The cross-sectional structures of the first storage cell MCa and the second storage cell MCb will be described below in turn.

[0097] (Cross-sectional structure of storage cell MCa)

[0098] Figure 9This is a cross-sectional view showing an example of the cross-sectional structure of the first storage cell MCa in the storage device 20 according to the first embodiment. For example... Figure 9 As shown, the first memory cell MCa includes, for example, a lower electrode 50, a silicon oxide film 51a, an upper electrode 52, a ferromagnetic layer 60, a non-magnetic layer 61, and a ferromagnetic layer 62.

[0099] The lower electrode 50, silicon oxide film 51a, and upper electrode 52 correspond to the selector SELa. The lower electrode 50 is disposed above the conductor layer 40 (local source line LSLa). The silicon oxide film 51a is disposed above the lower electrode 50. The upper electrode 52 is disposed above the silicon oxide film 51a. The lower electrode 50 and upper electrode 52 respectively contain TiN, TaN, etc. The silicon oxide film 51a is doped with arsenic (As). The As concentration in the silicon oxide film 51a is 30 (at%: atomic percentage) or higher. Hereinafter, the thickness (film thickness) of the silicon oxide film 51a along the Z direction will be referred to as "FT1".

[0100] The group consisting of ferromagnetic layer 60, non-magnetic layer 61, and ferromagnetic layer 62 corresponds to the resistive switching element MTJ. Ferromagnetic layer 60 is disposed above the upper electrode 52. Non-magnetic layer 61 is disposed above ferromagnetic layer 60. Ferromagnetic layer 62 is disposed above non-magnetic layer 61. A conductive layer 41 (local bit line LBLa) is disposed above ferromagnetic layer 62.

[0101] Ferromagnetic layers 60 and 62 are each composed of a ferromagnetic material and have a magnetization direction perpendicular to the film surface. For example, the magnetization direction of ferromagnetic layer 60 can be fixed, while the magnetization direction of ferromagnetic layer 62 can be variable. In this case, ferromagnetic layer 60 functions as a reference layer of the MTJ element, and ferromagnetic layer 62 functions as a storage layer of the MTJ element. The nonmagnetic layer 61 is composed of an insulator such as MgO and functions as a tunnel barrier layer. Ferromagnetic layers 60 and 62, together with nonmagnetic layer 61, form a magnetic tunnel junction. This resistive switching element (MTJ) functions as a vertically magnetized MTJ element utilizing the TMR (tunneling magnetoresistive) effect.

[0102] The resistive switching element MTJ can take on either a low-resistance state or a high-resistance state depending on the relative magnetization directions of the ferromagnetic layers 60 and 62. Furthermore, the MTJ stores data based on the magnetization direction of the ferromagnetic layer 62 (storage layer). For example, the MTJ with the magnetization directions of the reference layer and the storage layer being antiparallel (AP state) is in a high-resistance state (data "1"). On the other hand, the MTJ with the magnetization directions of the reference layer and the storage layer being parallel (P state) is in a low-resistance state (data "0").

[0103] In this example, the resistive switching element MTJ is in the AP state when a write current flows from the ferromagnetic layer 60 to the ferromagnetic layer 62, and in the P state when a write current flows from the ferromagnetic layer 62 to the ferromagnetic layer 60. This writing method, in which a write current flows through the resistive switching element MTJ to inject spin torque into the storage layer and the reference layer and control the magnetization direction of the storage layer, is called spin injection writing. The resistive switching element MTJ is configured such that when a current of magnitude sufficient to reverse the magnetization direction of the ferromagnetic layer 62 flows through the resistive switching element MTJ, the magnetization direction of the ferromagnetic layer 60 does not change.

[0104] Furthermore, in this specification, "variable magnetization direction" means that the magnetization direction changes due to the write current. "Fixed magnetization direction" means that the magnetization direction does not change due to the write current. In a resistive switching device (MTJ), the configuration of the storage layer and the reference layer can also be interchanged. Additionally, the resistive switching device (MTJ) can also have other layers. For example, the resistive switching device (MTJ) can also have a shift cancel layer to suppress the influence of the leakage magnetic field of the reference layer, or a SAF (Synthetic Anti-Ferromagnetic) structure.

[0105] (Cross-sectional structure of the memory cell MCb)

[0106] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the second storage cell MCb in the storage device 20 according to the first embodiment. For example... Figure 10 As shown, the second memory cell MCb includes, for example, a lower electrode 50, a silicon oxide film 51b, an upper electrode 52, a ferromagnetic layer 60, a non-magnetic layer 61, and a ferromagnetic layer 62.

[0107] The lower electrode 50, silicon oxide film 51b, and upper electrode 52 correspond to the selector SELb. The lower electrode 50 is disposed above the conductive layer 40 (local source line LSLb). The silicon oxide film 51b is disposed above the lower electrode 50. The thickness FT2 of the silicon oxide film 51b along the Z direction is approximately equal to the thickness FT1 of the silicon oxide film 51a. The upper electrode 52 is disposed above the silicon oxide film 51b.

[0108] In addition, similar to silicon oxide film 51a, silicon oxide film 51b is also doped with arsenic. The As concentration in silicon oxide film 51b is 10 (at%) or less. That is, in the memory device 20 according to the first embodiment, the As concentration of selector SELa used in the small MAT (MATa) is designed to be higher than the As concentration of selector SELb used in the large MAT (MATb) (≤10 (at%)). The As concentration of selector SELa differs from that of selector SELb by at least one bit. Moreover, the difference in threshold voltage between selectors SELa and SELb is designed based on the difference in As concentration. The other structures of memory cell MCb are the same as those of memory cell MCa.

[0109] [1-2] Actions

[0110] Figure 11 This is a schematic diagram illustrating an example of the read operation of the storage device 20 according to the first embodiment, showing an example of the voltage applied to each wiring at a certain moment. For example... Figure 11 As shown, during the read operation, the memory device 20 performs a read operation that selects one bit line BL and one source line SL. The following example illustrates the read operation when the local bit line LBL0 and the local source line LSL0 are selected.

[0111] Furthermore, in the following description, the selected memory cell MC is referred to as the selected memory cell MC. The group of local source lines LSL and local bit lines LBL associated with the selected memory cell MC is referred to as the selected local source line and the selected local bit line, respectively. The local source line LSL other than the selected local source line is referred to as the non-selected local source line. The local bit line LBL other than the selected local bit line is referred to as the non-selected local bit line. Each of the memory cell MCs connected to both the selected local source line and the non-selected local bit line, and the memory cell MCs connected to both the selected local bit line and the non-selected local source line, is referred to as the half-selected memory cell MC.

[0112] During the read operation, Vss is applied to the selected local source line (LSL0). Vread / 2 is applied to each of the non-selected local source lines (LSL1, LSL2, ...). Vread is applied to the selected local bit line (LBL0). Vread / 2 is applied to each of the non-selected local bit lines (LBL1, LBL2, ...). Vss is the ground voltage. Vread is a read voltage higher than Vss. Preferably, the voltages applied to the non-selected local source lines and non-selected local bit lines are approximately the same.

[0113] Therefore, a voltage in the first direction (from the local source line LSL to the local bit line LBL) is applied to the selected memory cell (MC00). A voltage in the first direction is applied to the half-selected memory cells (MC01, MC02, ...) connected to the selected local bit line (LBL0). A voltage in the first direction is applied to the half-selected memory cells (MC10, MC20, ...) connected to the selected local source line (LSL0). Since approximately the same voltage is applied across the non-selected memory cell MC, the voltage difference across the non-selected memory cell MC is suppressed.

[0114] The voltage difference across the selected memory cell MC is greater than the voltage difference across the half-selected memory cell MC, and is above the threshold voltage of the selector SEL. Conversely, the voltage difference across the half-selected memory cell MC is less than the threshold voltage of the selector SEL. As a result, the read current through the selected memory cell (MC00) can flow from the selected local bit line (LBL) to the selected local source line (LSL0). On the other hand, current flowing through the non-selected memory cell MC between the non-selected local bit line LBL and the non-selected local source line LSL is suppressed. Furthermore, current flowing through the half-selected memory cell MC between the selected local bit line (LBL0) and the non-selected local source line LSL, or between the non-selected local bit line LBL and the selected local source line (LSL0), is also suppressed.

[0115] The magnitude of the read current flowing through the select memory cell MC varies depending on the resistance state of the resistive switching element MTJ included in the select memory cell MC. Therefore, the read circuit 32 can determine the data stored in the select memory cell MC by detecting the read current flowing through the select memory cell MC via the global bit line GBL connected to the select local bit line LBL.

[0116] As described above, in the read operation of the storage device 20 having a storage cell MC using a two-terminal selector SEL, a half-selected storage cell MC exists. A half-selected storage cell MC also exists in the write operation. In the storage device 20 according to the first embodiment, since the threshold voltage of the selector SELa used in the storage matrix MATa is different from the threshold voltage of the selector SELb used in the storage matrix MATb, it is preferable to optimize the settings of the read voltage Vread used in the read operation and / or the write voltage in the write operation in the storage matrices MATa and MATb, respectively.

[0117] [1-3] Manufacturing method

[0118] Figure 12 This is a flowchart illustrating an example of a method for manufacturing the storage device 20 according to the first embodiment. Figures 13-18These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 20 according to the first embodiment, showing a cross-section including the first storage region RG1 and the second storage region RG2. Hereinafter, reference will be made as appropriate. Figure 12 An example of the method for forming selectors SELa and SELb and MTJ elements in the first embodiment will be described.

[0119] First, such as Figure 13 As shown, a lower electrode 50 and a silicon oxide film 51 are formed (step S10). Specifically, a conductor used as the lower electrode 50 and a silicon oxide film 51 are sequentially stacked on the conductor layer 40 (local source line LSL).

[0120] Next, as Figure 14 As shown, As ions are implanted into the silicon oxide film 51 (step S11). Specifically, arsenic is doped into the silicon oxide film 51 by using an As ion implantation process. In this ion implantation process, the As concentration in the silicon oxide film 51 is set to be the As concentration of the selector SELb as designed. That is to say, the silicon oxide film 51b is formed through the process of step S11.

[0121] Next, as Figure 15 As shown, a mask PR1 is formed (step S12). For example, the mask PR1 is formed using photolithography. The mask PR1 covers the portion corresponding to the second memory region RG2. On the other hand, an opening is formed in the mask PR1 at the portion corresponding to the first memory region RG1. That is, the surface of the silicon oxide film 51b is exposed within the first memory region RG1.

[0122] Next, as Figure 16 As shown, As ions are implanted into the silicon oxide film 51b (step S13). Specifically, an ion implantation process using As ions is performed using mask PR1. In this case, arsenic is doped into the silicon oxide film 51b within the opening portion of mask PR1, i.e., the first storage region RG1. In this ion implantation process, the As concentration in the silicon oxide film 51b within the first storage region RG1 is set to the As concentration of the selector SELa, which is the design value. That is, through the process of step S13, a silicon oxide film 51a is formed within the first storage region RG1. As a result, the As concentration of the silicon oxide film 51a formed has different structures in the first storage region RG1 and the second storage region RG2.

[0123] Next, remove mask PR1 (step S14).

[0124] Next, as Figure 17As shown, an upper electrode 52, a ferromagnetic layer 60, a non-magnetic layer 61, and a ferromagnetic layer 62 are formed (step S15). Specifically, a conductor used as the upper electrode 52, a ferromagnetic layer 60, a non-magnetic layer 61, and a ferromagnetic layer 62 are sequentially stacked on silicon oxide films 51a and 51b.

[0125] Next, as Figure 18 As shown, the stacked structure is separated according to the memory cell MC (step S16). The "stacked structure" includes the stacked structure corresponding to the selector SEL (lower electrode 50, silicon oxide films 51a and 51b, upper electrode 52) and the stacked structure corresponding to the resistive switching element MTJ (ferromagnetic layer 60, non-magnetic layer 61, ferromagnetic layer 62).

[0126] In simple terms, first, a hard mask HM is formed covering the portion corresponding to the local source line LSL. Then, anisotropic etching processes such as RIE (Reactive Ion Etching) are performed using the hard mask HM. As a result, for example, the ferromagnetic layer 62, the non-magnetic layer 61, the ferromagnetic layer 60, the upper electrode 52, the silicon oxide films 51a and 51b, the lower electrode 50, and the conductive layer 40 are each segmented.

[0127] Subsequently, although the illustrations are omitted, for example, a formation with along... Figure 18 A hard mask with multiple openings extending in the depth direction (X direction) is used to perform anisotropic etching. As a result, a memory cell MC is formed, each connected to a local bit line LBL and a local source line LSL. The memory cell MC formed in the first memory region RG1 corresponds to a memory cell MCa including a selector SELa using a silicon oxide film 51a. The memory cell formed in the second memory region RG2 corresponds to a memory cell MCb including a selector SELb using a silicon oxide film 51b.

[0128] Through the manufacturing processes described above, the selector SELa and SELb, as well as the memory cell MC, of ​​the first embodiment are formed. Furthermore, the impurities doped in the silicon oxide films 51a and 51b are activated by heat treatment following ion implantation. The timing for activating the impurities doped in the silicon oxide films 51a and 51b can be appropriately set. Additionally, different processes can be added between the processes described above, and the number and type of layers formed in steps S10 and S15 can be increased depending on the structure of the selector SEL and the resistive switching element MTJ. The hard mask HM can also be removed, and local bit lines LBL can be connected on the hard mask HM.

[0129] (Detailed design of selectors SELa and SELb)

[0130] Figure 19This is a graph showing the correlation between selector film thickness and dose between the first storage cell MCa and the second storage cell MCb in the storage device 20 according to the first embodiment. Figure 19 The horizontal axis represents the selector film thickness, i.e., the thickness of the silicon oxide film 51. Figure 19 The vertical axis represents the As-Dose (log), i.e., the arsenic (As) dosage setting during ion implantation, expressed on a logarithmic scale. See below for reference. Figure 19 An example of the setting of the ion implantation process used to form selectors SELa and SELb in the storage device 20 according to the first embodiment will be described.

[0131] With a selector film thickness of 10 nm, if the As dose is set to be greater than 10 nm... 17 With ion implantation, the As concentration in the corresponding selector SEL can become higher than 30 (at%). Furthermore, when the selector film thickness is 15 nm, if the As dose is set to more than 10... 18 With ion implantation, the As concentration of the corresponding selector SEL can become higher than 30 (at%). Ion implantation with these settings (e.g., step S13) can form a silicon oxide film 51a with a suitable concentration of small MAT (MATa).

[0132] With a selector film thickness of 10 nm, if the As dose is set to less than 10 nm... 16 With ion implantation, the As concentration in the corresponding selector SEL can be reduced to below 10 (at%). Furthermore, when the selector film thickness is 15 nm, if the As dose is set to less than 10... 17 With ion implantation, the As concentration of the corresponding selector SEL can become less than 10 (at%). Ion implantation with these settings (e.g., step S11) can form a silicon oxide film 51b with a concentration of MAT (MATb) suitable for a large concentration.

[0133] As described above, the As concentration of the silicon oxide film 51 is determined based on the correlation between the As dose during the ion implantation process and the selector film thickness (the film thickness of the silicon oxide film 51). Settings other than those described above can also be used as long as an appropriate As concentration of silicon oxide film 51 can be formed in each of the selectors SELa and SELb.

[0134] In the memory device 20 according to the first embodiment, the selector film thickness of memory cell MCa is approximately equal to that of memory cell MCb. Therefore, multiple ion implantation processes are performed on the silicon oxide film 51 within the first memory region RG1, which is preferably highly doped with As. Not limited to this, ion implantation processes targeting selector SELa and selector SELb can also be performed separately. In this case, silicon oxide film 51a is formed by a single ion implantation process using a mask with an opening in the region of selector SELa, and silicon oxide film 51b is formed by a single ion implantation process using a mask with an opening in the region of selector SELb.

[0135] [1-4] Effects of the first embodiment

[0136] The storage system 1 according to the first embodiment described above can improve the performance of the storage device 20. Hereinafter, the effects of the storage system 1 according to the first embodiment will be explained in detail.

[0137] To maximize the performance of a storage system, a single module is preferred, for example, to have both SCM (Storage Class Memory) and DRAM (Dynamic Random Access Memory). As the SCM, for example, a resistive random access memory (RRAM) with a cross-point array of memory cells is used. DRAM stores frequently accessed data and serves as a buffer area for the storage system. However, adding DRAM chips to a storage system is a major reason for the increased cost of the storage system.

[0138] To address this, a portion of the SCM's storage area can be used as a cache memory, similar to DRAM. This configuration of the storage system can suppress costs and improve the overall performance of the storage system. When using resistive random access memory (MRAM) as the SCM, by reducing the threshold voltage of the selector SEL used to select the memory cells (MC) within the storage matrix MAT, the latency in read and write operations of the storage matrix MAT can be improved, thus enhancing access performance.

[0139] Figure 20 This is a graph showing the correlation between the threshold voltage of the selector SEL and the leakage current of the half-select memory cell MC. Vth represents the threshold voltage of the selector SEL. Ihalf represents the magnitude of the half-select leakage current flowing from the half-select memory cell MC during a read operation. Figure 20As shown, the lower the threshold voltage of selector SEL, the larger Ihalf is; the higher the threshold voltage of selector SEL, the smaller Ihalf is.

[0140] Selector SELs with low threshold voltages (hereinafter referred to as low-Vth selector SELs) exhibit good write tolerance (endurance). For example, a silicon oxide film highly doped with arsenic is used as a low-Vth selector SEL. Furthermore, because the voltage required to turn on a low-Vth selector SEL is low, the operating voltage can be reduced, resulting in lower power consumption. Additionally, to accurately determine the data in the memory cell MC, it is necessary to suppress the total Ihalf. Ihalf can become noise when reading data from the selected memory cell MC. Therefore, when using low-Vth selector SELs that may generate high Ihalf, it is preferable to suppress the number of memory cells MC connected to a single local bit line LBL. That is, it is difficult to increase the size of the memory matrix MAT using low-Vth selector SELs, resulting in a smaller storage capacity.

[0141] On the other hand, selector SELs with high threshold voltages (hereinafter referred to as high-Vth selector SELs) have lower write tolerance compared to low-Vth selector SELs. For example, a silicon oxide film with low-concentration arsenic doping is used as a high-Vth selector SEL. Because a high-Vth selector SEL requires a higher voltage to turn on, its operating voltage is increased, resulting in higher power consumption. Furthermore, when using a high-Vth selector SEL where Ihalf may be lower than that of a low-Vth selector SEL, the number of memory cells (MCs) connected to a single local bit line (LBL) can be increased compared to when using a low-Vth selector SEL. That is, compared to a memory matrix MAT using a low-Vth selector SEL, a memory matrix MAT using a high-Vth selector SEL can have a larger size and thus a larger storage capacity.

[0142] Therefore, in the storage system 1 according to the first embodiment, the storage device 20 has two storage matrices, MATa and MATb, with selectors SEL having different threshold voltages. Specifically, the storage matrix MATa has a low-Vth selector SELa, which has high performance. On the other hand, the storage matrix MATb has a high-Vth selector SELb, which has a large storage capacity.

[0143] Figure 21 This is a schematic diagram illustrating an example of the usage method of the storage system 1 according to the first embodiment, showing a storage matrix MATa and a storage matrix MATb extracted from the storage device 20. Figure 21As shown, storage system 1 uses storage matrix MATa to store data that is likely to be accessed frequently, and storage matrix MATb to store data that is not frequently accessed. Data that is likely to be accessed frequently is, for example, computational data from a program. Data that is not frequently accessed is, for example, program data.

[0144] In other words, when the storage controller 10 receives write data from the host device 2 that is likely to be accessed frequently, it instructs the storage device 20 to write the write data to the storage matrix MATa. On the other hand, when the storage controller 10 receives write data from the host device 2 that is not frequently accessed, it instructs the storage device 20 to write the write data to the storage matrix MATb. That is to say, the storage controller 10 can change the write destination (storage matrix MATa or MATb) within the storage device 20 according to the access frequency of the write data.

[0145] As described above, the storage system 1 according to the first embodiment can use the storage matrix MATa as a buffer memory such as DRAM, and the storage matrix MATb as a large-capacity storage area. As a result, the storage system 1 according to the first embodiment can balance performance and storage capacity, and can maximize chip performance. That is, the storage system 1 according to the first embodiment can improve the performance of the storage device 20.

[0146] [2] Second Embodiment

[0147] The storage device 20 according to the second embodiment achieves the same effect as the first embodiment by changing the thickness of the selector SEL between the storage matrices MATa and MATb. Hereinafter, the differences between the storage device 20 according to the second embodiment and the first embodiment will be explained.

[0148] [2-1] Cross-sectional structure of memory cell MCa

[0149] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the first storage cell MCa in the storage device 20 according to the second embodiment. For example... Figure 22 As shown, the first storage cell MCa in the second embodiment has the following configuration: the silicon oxide film 51a in the selector SELa is replaced with a silicon oxide film 51c, according to the first storage cell MCa described in the first embodiment. On the other hand, the configuration of the second storage cell MCb in the second embodiment is the same as that of the second storage cell MCb described in the first embodiment.

[0150] Specifically, arsenic is doped into the silicon oxide film 51c. The As concentration in the silicon oxide film 51c is higher than that in the silicon oxide film 51b, and approximately equal to that in the silicon oxide film 51a. The thickness FT3 of the silicon oxide film 51c along the Z direction is thinner than the thickness FT2 of the silicon oxide film 51b. Therefore, the height of the first memory cell MCa in the second embodiment is lower than the height of the second memory cell MCb. Similar to the first embodiment, the threshold voltage of the selector SELa is lower than the threshold voltage of the selector SELb. Other configurations of the first memory cell MCa in the second embodiment are the same as those of the first memory cell MCa described in the first embodiment. Furthermore, other configurations of the memory system 1 in the second embodiment are the same as those in the first embodiment.

[0151] [2-2] Manufacturing method

[0152] Figure 23 This is a flowchart illustrating an example of a method for manufacturing the storage device 20 according to the second embodiment. Figures 24-28 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the storage device 20 according to the second embodiment, showing a cross-section including the first storage region RG1 and the second storage region RG2. Hereinafter, reference will be made as appropriate. Figure 23 An example of the method for forming selectors SELa and SELb and MTJ elements in the second embodiment will be described.

[0153] First, similar to the first embodiment, a lower electrode 50 and a silicon oxide film 51 are formed (step S10).

[0154] Next, as Figure 24 As shown, mask PR2 is formed (step S20). For example, mask PR2 is formed using photolithography. Mask PR2 covers the portion corresponding to the second memory region RG2. On the other hand, in mask PR2, there is an opening in the portion corresponding to the first memory region RG1. That is, the surface of the silicon oxide film 51 is exposed within the first memory region RG1.

[0155] Next, as Figure 25 As shown, a portion of the silicon oxide film 51 is etched (step S21). Specifically, an etching process using a mask PR2 is performed, etching the silicon oxide film 51 exposed at the opening of the mask PR2 (first storage region RG1), while the portion of the silicon oxide film 51 covered by the mask PR2 (second storage region RG2) is protected by the mask PR2. Thus, the thickness of the silicon oxide film 51 in the first storage region RG1 becomes thinner than the thickness of the silicon oxide film 51 in the second storage region RG2. The thickness of the silicon oxide film 51 in the first storage region RG1 corresponds to FT3, and the thickness of the silicon oxide film 51 in the second storage region RG2 corresponds to FT2.

[0156] Next, remove mask PR2 (step S22).

[0157] Next, as Figure 26 As shown, As ions are implanted into the silicon oxide film 51 (step S23). Specifically, an ion implantation process using As ions is performed with the mask PR2 removed, and arsenic is doped into the silicon oxide film 51 in the first storage region RG1 and the silicon oxide film 51 in the second storage region RG2, respectively. In this ion implantation process, although arsenic is doped into both the first storage region RG1 and the second storage region RG2, the As concentration in the first storage region RG1 differs from that in the second storage region RG2 depending on the thickness of the silicon oxide film 51. In this example, the thickness of the silicon oxide film 51 in the first storage region RG1 is thinner than that in the second storage region RG2; therefore, the As concentration of the silicon oxide film 51 in the first storage region RG1 is higher than that in the second storage region RG2. As a result, a silicon oxide film 51c is formed in the first storage region RG1, and a silicon oxide film 51b is formed in the second storage region RG2.

[0158] Next, as Figure 27 As shown, similarly to the first embodiment, a ferromagnetic layer 60, a non-magnetic layer 61, and a ferromagnetic layer 62 are formed (step S15). In the second embodiment, since the silicon oxide film 51c in the first storage region RG1 and the silicon oxide film 51b in the second storage region RG2 have different thicknesses, a horizontal difference may form between the first storage region RG1 and the second storage region RG2.

[0159] Next, as Figure 28 As shown, similarly to the first embodiment, the stacked structure is separated according to the memory cell MC (step S16). Specifically, by using etching processes such as hard mask HM, the ferromagnetic layer 62, non-magnetic layer 61, ferromagnetic layer 60, upper electrode 52, silicon oxide films 51c and 51b, and lower electrode 50 are each separated according to the memory cell MC. The memory cell MC formed in the first memory region RG1 corresponds to the memory cell MCa that includes the selector SELa using the silicon oxide film 51c. The memory cell formed in the second memory region RG2 corresponds to the memory cell MCb that includes the selector SELb using the silicon oxide film 51b.

[0160] Through the manufacturing processes described above, the selector SELa and SELb, as well as the memory cell MC, of ​​the second embodiment are formed. Furthermore, the impurities doped in the silicon oxide films 51c and 51b are activated by heat treatment following ion implantation. The timing for activating the impurities doped in the silicon oxide films 51c and 51b can be appropriately set. Additionally, different processes can be added between the processes described above, and the number and type of layers formed in steps S10 and S15 can be increased depending on the structure of the selector SEL and the resistive switching element MTJ. The hard mask HM can also be removed, and local bit lines LBL can be connected on the hard mask HM.

[0161] [2-3] Effects of the second embodiment

[0162] The storage system 1 described in the second embodiment above, like the first embodiment, can balance performance and storage capacity, maximizing chip performance. That is, the storage system 1 in the second embodiment, like the first embodiment, can improve the performance of the storage device 20.

[0163] [3] Other

[0164] In the manufacturing process of the memory device 20 according to the second embodiment, the number of ion implantation processes is less than that in the manufacturing process of the memory device 20 according to the first embodiment, and an etching process is added. Therefore, by selecting the first embodiment or the second embodiment according to the capacity of the manufacturing apparatus, the user can utilize the optimal manufacturing process corresponding to the equipment in the factory.

[0165] The structure of the memory cell MC described in the above embodiment is only one example. For example, the memory cell MC may also include other conductors. For example, a conductor may be inserted between the selector SEL and the source line SL, between the resistive switching element MTJ and the bit line BL, or between the selector SEL and the resistive switching element MTJ. The area, configuration, etc. of the first memory region RG1 and the second memory region RG2 can be appropriately changed. The storage device 20 may also have three or more memory regions RG with different sizes of the memory matrix MAT. The different sizes of the memory matrix MAT, subarray SA, etc. can be compared, for example, based on the area of ​​the cross-point type structure including multiple memory cells MC. The size of memory cell MCa and the size of memory cell MCb may also be different. As long as selectors SEL with different threshold voltages are used for the memory regions RG, it is sufficient.

[0166] In the above embodiments, the case of using an MRAM employing a magnetoresistive element as the storage device 20 was described as an example, but it is not limited to this. These embodiments can also be applied to other resistive random access memories such as ReRAM (Resistance Random Access Memory), PCM (Phase Change Memory), iPCM (Interfacial Phase Change Memory), and PRAM (Phase-change RAM). Depending on the type of resistive element used in the memory cell MC, the memory cell MC can store more than 2 bits of data. In this case, the resistive element included in the memory cell MC can have at least three resistive states. Furthermore, the above embodiments are applicable to selectors (SELs) used in cross-point constructed memory cell arrays, regardless of whether they are volatile or non-volatile memories.

[0167] In the above embodiment, the voltage applied to the source line SL (local source line LSL) corresponds to the voltage supplied by the drive circuit 24 to the read circuit 32 or the write circuit 33, which is applied to the local source line LSL via the global source line GSL and the row selection circuit RSC. The voltage applied to the bit line BL (local bit line LBL) corresponds to the voltage supplied by the drive circuit 24 to the read circuit 32 or the write circuit 33, which is applied to the local bit line LBL via the global bit line GBL and the column selection circuit CSC. The applied ground voltage, for example, corresponds to the wiring for which the ground voltage is applied, and is grounded via the sink circuit 31.

[0168] In this specification, "arsenic (As) concentration of selector SEL" refers to the As concentration of silicon oxide film 51. The distribution of As concentration within silicon oxide film 51 can be determined, for example, by secondary ion mass spectrometry (SIMS). The measured value of Ihalf is obtained, for example, by measuring the current leaking from other addresses (local bit lines LBL) while a local bit line LBL is selected and a voltage is applied. The write tolerance of memory cell MC is evaluated based on the number of times the data in the memory cell MC of the evaluated object has been rewritten.

[0169] In this specification, "connection" means electrical connection, excluding the possibility of intermediate connections via other components. "Subarray" may also be referred to as "memory area" or "memory cell array". "First memory area RG1" and "Second memory area RG2" may also be referred to as "first memory cell array" and "second memory cell array", respectively.

[0170] In this specification, "region" can also be considered as a configuration encompassed by the semiconductor substrate forming the memory device 20. For example, if the semiconductor substrate is specified to include a first memory region RG1 and a second memory region RG2, the first memory region RG1 and the second memory region RG2 are respectively associated with different regions above the semiconductor substrate. "Height" corresponds, for example, to the distance between the configuration of the object being measured and the semiconductor substrate in the Z direction. As a reference for "height," configurations other than the semiconductor substrate can also be used. "Height of memory cell MC" corresponds, for example, to the length in the Z direction between the bottom surface of the selector SEL and the upper surface of the resistive switching element MTJ. When comparing the height of memory cell MC, the height between memory cells MC can be compared at least based on the portion including the silicon oxide film 51 of the selector SEL and the resistive switching element MTJ. "Thickness" or "film thickness" corresponds to the thickness of the configuration being measured along the Z direction. The dimensions of the resistive switching element MTJ can be compared based on the area of ​​a plane parallel to the substrate or based on volume. "Wire length" is compared, for example, based on the conductor used in the portion of the memory cell array 30 that is configured as an intersection point.

[0171] While several embodiments of the invention have been described, these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the patent claims and their equivalents.

Claims

1. A storage device comprising: The storage cell array includes multiple first subarrays and multiple second subarrays; A plurality of first storage units are included in each of the plurality of first subarrays; A plurality of second storage units are included in each of the plurality of second subarrays; The first read circuit reads data from the plurality of first storage units; The second read circuit, unlike the first read circuit, reads data from the plurality of second storage units; The first write circuit writes data to the plurality of first memory cells; as well as The second write circuit, unlike the first write circuit, writes data to the plurality of second storage cells. The area of ​​the first subarray is different from the area of ​​the second subarray. Each of the plurality of first subarrays further includes a plurality of first bit lines and a plurality of first source lines. Each of the plurality of first memory cells is connected between a first bit line and a first source line, including a first resistive switching element and a first switching element connected in series between the first bit line and the first source line. Each of the plurality of second subarrays further includes a plurality of second bit lines and a plurality of second source lines. Each of the plurality of second memory cells is connected between a second bit line and a second source line, including a second resistive switching element and a second switching element connected in series between the second bit line and the second source line. The threshold voltage of the first switching element is different from the threshold voltage of the second switching element. The subarray of the first subarray and the second subarray, which includes the one with the lower threshold voltage of the first switching element and the second switching element, is used as a cache memory.

2. The storage device according to claim 1, The area of ​​the first subarray is smaller than the area of ​​the second subarray. The threshold voltage of the first switching element is lower than the threshold voltage of the second switching element.

3. The storage device according to claim 2, The first switching element includes a first silicon oxide film, the first silicon oxide film containing arsenic and electrically connected between the first bit line and the first source line. The second switching element includes a second silicon oxide film, the second silicon oxide film containing arsenic and electrically connected between the second bit line and the second source line. The concentration of arsenic contained in the first silicon oxide film is different from the concentration of arsenic contained in the second silicon oxide film.

4. The storage device according to claim 3, The first silicon oxide film contains arsenic at a concentration of 30 atomic percent or more. The concentration of arsenic contained in the second silicon oxide film is less than 10 atomic percent.

5. The storage device according to claim 3, The thickness of the first silicon oxide film is equal to the thickness of the second silicon oxide film.

6. The storage device according to claim 3, The thickness of the first silicon oxide film is thinner than that of the second silicon oxide film.

7. The storage device according to claim 6, The height of the first storage cell in the first direction is lower than the height of the second storage cell in the first direction.

8. The storage device according to claim 1, The dimensions of the first resistive switching element are equal to the dimensions of the second resistive switching element.

9. The storage device according to claim 1, The first resistive switching element and the second resistive switching element are both magnetoresistive switching elements. The magnetoresistive switching element has a first ferromagnetic layer, a non-magnetic layer disposed above the first ferromagnetic layer, and a second ferromagnetic layer disposed above the non-magnetic layer.

10. The storage device according to claim 1, The wiring length of the first bit line is shorter than that of the second bit line. The number of the first memory cells connected to the first bit line is less than the number of the second memory cells connected to the second bit line.

11. The storage device according to claim 1, The storage capacity of the second subarray is greater than that of the first subarray.

12. The storage device according to claim 1, The plurality of first subarrays and the plurality of second subarrays are formed on the same substrate. The area of ​​the plurality of second subarrays is greater than the area of ​​the plurality of first subarrays.

13. The storage device according to claim 1, The write tolerance of the first storage cell is higher than that of the second storage cell.

14. The storage device according to any one of claims 1 to 13, further comprising: Multiple first global bit lines connected to the plurality of first subarrays; Multiple first global source lines connected to the plurality of first subarrays; Multiple second global bit lines connected to the plurality of second subarrays; and Multiple second global source lines connected to the plurality of second sub-arrays, Each of the plurality of first subarrays is associated with a first global bit line and a first global source line, and further includes a first column select circuit and a first row select circuit, wherein the first column select circuit is selectively connected between the one first global bit line and the plurality of first bit lines, and the first row select circuit is selectively connected between the one first global source line and the plurality of first source lines. Each of the plurality of second subarrays is associated with a second global bit line and a second global source line, and further includes a second column selection circuit and a second row selection circuit, the second column selection circuit being able to selectively connect between the one second global bit line and the plurality of second bit lines, and the second row selection circuit being able to selectively connect between the one second global source line and the plurality of second source lines.

15. A storage system comprising: The storage device according to any one of claims 1 to 14; and A memory controller capable of controlling the memory device. The storage controller When an external host device commands the writing of a first piece of data that is shown to have a high access frequency, the storage device is commanded to write the first piece of data to any one of the plurality of first subarrays. If an external host device commands the writing of second data, which is shown to have a lower access frequency than the first data, the storage device is commanded to write the second data to any one of the plurality of second subarrays.

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