Method for manufacturing memory floating gate

Abstract

The application provides a manufacturing method of a memory floating gate. A substrate is provided, and an active region is formed on the substrate. A plurality of floating gate structures are formed on the active region. Then, a tunneling oxide layer covering the floating gate structures is formed on the substrate. An amorphous silicon layer, a titanium nitride layer and a first mask layer are sequentially stacked on the floating gate structures from bottom to top. A storage region and a non-storage region are defined by photolithography. The exposed first mask layer is etched and removed. A photoresist layer is removed. Then, the titanium nitride layer and the amorphous silicon layer on the non-storage region are etched and removed. A second mask layer covering the remaining first mask layer is formed. Part of the first and second mask layers is etched and removed, so that the remaining first and second mask layers or the first mask layer is reserved on the sidewall of the tunneling oxide layer. In the application, an amorphous silicon layer is deposited before the existing metal floating gate is deposited, so that a combined floating gate is formed, the potential barrier is reduced, and the purpose of reducing the erase voltage is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a floating gate for a memory. Background Technology

[0002] Current processes use vertical TIN as the floating gate material, and horizontal electric field-guided write operations and voltage-coupled erase operations at the tip of the TIN can greatly improve write and erase efficiency. However, the TIN metal material has a high work function and a large potential barrier (TIN / OX), which means that when using metal material as the floating gate, electrons need a higher operating voltage to be driven out of the TIN floating gate during the erase process. This places higher demands on the breakdown voltage of the peripheral circuit and increases the difficulty of the process.

[0003] To solve the above problems, a new method for fabricating floating gates in memory is needed. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing a floating gate for a memory, which solves the problem that the existing technology uses TIN metal material with a high work function and a large potential barrier, which causes electrons to be driven out of the TIN floating gate during the erasure process. This places high demands on the breakdown voltage of the peripheral circuit and increases the difficulty of the process.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a floating gate for a memory, comprising:

[0006] Step 1: Provide a substrate on which an active region is formed, and on which a plurality of floating gate structures are formed, and then form a tunneling oxide layer covering the floating gate structures on the substrate;

[0007] Step 2: Form an amorphous silicon layer, a titanium nitride layer, and a first mask layer stacked sequentially from bottom to top on the floating gate structure;

[0008] Step 3: Form a photoresist layer on the first mask layer, define the storage region and non-storage region by photolithography, and then open the photoresist layer on the non-storage region to expose the first mask layer underneath.

[0009] Step 4: Etch away the exposed first mask layer, remove the photoresist layer, and then etch away the titanium nitride layer and the amorphous silicon layer on the non-storage area;

[0010] Step 5: Form a second mask layer that covers the remaining first mask layer;

[0011] Step 6: Etch away part of the first and second mask layers, so that the remaining first and second mask layers or the first mask layer remain on the sidewall of the tunneling oxide layer, and the titanium nitride layer and the amorphous silicon layer outside the sidewall of the tunneling oxide layer are exposed.

[0012] Step 7: Etch away the exposed titanium nitride layer and the amorphous silicon layer, and then remove the remaining first and second mask layers or the first mask layer.

[0013] Preferably, the substrate in step one is a silicon substrate.

[0014] Preferably, the floating gate structure in step one consists of an oxide layer, a floating gate polysilicon layer, and a control gate polysilicon layer stacked sequentially from bottom to top.

[0015] Preferably, the material of the first mask layer in step two is silicon dioxide.

[0016] Preferably, in step two, amorphous silicon material is deposited on the floating gate structure, and then the amorphous silicon layer is formed by annealing.

[0017] Preferably, the annealing temperature in step two is 370 to 390 degrees Celsius.

[0018] Preferably, the thickness of the amorphous silicon layer in step two is 30 to 50 angstroms.

[0019] Preferably, the thickness of the titanium nitride layer in step two is 30 to 50 angstroms.

[0020] Preferably, the titanium nitride layer in step two is deposited at a temperature of 390 to 410 degrees Celsius.

[0021] Preferably, the thickness of the first mask layer in step two is 25 to 35 angstroms.

[0022] Preferably, the material of the second mask layer in step five is silicon dioxide.

[0023] Preferably, wet etching is used to remove the first and second mask layers in both steps four and six.

[0024] Preferably, the titanium nitride layer is removed by wet etching in steps four and seven, and then the amorphous silicon layer is removed by wet etching.

[0025] As described above, the method for manufacturing the floating gate of the memory according to the present invention has the following beneficial effects:

[0026] This invention reduces the erase voltage by depositing an amorphous silicon layer before depositing a conventional metal floating gate to form a combined floating gate, thereby lowering the potential barrier. Attached Figure Description

[0027] Figure 1 The diagram shown is a schematic representation of the substrate of this invention.

[0028] Figure 2 The diagram shown is a photolithography schematic of the present invention.

[0029] Figure 3 The diagram shows a schematic of the etching process to remove the first mask layer in the non-memory region according to the present invention.

[0030] Figure 4 The diagram shown illustrates the removal of the photoresist layer according to the present invention.

[0031] Figure 5 The diagram shows the etching process used in this invention to remove the titanium nitride layer and amorphous silicon layer from the non-memory region.

[0032] Figure 6 The diagram shown illustrates the formation of the second mask layer according to the present invention.

[0033] Figure 7 The diagram shows a schematic of etching away a portion of the titanium nitride layer and amorphous silicon layer in the storage region according to the present invention.

[0034] Figure 8 The diagram shown is a schematic representation of the process flow of this invention. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Please see Figure 8 This invention provides a method for manufacturing a floating gate for a memory, comprising:

[0037] Step 1: Provide a substrate 01, on which an active region is formed, and on which multiple floating gate structures 02 are formed, and then form a tunneling oxide layer 06 covering the floating gate structures 02 on the substrate 01.

[0038] In an embodiment of the present invention, the substrate 01 in step one is a silicon substrate 01.

[0039] In an embodiment of the present invention, the floating gate structure 02 in step one is composed of an oxide layer 021, a floating gate polysilicon layer 022 and a control gate polysilicon layer 023 stacked sequentially from bottom to top. The material of the oxide layer 021 is usually silicon dioxide.

[0040] Step 2, please refer to Figure 1 An amorphous silicon layer 03, a titanium nitride layer 04, and a first mask layer 05 are formed on the floating gate structure 02, stacked sequentially from bottom to top.

[0041] In an embodiment of the present invention, the material of the first mask layer 05 in step two is silicon dioxide, which can be formed by atomic vapor deposition.

[0042] In an embodiment of the present invention, in step two, amorphous silicon material is deposited on the floating gate structure 02, and then an amorphous silicon layer 03 is formed by annealing.

[0043] In an embodiment of the present invention, the annealing temperature in step two is 370 to 390 degrees Celsius.

[0044] In an embodiment of the present invention, the thickness of the amorphous silicon layer 03 in step two is 30 to 50 angstroms.

[0045] In an embodiment of the present invention, the thickness of the titanium nitride layer 04 in step two is 30 to 50 angstroms.

[0046] In an embodiment of the present invention, the titanium nitride layer 04 in step two is deposited at a temperature of 390 to 410 degrees Celsius.

[0047] In an embodiment of the present invention, the thickness of the first mask layer 05 in step two is 25 to 35 angstroms.

[0048] Step 3, please refer to Figure 2 A photoresist layer 07 is formed on the first mask layer 05. The storage region and the non-storage region are defined by photolithography. Then, the photoresist layer 07 on the non-storage region is opened, so that the first mask layer 05 underneath is exposed.

[0049] Step four, please refer to Figure 3 The first mask layer 05 is etched away to remove the exposed photoresist layer 07, forming a layer as shown in the image. Figure 4 The structure shown was then etched away to remove the titanium nitride layer 04 and the amorphous silicon layer 03 on the non-memory regions, forming a structure as shown. Figure 5 The structure shown;

[0050] In an embodiment of the present invention, step four involves removing the first mask layer using a wet etching method.

[0051] In an embodiment of the present invention, step four involves removing the titanium nitride layer 04 using a wet etching method, followed by removing the amorphous silicon layer 03 using a wet etching method.

[0052] Specifically, the titanium nitride layer O4 is removed by a mixed cleaning solution of NH4OH, H2O2 and H2O, and then the amorphous silicon layer O3 in the non-storage area is removed by NH4OH.

[0053] Step 5, please refer to Figure 6 This forms a second mask layer 08 that covers the remaining first mask layer 05;

[0054] In an embodiment of the present invention, the material of the second mask layer 08 in step five is silicon dioxide, which can be formed by atomic vapor deposition.

[0055] Step 6: Etch away part of the first and second mask layers, so that the remaining first and second mask layers or the first mask layer 05 layer are retained on the sidewall of the tunnel oxide layer 06, and the titanium nitride layer 04 and amorphous silicon layer 03 outside the sidewall of the tunnel oxide layer 06 expose the photoresist layer 07.

[0056] In an embodiment of the present invention, the first and second mask layers are removed by wet etching in step six.

[0057] Step 7: Etch away the exposed titanium nitride layer 04 and amorphous silicon layer 03. Here, the first and second mask layers or the first mask layer 05 can act as a protective layer for the titanium nitride layer 04 and amorphous silicon on the sidewalls of the trench. Then, remove the remaining first and second mask layers or the first mask layer 05 to form a structure as shown in the image. Figure 7 The structure shown.

[0058] In an embodiment of the present invention, in step seven, the titanium nitride layer 04 is removed by wet etching, and then the amorphous silicon layer 03 is removed by wet etching.

[0059] Specifically, the titanium nitride layer 04 is removed by a mixed cleaning solution of NH4OH, H2O2 and H2O, and then the amorphous silicon layer 03 at the top and bottom of the trench in the storage area is removed by NH4OH.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] In summary, this invention lowers the potential barrier by depositing an amorphous silicon layer before the existing metal floating gate deposition, thereby reducing the erase voltage. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a memory floating gate, comprising: At least comprising: Step one, providing a substrate, the substrate is formed with an active region, the active region is formed with a plurality of floating gate structures, then a tunneling oxide layer covering the floating gate structures is formed on the substrate; Step two, forming an amorphous silicon layer, a titanium nitride layer and a first mask layer successively from bottom to top on the floating gate structures, wherein the thickness of the amorphous silicon layer is 30 to 50 angstroms, the thickness of the titanium nitride layer is 30 to 50 angstroms; Step three, forming a photoresist layer on the first mask layer, defining a storage area and a non-storage area by photoetching, then opening the photoresist layer on the non-storage area, so that the first mask layer thereunder is exposed; Step four, etching to remove the exposed first mask layer, removing the photoresist layer, then etching to remove the titanium nitride layer and the amorphous silicon layer on the non-storage area; Step five, forming a second mask layer covering the remaining first mask layer; Step six, etching to remove part of the first and second mask layers, so that the remaining first and second mask layers or the first mask layer remain on the sidewall of the tunneling oxide layer, and the titanium nitride layer and the amorphous silicon layer outside the tunneling oxide layer sidewall are exposed; Step seven, etching to remove the exposed titanium nitride layer and amorphous silicon layer, then removing the remaining first and second mask layers or the first mask layer.

2. The method of claim 1, wherein: The substrate in step one is a silicon substrate.

3. The method of claim 1, wherein: The floating gate structure in step one is composed of an oxide layer, a floating gate polysilicon layer and a control gate polysilicon layer successively from bottom to top.

4. The method of claim 1, wherein: The material of the first mask layer in step two is silicon dioxide.

5. The method of claim 1, wherein: In step two, amorphous silicon material is deposited on the floating gate structure, then the amorphous silicon layer is formed by annealing.

6. The method of claim 5, wherein: The annealing temperature in step two is 370 to 390 degrees Celsius.

7. The method of claim 1, wherein: The titanium nitride layer in step two is deposited at a temperature of 390 to 410 degrees Celsius.

8. The method of claim 1, wherein: The thickness of the first mask layer in step two is 25 to 35 angstroms.

9. The method of claim 1, wherein: The material of the second mask layer in step five is silicon dioxide.

10. The method of claim 1, wherein: In step four and step six, the first and second mask layers are removed by wet etching.

11. The method of claim 1, wherein: In step four and step seven, the titanium nitride layer is removed by wet etching, then the amorphous silicon layer is removed by wet etching.

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