Test Structure and Test Method for Through-Silicon Via

Abstract

The present application provides a test structure and a test method for through-silicon vias. The test structure includes: a semiconductor substrate; at least one reference test unit located in the semiconductor substrate for outputting test data, including a reference test trench capacitor group and a through-silicon via structure, wherein the reference test trench capacitor group is distributed around the through-silicon via structure; a reference test unit located in the semiconductor substrate for outputting reference data, including a reference test trench capacitor group, and the reference test trench capacitor group has the same structure as the reference test trench capacitor group. The test structure and the test method can monitor the process impact on the dielectric layer during TSV fabrication, and estimate the electrical thickness and isolation ability of the TSV isolation layer by testing the resistance, capacitance, and leakage current between the test substrate and the TSV, which is helpful for assisting failure analysis when problems occur in the manufacturing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing, and in particular, to a test structure and a test method for through-silicon vias. Background Art

[0002] With the increase in the driving strength of semiconductor devices, the devices have higher current density and larger current transients, resulting in the chip being more sensitive to the fluctuations of the power supply voltage. The circuit needs to reduce the PDN impedance through decoupling capacitors and suppress noise through decoupling or bypass circuits. Therefore, it is necessary to control the parasitic resistance and inductance, and the decoupling capacitors must be close to the circuit. Therefore, in a packaging structure (2.5D Interposer) that applies a vertical interconnect through-silicon via (TSV) adapter board, a relatively large number of trench capacitors (DTC) and TSVs need to be integrated.

[0003] Since the TSV itself occupies a relatively large area and has a stress influence area, there is an urgent need to further miniaturize and improve the integration degree. During the manufacturing process of TSVs, there are many potential process problems. For example, there are a large number of plasma charges in processes such as dry etching, ashing process, and plasma-enhanced chemical vapor deposition (PECVD). These plasma charges accumulate in the isolation layer of the TSV, and in severe cases, tunneling current will be formed, damaging the isolation layer. In addition, there is also a problem of metal diffusion during the TSV filling preparation process, and these cannot be detected by traditional test structures. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a test structure for through-silicon vias, which can monitor the process effects on the dielectric layer of trench capacitors during the preparation of TSVs, and estimate the electrical thickness and isolation ability and other properties of the TSV isolation layer by testing the resistance, capacitance, and leakage current between the test substrate and the TSV, which is helpful for auxiliary failure analysis when problems occur in the manufacturing process.

[0005] To solve the above technical problem, this application provides a test structure for through-silicon vias, including: a semiconductor substrate; at least one reference test unit located in the semiconductor substrate for outputting test data, including a reference test trench capacitor group and a through-silicon via structure, wherein the reference test trench capacitor group is distributed around the through-silicon via structure; a reference test unit located in the semiconductor substrate for outputting reference data, including a reference test trench capacitor group, and the reference test trench capacitor group has the same structure as the reference test trench capacitor group.

[0006] In the embodiments of the present application, both the reference test trench capacitor group and the reference test trench capacitor group include: an inner trench test capacitor group, including a plurality of inner trench test capacitors distributed in a surrounding manner; an outer trench test capacitor group, including a plurality of outer trench test capacitors distributed around the inner trench test capacitor group.

[0007] In the embodiments of the present application, adjacent inner trench test capacitors are either connected or not connected.

[0008] In the embodiments of the present application, adjacent outer trench test capacitors are not connected.

[0009] In the embodiments of the present application, the inner trench test capacitors and the outer trench test capacitors are correspondingly arranged and distributed in parallel.

[0010] In the embodiments of the present application, the inner trench test capacitor includes: an inner trench located in the semiconductor substrate; a first inner electrode plate located on the bottom and side walls of the inner trench, and on a part of the semiconductor substrate; an inner dielectric layer located on the surface of the first inner electrode plate and exposing a part of the first inner electrode plate on the semiconductor substrate; a second inner electrode plate located on the surface of the inner dielectric layer and filling the inner trench; the second inner electrode plates of each inner trench test capacitor are connected in parallel.

[0011] In the embodiments of the present application, the test structure of the through-silicon via further includes a first measurement disk, and the second inner electrode plates of each inner trench test capacitor are connected in parallel and connected to the first measurement disk.

[0012] In the embodiments of the present application, the outer trench test capacitor includes: an outer trench located in the semiconductor substrate; a first outer electrode plate located on the bottom and side walls of the outer trench, and on a part of the semiconductor substrate; an outer dielectric layer located on the surface of the first outer electrode plate and exposing a part of the first outer electrode plate on the semiconductor substrate; a second outer electrode plate located on the surface of the outer dielectric layer and filling the outer trench; the second outer electrode plates of each outer trench test capacitor are connected in parallel.

[0013] The first inner electrode plate, the first outer electrode plate and the semiconductor substrate are connected in parallel and connected to the third measurement disk.

[0014] In the embodiments of the present application, the through-silicon via structure includes: at least one through-silicon via located in the semiconductor substrate; an isolation layer located on the bottom and side wall surfaces of the through-silicon via and higher than the surface of the semiconductor substrate; a conductive layer located on the surface of the isolation layer and filling the through-silicon via; the conductive layers of each through-silicon via structure are connected in parallel.

[0015] In the embodiments of the present application, the conductive layers of each through-silicon via structure are connected in parallel to the fourth measurement disk.

[0016] In an embodiment of the present application, the test structure of the through-silicon via includes a first reference test unit and a second reference test unit, and the number of through-silicon vias in the first reference test unit and the second reference test unit is different.

[0017] The technical solution of the present application also provides a method for testing a through-silicon via. Using the above-mentioned test structure of the through-silicon via, it includes: obtaining the test data output by the reference test unit and the reference data output by the reference test unit; comparing the test data and the reference data to obtain the deviation range of the test data; based on the deviation range, performing failure analysis on the dielectric layer and the through-silicon via.

[0018] In an embodiment of the present application, the test data and the reference data are one of capacitance value, leakage of capacitance, resistance, or current value.

[0019] The technical solution of the present application provides a new test structure and test method for through-silicon vias, which can detect the influence of the through-silicon via manufacturing process on the dielectric layer of the trench capacitance (DTC) and estimate the electrical thickness and isolation ability of the through-silicon via isolation layer, helping with auxiliary failure analysis when problems occur in the process. Moreover, the test structure of the through-silicon via has high sensitivity and its test results have high accuracy. Description of the Drawings

[0020] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive intent of the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0021] Figure 1 is a schematic structural diagram of the first reference test unit (open-loop structure) of an embodiment of the present application;

[0022] Figure 2 is a schematic structural diagram of the first reference test unit (closed-loop structure) of an embodiment of the present application;

[0023] Figure 3 is a schematic structural diagram of the second reference test unit (open-loop structure) of an embodiment of the present application;

[0024] Figure 4 is a schematic structural diagram of the second reference test unit (closed-loop structure) of an embodiment of the present application;

[0025] Figure 5 is a cross-sectional view taken along the Figure 2 dotted line L;

[0026] Figure 6 Schematic diagram of the (open-loop structure) of the benchmark test unit according to an embodiment of the present application;

[0027] Figure 7 Schematic diagram of the (closed-loop structure) of the benchmark test unit according to an embodiment of the present application. Specific embodiments

[0028] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but has the broadest scope consistent with the claims.

[0029] To monitor problems existing in the through-silicon via manufacturing process, an embodiment of the present application provides a test structure for through-silicon vias, and the through-silicon via test structure includes a semiconductor substrate, at least one reference test unit, and a benchmark test unit.

[0030] Reference Figure 1 , the reference test unit is located in the semiconductor substrate 100 and is used to output test data, and the test data can be at least one of a capacitance value, capacitance leakage, resistance, or breakdown voltage. The reference test unit includes a reference test trench capacitor group 200 and a through-silicon via structure 300, and the reference test trench capacitor group 200 is distributed around the through-silicon via structure 300.

[0031] The reference test trench capacitor bank 200 includes an inner trench test capacitor bank 210 and an outer trench test capacitor bank 220. The inner trench test capacitor bank 210 includes a plurality of inner trench test capacitors 211 distributed in a surrounding manner. The inner trench test capacitors 211 surround the through-silicon via structure 300. When the through-silicon via structure is formed by dry etching, a large amount of plasma is generated and diffused, and during the metal filling process, there is a problem of metal diffusion. Due to these reasons, the charges generated will enter the inner trench test capacitors 211, thereby changing the capacitance values of the inner trench test capacitors 211, and further causing the capacitance values at the reference test trench capacitor bank 200 to change. By testing the capacitance values of the reference test trench capacitor bank 200 and analyzing them, the leakage current situation of the through-silicon via structure 300 or the electrical thickness and isolation ability of the isolation layer of the through-silicon via structure 300 can be obtained. The number of the inner trench test capacitors 211 is determined according to the actual situation. In the embodiment of the present application, four inner trench test capacitors 211 are used to form the inner trench test capacitor bank 210 by surrounding. Adjacent inner trench test capacitors 211 are not connected to make the inner trench test capacitor bank 210 in an unclosed-loop structure, and the unclosed-loop structure can detect the vast majority of the leaked charges.

[0032] Since adjacent inner trench test capacitors 211 are not connected, the semiconductor substrate 100 exists between adjacent inner trench test capacitors 211, and the semiconductor substrate 100 is at a low potential. Therefore, when the charges move between adjacent inner trench test capacitors 211, they are preferentially conducted away by the semiconductor substrate 100, so the charges conducted away in this part cannot be detected by the inner trench test capacitors 211, affecting the accuracy of the detection result.

[0033] Please refer to Figure 2 , to improve the sensitivity and accuracy of the test structure, the unclosed-loop structure can be improved into a closed-loop structure, that is, adjacent inner trench test capacitors 211 are connected to each other. Since the inner trench test capacitors 211 surround the through-silicon via structure 300 seamlessly, the charges leaked from the through-silicon via structure 300 in all directions can be detected by the outer peripheral inner trench test capacitors 211.

[0034] Combined with Figure 1 and Figure 2, To further improve the sensitivity and accuracy of the test structure, an outer groove test capacitor group 220 may also be formed around the inner groove test capacitor group 210. The outer groove test capacitor group 220 includes a plurality of outer groove test capacitors 221 distributed around the inner groove test capacitor group 210. If the leaked charge does not enter the inner groove test capacitor group 210, it may also enter the outer groove test capacitor group 220. Since the inner groove test capacitor group 210 can adopt a closed-loop structure, for the outer groove test capacitor group 220, whether the adjacent outer groove test capacitors 221 are connected has little impact on the accuracy of the detection result. Therefore, the adjacent outer groove test capacitors 221 may not be connected.

[0035] The inner groove test capacitor 211 and the outer groove test capacitor 221 are correspondingly arranged and parallelly distributed. That is to say, the groove test capacitor 211 and the outer groove test capacitor 221 are arranged in pairs, and each pair of the groove test capacitor 211 and the outer groove test capacitor 221 is parallel to each other. Such a layout can make the process easier to implement and is most conducive to improving the integration degree.

[0036] The silicon through-hole structure 300 of the reference test unit may include at least one silicon through-hole. For example, the number of the silicon through-holes may be two, four, seven, etc. The number of the silicon through-holes in the silicon through-hole structure 300 is determined according to the actual situation.

[0037] In addition to the foregoing reference test unit, the test structure of the silicon through-hole in the embodiment of the present application may also include another reference test unit. For convenience, the foregoing reference test unit is referred to as the first reference test unit, and the other reference test unit is referred to as the second reference test unit.

[0038] Reference Figure 3 and Figure 4, the second reference test unit has the same main structure as the first reference test unit, including a reference test trench capacitor group 200 and a through-silicon via structure 300. The reference test trench capacitor group 200 includes an inner trench test capacitor group 210 and an outer trench test capacitor group 220. The inner trench test capacitor group 210 includes a plurality of inner trench test capacitors 211 distributed in a surrounding manner, and the outer trench test capacitor group 220 includes a plurality of outer trench test capacitors 221 distributed around the inner trench test capacitor group 210. Similar to the first reference test unit, the adjacent inner trench test capacitors 211 in the second reference test unit are either connected or not connected, so that the inner trench test capacitor group 210 forms a closed-loop or non-closed-loop structure, and the adjacent outer trench test capacitors are not connected. The number of through-silicon vias in the second reference test unit is at least one. For example, the number of through-silicon vias is two, four, seven, etc. The difference between the first reference test unit and the second reference test unit lies in the number of through-silicon vias in the through-silicon via structure 300. The number of through-silicon vias in the second reference test unit can be more than that in the first reference test unit or less than that in the first reference test unit, as long as the number of through-silicon vias in the first reference test unit and the second reference test unit is different, which can improve the universality of the through-silicon via test structure. Of course, in other embodiments, the through-silicon via test structure may further include a third reference test unit, the number of through-silicon vias in the third reference test unit is two, and other structures are similar to those of the second reference test unit and the first reference test unit. In the embodiment of the present application, the through-silicon via test structure includes a first reference test unit with four through-silicon vias and a second reference test unit with seven through-silicon vias.

[0039] The following introduces the specific structures of the inner trench test capacitor 211, the outer trench test capacitor 221 and the through-silicon via of the reference test unit. Cut along Figure 2 the dashed line L to obtain a cross-sectional view as shown in Figure 5 .

[0040] Refer to Figure 5 , the inner trench test capacitor 211 mainly includes an inner trench 211a, a first inner electrode 211b, an inner dielectric layer 211c and a second inner electrode 211d. Among them, the inner trench 211a is located in the semiconductor substrate 100, and the inner trench 211a can be formed by a conventional etching process. The depth of the inner trench 211a can be less than the depth of the through-silicon via 310, and the specific depths of the two are determined according to the actual situation.

[0041] In addition, the inner groove test capacitor 211 may further include a first inner dielectric layer 211e and a second inner dielectric layer 211f. The first inner dielectric layer 211e is located on the bottom surface and sidewall surface of the inner groove 211a and on the surface of a part of the semiconductor substrate 100. The second inner dielectric layer 211f is located on the surface of the first inner dielectric layer 211e. The first inner dielectric layer 211e and the second inner dielectric layer 211f are used to isolate the first inner electrode plate 211b and the semiconductor substrate 100 and prevent the metal in the first inner electrode plate 211b from diffusing. The material of the first inner dielectric layer 211e may include silicon oxide, and the material of the second inner dielectric layer 211f may include silicon nitride. The forming process of the first inner dielectric layer 211e and the second inner dielectric layer 211f may be a conventional deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0042] The first inner electrode plate 211b is located on the bottom and sidewalls of the inner groove 211a and on a part of the semiconductor substrate 100. Specifically, the first inner electrode plate 211b is located on the surface of the second inner dielectric layer 211f. The material of the first inner electrode plate 211b may include metals, such as copper, tungsten, etc. The thickness of the first inner electrode plate 211b is determined according to actual conditions. The process for forming the first inner electrode plate 211b may be a conventional deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0043] The inner dielectric layer 211c is located on the surface of the first inner electrode plate 211b and exposes a part of the first inner electrode plate 211b on the semiconductor substrate 100. The inner dielectric layer 211c can isolate the first inner electrode plate 211b and the second inner electrode plate 211d. The thickness of the inner dielectric layer 211c is determined according to specific process requirements. The process for forming the inner dielectric layer 211c may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0044] The second inner electrode plate 211d is located on the surface of the inner dielectric layer 211c and fills the inner groove 211a. The material of the second inner electrode plate 211d may be the same as that of the first inner electrode plate 211b. The thickness of the second inner electrode plate 211d is determined according to actual conditions and is not specially limited here. The forming process of the second inner electrode plate 211d may refer to that of the first inner electrode plate 211b. The second inner electrode plates 211d of the inner groove test capacitors 211 are connected in parallel and connected to the first measurement disk 410. Tests can be performed at the first measurement disk 410 to obtain relevant test data of the inner groove test capacitor group 210.

[0045] Continue to refer to Figure 5, the outer groove test capacitor 221 includes an outer groove 221a, a first outer electrode plate 221b, an outer dielectric layer 221c, and a second outer electrode plate 221d. The outer groove test capacitor 221 may further include a first outer dielectric layer 221e and a second outer dielectric layer 221f. The outer groove 221a may be formed by a conventional etching process. The depth of the outer groove 221a may be the same as or different from the depth of the inner groove 211a, which is specifically determined according to the actual situation. The first outer dielectric layer 221e is located on the bottom surface and sidewall surface of the outer groove 221a and on a part of the surface of the semiconductor substrate 100. The second outer dielectric layer 221f is located on the surface of the first outer dielectric layer 221e. The formation process of the first outer dielectric layer 221e and the second outer dielectric layer 221f may refer to that of the first inner dielectric layer 211e and the second inner dielectric layer 211f. The material of the first outer dielectric layer 221e may include silicon oxide, and the material of the second outer dielectric layer 221f may include silicon nitride. The first outer dielectric layer 221e and the second outer dielectric layer 221f can prevent metal diffusion in the first outer electrode plate 221b.

[0046] The first outer electrode plate 221b is located on the bottom and sidewall of the outer groove 221a and on a part of the semiconductor substrate 100. Specifically, the first outer electrode plate 221b may be located on the surface of the second outer dielectric layer 221f. The material of the first outer electrode plate 221b may include a metal, such as copper, tungsten, etc. The formation process of the first outer electrode plate 221b may refer to that of the first inner electrode plate 211b.

[0047] The outer dielectric layer 221c is located on the surface of the first outer electrode plate 221b and exposes a part of the first outer electrode plate 221b on the semiconductor substrate 100. The outer dielectric layer 221c is used to isolate the first outer electrode plate 221b and the second outer electrode plate 221d. The thickness of the outer dielectric layer 221c is determined according to the requirements of the actual process, and the formation process of the outer dielectric layer 221c may refer to that of the inner dielectric layer 211c.

[0048] The second outer electrode plate 221d is located on the surface of the outer dielectric layer 221c and fills the outer groove 221a. The thickness of the second outer electrode plate 221d may be determined according to the actual process, and its formation process may refer to that of the first outer electrode plate 221b. The second outer electrode plates of the outer groove test capacitors 221 are connected in parallel and connected to the second measurement disk 420. By testing the second measurement disk 420, relevant test data of the outer groove test capacitor group 220 can be obtained.

[0049] In an embodiment of the present application, the first inner electrode plate 211b and the first outer electrode plate 221b are connected in parallel with the semiconductor substrate 100 and are connected to the third measurement disk 430, and the third measurement disk 430 is a test common terminal.

[0050] Reference Figure 5 , the through-silicon via structure 300 includes at least one through-silicon via 310, and the through-silicon via 310 is located in the semiconductor substrate 100. Since the actual manufacturing process is to fabricate trench capacitors first and then TSVs, when fabricating TSVs, there are still other film layers (not shown) on the surface of the semiconductor substrate where the TSVs are located. Therefore, a part of the through-silicon via 310 structure is also located in other film layers on the surface of the semiconductor substrate 100, and the through-silicon via can be formed by an etching process. An isolation layer 320 is formed on the bottom and sidewall surfaces of the through-silicon via 310. The isolation layer 320 can be a laminated structure. For example, the isolation layer 320 can include a silicon oxide layer 321 on the bottom and sidewall surfaces of the through-silicon via 310 and a silicon nitride layer 322 on the surface of the silicon oxide layer 321. The silicon oxide layer 321 and the silicon nitride layer 322 can be formed by physical vapor deposition or chemical vapor deposition processes. Since a part of the structure of the through-silicon via 310 is located in other film layers on the surface of the semiconductor substrate 100, the isolation layer 320 is higher than the surface of the semiconductor substrate. The through-silicon via structure 300 further includes a conductive layer 330. The conductive layer 330 is located on the surface of the isolation layer 320 and fills the through-silicon via 310. The conductive layer 330 can be formed by physical vapor deposition, chemical vapor deposition, electroplating and other processes. The conductive layers 330 of each through-silicon via structure are connected in parallel and are connected to the fourth measurement disk 440.

[0051] During the fabrication process of the through-silicon via structure 300, for example, in processes such as dry etching, ashing, and plasma-enhanced chemical vapor deposition, a large amount of plasma charges will be generated, and some plasma charges will accumulate in the isolation layer 320, and in severe cases, a tunneling current will be formed, damaging the isolation layer 320. The test structure of the embodiment of the present application can detect the influence of the fabrication process of the through-silicon via structure 300 on the isolation layer 320, and can also estimate the electrical thickness and isolation ability of the isolation layer 320 by testing the resistance, capacitance, and leakage current between the semiconductor substrate 100 and the through-silicon via 310.

[0052] Reference Figure 6 and Figure 7 , the test structure of the through-silicon via of the embodiment of the present application further includes a reference test unit, and the reference test unit is used to output reference data, and the reference data can include one of a capacitance value, capacitance leakage, resistance, or current value.

[0053] The benchmark test unit is located in the semiconductor substrate 100 and includes a benchmark test trench capacitor group 500, which has the same structure as the reference test trench capacitor group 200. The benchmark test trench capacitor group 500 includes an inner trench test capacitor group 510 and an outer trench test capacitor group 520. The inner trench test capacitor group 510 includes a plurality of inner trench test capacitors 511 distributed in a surrounding manner, and the outer trench test capacitor group 520 includes a plurality of outer trench test capacitors 521 distributed around the inner trench test capacitor group 510. The connection states between adjacent inner trench test capacitors 511 and between adjacent outer trench test capacitors 521 in the benchmark test unit are the same as those between adjacent inner trench test capacitors 511 and between adjacent outer trench test capacitors 521 in the reference test unit.

[0054] Correspondingly, an embodiment of the present application further provides a method for testing through-silicon vias. Using the above-mentioned test structure of through-silicon vias, it mainly includes:

[0055] Step S1: Obtain the test data output by the reference test unit and the reference data output by the benchmark test unit;

[0056] Step S2: Compare the test data and the reference data to obtain the deviation range of the test data;

[0057] Step S3: Based on the deviation range, perform failure analysis on the dielectric layer and the through-silicon vias.

[0058] In some embodiments, by testing and comparing the capacitance values and leakage currents of the inner and outer two groups of trench detection capacitors of the benchmark test unit and the reference test unit, the process effects on the dielectric layer of the trench capacitors during the TSV fabrication are monitored.

[0059] In other embodiments, by testing the resistance, capacitance, and leakage current between the substrate and the TSV, the electrical thickness and isolation ability of the TSV isolation layer are deduced, which helps to perform failure analysis when problems occur during the manufacturing process.

[0060] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0061] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements.

[0062] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intermediate elements. In contrast, the term "directly" means without intermediate elements. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recited features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0063] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0064] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A test structure for a through-silicon via, characterized in that Comprising: A semiconductor substrate; At least one reference test unit located in the semiconductor substrate for outputting test data, including a reference test trench capacitor group and a through-silicon via structure, wherein the reference test trench capacitor group is distributed around the through-silicon via structure, and the reference test trench capacitor group includes an inner trench test capacitor group and an outer trench test capacitor group. The inner trench test capacitor group includes a plurality of inner trench test capacitors distributed in a surrounding manner, and the inner trench test capacitors surround the through-silicon via structure; the outer trench test capacitor group includes a plurality of outer trench test capacitors distributed around the inner trench test capacitor group, and adjacent outer trench test capacitors are not connected. The inner trench test capacitors and the outer trench test capacitors are correspondingly arranged and distributed in parallel; A reference test unit located in the semiconductor substrate for outputting reference data, including a reference test trench capacitor group, and the reference test trench capacitor group has the same structure as the reference test trench capacitor group.

2. The test structure of the through-silicon via according to claim 1, characterized in that, Adjacent inner trench test capacitors are either connected or not connected.

3. The test structure of the through-silicon via according to claim 1, characterized in that, The inner trench test capacitor includes: An inner trench located in the semiconductor substrate; A first inner electrode plate located on the bottom and side walls of the inner trench and on a part of the semiconductor substrate; An inner dielectric layer located on the surface of the first inner electrode plate and exposing a part of the first inner electrode plate on the semiconductor substrate; A second inner electrode plate located on the surface of the inner dielectric layer and filling the inner trench; The second inner electrode plates of each of the inner trench test capacitors are connected in parallel.

4. The test structure of the through-silicon via according to claim 3, wherein It further includes a first measurement disk, and the second inner electrode plates of each of the inner trench test capacitors are connected in parallel and connected to the first measurement disk.

5. The test structure of the through-silicon via according to claim 3, characterized in that, The outer trench test capacitor includes: An outer trench located in the semiconductor substrate; A first outer electrode plate located on the bottom and side walls of the outer trench and on a part of the semiconductor substrate; An outer dielectric layer located on the surface of the first outer electrode plate and exposing a part of the first outer electrode plate on the semiconductor substrate; A second outer electrode plate located on the surface of the outer dielectric layer and filling the outer trench; The second outer electrode plates of each of the outer trench test capacitors are connected in parallel.

6. The test structure of the through-silicon via according to claim 5, wherein, It further includes a second measurement disk, and the second outer electrode plates of each of the outer trench test capacitors are connected in parallel and connected to the second measurement disk.

7. The test structure of the through-silicon via according to claim 5, wherein The first inner electrode plate, the first outer electrode plate are connected in parallel with the semiconductor substrate and connected to a third measurement disk.

8. The test structure of the through-silicon via according to claim 1, characterized in that, The through-silicon via structure includes: At least one through-silicon via located in the semiconductor substrate; An isolation layer located on the bottom and side wall surfaces of the through-silicon via and higher than the surface of the semiconductor substrate; A conductive layer located on the surface of the isolation layer and filling the through-silicon via; The conductive layers of each of the through-silicon via structures are connected in parallel.

9. The test structure of the through-silicon via according to claim 8, characterized in that, The conductive layers of each of the through-silicon via structures are connected in parallel to a fourth measurement disk.

10. The test structure of the through-silicon via according to claim 1, wherein It includes a first reference test unit and a second reference test unit, and the number of through-silicon vias in the first reference test unit and the second reference test unit is different.

11. A test method for through-silicon vias, characterized in that, Adopting the test structure of the through-silicon via according to any one of claims 1 to 10, including: Obtaining the test data output by the reference test unit and the reference data output by the reference test unit; Compare the test data with the reference data to obtain the deviation range of the test data; Based on the deviation range, perform failure analysis on the dielectric layer and the through-silicon via.

12. The test method for the through-silicon via according to claim 11, wherein, The test data and the reference data are at least one of capacitance value, leakage current of the capacitor, resistance, or breakdown voltage.

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