A driving backplane, a display panel, and a manufacturing method of the driving backplane

Abstract

The present invention discloses a driving backplane, a display panel and a manufacturing method of the driving backplane. The driving backplane includes: a first insulating layer disposed on a side of a low-temperature polysilicon semiconductor layer and an oxide semiconductor layer away from a substrate; contact holes penetrating the first insulating layer include: a first via hole and a second via hole, the first via hole extending to a side of the low-temperature polysilicon semiconductor layer away from the substrate; the second via hole extending to a side of the oxide semiconductor layer away from the substrate; a connection hole is disposed at a position of the oxide semiconductor layer corresponding to the second via hole; a first electrode structure disposed in the first via hole contacts the low-temperature polysilicon semiconductor layer; a second electrode structure disposed in the second via hole and the connection hole forms a side contact with the oxide semiconductor layer in the connection hole. When manufacturing the driving backplane of the present invention, the patterning mask process steps can be reduced, and the process cost can be lowered.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a driving backplane, a display panel, and a manufacturing method of the driving backplane. Background Art

[0002] In recent years, AR (Augmented Reality) and VR (Virtual Reality) high-PPI (pixels per inch) products have received much attention in the display industry. However, due to reasons such as an increase in the metal wiring density, the aperture ratio and transmittance of AR and VR products are much lower than those of conventional products. To improve the aperture ratio and transmittance of AR and VR products, more complex process procedures need to be implemented, such as using LTPO (Low Temperature Polycrystalline Oxide) technology. However, since the LTPO technology integrates two types of TFTs (Thin Film Transistors), namely LTPS (Low Temperature Poly-Silicon) and Oxide, there are many process procedures in the manufacturing process, which in turn leads to an increase in production costs.

[0003] Therefore, how to optimize the manufacturing process of the driving substrate of the display panel that integrates two types of TFTs, LTPS and Oxide, has become an urgent problem to be solved at present. Summary of the Invention

[0004] In view of the above problems, the present invention provides a driving backplane, a display panel, and a manufacturing method of the driving backplane, which can reduce the process steps of the patterning mask, achieve process optimization, and reduce the process cost.

[0005] In a first aspect, the present application provides the following technical solution through an embodiment:

[0006] A driving backplane, comprising:

[0007] Substrate; the substrate includes a first region and a second region; a low-temperature polycrystalline silicon semiconductor layer disposed in the first region of the substrate; an oxide semiconductor layer disposed in the second region of the substrate; a first insulating layer disposed on a side of the low-temperature polycrystalline silicon semiconductor layer and the oxide semiconductor layer away from the substrate; a contact hole penetrating the first insulating layer; the contact hole includes: a first via hole and a second via hole, the first via hole extending to a side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate; the second via hole extending to a side of the oxide semiconductor layer away from the substrate; a connection hole is provided at a position of the oxide semiconductor layer corresponding to the second via hole; a first electrode structure disposed in the first via hole and in contact with the low-temperature polycrystalline silicon semiconductor layer; and a second electrode structure disposed in the second via hole and the connection hole and forming a side contact with the oxide semiconductor layer in the connection hole.

[0008] Optionally, the connection hole penetrates the oxide semiconductor layer.

[0009] Optionally, further includes:

[0010] A first gate insulating layer disposed on a side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate; a first gate and a light-shielding structure disposed on a side of the first gate insulating layer away from the substrate; the first gate is located in the first region, and the light-shielding structure is located in the second region; a second insulating layer disposed on a side of the first gate and the light-shielding structure away from the substrate; the oxide semiconductor layer is disposed on a side of the second insulating layer away from the substrate; a second gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate; and a second gate disposed between the second gate insulating layer and the first insulating layer; wherein, the first via hole further penetrates the second insulating layer and the second gate insulating layer.

[0011] Optionally, the contact hole further includes: a third via hole disposed on a side of the light-shielding structure away from the substrate, and a third electrode structure in contact with the light-shielding structure is disposed in the third via hole;

[0012] The driving backplane further includes: a third insulating layer disposed on a side of the first electrode structure, the second electrode structure and the third electrode structure away from the substrate; a bridging via hole is provided in the first insulating layer and the third insulating layer; a conductive bridging structure is disposed in the bridging via hole, and the conductive bridging structure is respectively connected to the third electrode structure and the second gate.

[0013] Optionally, further includes:

[0014] A buffer layer is disposed between the substrate and the low-temperature polysilicon semiconductor layer; wherein, the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer are disposed on the same layer.

[0015] In a second aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0016] A manufacturing method of a driving backplane, comprising:

[0017] Forming a low-temperature polysilicon semiconductor layer in a first region of a substrate and an oxide semiconductor layer in a second region; forming a first insulating layer on a side of the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer away from the substrate; covering a patterned mask on the first insulating layer, and forming a contact hole penetrating the first insulating layer; wherein, the contact hole includes: a first via formed on a side of the low-temperature polysilicon semiconductor layer away from the substrate, and a second via formed on a side of the oxide semiconductor layer away from the substrate; forming a first electrode structure in contact with the low-temperature polysilicon semiconductor layer in the first via, and forming a second electrode structure in contact with the oxide semiconductor layer in the second via.

[0018] Optionally, before forming the first electrode structure in contact with the low-temperature polysilicon semiconductor layer in the first via, further comprising:

[0019] Removing an oxide layer on a surface of the low-temperature polysilicon semiconductor layer at a bottom of the first via by wet etching, and etching the oxide semiconductor layer at a bottom of the second via to form a connection hole; forming the second electrode structure in contact with the oxide semiconductor layer in the second via includes: forming the second electrode structure in the second via and the connection hole, and making the second electrode structure form a side contact with the oxide semiconductor layer in the connection hole.

[0020] Optionally, etching the oxide semiconductor layer at a bottom of the second via to form a connection hole includes:

[0021] Etching and penetrating the oxide semiconductor layer at a bottom of the second via to form the connection hole.

[0022] Optionally, after forming the low-temperature polysilicon semiconductor layer and before forming the oxide semiconductor layer, further comprising:

[0023] A first gate insulating layer, a first gate, a light-shielding structure, and a second insulating layer are sequentially formed on a side of the low-temperature polysilicon semiconductor layer away from the substrate; wherein, the first gate is located in the first region, and the light-shielding structure is located in the second region; forming the oxide semiconductor layer includes: forming the oxide semiconductor layer in the second region on a side of the second insulating layer away from the substrate; after forming the oxide semiconductor layer and before forming the first insulating layer, further includes: sequentially forming a second gate insulating layer and a second gate on the oxide semiconductor layer.

[0024] Optionally, the contact hole further includes: a third via formed on a side of the light-shielding structure away from the substrate; when forming the first electrode structure and the second electrode structure, the manufacturing method further includes: forming a third electrode structure in contact with the light-shielding structure in the third via; after forming the first electrode structure and the second electrode structure, further includes: covering a third insulating layer on the first electrode structure, the second electrode structure, and the third electrode structure; etching the third insulating layer and the first insulating layer to form a via for connecting the third electrode structure and the second gate; forming a connecting structure in the via for electrically connecting the third electrode structure and the second gate.

[0025] Optionally, forming the low-temperature polysilicon semiconductor layer in the first region of the substrate and the oxide semiconductor layer in the second region includes:

[0026] Forming a buffer layer on one side of the substrate; forming a low-temperature polysilicon semiconductor layer in the first region on a side of the buffer layer away from the substrate and forming an oxide semiconductor layer in the second region; after forming the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer and before forming the first insulating layer, further includes: sequentially forming a first gate insulating layer, a first gate, a second gate, and a second insulating layer on the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer; wherein, the first gate is located in the first region and the second gate is located in the second region.

[0027] Optionally, forming the contact hole in the first insulating layer includes:

[0028] Dry-etching the first insulating layer under an oxygen-containing atmosphere condition to form the first via extending to the low-temperature polysilicon semiconductor layer and the second via extending to the oxide semiconductor layer; dry-etching an oxide layer on a surface of the low-temperature polysilicon semiconductor layer at a bottom of the first via under an oxygen-free atmosphere condition.

[0029] In a third aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0030] A display panel, characterized in that it includes the driving backplane described in any one of the foregoing first aspects; or includes a driving backplane manufactured by the manufacturing method of the driving backplane described in any one of the foregoing second aspects.

[0031] In the embodiments of the present invention, a driving backplane, a display panel, and a manufacturing method of the driving backplane are provided. Among them, for the driving backplane and its manufacturing method, a low-temperature polycrystalline silicon semiconductor layer is formed in a first region of a substrate, and an oxide semiconductor layer is formed in a second region; a first insulating layer is formed on a side of the low-temperature polycrystalline silicon semiconductor layer and the oxide semiconductor layer away from the substrate; a patterned mask is covered on the first insulating layer, and a contact hole is formed in the first insulating layer; wherein the contact hole includes: a first via formed on a side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate, and a second via formed on a side of the oxide semiconductor layer away from the substrate; a first electrode structure in contact with the low-temperature polycrystalline silicon semiconductor layer is formed in the first via, and a second electrode structure in contact with the oxide semiconductor layer is formed in the second via. When manufacturing the driving backplane in the embodiments of the present invention, during the process of forming the first via and the second via, only one patterned mask (mask) needs to be used, and it is not necessary to etch the first via and the second via successively, saving the process cost.

[0032] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically illustrates the specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figures 1 to 6 , and Figure 10 is a schematic structural diagram of the driving backplane corresponding to each step stage of the manufacturing method of the driving backplane in the embodiments of the present invention;

[0035] Figures 7 to 9 is a schematic diagram of the layer structure connection relationship of the driving backplane in the embodiments of the present invention;

[0036] Figures 11 to 18 is a schematic structural diagram of the driving backplane corresponding to each step stage of another manufacturing method of the driving backplane in the embodiments of the present invention;

[0037] Figures 19 to 23 Schematic diagram of the structure of another driving backplane corresponding to each step stage of the manufacturing method of the driving backplane in the embodiment of the present invention;

[0038] Figures 24 to 26 Schematic diagram of the connection relationship of the layer structure of another driving backplane in the embodiment of the present invention;

[0039] Figures 27 to 29 Schematic diagram of the structure of another driving backplane corresponding to each step stage of the manufacturing method of the driving backplane in the embodiment of the present invention;

[0040] Figure 30 Schematic diagram of the structure of a driving backplane in the embodiment of the present invention;

[0041] Figure 31 Schematic diagram of the structure of another driving backplane in the embodiment of the present invention. Detailed implementation manners

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0043] Various schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures and their relative sizes and positional relationships are merely exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0044] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0045] Please refer to Figure 1, for the driving backplane of a display panel integrating two types of TFTs, namely LTPS and Oxide, the present invention provides a manufacturing method for the driving backplane. In this manufacturing method, a buffer layer 12, a low-temperature polysilicon semiconductor layer 121 (P-Si), a first gate insulating layer 13, a first gate 131, a light-shielding structure 132 (Lightshielding, LS), a first insulating layer 14, an oxide semiconductor layer 141, a second gate insulating layer 15, a second gate 151, and a second insulating layer 16 are sequentially formed on a substrate 11. Among them, the oxide semiconductor layer 141 can be indium gallium zinc oxide (IndiumGallium Zinc Oxide, IGZO) in this embodiment, but it is not limited thereto. The substrate 11 is divided into a GOA (Gate Driver on Array) region and a Pixel region. Among them, the low-temperature polysilicon semiconductor layer 121 and the first gate 131 are located in the GOA region, and the oxide semiconductor layer 141, the light-shielding structure 132, and the second gate 151 are located in the Pixel region.

[0046] Next, a first mask layer (not shown in the figure) is covered on the side of the second insulating layer 16 away from the substrate 11. The first mask layer is used to etch and form a first via 1211 corresponding to the low-temperature polysilicon semiconductor layer 121, and a second via 1321 corresponding to the light-shielding structure 132, as Figure 2 shown. Further, in order to improve the contact resistance on the surface of the low-temperature polysilicon semiconductor layer 121 and avoid damage to the oxide semiconductor layer 141 by BOE Etch (Buffered Oxide Etch); therefore, when the via corresponding to the oxide semiconductor layer 141 is not opened, the surface oxide at the via position of the low-temperature polysilicon semiconductor layer 121 is removed by BOE Etch. At this time, since the via corresponding to the oxide semiconductor layer 141 is not opened, damage to the oxide semiconductor layer 141 can be avoided.

[0047] Then, a second mask layer (not shown in the figure) is covered on the side of the second insulating layer 16 away from the substrate 11. The second mask layer is used to etch and form a third via 1411 corresponding to the oxide semiconductor layer 141, and a fourth via 1511 corresponding to the second gate 151, as Figure 3 shown.

[0048] Next, a conductive material is formed in these vias. After filling the vias corresponding to the low-temperature polysilicon semiconductor layer 121 and the oxide semiconductor layer 141 with the conductive material, the corresponding first electrode structure 1212 and second electrode structure 1412 are formed; the first electrode structure 1212 can be used as the source / drain electrode (SD) of the low-temperature polysilicon semiconductor layer 121, and the second electrode structure 1412 can be used as the source / drain electrode of the oxide semiconductor layer 141. After filling the vias corresponding to the second gate 151 and the light-shielding structure 132 with the conductive material and forming the overlapping structure 1322, the second gate 151 and the light-shielding structure 132 are connected to form a double-gate structure of the oxide semiconductor layer 141, as Figure 4 shown.

[0049] Next, a third insulating layer 17 is covered on the side of the second insulating layer 16 away from the substrate 11, and then the third insulating layer 17 and the second insulating layer 16 are etched to form a fifth via 1413 connected to the oxide semiconductor layer 141, as Figure 5 shown; a conductive material is filled in the fifth via 1413 to form a third electrode structure 1414, and the third electrode structure 1414 is led out from the fifth via 1413 to connect to the electrode of the pixel structure, as Figure 6 shown.

[0050] Specifically, the partial structural relationship of the driving backplane can be referred to Figure 7 , 8 and shown in FIG. 9. Among them, in Figure 7 , the low-temperature polysilicon semiconductor layer 121 in the GOA region and the first gate 131 located on the side of the low-temperature polysilicon semiconductor layer 121 away from the substrate 11 are shown; both ends of the low-temperature polysilicon semiconductor layer 121 lead out traces in the direction away from the substrate 11 through the first electrode structure 1212 provided in the first via 1211. In Figure 8 , it is shown that the oxide semiconductor layer 141 in the Pixel region is located between the second gate 151 and the light-shielding structure 132; one end of the oxide semiconductor layer 141 leads out in the direction away from the substrate 11 through the second electrode in the third via 1411, and the other end leads out in the direction away from the substrate 11 through the third electrode structure 1414 in the fifth via 1413. In Figure 9 , it is shown that the light-shielding structure 132 and the second gate 151 in the Pixel region are respectively led out and connected in the direction away from the substrate 11 through the overlapping structure 1322 in the second via 1321 and the fourth via 1511.

[0051] Finally, a planarization layer 18 and a passivation layer 19 are formed on the side of the second insulating layer 16 away from the substrate 11; to facilitate the subsequent manufacture of the corresponding pixel structure, for example, manufacturing the corresponding pixel electrode 181, common electrode 191, pixel support 192, etc., asFigure 10 as shown

[0052] In this implementation, two mask layers are used when forming vias corresponding to the low-temperature polysilicon layer and the oxide semiconductor layer 141 respectively. The first mask layer is used to form the via corresponding to the low-temperature polysilicon semiconductor layer 121, and the second mask layer is used to form the via corresponding to the oxide semiconductor layer 141. Therefore, the entire process is relatively complex, which is not conducive to the control of manufacturing costs.

[0053] In another embodiment of the present invention, another manufacturing method of a driving backplane is also provided, which can be used to manufacture the driving backplane of a display panel integrating two types of TFTs, LTPS and Oxide; the pixel region corresponding to the driving backplane can be a single-gate structure or a double-gate structure. In this manufacturing method, only one patterning mask process is required to etch and form the vias corresponding to the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer, that is, only one exposure process is required to open the vias corresponding to the two types of semiconductor structures, which simplifies the manufacturing process and can significantly reduce the manufacturing cost.

[0054] Furthermore, although using one patterning mask process for etching in the manufacturing process reduces the process steps and the production cost. However, it is found through analysis that there is certain erosion damage to the oxide semiconductor layer at the bottom of the via, and this damage will cause certain problems such as poor contact and unstable performance defects. Therefore, in this application, the following technical problems also need to be solved: how to avoid damaging the oxide semiconductor layer during the process of forming vias using one patterning mask. Or, after the oxide semiconductor layer is damaged during the process of forming vias using one patterning mask, how to remedy the damaged oxide semiconductor layer to avoid generating unstable defects.

[0055] Therefore, in subsequent embodiments of the present invention, in the case of one patterning mask, an oxygen-containing gas etching is used to form vias corresponding to the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer; then, a gas without oxygen is used to etch the oxide layer on the surface of the low-temperature polysilicon semiconductor layer to avoid damaging the oxide semiconductor layer. In addition, in subsequent embodiments of the present invention, in the case of only using one patterning mask, the oxide semiconductor layer that may be damaged is etched until it penetrates; then the formed electrode is connected to the oxide semiconductor layer in a side-contact manner, thereby compensating for unstable defects such as poor contact caused by the damage to the oxide semiconductor layer. The following is further illustrated through specific examples.

[0056] 1. For the driving backplane with a single-gate structure:

[0057] First, a substrate 21 is provided; the substrate 21 can be a glass substrate; of course, it is not limited thereto, and other common organic or inorganic substrate materials can also be used, such as a flexible substrate 21 PI (Polyimide). The substrate 21 can be divided into a first region BM and a second region AA, as Figure 11 shown; it can be understood that either the first region BM or the second region AA is a GOA region, and the other is a Pixel region. In this embodiment, the first region BM is taken as the GOA region and the second region AA is taken as the Pixel region as an example for illustration.

[0058] Next, a buffer layer 22 is formed on the substrate 21; then, a low-temperature polysilicon semiconductor layer 221 is formed in the first region BM on the side of the buffer layer 22 away from the substrate 21, and an oxide semiconductor layer 222 is formed in the second region AA on the side of the buffer layer 22 away from the substrate 21, as Figure 12 shown. The low-temperature polysilicon semiconductor layer 221 and the oxide semiconductor layer 222 can be located in different layers or in the same layer; the low-temperature polysilicon semiconductor layer 221 and the oxide semiconductor layer 222 can be fabricated in the same layer to reduce process steps. It can be understood that both the low-temperature polysilicon semiconductor layer 221 and the oxide semiconductor layer 222 are patterned structures.

[0059] Then, a first gate insulating layer 23, a first gate 231, a second gate 232, and an insulating layer are sequentially formed on the side of the low-temperature polysilicon semiconductor layer 221 and the oxide semiconductor layer 222 away from the substrate 21, as Figure 13 shown. The first gate 231 is located in the first region BM and is used as the gate of the low-temperature polysilicon semiconductor layer 221, and the second gate 232 is located in the second region AA and is used as the gate of the oxide semiconductor layer 222. The first gate insulating layer 23 can be used to isolate the first gate 231 from the low-temperature polysilicon semiconductor layer 221 and to isolate the second gate 232 from the oxide semiconductor layer 222. Further, since the gate corresponding to the oxide semiconductor layer 222 is a single-gate structure, in this embodiment, the first gate 231 and the second gate 232 can be fabricated in the same layer to reduce process steps. In some implementation manners, the insulating layer can include a first insulating layer 24 and a second insulating layer 25. The second insulating layer 25 is formed on the side of the first gate insulating layer 23 away from the substrate 21 and covers the first gate 231 and the second gate 232, and the first insulating layer 24 is formed on the side of the second insulating layer 25 away from the substrate 21.

[0060] Then, since contact holes corresponding to the low-temperature polysilicon semiconductor layer 221 and the oxide semiconductor layer 222 need to be formed through a single patterning mask, the following process method can be adopted.

[0061] One way is to protect the oxide semiconductor layer 222 and avoid process damage to the oxide semiconductor layer 222. The method is as follows:

[0062] First, a patterned mask (not shown in the figure) is covered on the first insulating layer 24, and contact holes are formed in the first insulating layer 24; wherein, the contact holes include: a first via 2211 formed on the side of the low-temperature polycrystalline silicon semiconductor layer 221 away from the substrate 21, and a second via 2221 formed on the side of the oxide semiconductor layer 222 away from the substrate 21, as Figure 14 shown. It can be understood that the first via 2211 penetrates through the first insulating layer 24 and the second insulating layer 25, and its bottom extends to the low-temperature polycrystalline silicon semiconductor layer 221; similarly, the second via 2221 penetrates through the first insulating layer 24 and the second insulating layer 25, and its bottom extends to the oxide semiconductor layer 222. In some alternative implementation manners, dry etching of the first insulating layer 24 can be performed under an oxygen-containing atmosphere condition to form the first via 2211 extending to the polycrystalline silicon semiconductor layer and the second via 2221 extending to the oxide semiconductor layer 222.

[0063] Among them, the oxygen-containing atmosphere condition can include any one of the following:

[0064] CF 4 and O 2 ; SF 6 and O 2 ; and CHF 3 and O 2 .

[0065] Since the process of etching the contact holes is carried out under an oxygen-containing atmosphere condition, an oxide layer may be formed on the low-temperature polycrystalline silicon semiconductor layer 221. In order to improve the contact resistance and ensure good electrical contact; then, the oxide layer on the surface of the low-temperature polycrystalline silicon semiconductor layer 221 at the bottom of the first via 2211 is removed. In some alternative implementation manners, the oxide layer on the surface of the low-temperature polycrystalline silicon semiconductor layer 221 at the bottom of the first via 2211 can be etched off under an oxygen-free atmosphere condition.

[0066] Among them, the oxygen-free atmosphere condition can include any one of the following:

[0067] CF 4 ; SF 6 ; CHF 3 ; CF 4 and Ar; SF 6 and Ar; CHF 3 .

[0068] Through the above dry etching process, contact holes are etched in the first insulating layer 24 by a gas containing O 2 ; then, by a gas without O2 The gas removes the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 221. The use of the BOE Etch process can be avoided, and the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 221 can be removed, thereby avoiding damage to the oxide semiconductor layer 222 during the BOE Etch process.

[0069] Next, a first electrode structure 2212 in contact with the low-temperature polysilicon semiconductor layer 221 is formed in the first via 2211, and a second electrode structure 2222 in contact with the oxide semiconductor layer 222 is formed in the second via 2221, as Figure 15 shown. Since the oxide layer on the surface of the low-temperature polysilicon semiconductor is removed by two-step dry etching with and without oxygen in the previous steps, and damage to the oxide semiconductor layer 222 is avoided at the same time; therefore, the first electrode structure 2212 can form good electrical contact with the low-temperature polysilicon semiconductor layer 221 at the bottom of the first via 2211; the second electrode structure 2222 can also form good electrical contact with the oxide semiconductor layer 222 at the bottom of the second via 2221.

[0070] Next, a third insulating layer 26 is covered on the side of the first insulating layer 24 away from the substrate 21, and the third insulating layer 26 is etched to form a third via 2223; a third electrode structure 2224 is formed in the third via 2223 to serve as the source / drain lead-out of the oxide semiconductor layer 222, as Figure 16 shown.

[0071] Another implementation method is not to protect the oxide semiconductor layer 222. The method is as follows:

[0072] First, a patterned mask is covered on the first insulating layer 24, and contact holes are formed on the first insulating layer 24; it can be realized by existing etching processes without limitation. Then, the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 221 at the bottom of the first via 2211 is removed, and the oxide semiconductor layer 222 at the bottom of the second via 2221 is etched to form a connection hole 2227. In some implementation methods, the BOE Etch process can be used to remove the oxide layer and at the same time etch the oxide semiconductor layer 222 to form a connection hole 2227, as Figure 17 shown. Finally, a second electrode structure 2222 is formed in the second via 2221 and the connection hole 2227, and the second electrode structure 2222 forms a side contact with the oxide semiconductor layer 222 in the connection hole 2227, as Figure 18As shown. By etching the oxide semiconductor layer 222 until it penetrates, thus, with respect to the area at the bottom of the second via 2221, the oxide semiconductor layer 222 has a specifically larger annular side area in the connection hole 2227, thereby effectively improving the contact resistance between the second electrode structure 2222 and the oxide semiconductor layer 222 and avoiding unstable defects caused by damage to the oxide semiconductor layer 222 during the process.

[0073] Furthermore, in some implementation manners, when etching the oxide semiconductor layer 222, the oxide semiconductor layer 222 can be etched through, that is, the connection hole 2227 is a connection hole 2227 that penetrates the oxide semiconductor layer 222; thereby ensuring that the second electrode structure 2222 and the oxide semiconductor layer 222 form a better side contact structure.

[0074] Furthermore, in some implementation manners, after etching the oxide semiconductor layer 222 through, side erosion of the oxide semiconductor layer 222 in the connection hole 2227 should be avoided; that is to say, the aperture at the bottom of the connection hole 2227 should be less than or equal to the aperture at the bottom of the second via 2221, so as to ensure that after forming the second electrode structure 2222, the side contact formed between the second electrode structure 2222 and the oxide semiconductor layer 222 is more stable and reliable.

[0075] In a specific implementation manner, the slope angle of the second via 2221 formed above the oxide semiconductor layer 222 can be controlled between 70° and 80°. When the oxide semiconductor layer 222 is etched through by BOE Etch, the slope angle of the oxide semiconductor layer 222 can be controlled between 70° and 90°; the sizes of the second via 2221 and the connection hole 2227 can be controlled between 2.0u and 2.5u. In this implementation manner, by controlling the diameter and slope of the via, the stability of each film layer structure during the manufacturing process can be ensured, collapse can be avoided, and the process yield can be improved.

[0076] Through the above process method, the manufacturing of the contact hole and the electrode structure can also be completed by only using one patterning mask, which simplifies the manufacturing process and reduces the production cost.

[0077] 2. For the driving backplane with a double-gate structure:

[0078] Please refer to Figure 19, similar to the process steps corresponding to the aforementioned single-gate structure, first, a substrate 31 is provided; then, a buffer layer 32 is formed on the substrate 31; then, a low-temperature polysilicon semiconductor layer 321 is formed in a first region BM corresponding to the side of the buffer layer 32 away from the substrate 31, and an oxide semiconductor layer 351 is formed in a corresponding second region AA. Specifically, different from the process steps of the single-gate structure in the aforementioned example, since a double-gate structure corresponding to the oxide semiconductor layer 351 needs to be formed in this example, the low-temperature polysilicon semiconductor layer 321 and the oxide semiconductor layer 351 can be located in different layers, such as Figure 19 as shown.

[0079] In some implementation manners, after the buffer layer 32 is formed, a low-temperature polysilicon semiconductor layer 321 can be formed on the surface of the buffer layer 32 away from the substrate 31. Then, a first gate insulating layer 33 is covered on the low-temperature polysilicon semiconductor layer 321; then, a first gate 331 and a light-shielding structure 332 are formed on the first gate insulating layer 33, and the first gate 331 and the light-shielding structure 332 can be in the same layer. Among them, the first gate 331 is located in the first region BM, and the first gate 331 can be used as the gate of the low-temperature polysilicon semiconductor layer 321; the light-shielding structure 332 is located in the second region AA and can be used as the back-gate structure of the oxide semiconductor layer 351. Further, a second insulating layer 35 is covered on the first gate 331 and the light-shielding structure 332; then, an oxide semiconductor layer 351 is formed in the second region AA on the side of the second insulating layer 35 away from the substrate 31, and a second gate insulating layer 36 is covered on the side of the oxide semiconductor layer 351 away from the substrate 31; then, a first insulating layer 34 is covered on the side of the second gate 361 away from the substrate 31, such as Figure 19 as shown. Next, contact holes corresponding to the low-temperature polysilicon semiconductor layer 321 and the oxide semiconductor layer 351 are opened in the film layer structure manufactured above. Two specific ways to form the contact holes are provided below:

[0080] In some optional implementation manners, protection of the oxide semiconductor layer 351 is considered during the formation of the contact holes. In some optional implementation manners, the manufacturing method is as follows:

[0081] First, a patterned mask is covered on the first insulating layer 34, and contact holes are formed in the first insulating layer 34. Among them, the contact holes include: a first via hole 3211 formed on the side of the low-temperature polysilicon semiconductor layer 321 away from the substrate 31, and a second via hole 3511 formed on the side of the oxide semiconductor layer 351 away from the substrate 31. It can be understood that the first via hole 3211 penetrates the first insulating layer 34, the second gate insulating layer 36, and the second insulating layer 35, and its bottom extends to the low-temperature polysilicon semiconductor layer 321; the second via hole 3511 penetrates the first insulating layer 34, and its bottom extends to the oxide semiconductor layer 351. Further, the contact holes may further include: a third via hole 3321 formed on the side of the light-shielding structure 332 away from the substrate 31; this third via hole 3321 can be used to connect the corresponding back gate (light-shielding structure 332) of the oxide semiconductor layer 351, such as Figure 20 shown.

[0082] Further, the first insulating layer 34 can be dry-etched under an oxygen-containing atmosphere condition to form the first via hole 3211 extending to the polysilicon semiconductor layer and the second via hole 3511 extending to the oxide semiconductor layer 351. Then, the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 321 at the bottom of the first via hole 3211 is removed. The oxide layer on the surface of the low-temperature polysilicon semiconductor layer 321 at the bottom of the first via hole 3211 can be etched off under an oxygen-free atmosphere condition. The use of the BOE Etch process is avoided, so that while improving the contact resistance of the surface of the low-temperature polysilicon semiconductor layer 321, the oxide semiconductor layer 351 is protected from being damaged.

[0083] For the specific implementation of the two-step process of the above dry-etching process, reference can be made to the description in the driving backplane example of the aforementioned single-gate structure, which will not be elaborated in this example.

[0084] Then, a first electrode structure 3212 in contact with the low-temperature polysilicon semiconductor layer 321 is formed in the first via hole 3211, a second electrode structure 3512 in contact with the oxide semiconductor layer 351 is formed in the second via hole 3511, and a third electrode structure 3322 in contact with the light-shielding structure 332 is formed in the third via hole 3321, such as Figure 21 shown. Since, in the previous steps, the oxide layer on the surface of the low-temperature polysilicon semiconductor is removed through two-step dry etching with oxygen and without oxygen, and at the same time, the damage to the oxide semiconductor layer 351 is avoided; therefore, the first electrode structure 3212 can form a good electrical contact with the low-temperature polysilicon semiconductor layer 321 at the bottom of the first via hole 3211; the second electrode structure 3512 can also form a good electrical contact with the oxide semiconductor layer 351 at the bottom of the second via hole 3511; the third electrode structure 3322 can also form a good electrical contact with the light-shielding structure 332.

[0085] Next, a third insulating layer 37 is covered on the first electrode structure 3212, the second electrode structure 3512, and the third electrode structure 3322. It can be understood that the third insulating layer 37 covers the side of the first insulating layer 34 away from the substrate 31 and covers the ends of the first electrode structure 3212, the second electrode structure 3512, and the third electrode structure 3322 away from the substrate 31. Further, the third insulating layer 37 and the first insulating layer 34 are etched to form a via hole 3611 for connecting the third electrode structure 3322 and the second gate 361, as Figure 22 shown. Then, a connection structure 3612 is formed in the via hole 3611 to electrically connect the light-shielding structure 332 and the second gate 361, as Figure 23 shown.

[0086] In the above manufacturing process, the via hole 3611 is etched after the third electrode structure 3322 is formed. Therefore, the depth of etching the third via hole 3321 can be accurately controlled, and the second gate 361 will not be damaged; good electrical contact can be ensured after the connection structure 3612 is formed. When the first via hole 3211 and the second via hole 3511 are etched to form the third via hole 3321, since there is only the first gate insulating layer 33 between the low-temperature polysilicon semiconductor layer 321 and the light-shielding structure 332, the thickness difference between the low-temperature polysilicon semiconductor layer 321 and the light-shielding structure 332 is small, and the light-shielding structure 332 is hardly damaged during the formation of the first via hole 3211, the second via hole 3511, and the third via hole 3321. In addition, since there is a large thickness difference (the second insulating layer 35 and the second gate insulating layer 36) between the light-shielding structure 332 and the second gate 361, by forming the third via hole 3321 and the via hole 3611 separately, it is possible to avoid damaging or etching through the second gate 361 in order to etch through the first insulating layer 34, the second gate insulating layer 36, and the second gate 361.

[0087] Further, when the via hole 3611 is formed, a fourth via hole 3513 can be formed simultaneously. The bottom of the fourth via hole 3513 extends to the oxide semiconductor layer 351, as Figure 22 shown; then when the connection structure 3612 is formed, a fourth electrode structure 3514 is formed in the fourth via hole 3513. The fourth electrode structure 3514 is in surface electrical contact with the oxide semiconductor layer, as Figure 23 shown. The fourth electrode structure 3514 and the second electrode structure 3512 can serve as the source / drain electrodes of the oxide semiconductor layer 351.

[0088] To make the structure of the driving backplane of the double-gate structure in the above example easier to understand, the following is illustrated by Figure 24 、 25 and 26;

[0089] In Figure 24 it is shown that in the first region BM, a first gate 331 is provided on the side of the low-temperature oxide semiconductor layer 351 away from the substrate 31 to control the channel; electrodes in the first vias 3211 at both ends of the low-temperature oxide semiconductor layer 351 are led out in a direction away from the substrate 31 for routing.

[0090] In Figure 25 it is shown that in the second region AA, dual-gate structures corresponding to the oxide semiconductor layer 351 are located on its upper and lower sides to control the channel of the oxide semiconductor layer 351; that is, the light-shielding structure 332 is located on the side of the oxide semiconductor layer 351 close to the substrate 31, and the second gate 361 is located on the side of the oxide semiconductor layer 351 away from the substrate 31. A second electrode structure 3512 formed in the second via 3511 is led out in a direction away from the substrate 31 and connected to the corresponding common electrode; a fourth electrode structure 3514 formed in the fourth via 3513 is led out in a direction away from the substrate 31 and can be used to connect to the electrode of the pixel structure.

[0091] In Figure 26 it is shown that in the second region AA, the light-shielding structure 332 is led out in a direction away from the substrate 31 through the third electrode structure 3322 in the overlapping via 3611 and connected to the second gate 361 through the overlapping structure 3612.

[0092] In some alternative implementation manners, the oxide semiconductor layer 351 is not protected during the formation of the contact holes, and the manufacturing method is as follows:

[0093] Different from the manufacturing method for protecting the oxide semiconductor layer 351 of the dual-gate structure in the previous example: in this implementation method, a patterned mask is first covered on the first insulating layer 34, and contact holes are formed in the first insulating layer 34; it can be realized by using existing etching processes, without limitation. Then, the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 321 at the bottom of the first via 3211 is removed, and the oxide semiconductor layer 351 at the bottom of the second via 3511 is etched to form a connection hole 3518. In some implementation manners, the BOE Etch process can be used to remove the oxide layer and at the same time etch the oxide semiconductor layer 351 to form the connection hole 3518, as Figure 27 shown. Finally, a second electrode structure 3512 is formed in the second via 3511 and the connection hole 3518, and the second electrode structure 3512 forms a side contact with the oxide semiconductor layer 351 in the connection hole 3518, as Figure 28 shown, to achieve good electrical connection.

[0094] Further, in some implementation manners, when etching the oxide semiconductor layer 351, the oxide semiconductor layer 351 can be etched through, that is, the via hole 3518 is a via hole 3518 that penetrates the oxide semiconductor layer 351; thereby ensuring that the second electrode structure 3512 and the oxide semiconductor layer 351 form a better side contact structure.

[0095] Further, in some implementation manners, after etching the oxide semiconductor layer 351 through, side erosion of the oxide semiconductor layer 351 in the via hole 3518 should be avoided; that is to say, the aperture diameter at the bottom of the via hole 3518 should be less than or equal to the aperture diameter at the bottom of the second via hole 3511, so as to ensure that after the second electrode structure 3512 is formed, the side contact formed by the second electrode structure 3512 and the oxide semiconductor layer 351 is more stable and reliable. In a specific implementation manner, the slope angle of the second via hole 3511 formed above the oxide semiconductor layer 351 can be controlled at 70° to 80°, and when the oxide semiconductor layer 351 is etched through by BOE Etch, the slope angle of the oxide semiconductor layer 351 can be controlled at 70° to 90°; the total depth of the second via hole 3511 and the via hole 3518 is: H = 500 nm (thickness of the first insulating layer 34) + 150 nm (thickness of the second gate insulating layer 36) + 40 nm (thickness of the oxide semiconductor layer 351) = 690 nm, and the total depth is about 700 nm; the sizes of the second via hole 3511 and the via hole 3518 can be controlled at 2.0u to 2.5u. In this implementation manner, by controlling the diameter, depth, and slope of the via hole, the stability of each film layer structure during the manufacturing process can be ensured, collapse can be avoided, and the process yield can be improved.

[0096] Therefore, in this implementation manner, it is also possible to complete the manufacturing of the contact hole and the electrode structure by only using one patterning mask, which simplifies the manufacturing process and reduces the production cost.

[0097] For the formation processes of the electrode structure, the third insulating layer 37, the overlapping structure 3612, etc. in the subsequent processes and the corresponding beneficial effects, reference can be made to the process of the driving backplane with a double-gate structure in the previous example, which will not be elaborated here; after the manufacturing is completed, the driving backplane structure is as Figure 29 shown.

[0098] Please refer to Figure 30 , based on the same inventive concept, in another embodiment of the present invention, a driving backplane 500 is further provided, and the driving backplane 500 includes: a substrate substrate 51, a low-temperature polycrystalline silicon semiconductor layer 521, an oxide semiconductor layer 522, a first insulating layer 54, a first electrode structure 5212, and a second electrode structure 5222.

[0099] The substrate 51 includes a first region BM and a second region AA; a low-temperature polysilicon semiconductor layer 521 is disposed on the first region BM of the substrate 51; an oxide semiconductor layer 522 is disposed on the second region AA of the substrate 51; a first insulating layer 54 is disposed on the side of the low-temperature polysilicon semiconductor layer 521 and the oxide semiconductor layer 522 away from the substrate 51; contact holes are provided in the first insulating layer 54; the contact holes include: a first via hole and a second via hole, the first via hole extends to the low-temperature polysilicon semiconductor layer 521; the second via hole extends to the oxide semiconductor layer 522; a connection hole 5223 is provided at a position corresponding to the bottom of the second via hole in the oxide semiconductor layer 522; a first electrode structure 5212 is disposed in the first via hole and contacts the low-temperature polysilicon semiconductor layer 521; and a second electrode structure 5222 is disposed in the second via hole and the connection hole 5223, and forms a side contact with the oxide semiconductor layer 522 in the connection hole 5223.

[0100] In the above driving backplane 500 structure, since a connection hole 5223 is provided in the oxide semiconductor layer 522, during the manufacturing process, the first via hole and the second via hole can be simultaneously opened in a single patterning mask process, and the oxide semiconductor layer 522 can be etched to form the connection hole 5223 when cleaning the oxide layer on the surface of the low-temperature polysilicon semiconductor layer 521, and the oxide semiconductor layer 522 forms a side contact with the second electrode structure 5222 in the connection hole 5223 to achieve stable electrical connection. This structure can avoid opening the first via hole and the second via hole successively, simplifies the manufacturing process, and reduces costs.

[0101] Further, the connection hole 5223 can penetrate the oxide semiconductor layer 522 to ensure the stability of the side contact.

[0102] In some alternative implementation manners, the oxide semiconductor layer 522 can be correspondingly configured as a single-gate structure, and the implementation manner is as follows:

[0103] Please refer to Figure 31 , the driving backplane 510 may further include: a buffer layer 52; the buffer layer 52 is disposed between the substrate 51 and the low-temperature polysilicon semiconductor layer 521; the low-temperature polysilicon semiconductor layer 521 and the oxide semiconductor layer 522 are disposed on the same layer. Further, a second insulating layer 55 is further disposed between the first insulating layer 54 and the semiconductor layer (the low-temperature polysilicon semiconductor layer 521 and the oxide semiconductor layer 522).

[0104] In some alternative implementation manners, the oxide semiconductor layer 522 can be correspondingly configured as a double-gate structure, and the implementation manner is as follows:

[0105] Please refer to Figure 30, the driving backplane 500 may further include: a first gate insulating layer 53, a first gate 531, a light-shielding structure 531a, a second insulating layer 55, a second gate insulating layer 56, and a second gate 532.

[0106] Please continue to refer to Figure 30 , the first gate insulating layer 53 is disposed on a side of the low-temperature polysilicon semiconductor layer 521 away from the substrate 51; the first gate 531 and the light-shielding structure 531a are disposed on a side of the first gate insulating layer 53 away from the substrate 51; the first gate 531 is located in the first region BM, and the light-shielding structure 531a is located in the second region AA; the first gate 531 and the light-shielding structure 531a may be located on the same layer and may be formed by the same etching process. The second insulating layer 55 is disposed on a side of the first gate 531 and the light-shielding structure 531a away from the substrate 51; the oxide semiconductor layer 522 is disposed on a side of the second insulating layer 55 away from the substrate 51; the second gate insulating layer 56 is disposed on a side of the oxide semiconductor layer 522 away from the substrate 51; the second gate 532 is disposed between the second gate insulating layer 56 and the first insulating layer 54.

[0107] In some alternative implementation manners, the contact holes of the driving backplane 500 may further include: a third via hole; the third via hole is disposed on a side of the light-shielding structure 531a away from the substrate 51; a third electrode structure 5322 in contact with the light-shielding structure 531a is disposed in the third via hole; the driving backplane 500 may further include: a third insulating layer 57, the third insulating layer 57 is disposed on a side of the first electrode structure 5212, the second electrode structure 5222, and the third electrode structure 5322 away from the substrate 51; via holes are disposed in the first insulating layer 54 and the third insulating layer 57; a conductive overlapping structure 5612 is disposed in the via holes, and the conductive overlapping structure 5612 is respectively connected to the light-shielding structure 531a and the second gate 532, as Figure 30 shown. This structure can avoid damaging or etching through the second gate 532 during the manufacturing process.

[0108] It should be noted that the driving backplane 500 in this embodiment may be manufactured by the manufacturing method of the driving backplane 500 in the foregoing method embodiment; therefore, for the structure of the driving backplane 500 in this embodiment that is not further described, such as another fourth electrode structure 5225 corresponding to the oxide semiconductor layer 522 ( Figure 31 not shown in the figure), etc., reference may be made to the structure described in the foregoing method embodiment, and details are not described herein again.

[0109] Based on the same inventive concept, in another embodiment of the present invention, a display panel is further provided, including the driving backplane described in any one of the foregoing embodiments.

[0110] It should be noted that for a display panel provided in this embodiment, the structure of the driving backplane can refer to the foregoing embodiment, and the beneficial effects produced have been described in the foregoing embodiment regarding the substrate sealing frame structure. Specifically, reference can be made to the foregoing embodiment regarding the substrate sealing frame structure, and details will not be repeated in this embodiment. For structures such as the pixel light-emitting structure and color filter substrate in the display panel that have not been introduced, reference can be made to the existing prior art, and details will not be repeated in this embodiment.

[0111] In the above description, no detailed description is made of technical details such as the layout and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0112] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0113] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A manufacturing method of a driving backplane, characterized in that, comprising: forming a low-temperature polysilicon semiconductor layer in a first region of a substrate, and forming an oxide semiconductor layer in a second region; forming a first insulating layer on a side of the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer away from the substrate; covering a patterned mask on the first insulating layer, and forming contact holes penetrating the first insulating layer; wherein, the contact holes include: a first via hole formed on a side of the low-temperature polysilicon semiconductor layer away from the substrate, and a second via hole formed on a side of the oxide semiconductor layer away from the substrate; forming a first electrode structure in contact with the low-temperature polysilicon semiconductor layer in the first via hole, and forming a second electrode structure in contact with the oxide semiconductor layer in the second via hole; forming the contact holes on the first insulating layer includes: dry etching the first insulating layer under an oxygen-containing atmosphere condition to form the first via hole extending to the low-temperature polysilicon semiconductor layer, and forming the second via hole extending to the oxide semiconductor layer; dry etching to remove an oxide layer on a surface of the low-temperature polysilicon semiconductor layer at a bottom of the first via hole under an oxygen-free atmosphere condition.

2. The manufacturing method according to claim 1, characterized in that, before forming the first electrode structure in contact with the low-temperature polysilicon semiconductor layer in the first via hole, further comprising: using wet etching to remove an oxide layer on a surface of the low-temperature polysilicon semiconductor layer at a bottom of the first via hole, and etching the oxide semiconductor layer at a bottom of the second via hole to form a connection hole; forming the second electrode structure in contact with the oxide semiconductor layer in the second via hole includes: forming a second electrode structure in the second via hole and the connection hole, and making the second electrode structure form a side contact with the oxide semiconductor layer in the connection hole.

3. The manufacturing method according to claim 1, characterized in that, after forming the low-temperature polysilicon semiconductor layer and before forming the oxide semiconductor layer, further comprising: sequentially forming a first gate insulating layer, a first gate, a light-shielding structure, and a second insulating layer on a side of the low-temperature polysilicon semiconductor layer away from the substrate; wherein, the first gate is located in the first region, and the light-shielding structure is located in the second region; forming the oxide semiconductor layer includes: forming the oxide semiconductor layer in the second region on a side of the second insulating layer away from the substrate; after forming the oxide semiconductor layer and before forming the first insulating layer, further comprising: sequentially forming a second gate insulating layer and a second gate on the oxide semiconductor layer.

4. The manufacturing method according to claim 3, characterized in that, the contact holes further include: a third via hole formed on a side of the light-shielding structure away from the substrate; when forming the first electrode structure and the second electrode structure, the manufacturing method further comprises: forming a third electrode structure in contact with the light-shielding structure in the third via hole; after forming the first electrode structure and the second electrode structure, further comprising: Cover a third insulating layer on the first electrode structure, the second electrode structure and the third electrode structure; Etch the third insulating layer and the first insulating layer to form a via hole for connecting the third electrode structure and the second gate; Form a connecting structure in the via hole to electrically connect the third electrode structure and the second gate.

5. The manufacturing method according to claim 1, characterized in that forming a low-temperature polysilicon semiconductor layer in the first region of the substrate and an oxide semiconductor layer in the second region includes: forming a buffer layer on one side of the substrate; forming a low-temperature polysilicon semiconductor layer in the first region on the side of the buffer layer away from the substrate and an oxide semiconductor layer in the second region; after forming the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer and before forming the first insulating layer, further includes: forming a first gate insulating layer, a first gate, a second gate and a second insulating layer on the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer in sequence; wherein, the first gate is located in the first region and the second gate is located in the second region.

6. A driving backplane, the driving backplane is manufactured by using the method according to any one of claims 1-5, characterized in that including: a substrate; the substrate includes a first region and a second region; a low-temperature polysilicon semiconductor layer disposed in the first region of the substrate; an oxide semiconductor layer disposed in the second region of the substrate; a first insulating layer disposed on the sides of the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer away from the substrate; contact holes penetrating the first insulating layer; the contact holes include: a first via hole and a second via hole, the first via hole extends to the side of the low-temperature polysilicon semiconductor layer away from the substrate; the second via hole extends to the side of the oxide semiconductor layer away from the substrate; a connection hole is disposed at a position of the oxide semiconductor layer corresponding to the second via hole; a first electrode structure disposed in the first via hole and in contact with the low-temperature polysilicon semiconductor layer; and a second electrode structure disposed in the second via hole and the connection hole and forming a side contact with the oxide semiconductor layer in the connection hole.

7. The driving backplane according to claim 6, characterized in that the connection hole penetrates the oxide semiconductor layer.

8. The driving backplane according to claim 6, characterized in that further includes: a first gate insulating layer disposed on the side of the low-temperature polysilicon semiconductor layer away from the substrate; a first gate and a light-shielding structure disposed on the side of the first gate insulating layer away from the substrate; the first gate is located in the first region and the light-shielding structure is located in the second region; a second insulating layer disposed on the sides of the first gate and the light-shielding structure away from the substrate; the oxide semiconductor layer is disposed on the side of the second insulating layer away from the substrate; A second gate insulating layer, disposed on a side of the oxide semiconductor layer away from the substrate; and a second gate, disposed between the second gate insulating layer and the first insulating layer; Wherein, the first via further penetrates through the second insulating layer and the second gate insulating layer.

9. The driving backplane according to claim 8, Characterized in that The contact hole further includes: a third via, disposed on a side of the light shielding structure away from the substrate, and a third electrode structure in contact with the light shielding structure is disposed in the third via; The driving backplane further includes: a third insulating layer, disposed on a side of the first electrode structure, the second electrode structure, and the third electrode structure away from the substrate; via holes are provided in the first insulating layer and the third insulating layer; and a conductive overlapping structure is disposed in the via holes, and the conductive overlapping structure is respectively connected to the third electrode structure and the second gate.

10. The driving backplane according to claim 6, Characterized in that Further includes: A buffer layer, disposed between the substrate and the low-temperature polysilicon semiconductor layer; wherein, the low-temperature polysilicon semiconductor layer and the oxide semiconductor layer are disposed on the same layer.

11. A display panel, Characterized in that It includes the driving backplane according to any one of claims 6-10; or includes a driving backplane manufactured by the manufacturing method of the driving backplane according to any one of claims 1-5.

Images