High-speed active pixel device based on negative voltage clamping layer structure

Abstract

The present invention relates to the field of analog integrated circuit design. By increasing the potential difference between the PPD and the FD, photo-generated electrons are aggregated near the transfer gate, ultimately improving the transfer rate and transfer efficiency of photo-generated electrons. To this end, the technical solution adopted by the present invention is a high-speed active pixel device based on a negative voltage clamping layer structure. For an N-type PPD, it includes a high-concentration P-doped clamping layer, an N-doped region, and a low-concentration P-doped high-resistance substrate. Two P-doped regions and the N-doped region respectively form a P+N abrupt junction and a linearly graded junction, and the clamping layer is connected to a negative voltage. The present invention is mainly applied to the occasions of analog integrated circuit design and manufacturing.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, in particular to the field of image sensor pixel design, and more particularly to a high-speed active pixel device with a negative voltage clamping layer structure. Background Art

[0002] High-speed CMOS image sensors can capture high-speed phenomena that the human eye cannot distinguish, and are widely used in scientific research, machine vision, military and aerospace fields. The operating frequency and imaging quality of high-speed image sensors are determined by pixels, so the design and modification of pixels are particularly important.

[0003] Since the exposure time of high-speed pixels is short, the number of photons that can be collected by the pixels is usually very small. In order to solve this problem, the area of ​​the pinned photodiode PPD (Pinned Photodiode) is usually designed to be very large. PPD refers to the pixel structure of the Pinned PhotodiodePixel, which is prone to the following two problems. First, the design of a large-size PPD usually leads to a weak lateral electric field. During charge transfer, the drift effect of carriers is not enough to allow the photogenerated charge to be transferred quickly, so the readout rate of the pixel will be limited. Second, the large-size PPD structure will lead to an increase in the N-type doping dosage and capacitance of the photodiode, resulting in a larger clamping voltage. The minimum voltage difference between the PPD and the floating diffusion node FD (Floating Diffusion) may be small, which is not enough to completely transfer the photogenerated charge in the PPD, resulting in a tailing phenomenon in the image. In order to solve the above problems, the present invention proposes a high-speed active pixel structure with a negative voltage clamping layer structure, introduces a negative electrode into the clamping layer, and introduces a small voltage (Vpinning-layer) opposite to the pixel operating voltage into the clamping layer without blocking the light-receiving area and introducing impurity electrons. That is, when the PPD is N-type doped, the voltage is negative; when the PPD is N-type doped, the voltage is positive. By reducing the PPD clamping voltage and allowing the photogenerated electrons to gather at a position close to the transmission gate, the charge transfer rate and transfer efficiency of the PPD are improved. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention aims to increase the potential difference between PPD and FD, so that the photogenerated electrons gather at a position close to the transmission gate, and finally improve the transfer rate and transfer efficiency of the photogenerated electrons. To this end, the technical solution adopted by the present invention is a high-speed active pixel device based on a negative voltage clamping layer structure. For an N-type PPD, it includes a high-concentration P-doped clamping layer, an N-doped region and a low-concentration P-doped high-resistance substrate. The two P-doped regions and the N-doped region form a P + N-type abrupt junction and a linear graded junction, the clamping layer is connected to a negative voltage.

[0005] P+ The depletion region widths of the N-type abrupt junction and the linear gradual PN junction are:

[0006]

[0007]

[0008] where ε r , ε 0 are the relative dielectric constant of silicon and the dielectric constant of vacuum, V N 、V pinning-layer are the highest potential of the N region and the external voltage of the clamping layer, q is the unit charge, N is the doping concentration of the N region, α j is the doping concentration gradient of the linear graded junction, the depth of the N region is L, and the depth of the non-depleted region in the N region is L N According to the depletion region distribution characteristics of the abrupt junction and the linear graded junction, X D1 , X D2 ,L,L N The relationship is expressed as:

[0009] L N =LX D1 -X D2 (3)

[0010] Clamping voltage V pin is defined as the highest potential after PPD has transferred all the charges. According to this definition, when L N = 0, the calculated V N That is the clamping voltage V pin ,Right now

[0011]

[0012] When a negative voltage is applied to the clamping layer, V pinning-layer <0, in order to maintain the equality, V pin will be pulled down, the voltage difference between PPD and FD will increase, and the large voltage difference will increase the lateral electric field, causing the photogenerated electrons to transfer from PPD to FD faster.

[0013] For P-type PPD, it includes a high-concentration N-doped clamping layer, a P-doped region, and a low-concentration N-doped high-resistance substrate. The two N-doped regions and the P-doped region form an N + P abrupt junction and a linear graded junction, the clamping layer is connected to a positive voltage.

[0014] The characteristics and beneficial effects of the present invention are:

[0015] The negative voltage clamping layer structure described in the present invention is suitable for high-speed pixels of CMOS image sensors and is suitable for standard CMOS process conditions. By providing a negative voltage to the PPD clamping layer, the PPD clamping voltage can be effectively reduced, the potential difference between the PPD and the FD can be increased, and the photogenerated electrons can be gathered near the transmission gate, so that the photogenerated electrons can be transferred and read out more quickly and completely. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of the cross section of a clamped photodiode.

[0017] Figure 2 It is a schematic diagram of a high-speed pixel circuit described in the present invention.

[0018] Figure 3 This is a schematic diagram of the clamped photodiode layout. DETAILED DESCRIPTION

[0019] The present invention proposes a high-speed active pixel structure with a negative voltage clamping layer structure, introducing a negative electrode into the clamping layer to reduce the clamping voltage of the PPD, increase the potential difference between the PPD and the FD, and allow the photogenerated electrons to gather at a position close to the transmission gate, ultimately improving the transfer rate and transfer efficiency of the photogenerated electrons.

[0020] The main purpose of this scheme is to adjust the PPD clamping layer voltage to adjust V pin Taking N-type PPD as an example, the schematic diagram of the PPD structure is shown in the attached figure. Figure 1 As shown, it includes a high-concentration P-doped clamping layer, an N-doped region and a low-concentration P-doped high-resistance substrate, and the two P-doped regions and the N-doped region each form a P + N abrupt junction and a linear gradual junction. According to the basic principles of semiconductor physics, the depletion region widths of the two junctions are

[0021]

[0022]

[0023] where ε r , ε 0 are the relative dielectric constant of silicon and the dielectric constant of vacuum, V N 、V pinning-layer are the highest potential of the N region and the external voltage of the clamping layer, q is the unit charge, N is the doping concentration of the N region, α j is the doping concentration gradient of the linear graded junction. Let the depth of the N region be L, and the depth of the non-depleted region in the N region be L N According to the depletion region distribution characteristics of the abrupt junction and the linear graded junction, X D1 , X D2 ,L,LN The relationship can be expressed as

[0024] L N =LX D1 -X D2 (7)

[0025] Clamping voltage V pin is defined as the highest potential after PPD has transferred all the charges. According to this definition, in equation (7), when L N = 0, the calculated V N That is the clamping voltage V pin ,Right now

[0026]

[0027] In a conventional active pixel, the clamping layer of the PPD is connected to the substrate and grounded. pinning-layer = 0, the clamping voltage can be calculated by equation (8). When a negative voltage is applied to the clamping layer, it can be known from equation (8) that V pinning-layer <0, in order to maintain the equality, V pin will be pulled down. The voltage difference between PPD and FD will increase, and the lateral electric field caused by the large voltage difference will increase, causing the photogenerated electrons to transfer from PPD to FD faster. In addition, when the negative electrode of the clamping layer is placed far away from TX, the photogenerated electrons collected by PPD will gather near TX due to the mutual repulsion of charges of the same kind, making it easier to transfer completely.

[0028] For P-type PPD, it includes a high-concentration N-doped clamping layer, a P-doped region, and a low-concentration N-doped high-resistance substrate. The two N-doped regions and the P-doped region form an N + The P-type abrupt junction and a linear graded junction, the clamping layer is connected to a positive voltage. Since the design schemes of the two doping types of PPD are similar, the design scheme of the P-type PPD can be inferred from that of the N-type PPD.

[0029] In order to more intuitively express the implementation conditions, advantages, etc. of the present invention, the implementation methods of the present invention are described below with reference to examples.

[0030] The core idea of ​​the present invention is to reduce the potential of the PPD clamping layer by applying an external voltage, lower the clamping voltage of the PPD, and increase the potential difference between the FD and PPD during charge transfer. The electrons will be transferred to the FD faster under the action of a larger lateral electric field. The repulsive effect of the negative electrode allows the photogenerated electrons to gather near the transfer gate, making the transfer of the photogenerated electrons more complete. Figure 2 and attached Figure 3 As shown, Figure 2 The PPD cross section is derived from the attached Figure 3 The black dotted line is Figure 3The clamping layer covers the PPD and extends to the STI. The doping concentration of the clamping layer is 1×10 18 , unit: cm 2 , the doping concentration of N region is 1×10 16 , the p-impurity concentration of the high-resistance substrate is 1×10 15 .

[0031] Due to the short exposure time of high-speed pixels, the area of ​​PPD is usually designed to be large. In order to solve a series of limitations caused by large-area PPD, the attached Figure 3 For example, when the pixel begins to be exposed, the PPD begins to collect photogenerated electrons. At this time, the charge pump increases V pinning-layer Assuming a stable -1V voltage, according to equation (8), V pin will be pulled down to about 0.6V, which is about the same as the previous V pin The electrons collected by PPD will also be gathered in the surrounding Figure 3 In this way, when TX is at a high potential, the electrons in the white dotted box will be transferred to the FD with a higher potential faster and more completely, and the transfer rate and transfer efficiency will be improved.

[0032] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-speed active pixel device based on a negative voltage clamping layer structure, characterized in that: For N-type PPD, it includes a high-concentration P-doped clamping layer, an N-doped region, and a low-concentration P-doped high-resistance substrate. The two P-doped regions and the N-doped region form a P + N abrupt junction and a linear gradual junction, the clamping layer is connected to a negative voltage; + The depletion region widths of the N-type abrupt junction and the linear gradual PN junction are: where ε r , ε0 are the relative dielectric constant of silicon and the dielectric constant of vacuum, V N 、V pinning-layer are the highest potential of the N region and the external voltage of the clamping layer, q is the unit charge, N is the doping concentration of the N region, α j is the doping concentration gradient of the linear graded junction, the depth of the N region is L, and the depth of the non-depleted region in the N region is L N According to the depletion region distribution characteristics of the abrupt junction and the linear graded junction, X D1 , X D2 ,L,L N The relationship is expressed as: L N =L-X D1 -X D2 (3) Clamping voltage V pin is defined as the highest potential after PPD has transferred all the charges. According to this definition, when L N = 0, the calculated V N That is the clamping voltage V pin ,Right now When a negative voltage is applied to the clamping layer, V pinning-layer <0, in order to maintain the equality, V pin will be pulled down, the voltage difference between PPD and FD will increase, and the large voltage difference will increase the lateral electric field, causing the photogenerated electrons to transfer from PPD to FD faster.

2. The high-speed active pixel device based on the negative voltage clamping layer structure according to claim 1, characterized in that: For P-type PPD, it includes a high-concentration N-doped clamping layer, a P-doped region, and a low-concentration N-doped high-resistance substrate. The two N-doped regions and the P-doped region form an N + P abrupt junction and a linear graded junction, the clamping layer is connected to a positive voltage.

Images