A SiC MOSFET device with an L-shaped vertical source electrode and a manufacturing method thereof

Abstract

The present invention discloses an L-shaped vertical source silicon carbide MOSFET device and a manufacturing method thereof, including: an N-type substrate, an N-type epitaxial layer, a P-type well region, and an N-type source region arranged in sequence; a P-type ion implantation region located in the N-type epitaxial layer and the P-type well region; trenches are provided in the N-type epitaxial layer, the P-type well region, the N-type source region, and the P-type ion implantation region; a gate oxide layer is located on the sidewall of the trench far from the P-type ion implantation region and a part of the trench bottom connected to the sidewall; a source is located on the sidewall of the trench close to the P-type ion implantation region and another part of the trench bottom connected to the sidewall; a gate is located in the trench and is in contact with the gate oxide layer; an isolation region is located in the trench between the gate and the source; a drain is located on the side of the N-type substrate far from the N-type epitaxial layer. The solution of the present invention can improve the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a silicon carbide MOSFET device with an L-shaped vertical source and a manufacturing method thereof. Background Art

[0002] Due to the limitations of silicon-based materials themselves, the performance of silicon-based Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has approached the theoretical limit and cannot meet the requirements of existing applications. Silicon carbide materials have advantages such as a large bandgap width, a high breakdown field strength, a high electron saturation drift rate, and a high thermal conductivity. When using silicon carbide materials to prepare power devices, it is not only beneficial to reduce the on-resistance of the devices, but also can greatly improve the switching time, switching loss, and heat dissipation performance compared with silicon-based MOSFETs. Therefore, silicon carbide has become the preferred material for developing high-power, high-temperature, and high-frequency power devices and has a very broad application prospect.

[0003] However, in traditional trench-gate silicon carbide MOSFETs, electric field concentration is likely to occur at the bottom corners of the trench gates, resulting in premature breakdown of the device at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics of the device. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a silicon carbide MOSFET device with an L-shaped vertical source and a manufacturing method thereof. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0005] The present invention provides a silicon carbide MOSFET device with an L-shaped vertical source, including:

[0006] An N-type substrate, an N-type epitaxial layer, a P-type well region, and an N-type source region arranged in sequence;

[0007] A P-type ion implantation region located in the N-type epitaxial layer and the P-type well region; wherein, trenches are provided in the N-type epitaxial layer, the P-type well region, the N-type source region, and the P-type ion implantation region;

[0008] A gate oxide layer located on the sidewall of the trench away from the P-type ion implantation region and a part of the trench bottom connected to the sidewall;

[0009] A source located on the sidewall of the trench close to the P-type ion implantation region and another part of the trench bottom connected to the sidewall; wherein, at the bottom of the trench, the P-type ion implantation region completely surrounds the source;

[0010] The gate is located in the trench and is in contact with the gate oxide layer;

[0011] The isolation region is located in the trench between the gate and the source;

[0012] The drain is located on the side of the N-type substrate away from the N-type epitaxial layer.

[0013] Optionally, the interface between the source and the N-type source region and the P-type ion implantation region is an ohmic contact.

[0014] Optionally, the thickness of the N-type substrate is 200 μm to 500 μm, and the doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 .

[0015] Optionally, the thickness of the N-type epitaxial layer is 10 μm to 12 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 16 cm -3 .

[0016] Optionally, the thickness of the P-type well region is 0.5 μm to 0.8 μm, and the doping concentration is 5×10 16 cm -3 ~5×10 17 cm -3 ; the thickness of the N-type source region is 0.2 μm to 0.5 μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0017] Optionally, the doping concentration of the P-type ion implantation region is 1×10 19 cm -3 ~1×10 20 cm -3 , and the P-type ion implantation region is Gaussian doped, with a surface doping concentration of 1×10 18 cm -3 , and a peak doping concentration of 1×10 20 cm -3 ; the distance between the side surface of the P-type ion implantation region and the side surface of the source is 0.5 μm to 0.8 μm, and the distance between the bottom surface of the P-type ion implantation region and the bottom surface of the source is 0.5 μm to 0.8 μm.

[0018] Optionally, the material of the gate oxide layer includes silicon dioxide; the material of the source electrode includes titanium, nickel, molybdenum or tungsten; the material of the gate electrode includes polysilicon; the material of the drain electrode includes titanium, nickel or silver.

[0019] Optionally, the trench depth is 1 μm to 2 μm, and the width is 2 μm to 3 μm.

[0020] Optionally, the width of the gate electrode is 0.5 μm to 0.8 μm.

[0021] The second embodiment of the present invention also provides a manufacturing method of a silicon carbide MOSFET device with an L-shaped vertical source electrode, including:

[0022] Providing an N-type substrate, and growing an N-type epitaxial layer on the N-type substrate;

[0023] Using an ion implantation process to form a P-type well region on the N-type epitaxial layer;

[0024] Using an ion implantation process to form a P-type ion implantation region in the N-type epitaxial layer and the P-type well region;

[0025] Etching the N-type epitaxial layer, the P-type well region and the P-type ion implantation region to form a trench;

[0026] Using an ion implantation process to form an N-type source electrode region on the P-type well region;

[0027] Growing a gate oxide layer on the sidewall and bottom of the trench;

[0028] Growing a gate electrode on the sidewall of the trench far from the P-type ion implantation region and a part of the trench bottom connected to the sidewall;

[0029] Filling a first insulating material in the trench;

[0030] Etching the first insulating material in the trench near the P-type ion implantation region to form a trench for filling source electrode metal;

[0031] Adopting a physical vapor deposition process to grow an L-shaped source electrode on the sidewall of the trench for filling source electrode metal near the P-type ion implantation region and the trench bottom connected to the sidewall;

[0032] Filling a second insulating material in the trench for filling source electrode metal; wherein, the first insulating material and the second insulating material together form the isolation region;

[0033] Depositing a drain electrode on one side of the N-type substrate far from the N-type epitaxial layer to complete the preparation of the silicon carbide MOSFET device with an L-shaped vertical source electrode.

[0034] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0035] A silicon carbide MOSFET device with an L-shaped vertical source provided by the present invention includes an N-type substrate, an N-type epitaxial layer, and a P-type well region; a P-type ion implantation region located in the N-type epitaxial layer and the P-type well region; an N-type source region located on one side of the P-type well region and covering the P-type well region and the P-type ion implantation region; a gate oxide layer located at the bottom of the trench and on the sidewall far from the P-type ion implantation region; a gate located on the sidewall of the gate oxide layer; a source distributed in an L-shaped structure at the bottom of the trench and on the sidewall close to the P-type ion implantation region, and the P-type ion implantation region surrounds the source; an isolation region for isolating the gate and the source; a drain located in the N-type substrate and on the side far from the N-type epitaxial layer. In the solution of the present invention, on the one hand, the corner of the source is surrounded by the P-type ion implantation region, which can effectively avoid the aggregation of the electric field at the corner of the source and prevent the device from directly breaking down at the source. On the other hand, the source and the gate are integrated in the same trench, and the gate is a vertical strip shape, and insulation is carried out by using the isolation region, which can effectively reduce the cell width, and then the P-type ion implantation regions of two adjacent cells form a shielding layer structure, effectively alleviating the electric field aggregation at the corner of the gate oxide layer, preventing the device from prematurely breaking down at the corner of the gate oxide layer, and improving the breakdown voltage of the device.

[0036] In addition, the source distributed in an L-shaped structure and the P-type ion implantation region can form a good ohmic contact, so that the P-type well region is set to zero, and further the uniformity of the ohmic contact can be improved, alleviating the problem of too high threshold voltage caused by too large local ohmic contact of the device. By short-circuiting the source to the N-type source region and the P-type ion implantation region, the hole current directly flows from the P-type ion implantation region to the source, avoiding the parasitic NPN transistor effect in the blocking state and realizing a reverse breakdown voltage equivalent to that of a PiN diode.

[0037] The present invention will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.

[0039] Figure 1 It is a schematic structural diagram of a silicon carbide MOSFET device with an L-shaped vertical source provided by the first embodiment of the present invention;

[0040] Figure 2 It is a schematic flowchart of the manufacturing method of a silicon carbide MOSFET device with an L-shaped vertical source provided by the second embodiment of the present invention;

[0041] Figure 3 (a)~ Figure 3 (l) is a schematic structural diagram corresponding to each step of the manufacturing method of the L-shaped vertical source silicon carbide MOSFET device provided by the second embodiment of the present invention.

[0042] Description of reference numerals:

[0043] 101 - Source electrode; 102 - Gate electrode; 103 - Drain electrode; 110 - N-type substrate; 120 - N-type epitaxial layer; 130 - P-type well region; 140 - N-type source region; 150 - P-type ion implantation region; 160 - Gate oxide layer; 170 - Isolation region; 151 - Trench; 152 - Trench filled with source metal; 171 - First insulating material; 172 - Second insulating material. Detailed implementation manners

[0044] In order to avoid the premature breakdown of the device at a voltage lower than the rated breakdown voltage due to the electric field generated at the trench gate corner, the embodiments of the present invention provide an L-shaped vertical source silicon carbide MOSFET device and its manufacturing method. The following will detail the solutions provided in this embodiment with reference to the drawings.

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on each embodiment of the present invention with reference to the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0046] The first embodiment of the present invention provides an L-shaped vertical source silicon carbide MOSFET device. Refer to Figure 1 , Figure 1 which is a schematic structural diagram of an L-shaped vertical source silicon carbide MOSFET device provided by the first embodiment of the present invention, including:

[0047] An N-type substrate 110, an N-type epitaxial layer 120, a P-type well region 130, and an N-type source region 140 arranged in sequence.

[0048] Among them, the material of the N-type substrate 110 may include silicon carbide.

[0049] A P-type ion implantation region 150 is located in the N-type epitaxial layer 120 and the P-type well region 130.

[0050] Among them, the upper surface of the P-type ion implantation region 150 is flush with the upper surface of the P-type well region 130. Grooves (not shown) are provided in the N-type epitaxial layer 120, the P-type well region 130, the N-type source region 140, and the P-type ion implantation region 150. The depth of the groove is greater than the depth of the P-type well region 130.

[0051] The gate oxide layer 160 is located on the sidewall of the groove away from the P-type ion implantation region 150 and a part of the bottom of the groove connected to the sidewall. Among them, the gate oxide layer 160 has an L-shaped structure.

[0052] The source electrode 101 is located on the sidewall of the groove close to the P-type ion implantation region 150 and another part of the bottom of the groove connected to the sidewall; among them, at the bottom of the groove, the P-type ion implantation region 150 completely surrounds the source electrode 101.

[0053] Among them, the source electrode 101 has an L-shaped structure, and the corner of the source electrode 101 is completely surrounded by the P-type ion implantation region 150; the thickness of the source electrode 101 horizontally distributed at the bottom of the groove is higher than the thickness of the gate oxide layer 160 horizontally distributed at the bottom of the groove.

[0054] Furthermore, except for the part of the source electrode 101 in contact with the N-type source region 140, the source electrode 101 is completely in contact with the P-type ion implantation region 150, that is, it is surrounded by the P-type ion implantation region 150.

[0055] The gate electrode 102 is located in the groove and is in contact with the gate oxide layer 160.

[0056] The isolation region 170 is located in the grooves of the gate electrode 102 and the source electrode 101, and is used to isolate the source electrode 101 and the gate electrode 102.

[0057] The drain electrode 103 is located on the side of the N-type substrate 110 away from the N-type epitaxial layer 120.

[0058] An L-shaped vertical source SiC MOSFET device provided by an embodiment of the present invention includes an N-type substrate 110, an N-type epitaxial layer 120, and a P-type well region 130; a P-type ion implantation region 150 located in the N-type epitaxial layer 120 and the P-type well region 130; an N-type source region 140 located on one side of the P-type well region 130 and covering the P-type well region 130 and the P-type ion implantation region 150; a gate oxide layer 160 located at the bottom of the trench and on the sidewall far from the P-type ion implantation region 150; a gate 102 located in the trench and in contact with the sidewall of the gate oxide layer 160; a source 101 in an L-shaped structure located at the bottom of the trench and on the sidewall close to the P-type ion implantation region 150, and the P-type ion implantation region 150 surrounds the source 101; an isolation region 170 for isolating the gate 102 and the source 101; a drain 103 located on the side of the N-type substrate 110 away from the N-type epitaxial layer 120. It can be seen that in the solution provided by the embodiment of the present invention, on the one hand, the corner of the source 101 is completely surrounded by the P-type ion implantation region 150, which can effectively prevent the electric field from gathering at the corner of the source 101 and prevent the device from directly breaking down at the source 101. On the other hand, the source 101 and the gate 102 are integrated in the same trench, and the gate 102 is a vertical strip shape, and the isolation region 170 is used for insulation, which can effectively reduce the cell width. The cell width can be minimized to 3.5 μm, and then the P-type ion implantation regions 150 of two adjacent cells form a shielding layer structure, effectively alleviating the electric field gathering at the corner of the gate oxide layer 160 and preventing the device from prematurely breaking down at the corner of the gate oxide layer 160, thereby improving the breakdown voltage of the device.

[0059] In addition, the source 101 and the P-type ion implantation region 150 can form a good ohmic contact, so that the P-type well region 130 is set to zero, and then the uniformity of the ohmic contact can be improved, alleviating the problem that the threshold voltage of the device is too high due to excessive local ohmic contact. By short-circuiting the N-type source region 140 and the P-type ion implantation region 150 through the source 101, the hole current can directly flow from the P-type ion implantation region 150 to the source 101, avoiding the parasitic NPN transistor effect in the blocking state and realizing a reverse breakdown voltage equivalent to a PiN (formed between the P-type well region 130 and the N-type epitaxial layer 120) diode.

[0060] In the embodiment of the present invention, the interfaces between the source 101 and the N-type source region 140 and the P-type ion implantation region 150 are all ohmic contacts.

[0061] In the embodiment of the present invention, the thickness of the N-type substrate 110 is 200 μm to 500 μm, and the doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 。

[0062] In the embodiment of the present invention, the thickness of the N-type epitaxial layer 120 is 10 μm to 12 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 16 cm -3 .

[0063] In the embodiment of the present invention, the thickness of the P-type well region 130 is 0.5 μm to 0.8 μm, the total width is 1 μm to 1.5 μm, and the doping concentration is 5×10 16 cm -3 ~5×10 17 cm -3 The thickness of the N-type source region 140 is 0.2 μm to 0.5 μm, the total width is 1.5 μm to 2 μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0064] In the embodiment of the present invention, the doping concentration of the P-type ion implantation region 150 is 1×10 19 cm -3 ~1×10 20 cm -3 , and the P-type ion implantation region 150 is Gaussian doped, and the surface doping concentration is 1×10 18 cm -3 , the peak doping concentration is 1×10 20 cm -3 .

[0065] It can be understood that the doping concentration of the P-type ion implantation region 150 after ion implantation is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0066] Furthermore, the distance between the side surface of the P-type ion implantation region 150 (the surface in contact with the P-type well region 130) and the side surface of the source 101 (the surface in contact with the N-type source region 140 and the P-type ion implantation region 150) is 0.5μm to 0.8μm, and the distance between the bottom surface of the P-type ion implantation region 150 and the bottom surface of the source 101 is 0.5μm to 0.8μm.

[0067] In the embodiment of the present invention, the thickness of the gate oxide layer 160 distributed on the sidewall and the bottom of the trench is 0.05 μm to 0.08 μm; the material of the gate oxide layer 160 may include silicon dioxide, but is not limited to silicon dioxide.

[0068] In the embodiment of the present invention, the depth of the groove is 1 μm to 2 μm, and the width is 2 μm to 3 μm.

[0069] In an embodiment of the present invention, the width of the gate 102 is 0.5 μm to 0.8 μm; the material of the gate 102 may include polysilicon.

[0070] In an embodiment of the present invention, the thickness of the source electrode 101 distributed on the side wall and bottom of the trench is 0.2 μm to 0.3 μm; in order to prevent gate-source short circuit, the width of the source electrode 101 at the bottom of the trench is 0.4 μm to 0.6 μm; the material of the source electrode 101 may include titanium, nickel, molybdenum or tungsten.

[0071] In an embodiment of the present invention, the thickness of the drain 103 is 1 μm to 10 μm; the material of the drain 103 may include titanium, nickel or silver.

[0072] Through research by the inventor, it is found that electric field concentration is likely to occur at the bottom corner of the trench gate of the traditional trench-gate silicon carbide MOSFET, resulting in premature breakdown of the device at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics of the device. Therefore, in order to solve the above problems, an embodiment of the present invention proposes a new trench-gate structure, integrating the source electrode 101 and the gate 102 in the same trench 151, and in order to prevent gate-source short circuit and to increase the contact area between the source electrode 101 and the P-type ion implantation region 150 in the trench, the source electrode 101 is set as an L-shaped structure, thus ensuring the contact area between the source electrode 101 at the bottom of the trench and the P-type ion implantation region 150, and increasing the width of the isolation region 170 between the gate and the source to prevent the risk of gate-source short circuit.

[0073] It can be understood that integrating the source electrode 101 and the gate 102 in the same trench and making the gate 102 a vertical strip can effectively reduce the cell width, and then the P-type ion implantation regions 150 of two adjacent cells form a shielding layer structure, effectively alleviating the electric field concentration at the corner of the gate oxide layer 160, preventing premature breakdown of the device at the corner of the gate oxide layer 160, and improving the breakdown voltage of the device. If the width of the gate 102 is too wide, it will increase the cell width of the device, weakening the shielding layer effect formed by the P-type ion implantation regions 150 between adjacent cells. Through research by the inventor, it is found that when the width of the gate 102 in the groove is 0.5 μm to 0.8 μm, the shielding effect is the best.

[0074] A second embodiment of the present invention also provides a manufacturing method of a silicon carbide MOSFET device with an L-shaped vertical source electrode. Hereinafter, the manufacturing method of the silicon carbide MOSFET device with an L-shaped vertical source electrode provided by the second embodiment of the present invention will be described in detail. For the same or corresponding parts as the previous embodiment, reference may be made to the description of the previous embodiment, which will not be repeated hereinafter. Please refer to Figure 2 and Figure 3 (a) to Figure 3(l) is the structural schematic diagram corresponding to each step of the manufacturing method of the L-shaped vertical source SiC MOSFET device provided by the second embodiment of the present invention.

[0075] S10. Refer to Figure 3 (a), provide an N-type substrate 110, and grow an N-type epitaxial layer 120 on the N-type substrate 110.

[0076] Specifically, in the embodiment of the present invention, first, a SiC substrate with a thickness of 200 μm to 500 μm and a doping concentration of 1×10 18 cm -3 ~1×10 19 cm -3 is subjected to RCA standard cleaning as the N-type substrate 110; then, an N-type epitaxial layer 120 with a thickness of 10 μm to 12 μm and a doping concentration of 1×10 15 cm -3 ~1×10 16 cm -3 is epitaxially grown on the N-type substrate 110.

[0077] S20. Refer to Figure 3 (b), use the ion implantation process to form a P-type well region 130 on the N-type epitaxial layer 120.

[0078] Specifically, in the embodiment of the present invention, the P-type well region 130 is formed by ion implantation, and the doping concentration is 5×10 16 cm -3 ~5×10 17 cm -3 .

[0079] S30. Refer to Figure 3 (c), use the ion implantation process to form a P-type ion implantation region 150 in the N-type epitaxial layer 120 and the P-type well region 130.

[0080] Specifically, a mask layer is deposited on the upper surface of the P-type well region 130, a mask pattern is formed through photolithography and etching processes, and ion implantation is performed on the P-type well region 130 and a part of the N-type epitaxial layer 120. The implanted ions are Al ions to form the P-type ion implantation region 150.

[0081] Among them, the P-type ion implantation region 150 is Gaussian doped, the surface doping concentration is 1×10 18 cm -3 , the peak doping concentration is 1×10 20 cm -3 , and the doping concentration after the ion implantation of the P-type ion implantation region 150 is 1×10 19 cm -3 ~1×1020 cm -3 The P-type ion implantation region 150 is implanted into the N-type epitaxial layer 120 at a depth of 2.5 μm to 3.5 μm. The specific implantation depth depends on the depth of the trench 151 required subsequently. Here, the distance between the bottom of the trench 151 and the bottom of the P-type ion implantation region 150 is required to be 0.5 μm to 0.8 μm.

[0082] S40. Refer to Figure 3 (d), etch the N-type epitaxial layer 120, the P-type well region 130, and the P-type ion implantation region 150 to form a trench 151.

[0083] Specifically, first, deposit a mask layer on the upper surfaces of the P-type well region 130 and the P-type ion implantation region 150, and form a mask pattern through a photolithography and etching process; then, through an inductively coupled plasma (ICP) etching method, etch to form the trench 151. Among them, the depth of the trench 151 is 1 μm to 2 μm, the width is 2 μm to 3 μm, the trench 151 is located in the N-type epitaxial layer 120, the P-type well region 130, and the P-type ion implantation region 150. The bottom surface of the trench 151 is above the bottom surface of the P-type ion implantation region 150. The distance between the bottom surface of the trench 151 and the bottom surface of the P-type ion implantation region 150 is 0.5 μm to 0.8 μm. The distance between the side wall of the trench 151 close to the P-type ion implantation region 150 and the side wall of the P-type ion implantation region 150 away from the trench 151 is 0.5 μm to 0.8 μm.

[0084] S50. Refer to Figure 3 (e), use the ion implantation process to form an N-type source region 140 on the P-type well region 130.

[0085] Specifically, first, deposit a mask layer on the bottom of the trench 151, the upper surfaces of the P-type well region 130 and the P-type ion implantation region 150, and form a mask pattern through a photolithography and etching process; then, through ion implantation, form an N-type source region 140 in the P-type well region 130, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 。

[0086] S60. Refer to Figure 3 (f), grow a gate oxide layer 160 on the side walls and bottom of the trench.

[0087] Specifically, sacrificial oxidation is performed on the surface of the trench 151 by using the surface sacrificial layer technology. First, a sacrificial oxide layer is deposited, and then a part of the sacrificial oxide layer is etched. After that, a layer of silicon dioxide is grown by thermal oxidation as the gate oxide layer 160, and the thickness of the gate oxide layer 160 is 0.05 μm to 0.08 μm. Annealing is carried out in an atmosphere of nitric oxide, the annealing temperature is 1200 °C, and the annealing time is 1 h. Then, a mask layer is deposited on the gate oxide layer, and a mask pattern is formed through photolithography and etching processes to etch away the excess gate oxide layer 160, leaving only the gate oxide layer 160 on the sidewalls and bottom of the trench.

[0088] S70. Refer to Figure 3 (g), a gate 102 is grown on the sidewall of the trench 151 far from the P-type ion implantation region 150 and on a part of the bottom of the trench 151 connected to this sidewall.

[0089] Specifically, polysilicon is deposited on the bottom of the trench 151 and the N-type source implantation region 140, and then the polysilicon is polished flat by a chemical mechanical polishing process, and the N-type source implantation region 140 serves as a stop layer for chemical mechanical polishing. Then, a mask layer is deposited, and a mask pattern is formed through photolithography and etching processes to etch away the excess polysilicon in the trench 151 to form the gate 102. Among them, the width of the gate 102 is 0.5 μm to 0.8 μm.

[0090] S80. Refer to Figure 3 (h), a first insulating material 171 is filled in the trench 151.

[0091] Specifically, the first insulating material 171 is deposited in the trench 151 by chemical vapor deposition as an isolation layer 170 between the gate 102 and the subsequent source 101 to be fabricated. Among them, the first insulating material 171 can be silicon dioxide, but is not limited to silicon dioxide. Then, annealing is carried out in an atmosphere of nitric oxide, the annealing temperature can be 1200 °C, and the annealing time can be 1 h.

[0092] S90. Refer to Figure 3 (i), the first insulating material 171 in the trench 151 near the P-type ion implantation region 150 is etched to form a trench 152 for filling source metal.

[0093] Specifically, a mask layer is deposited on the first insulating material 171, and a mask pattern is formed through photolithography and etching processes to etch away part of the first insulating material 171 and the gate oxide layer 160 to etch out the trench 152 for filling source metal, which is used for subsequent fabrication of the source.

[0094] S100. Refer to Figure 3(j), using a physical vapor deposition process, a source electrode 101 in an L-shaped structure is grown on the sidewall of the trench 152 filled with the source electrode metal near the P-type ion implantation region 150 and on the bottom of the trench 152 filled with the source electrode metal connected to the sidewall.

[0095] Specifically, first, a source electrode metal is deposited in the trench 152 by physical vapor deposition. Among them, the source electrode metal can be titanium, nickel, molybdenum, or tungsten. Then, a mask layer is deposited on the upper surface of the first insulating layer material 171 and the source electrode metal. Through a photolithography and etching process, a part of the source electrode metal in the trench 152 is etched to form the L-shaped source electrode 101. The thickness of the source electrode 101 on the sidewall and bottom of the trench is 0.2 μm to 0.3 μm, and the width of the source electrode 101 at the bottom of the trench is 0.4 μm to 0.6 μm. Then, a rapid thermal annealing process is carried out in an argon atmosphere. The annealing temperature can be 1000 °C, and the duration is 3 min.

[0096] It can be understood that ohmic contacts are formed at the interfaces between the source electrode 101 and the N-type source region 140 and the P-type ion implantation region 150.

[0097] S110. Refer to Figure 3 (k), a second insulating material 172 is filled in the trench 152 filled with the source electrode metal.

[0098] Specifically, a second insulating material 172 is grown in the trench 152 filled with the source electrode metal by chemical vapor deposition. Then, the second insulating material 172 is polished to be flush with the upper surface of the first insulating material 171 by chemical mechanical polishing. Among them, the second insulating material 172 can be silicon dioxide, but is not limited to silicon dioxide. The first insulating material 171 and the second insulating material 172 can be made of the same material or different materials. In the embodiment of the present invention, it is preferably that the first insulating material 171 and the second insulating material 172 are made of the same material, and the isolation region 170 as shown is formed by the first insulating material 171 and the second insulating material 172. Figure 1 The isolation region 170 as shown.

[0099] S120. Refer to Figure 3 (l), a drain electrode 103 is deposited on one side of the N-type substrate 110 and far from the N-type epitaxial layer 120.

[0100] Specifically, a drain electrode metal is deposited on the surface of the N-type substrate 110 far from the N-type epitaxial layer 120 as the drain electrode 103, and the thickness of the drain electrode 103 is 1 μm to 10 μm. Among them, the deposited drain electrode metal can include titanium, nickel, or silver.

[0101] The manufacturing method of the L-shaped vertical source SiC MOSFET device provided by the embodiments of the present invention. On the one hand, the corner of the source electrode 101 is surrounded by the P-type ion implantation region 150, which can effectively avoid the aggregation of the electric field at the corner of the source electrode 101 and prevent the device from directly breaking down at the source electrode 101. On the other hand, the source electrode 101 and the gate electrode 102 distributed in an L-shaped structure are integrated in the same trench 151, and the gate electrode 102 is a vertical strip, insulated by the isolation region 170, which can effectively reduce the cell width. Furthermore, the P-type ion implantation regions 150 of two adjacent cells form a shielding layer structure, effectively alleviating the electric field aggregation at the corner of the gate oxide layer 160 and preventing the device from prematurely breaking down at the corner of the gate oxide layer 160, improving the breakdown voltage of the device.

[0102] In addition, the source electrode 101 and the P-type ion implantation region 150 distributed in an L-shaped structure can form a good ohmic contact, thereby making the P-type well region 130 zero, and further improving the uniformity of the ohmic contact, alleviating the problem that the threshold voltage of the device is too high due to excessive local ohmic contact. By short-circuiting the N-type source region 140 and the P-type ion implantation region 150 through the source electrode 101, the hole current directly flows from the P-type ion implantation region 150 to the source electrode 101, avoiding the parasitic NPN transistor effect in the blocking state and realizing a reverse breakdown voltage equivalent to that of a PiN diode.

[0103] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0104] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized.

[0105] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A silicon carbide MOSFET device with an L-shaped vertical source electrode, characterized in that, Including: An N-type substrate, an N-type epitaxial layer, a P-type well region, and an N-type source region arranged in sequence; A P-type ion implantation region located in the N-type epitaxial layer and the P-type well region; wherein, trenches are provided in the N-type epitaxial layer, the P-type well region, the N-type source region, and the P-type ion implantation region; A gate oxide layer located on the sidewalls of the trenches away from the P-type ion implantation region and a part of the trench bottom connected to the sidewalls; A source electrode in an L-shaped structure located on the sidewalls of the trenches close to the P-type ion implantation region and another part of the trench bottom connected to the sidewalls; wherein, at the bottom of the trenches, the P-type ion implantation region completely surrounds the source electrode; A gate electrode located in the trenches and in contact with the gate oxide layer; An isolation region located in the trenches between the gate electrode and the source electrode; A drain electrode located on the side of the N-type substrate away from the N-type epitaxial layer.

2. The L-shaped vertical source SiC MOSFET device according to claim 1, wherein The interface between the source electrode and the N-type source region and the P-type ion implantation region is an ohmic contact.

3. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, characterized in that, The thickness of the N-type substrate is 200 μm to 500 μm, and the doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 。 4. The L-shaped vertical source SiC MOSFET device according to claim 1, characterized in that, The thickness of the N-type epitaxial layer is 10 μm to 12 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 16 cm -3 .

5. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, wherein The thickness of the P-type well region is 0.5 μm to 0.8 μm, and the doping concentration is 5×10 16 cm -3 ~5×10 17 cm -3 ; The thickness of the N-type source region is 0.2 μm to 0.5 μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

6. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, characterized in that The doping concentration of the P-type ion implantation region is 1×10 19 cm -3 ~1×10 20 cm -3 , and the P-type ion implantation region is Gaussian doped, with a surface doping concentration of 1×10 18 cm -3 , and a peak doping concentration of 1×10 20 cm -3 ; the side surface of the P-type ion implantation region is 0.5 μm to 0.8 μm away from the side surface of the source electrode, and the bottom surface of the P-type ion implantation region is 0.5 μm to 0.8 μm away from the bottom surface of the source electrode.

7. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, characterized in that The material of the gate oxide layer includes silicon dioxide; the material of the source electrode includes titanium, nickel, molybdenum, or tungsten; the material of the gate electrode includes polysilicon; the material of the drain electrode includes titanium, nickel, or silver.

8. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, wherein The depth of the trenches is 1 μm to 2 μm, and the width is 2 μm to 3 μm.

9. The L-shaped vertical source silicon carbide MOSFET device according to claim 1, characterized in that, The width of the gate electrode is 0.5 μm to 0.8 μm.

10. A manufacturing method of a silicon carbide MOSFET device with an L-shaped vertical source electrode, characterized in that, Including: Providing an N-type substrate and growing an N-type epitaxial layer on the N-type substrate; Forming a P-type well region on the N-type epitaxial layer by using an ion implantation process; Forming a P-type ion implantation region in the N-type epitaxial layer and the P-type well region by using an ion implantation process; Etching the N-type epitaxial layer, the P-type well region, and the P-type ion implantation region to form trenches; Forming an N-type source region on the P-type well region by using an ion implantation process; Growing a gate oxide layer on the sidewalls and the bottom of the trenches; Growing a gate electrode on the sidewalls of the trenches away from the P-type ion implantation region and a part of the trench bottom connected to the sidewalls; Filling a first insulating material in the trenches; Etching the first insulating material in the trenches close to the P-type ion implantation region to form trenches for filling source electrode metal; Adopting a physical vapor deposition process to grow a source electrode in an L-shaped structure on the sidewalls of the trenches for filling source electrode metal close to the P-type ion implantation region and the trench bottom connected to the sidewalls; Filling a second insulating material in the trenches for filling source electrode metal; wherein, the first insulating material and the second insulating material together form an isolation region; Depositing a drain electrode on the side of the N-type substrate away from the N-type epitaxial layer to complete the preparation of the L-shaped vertical source silicon carbide MOSFET device.

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