A digital integrating charge-digital conversion circuit for measuring current or capacitance

Abstract

The present invention discloses a digital integrating charge-digital conversion circuit and a digital pixel circuit for a photodetector. In particular, a digital integrating charge-digital conversion circuit with an increased charge storage capacity and improved linearity is provided. The circuit consists of an injection tube / current source, an integrating capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor, etc. By using a unit charge storage capacitor and two switches connected thereto, when the current integrates to trigger the comparator to flip, the charge discharged from the integrating capacitor is supplemented with a unit charge Qo, replacing the traditional way of resetting the voltage in digital integration, avoiding the influence of the comparator decision voltage and delay time, and improving the linearity of charge-digital conversion.

Description

Technical Field

[0001] The present invention belongs to the field of electronic circuits, and relates to a digital integrating charge-digital conversion circuit for measuring current or capacitance. The present invention is suitable for application in readout circuits including optoelectronic detectors such as CMOS image sensors, infrared detectors, etc. and capacitance sensors, etc. Background Art

[0002] In optoelectronic detectors such as image sensors and infrared detectors, the pixels of the readout circuit are interconnected one by one with the optoelectronic detector units, and its main task is to extract, amplify, integrate the photocurrent generated by the detector and convert it into a voltage signal for output. The working principle of the pixel circuit is that the signal current I p integrates on the integration capacitor C int for a certain integration time T int , and the voltage V int across the capacitor is output through a multiplexer. At this time, the charge stored in the capacitor is Q, which is given by the following formula:

[0003]

[0004] After integration by the pixel circuit, the signal accumulates linearly, while the noise accumulates in root mean square. The signal-to-noise ratio of the output signal is proportional to the square root of the integration time. Prolonging the integration time can improve the signal-to-noise ratio and dynamic range of the detector output signal. However, the extension of the integration time is limited by the charge storage capacity Qmax of the pixel of the readout circuit, which is given by the following formula:

[0005] Q max = I p T int_max = C int V int_max (2)

[0006] The maximum output voltage V int_max of the pixel circuit is limited by the power supply voltage. Therefore, the charge storage capacity Q max is mainly limited by the capacity of the integration capacitor, that is, the dynamic range of the readout circuit is limited by the capacity of the integration capacitor. To increase the integration time of the photocurrent output by the detector, the capacity of the integration capacitor must be increased.

[0007] Since the integration capacitor must be integrated within the area of each pixel, under the current silicon CMOS process conditions, the unit capacitance value of the capacitor that can be integrated is several fF per square micron. Assuming that the pixel area is 20μm × 20μm, the maximum value of the capacitor that can be integrated within the pixel is only 2pF. Assuming that the integration capacitor capacity is 2pF and the power supply voltage is 3.3V, the charge storage capacity of the pixel circuit is about 41Me-. When the maximum output voltage is 3.3V and the photocurrent is 10nA, the longest integration time is:

[0008]

[0009] If the dark current and background current of the photodetector are taken into account, the longest integration time will be even shorter. Compared with the frame time of 20 ms of a normal image sensor or infrared detector, only less than 4% of the time is used for photocurrent integration, and the rest of the time is not utilized, which limits the further improvement of the performance of the photodetector.

[0010] With the further increase in the number of detector pixels, the pixel size is continuously reduced, and the capacitance of the integration capacitor integrated within the pixel is continuously decreased, resulting in the charge storage capacity limitation of the readout circuit becoming one of the most important factors affecting the performance of the photodetector.

[0011] To break through the charge storage capacity limitation of the pixel circuit, Ref. [1] uses digital integration technology to increase the charge storage capacity. Its working principle is that when the voltage V on the integration capacitor C reaches the comparator threshold voltage V each time, an automatic reset is triggered to clear the charge on the integration capacitor, and at the same time, the counter is incremented by 1. Such a process is repeated multiple times within the integration time. The digital integration technology changes the way of measuring the absolute value of the single-integration voltage on the measurement capacitor to the count value N of the multiple integration times, thereby avoiding the limitation of single integration by the integration capacitor and voltage, and increasing the equivalent charge storage capacity to N times the original. int on the voltage V int each time it reaches the comparator threshold voltage V th When this occurs, an automatic reset is triggered to clear the charge on the integration capacitor, and at the same time, the counter is incremented by 1. This process is repeated multiple times within the integration time. The digital integration technology changes the way of measuring the absolute value of the single-integration voltage on the measurement capacitor to the count value N of the multiple integration times, thereby avoiding the limitation of single integration by the integration capacitor and voltage, and increasing the equivalent charge storage capacity to N times the original.

[0012]

[0013] Since the integration time is extended, the digital integration technology improves the signal-to-noise ratio and dynamic range of the detector output signal. At the same time, the output value N is the quantization result of the photocurrent, so the digital integration technology also completes the conversion of charge to digital signal.

[0014] Another commonly used pixel circuit is to use a capacitive transimpedence amplifier (CTIA) to improve the signal-to-noise ratio and linearity, but the cost is that each pixel needs to add an amplifier, which not only occupies the limited pixel area and causes the integration capacitor to decrease, but also significantly increases the power consumption of the readout circuit.

[0015] The above pixel circuit for integrating the photodetector and measuring its photocurrent can be extended to a charge-digital conversion circuit for measuring current, except that the device to be measured changes from a photodetector to other devices that generate the current to be measured, and there are also problems of dynamic range and signal-to-noise ratio in its integration and charge-digital conversion.

[0016] In addition, a capacitive sensor also requires a similar readout circuit to complete charge-to-digital conversion. Only the measurement object changes from current to capacitance. By simply replacing the photodetector in the pixel circuit with a current source that provides a fixed current, the capacitance under test can be integrated and quantified. Its dynamic range and signal-to-noise ratio are also important performance metrics that need to be improved.

[0017] Although digital integration technology can increase the charge storage capacity of the pixel circuit, due to the voltage reset method, the delay time of the comparator circuit will cause integration non-linearity.

[0018] Ideally, the unit charge represented by each count is

[0019] Q0 = C int (V rst - V th ) (5) where V rst is the reset voltage and V th is the comparator threshold voltage. The count value output by the pixel is

[0020]

[0021] The count value N is linearly proportional to the photocurrent I p and can quantify the magnitude of the photocurrent generated by the detector.

[0022] However, due to the inevitable delay time T d of the comparator, the photocurrent is still discharging during this period, resulting in the effective unit charge becoming

[0023] Q'0 = C int (V rst = V th ) + I p T d (7)

[0024] The actual change in the integrated voltage changes from V rst - V th to

[0025]

[0026] So the actual output count value is

[0027]

[0028] The comparator delay T d introduces a non-linear term I p T d in the denominator of the count value expression, that is, the count value N is no longer linearly proportional to the photocurrent I pIt shows a linear proportional relationship, resulting in the output of the photodetector becoming a non-linear response affected by the input signal, which affects the performance of the photodetector and brings difficulties to the design and processing of the imaging system.

[0029] Reference [1] Sylvette Bisottoa, et al. “A 25μm pitch LWIR staring focalplane array with pixel-level 15-bit ADC ROIC achieving 2mK NETD”. Proceding of SPIE, 2010, 7834:78340J. Summary of the Invention

[0030] The object of the present invention is to provide a digital integrating charge-digital conversion circuit for measuring current or capacitance, especially a digital integrating charge-digital conversion circuit with increased charge storage capacity and improved linearity. On the one hand, digital integration technology is used to overcome the problem of limited charge storage capacity in traditional analog integration. On the other hand, the non-linear defect of the output response in the digital integration technology with the existing voltage reset structure is also solved. Thus, while improving the signal-to-noise ratio and dynamic range of charge-digital conversion, the output linearity is ensured, and the performance of photodetectors, current measurement, and capacitance measurement sensors is improved.

[0031] The general concept of the present invention includes:

[0032] (1) Use a unit charge storage capacitor Co and two switches connected thereto. When the current is integrated until the comparator flips, the unit charge Qo is used to supplement the charge discharged from the integration capacitor, replacing the traditional digital integration method of voltage reset, avoiding the influence of the comparator decision voltage and delay time, and improving the linearity of charge-digital conversion.

[0033] (2) Control the switch control signals S1 and S2 for the unit charge storage capacitor or the measured capacitor Co to store and transfer charges, and their effective levels are non-overlapping to avoid errors caused by charge leakage.

[0034] (3) The input of the control signal generation circuit and the counter is generated by a monostable circuit. It is characterized in that only one pulse Vp is generated when the output of the comparator flips during each integration process, and its effective level width is determined by the monostable circuit and is not affected by other circuits such as the comparator. The purpose is to avoid generating multiple incorrect pulses due to interference from non-ideal factors such as the supply voltage during one integration process, causing incorrect counting of the counter and incorrect operations of unit capacitance storage and transfer.

[0035] (4) The present invention is not only applicable to Figure 1 and Figure 2The integration of the shown current Ip discharging the integration capacitor is also applicable to the integration of the current Ip charging the integration capacitor.

[0036] The technical solution adopted by the present invention to achieve the above object is as follows:

[0037] According to a first aspect, the present invention provides a digital integrating charge-digital conversion circuit for measuring current, which is composed of an injection tube, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor, wherein:

[0038] One end of the injection tube is connected to the device generating the current to be measured, and the other end is connected to the upper plate of the integration capacitor and one input terminal of the comparator; the lower plate of the integration capacitor is connected to the common voltage Vcom; the other input terminal of the comparator is connected to the decision voltage Vth, and the output terminal is connected to the input of the monostable circuit, and the output of the monostable circuit is connected to the input of the counter and the input of the control signal generation circuit; the first output signal S1 of the control signal generation circuit controls the charge storage switch, and the second output signal S2 controls the charge transfer switch; one plate of the unit charge storage capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch is connected to the reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integration capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integration capacitor.

[0039] Further, the integration conversion of current to digital is completed through the timing relationships of signals such as RST, Vp, S1, and S2, wherein:

[0040] The voltage VB provides appropriate bias conditions for the device that generates the measured current through the injection tube; first, the reset signal RST is valid, the reset switch is turned on, and the voltage Vint on the integration capacitor Cint is reset to Vrst, and at the same time the counter is reset; then the reset signal RST becomes invalid, the reset switch is turned off, and integration starts, that is, the measured current Ip discharges the charge on the integration capacitor Cint. When the integration voltage Vint drops below the comparator decision voltage Vth, the output Vout of the comparator flips, and a pulse signal Vp is generated through the monostable circuit, and the output Do of the counter is incremented by 1; the pulse signal Vp generates two control signals S1 and S2 through the control signal generation circuit, where S1 controls the charge storage switch and S2 controls the charge transfer switch; during the reset and integration of the integration capacitor Cint, S1 is valid, the charge storage switch is closed, and the unit charge storage capacitor Co is connected to the reset voltage Vrst, so that the unit charge Qo is stored on the charge storage capacitor Co. During this period, S2 is invalid and the charge transfer switch is turned off; when the pulse signal Vp output by the monostable circuit is valid, S1 is invalid and the charge storage switch is turned off. After a certain time interval, S2 is valid and the charge transfer switch is closed, and the unit charge Qo is transferred to the integration capacitor Cint, and the voltage Vint on this capacitor is restored to be higher than the decision level Vth, causing the comparator output to recover; after the pulse signal Vp becomes invalid, a new integration starts, that is, the measured current Ip discharges the integration capacitor Cint again; after a certain time interval, S1 is valid and the charge storage switch is closed, and the unit charge storage capacitor Co is connected to the reset voltage Vrst; the above processes of integration, unit charge storage, transfer, and integration voltage recovery are repeated until the specified integration time Tint, and the value N of the counter output Do is the quantization result of the measured current Ip.

[0041] According to a second aspect, the present invention provides a digital integration charge-digital conversion circuit for measuring capacitance, which is composed of a current source, an integration capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, and a charge transfer switch, wherein:

[0042] The upper plate of the integrating capacitor is connected to a current source and one input terminal of a comparator. The lower plate of the integrating capacitor is connected to a common voltage Vcom. The other input terminal of the comparator is connected to a decision voltage Vth, and the output terminal is connected to the input of a monostable circuit. The output of the monostable circuit is connected to the input of a counter and the input of a control signal generation circuit. The first output signal S1 of the control signal generation circuit controls a charge storage switch, and the second output signal S2 controls a charge transfer switch. One plate of the capacitor under test is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to a reference voltage Vref. The other end of the charge storage switch is connected to a reset voltage Vrst. The other end of the charge transfer switch is connected to the upper plate of the integrating capacitor. One end of a reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor.

[0043] Further, the capacitance-to-digital integration conversion is completed through the timing relationships of signals such as RST, Vp, S1, and S2, where:

[0044] First, the reset signal RST is valid, the reset switch is turned on, and the voltage on the integrating capacitor Cint is reset to Vrst. At the same time, the counter is reset. Then, the reset signal RST becomes invalid, the reset switch is turned off, and integration starts, that is, the current Ip of the current source discharges the charge on the integrating capacitor. When the integration voltage Vint drops below the comparator decision voltage Vth, the output Vout of the comparator flips, and a pulse signal Vp is generated through the monostable circuit. The output Do of the counter is incremented by 1. The pulse signal Vp generates two control signals S1 and S2 through the control signal generation circuit, where S1 controls the charge storage switch and S2 controls the charge transfer switch. During the reset and integration of the integrating capacitor Cint, S1 is valid, the charge storage switch is closed, and the capacitor under test Co is connected to the reset voltage Vrst, so that a unit charge Qo is stored on the capacitor under test Co. During this period, S2 is invalid, and the charge transfer switch is turned off. When the pulse signal Vp output by the monostable circuit is valid, S1 is invalid, the charge storage switch is turned off. After a certain time interval, S2 is valid, the charge transfer switch is closed, and the unit charge Qo is transferred to the integrating capacitor Cint. The voltage on this capacitor returns to a level higher than the decision level Vth, causing the comparator output to recover. After the pulse signal Vp becomes invalid, a new integration starts, that is, the current Ip discharges the integrating capacitor Cint again. After a certain time interval, S1 is valid, the charge storage switch is closed, and the capacitor under test Co is connected to the reset voltage Vrst. The above processes of integration, unit charge storage, transfer, and integration voltage recovery are repeated until the specified integration time Tint, at which time the value N of the output Do of the counter is the quantization result of the capacitor under test Co.

[0045] The principle of the present invention is:

[0046] Taking the integration process of discharging the integration capacitor with the measured current (or the current of the current source) Ip as an example to illustrate the principle of the present invention, all control signals are active high. The working timings of the relevant signals are shown in Figure 2 .

[0047] In the reset stage, that is, when RST is valid, the integration capacitor Cint is connected to the reset voltage Vrst, and the voltage Vint on the capacitor is Vrst. Since Vint is greater than the comparator decision voltage Vth, the comparator output Vout is at a low level, the monostable circuit output Vp is at a low level, and the counter output is reset to 0. During the reset period, the output signal S1 of the control signal generation circuit is valid, and S2 is invalid, that is, the unit charge storage capacitor (or the measured capacitor) Co is connected to Vrst through the charge storage switch to store charge:

[0048] Q0 = C0(V rst -V ref )(10)

[0049] After the reset signal RST becomes invalid, the current Ip discharges the integration capacitor Cint until its voltage Vint is lower than Vth, causing the comparator output Vout to become high, triggering the monostable circuit output Vp to become high, and lasting for a certain time to form a narrow pulse, and the count value of the counter is incremented by 1. When Vp becomes high, it triggers the output signal S1 of the control signal generation circuit to become invalid, disconnecting the connection between the capacitor Co and the reset voltage Vrst. After a certain time interval, S2 becomes valid, transferring the charge Qo on the capacitor Co to the integration capacitor Cint, and the voltage Vint returns to be higher than Vth. Then S2 becomes invalid, disconnecting the connection between the capacitor Co and the integration capacitor Cint, and the current Ip starts a new integration of the integration capacitor Cint. After a certain time interval, S1 becomes valid, connecting the capacitor Co to Vrst, and re-storing the charge Qo onto the capacitor Co.

[0050] To prevent errors caused by charge leakage on the capacitor Co, the outputs S1 and S2 of the control signal generation circuit cannot be valid at the same time, that is, there must be a certain time interval between their high levels to form non-overlapping valid levels.

[0051] The above processes of integration, storing the charge Qo, and transferring the charge Qo are repeated until the specified integration time Tint, and the counter counts the number of pulses Vp to obtain the value N:

[0052]

[0053] Since the unit charge Qo is determined by the capacitance Co, the reset voltage Vrst, and the reference voltage Vref, and is not affected by the comparator decision voltage Vth and the delay time Td, the count value N has a linear proportional relationship with the current Ip and a linear inverse relationship with the capacitance Co. Therefore, the count value N can linearly quantify the current Ip or the capacitance Co to achieve charge-to-digital conversion.

[0054] The total charge storage capacity is

[0055] Q max = NQ0 = NC0(V rst -V ref )(11)

[0056] Since the charge storage capacity is increased by N times of Qo, the integration time can be extended, and the dynamic range and signal-to-noise ratio can be improved.

[0057] The present invention is also applicable to the integration process in which the current Ip charges the integration capacitor. As long as the Vrst voltage value is set to be lower than Vref and Vcom, the input signal polarity of the triggered monostable circuit output Vp is changed from low level to high level, or an inverter is inserted between the comparator and the monostable circuit to invert the signal, the same function can be achieved, and the current Ip or the capacitance Co can be measured.

[0058] According to the specific circuit implementation requirements, the circuit of the present invention can be configured such that the control signal is valid at a low level. The connection modes of the upper and lower plates of the relevant capacitor can also be adjusted according to the actual circuit requirements.

[0059] The beneficial effects of the present invention are as follows:

[0060] For the existing voltage reset digital integration circuit, since it is a voltage reset operation, the unit charge for each count (formula (7)) is affected by the comparator decision voltage Vth and the delay time Td, resulting in a non-linear relationship between the count value (i.e., formula (9)) and the current to be measured. However, for the technical solution provided by the present invention, while increasing the charge storage capacity to obtain an improvement in the dynamic range and signal-to-noise ratio, charge storage and transfer operations are adopted to avoid the non-linearity introduced by non-ideal factors such as the comparator in voltage operations. The obtained output result can linearly convert the current or capacitance into a digital value, reducing the requirements for the comparator circuit design, that is, a high-quality charge quantization can be achieved without a low delay time and a high-precision comparator, thereby reducing the power consumption and area of the charge-to-digital conversion circuit. At the same time, since the output result is a linear conversion of the current or capacitance, there is no need for subsequent circuits to perform complex processing to improve the linearity of current or capacitance measurement, reducing the design complexity of the entire sensor system. Description of the Drawings

[0061] Figure 1This is the schematic diagram of the digital integrating charge-digital conversion circuit for measuring current according to the present invention; Figure 1 Among them:

[0062] 300 - Digital integrating charge-digital conversion circuit for measuring current, 301 - Device for generating the current to be measured, 302 - Injection tube, 303 - Integrating capacitor, 304 - Reset switch, 305 - Comparator, 306 - Monostable circuit, 307 - Counter, 308 - Control signal generation circuit, 309 - Charge storage switch, 310 - Charge transfer switch, 311 - Unit charge storage capacitor.

[0063] Figure 2 This is the signal diagram of the digital integrating charge-digital conversion circuit for measuring current or capacitance according to the present invention.

[0064] Figure 3 This is the schematic diagram of the digital integrating charge-digital conversion circuit for measuring capacitance according to the present invention, Figure 3 Among them:

[0065] 500 - Digital integrating charge-digital conversion circuit for measuring capacitance, 501 - Capacitance to be measured, 502 - Current source, 503 - Integrating capacitor, 504 - Reset switch, 505 - Comparator, 506 - Monostable circuit, 507 - Counter, 508 - Control signal generation circuit, 509 - Charge storage switch, 510 - Charge transfer switch. Specific embodiments

[0066] The following further describes the present invention in detail through embodiments with reference to the accompanying drawings. However, the protection scope of the present invention is not limited to the following embodiments.

[0067] Embodiment 1

[0068] As Figure 1 shown, a digital integrating charge-digital conversion circuit 300 for measuring current is composed of an injection tube 302, an integrating capacitor 303, a reset switch 304, a comparator 305, a monostable circuit 306, a counter 307, a control signal generation circuit 308, a charge storage switch 309, a charge transfer switch 310 and a unit charge storage capacitor 311. Among them:

[0069] One end of the injection tube 302 is connected to the device 301 that generates the current to be measured, and the other end is connected to the upper plate of the integrating capacitor 303 and one input terminal of the comparator 305; the lower plate of the integrating capacitor 303 is connected to the common voltage Vcom; the other input terminal of the comparator 305 is connected to the decision voltage Vth, and the output terminal is connected to the input of the monostable circuit 306. The output of the monostable circuit 306 is connected to the input of the counter 307 and the input of the control signal generation circuit 308; the first output signal S1 of the control signal generation circuit 308 controls the charge storage switch 309, and the second output signal S2 controls the charge transfer switch 310; one plate of the unit charge storage capacitor 311 is connected to the charge storage switch 309 and the charge transfer switch 310, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch 309 is connected to the reset voltage Vrst; the other end of the charge transfer switch 310 is connected to the upper plate of the integrating capacitor 303; one end of the reset switch 304 is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor 303.

[0070] The function of the comparator 305 is to compare the input voltage with the decision voltage Vth. If the input voltage is higher than the decision voltage, the comparator 305 outputs a high level. If the input voltage is lower than the decision voltage, the comparator 305 outputs a low level. The monostable circuit 306 is used to generate a pulse with a certain width when the output of the comparator 305 flips, to avoid mis-triggering multiple pulses caused by power supply interference, noise, etc. The counter 307 and the control signal generation circuit 308 are both digital circuits. The former realizes counting and accumulation, and the latter generates Figure 2 the non-overlapping control signals S1 and S2 shown.

[0071] Furthermore, referring to Figure 2 , the current-to-digital integration conversion is completed through the timing relationships of signals such as RST, Vp, S1, and S2, where:

[0072] The voltage VB provides appropriate bias conditions for the device 301 that generates the current to be measured through the injection tube 302. First, the reset signal RST is valid, the reset switch 304 is turned on, and the voltage Vint on the integration capacitor 303 is reset to Vrst. At the same time, the counter 307 is reset. Then, the reset signal RST becomes invalid, the reset switch 304 is turned off, and the integration starts, that is, the current to be measured Ip discharges the charge on the integration capacitor 303. When the integration voltage Vint drops below the decision voltage Vth of the comparator 305, the output Vout of the comparator flips, and a pulse signal Vp is generated through the monostable circuit 306. The output Do of the counter 307 is incremented by 1. The pulse signal Vp generates two control signals S1 and S2 through the control signal generation circuit 308. Among them, S1 controls the charge storage switch 309, and S2 controls the charge transfer switch 310. During the reset and integration of the integration capacitor 303, S1 is valid, the charge storage switch 309 is closed, and the unit charge storage capacitor Co 311 is connected to the reset voltage Vrst, so that the unit charge Qo is stored on the capacitor Co 311. During this period, S2 is invalid, and the charge transfer switch 310 is turned off. When the pulse signal Vp output by the monostable circuit 306 is valid, S1 is invalid, the charge storage switch 309 is turned off. After a certain time interval, S2 is valid, the charge transfer switch 310 is closed, and the unit charge Qo is transferred to the integration capacitor Cint 303. The voltage Vint on this capacitor is restored to be higher than the decision level Vth, and the output of the comparator 305 is restored. After the pulse signal Vp becomes invalid, a new integration starts, that is, the current to be measured Ip discharges the integration capacitor Cint again. After a certain time interval, S1 is valid, the charge storage switch 309 is closed, and the unit charge storage capacitor Co 311 is connected to the reset voltage Vrst. The above process of integration, unit charge storage, transfer, and integration voltage restoration is repeated until it stops at the specified integration time Tint. The value N of the output Do of the counter 307 is the quantization result of the current Ip to be measured.

[0073] Embodiment 2

[0074] As Figure 3 shown, a digital integrating charge-digital conversion circuit 500 for measuring capacitance is composed of a current source 502, an integration capacitor 503, a reset switch 504, a comparator 505, a monostable circuit 506, a counter 507, a control signal generation circuit 508, a charge storage switch 509, and a charge transfer switch 510, where:

[0075] The upper plate of the integrating capacitor 503 is connected to the current source 502 and one input terminal of the comparator 505. The lower plate of the integrating capacitor 503 is connected to the common voltage Vcom. The other input terminal of the comparator 505 is connected to the decision voltage Vth, and the output terminal is connected to the input of the monostable circuit 506. The output of the monostable circuit 506 is connected to the input of the counter 507 and the input of the control signal generation circuit 508. The first output signal S1 of the control signal generation circuit 508 controls the charge storage switch 509, and the second output signal S2 controls the charge transfer switch 510. One plate of the measured capacitor 501 is connected to the charge storage switch 509 and the charge transfer switch 510, and the other plate is connected to the reference voltage Vref. The other end of the charge storage switch 509 is connected to the reset voltage Vrst. The other end of the charge transfer switch 510 is connected to the upper plate of the integrating capacitor 503. One end of the reset switch 504 is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor 503.

[0076] Further, referring to Figure 2 , the capacitance-to-digital integration conversion is completed through the timing relationships of signals such as RST, Vp, S1, and S2, where:

[0077] First, the reset signal RST becomes valid, turning on the reset switch 504, causing the voltage on the integration capacitor 503 to be reset to Vrst, and at the same time, the counter 507 is reset. Then, the reset signal RST becomes invalid, turning off the reset switch 504, and integration starts, that is, the current Ip of the current source discharges the charge on the integration capacitor 503. When the integration voltage Vint drops below the decision voltage Vth of the comparator 505, the output Vout of the comparator flips, and a pulse signal Vp is generated through the monostable circuit 506, and the output Do of the counter 507 is incremented by 1. The pulse signal Vp generates two control signals S1 and S2 through the control signal generation circuit 508, where S1 controls the charge storage switch 509 and S2 controls the charge transfer switch 510. During the reset and integration of the integration capacitor Cint 503, S1 is valid, closing the charge storage switch 509, connecting the measured capacitor Co 501 to the reset voltage Vrst, so that the unit charge Qo is stored on the measured capacitor Co 501. During this period, S2 is invalid, disconnecting the charge transfer switch 510. When the pulse signal Vp output by the monostable circuit 506 is valid, S1 is invalid, disconnecting the charge storage switch 509. After a certain time interval, S2 is valid, closing the charge transfer switch 510, transferring the unit charge Qo to the integration capacitor Cint 503, and the voltage on this capacitor is restored to be higher than the decision level Vth, causing the output of the comparator 505 to be restored. After the pulse signal Vp becomes invalid, a new integration starts, that is, the current Ip discharges the integration capacitor Cint again. After a certain time interval, S1 is valid, closing the charge storage switch 509, connecting the measured capacitor Co 501 to the reset voltage Vrst. The above process of integration, unit charge storage, transfer, and integration voltage restoration is repeated until it stops at the specified integration time Tint. The value N of the output Do of the counter 507 is the quantization result of the measured capacitor Co.

[0078] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A digital integrating charge-digital conversion circuit for measuring current, characterized in that, The circuit consists of an injection tube, an integrating capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, a charge transfer switch, and a unit charge storage capacitor, where: One end of the injection tube is connected to the device that generates the current to be measured, and the other end is connected to the upper plate of the integrating capacitor and one input terminal of the comparator; the lower plate of the integrating capacitor is connected to the common voltage Vcom; the other input terminal of the comparator is connected to the decision voltage Vth, and its output terminal is connected to the input of the monostable circuit, and the output of the monostable circuit is connected to the input of the counter and the input of the control signal generation circuit; the first output signal S1 of the control signal generation circuit controls the charge storage switch, and the second output signal S2 controls the charge transfer switch; one plate of the unit charge storage capacitor is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to the reference voltage Vref; the other end of the charge storage switch is connected to the reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor; During the reset and integration of the integrating capacitor, S1 is valid, closing the charge storage switch, connecting the unit charge storage capacitor to the reset voltage Vrst, so that a unit charge is stored on the charge storage capacitor. During this period, S2 is invalid and the charge transfer switch is disconnected; when the pulse signal Vp output by the monostable circuit is valid, S1 is invalid and the charge storage switch is disconnected. After a certain time interval, S2 is valid and the charge transfer switch is closed, transferring the unit charge to the integrating capacitor, and the voltage on the integrating capacitor is restored to be higher than the decision level Vth, causing the output of the comparator to be restored.

2. The digital integrating charge-digital conversion circuit for measuring current according to claim 1, wherein: The effective levels of the output signals S1 and S2 of the control signal generation circuit do not overlap, that is: when S1 is effective, S2 is invalid, and when S2 is effective, S1 is invalid.

3. The digital integrating charge-digital conversion circuit for measuring current according to claim 2, wherein: The effective levels of the output signals S1 and S2 are high levels.

4. The digital integrating charge-digital conversion circuit for measuring current according to claim 2, wherein: The effective levels of the output signals S1 and S2 are low levels.

5. A digital integrating charge-digital conversion circuit for measuring capacitance, characterized in that, The circuit consists of a current source, an integrating capacitor, a reset switch, a comparator, a monostable circuit, a counter, a control signal generation circuit, a charge storage switch, and a charge transfer switch; where: The upper plate of the integrating capacitor is connected to a current source and one input terminal of a comparator, and the lower plate of the integrating capacitor is connected to a common voltage Vcom; the other input terminal of the comparator is connected to a decision voltage Vth, and its output terminal is connected to the input of a monostable circuit, and the output of the monostable circuit is connected to the input of a counter and the input of a control signal generation circuit; the first output signal S1 of the control signal generation circuit controls a charge storage switch, and the second output signal S2 controls a charge transfer switch; one plate of the capacitor under test is connected to the charge storage switch and the charge transfer switch, and the other plate is connected to a reference voltage Vref; the other end of the charge storage switch is connected to a reset voltage Vrst; the other end of the charge transfer switch is connected to the upper plate of the integrating capacitor; one end of the reset switch is connected to the reset voltage Vrst, and the other end is connected to the upper plate of the integrating capacitor. During the reset and integration of the integrating capacitor, S1 is valid, closing the charge storage switch, connecting the capacitor under test to the reset voltage Vrst, so that a unit charge is stored on the capacitor under test. During this period, S2 is invalid, disconnecting the charge transfer switch; when the pulse signal Vp output by the monostable circuit is valid, S1 is invalid, disconnecting the charge storage switch, and after a certain time interval, S2 is valid, closing the charge transfer switch, transferring a unit charge to the integrating capacitor, and the voltage on the integrating capacitor is restored to be higher than the decision level Vth, causing the output of the comparator to recover.

6. The digital integrating charge-digital conversion circuit for measuring a capacitor according to claim 5, wherein: The effective levels of the output signals S1 and S2 of the control signal generation circuit do not overlap, that is: when S1 is effective, S2 is invalid, and when S2 is effective, S1 is invalid.

7. The digital integrating charge-digital conversion circuit for measuring a capacitor according to claim 6, wherein: The effective levels of the output signals S1 and S2 are high levels.

8. The digital integrating charge-digital conversion circuit for measuring a capacitor according to claim 6, wherein: The effective levels of the output signals S1 and S2 are low levels.

Images