Imaging element and ranging module

Abstract

This technology relates to an imaging element and a ranging module capable of reducing parasitic capacitance. The ranging module of the present invention includes: a first wiring that connects predetermined transistors in first adjacent pixels to each other and to a via formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring that connects predetermined transistors in second adjacent pixels to each other and to a via formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, wherein the first wiring is connected to a redundant wiring. For example, this technology can be applied to a ranging sensor that performs distance measurement.

Description

Technical Field

[0001] The present technology relates to an imaging element and a ranging module, and particularly to an imaging element and a ranging module capable of achieving reduction of cyclic error and dispersion of drive current. Background Art

[0002] A ToF sensor, which measures the distance to an object by measuring the time of flight of light, causes a light source to output modulated light and receives reflected light that is reflected by and returns from the object. Although the modulated light output from the light source is treated as having a sinusoidal waveform and undergoes signal processing for distance measurement, the light actually output from the light source has a rectangular waveform. Therefore, processing the rectangular wave as a sine wave causes a periodic error (hereinafter referred to as a cyclic error) in the measured value.

[0003] For example, there has been disclosed a technology for generating a pseudo-sine wave by shifting the phase of modulated light output from a light emitting source to thereby reduce a cyclic error (for example, see PTL 1).

[0004] Furthermore, the number of pixels in ToF sensors has been increasing in recent years. If a large number of pixels are driven simultaneously, the driving current becomes concentrated, and the strong charge and discharge currents can cause IR drop, making it impossible to accurately drive the pixels. Therefore, technologies have been considered to reduce peak current by distributing pixel driving to prevent IR drop (for example, see NPLs 1 and 2).

[0005] [Citation List]

[0006] [Patent Document]

[0007] [Patent Document 1]

[0008] WO 2009 / 051499

[0009] [Non-patent literature]

[0010] [NPL 1]

[0011] Cyrus S Bamji,et al.,5.8 1Mpixel 65nm BSI 320MHz Demodulated TOFImage Sensor with 3.5um Global Shutter Pixels and Analog Binning,MicrosoftCorp.,2018IEEE International Solid-State Circuits Conference SESSION 5 / IMAGESENSORS,February 12th,2018.

[0012] [NPL 2]

[0013] Min-Sun Keel,et al.,A 640×480Indirect Time-of-Flight CMOS ImageSensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase NoiseSelf-Compensation Scheme,Samsung Electronics Co.,Ltd.,2019Symposium on VLSICircuits Digest of Technical Papers. Summary of the Invention

[0014] [Technical Issues]

[0015] However, the techniques in NPL 1 and NPL 2 do not take loop errors into consideration, nor do they propose a method for achieving both reduction of loop errors and dispersion of drive currents.

[0016] The present technology has been made in view of such circumstances, and can achieve reduction in loop error and dispersion of drive current.

[0017] [Solution to the problem]

[0018] An imaging element according to one aspect of the present technology includes: a first wiring that connects a predetermined transistor in a first adjacent pixel to a through-hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring that connects a predetermined transistor in a second adjacent pixel to a through-hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, wherein the first wiring is connected to a redundant wiring.

[0019] A ranging module according to one aspect of the present technology includes: a light-emitting unit that emits irradiation light; and a light-receiving element that receives reflected light obtained by reflecting the light from the light-emitting unit by an object; wherein the light-receiving element includes a photoelectric conversion unit that performs photoelectric conversion, a plurality of charge accumulation units that accumulate charges obtained by the photoelectric conversion unit, and a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring that connects the transfer unit in a first adjacent pixel to a through hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring that connects the transfer unit in a second adjacent pixel to a through hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, and the first wiring is connected to a redundant wiring.

[0020] An imaging element according to one aspect of the present technology includes: a first wiring that connects a predetermined transistor in a first adjacent pixel to a through-hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring that connects a predetermined transistor in a second adjacent pixel to a through-hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, and the first wiring is connected to a redundant wiring.

[0021] A distance measuring module according to an aspect of the present technology includes: a light emitting unit that emits irradiation light; and a light receiving element that receives reflected light obtained by reflecting the light from the light emitting unit by an object. An imaging element is included as the light receiving element.

[0022] The ranging module may be an independent device or may be a module incorporated in another device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 : is a block diagram showing a schematic configuration example of a distance measurement module to which the present technology is applied.

[0024] Figure 2 is a block diagram showing a detailed configuration example of a light receiving unit.

[0025] Figure 3 is a diagram for explaining the operation of a pixel.

[0026] Figure 4 is a diagram showing an example of a circuit configuration of a pixel.

[0027] Figure 5 is a diagram showing an example of a planar configuration of pixels.

[0028] Figure 6 is a diagram showing an example of a cross-sectional configuration of a pixel.

[0029] Figure 7 It is a diagram for explaining a two-phase scheme and a four-phase scheme.

[0030] Figure 8 It is a diagram for explaining a two-phase scheme and a four-phase scheme.

[0031] Figure 9 It is a diagram for explaining a two-phase scheme and a four-phase scheme.

[0032] Figure 10 is a block diagram showing a more detailed configuration example of the light receiving unit.

[0033] Figure 11 is a diagram for explaining phase shift processing.

[0034] Figure 12 is a diagram for explaining the charge accumulation time of each phase.

[0035] Figure 13 is a diagram for explaining phase shift control of each block.

[0036] Figure 14 It is a diagram for explaining IQ mosaic driving.

[0037] Figure 15 It is a diagram for explaining IQ mosaic driving.

[0038] Figure 16 is a diagram showing an example of IQ mosaic driving, in which the number of divisions in phase control is four.

[0039] Figure 17 is a diagram for explaining phase shift control of each block.

[0040] Figure 18 is a diagram showing an example of IQ mosaic driving, in which the number of divisions in phase control is four.

[0041] Figure 19 is a diagram for explaining the effect of cyclic error using pseudo-sin.

[0042] Figure 20 This is a diagram for explaining wiring.

[0043] Figure 21 3 is a diagram for explaining wiring in the wiring layer M1 .

[0044] Figure 22 3 is a diagram for explaining wiring in the wiring layer M2.

[0045] Figure 23 3 is a diagram for explaining wiring in the wiring layer M3.

[0046] Figure 243 is a diagram for explaining wiring in the wiring layer M4.

[0047] Figure 25 3 is a diagram for explaining wiring connected to wiring in the wiring layer M4 .

[0048] Figure 26 is a perspective view showing an example of the chip configuration of a distance measuring sensor.

[0049] Figure 27 : is a block diagram showing a configuration example of a smartphone as an electronic device equipped with a distance measurement module.

[0050] Figure 28 is a block diagram showing an exemplary schematic configuration of a vehicle control system.

[0051] Figure 29 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0052] Modes for carrying out the present technology (hereinafter referred to as “embodiments”) will be described below.

[0053] <Schematic Configuration Example of Distance Measurement Module>

[0054] Figure 1 : is a block diagram showing a schematic configuration example of a distance measurement module to which the present technology is applied.

[0055] Figure 1 The ranging module 11 shown in FIG. 1 is a ranging module that performs distance measurement based on an indirect ToF scheme and includes a light emitting unit 12 and a ranging sensor 13. The ranging module 11 illuminates an object with light, receives light (reflected light) reflected from the object, and thereby generates and outputs a depth map as information about the distance to the object. The ranging sensor 13 is composed of a light emitting control unit 14, a light receiving unit 15, and a signal processing unit 16.

[0056] The light emitting unit 12 includes a vertical cavity surface emitting laser (VCSEL) array as a light emitting source, in which a plurality of VCSELs are arranged in a planar shape, for example, and emits light while modulating the light according to the timing of the light emitting control signal supplied from the light emitting control unit 14, and illuminates an object with the irradiation light.

[0057] The light emission control unit 14 controls the light emission unit 12 by supplying a light emission control signal of a predetermined frequency (e.g., 200 MHz) to the light emission unit 12. In addition, the light emission control unit 14 also supplies a light emission control signal to the light receiving unit 15 so as to drive the light receiving unit 15 when the light emission unit 12 performs light emission.

[0058] The light receiving unit 15 receives light reflected by an object through a pixel array unit 32 in which a plurality of pixels 31 are two-dimensionally arranged, which will be referred to later. Figure 2 Details are described. In addition, the light receiving unit 15 supplies pixel data constituted by a detection signal according to the light reception amount of the received reflected light to the signal processing unit 16 in units of pixels 31 in the pixel array unit 32 .

[0059] The signal processing unit 16 calculates a depth value (i.e., the distance between the ranging module 11 and the object) based on the pixel data provided from the light receiving unit 15 for each pixel 31 in the pixel array unit 32, generates a depth value to store as a depth map of the pixel value of each pixel 31, and outputs the depth map to the outside of the module.

[0060] <Basic pixel driving based on indirect ToF solution>

[0061] Before describing the details of pixel driving performed by the light receiving unit 15 according to the present disclosure, basic pixel driving based on the indirect ToF scheme (basic pixel driving) will be described.

[0062] Figure 2 2 is a block diagram showing a detailed configuration example of the light receiving unit 15 .

[0063] The light receiving unit 15 includes: a pixel array unit 32 in which pixels 31 that generate charges according to the amount of received light and output detection signals according to the charges are two-dimensionally arranged in a matrix shape in the row direction and the column direction; and a drive control circuit 33 arranged in the surrounding area of ​​the pixel array unit 32.

[0064] For example, the drive control circuit 33 outputs control signals for controlling driving of the pixels 31 (eg, a distribution signal DIMIX, a selection signal ADDRESSDECODE, and a reset signal RST to be described later) based on the emission control signal supplied from the emission control unit 14 .

[0065] Each pixel 31 includes a photodiode 51 serving as a photoelectric conversion unit that generates charge according to the amount of received light, and taps 52A and 52B that detect the charge generated by the photodiode 51. In the pixel 31, the charge generated by one photodiode 51 is distributed to either the tap 52A or the tap 52B. Of the charge generated by the photodiode 51, the charge distributed to the tap 52A is output from the signal line 53A as a detection signal A, and the charge distributed to the tap 52B is output from the signal line 53B as a detection signal B.

[0066] The tap 52A is composed of the transfer transistor 41A, the floating diffusion (FD) unit 42A, the selection transistor 43A, and the reset transistor 44A. Similarly, the tap 52B is composed of the transfer transistor 41B, the FD unit 42B, the selection transistor 43B, and the reset transistor 44B.

[0067] The modulated illumination light (1 period = 2T) is output from the light emitting unit 12 so that Figure 3 The illumination is repeatedly turned on and off for the illumination time T shown, and the reflected light is received by the photodiode 51 with a delay of delay time ΔT according to the distance to the object. Furthermore, the distribution signal DIMIX_A is used to control the on / off switching of the transfer transistor 41A, and the distribution signal DIMIX_B is used to control the on / off switching of the transfer transistor 41B. The distribution signal DIMIX_A is a signal in phase with the illumination light, and the distribution signal DIMIX_B is a signal in phase opposite to the distribution signal DIMIX_A.

[0068] Therefore, in Figure 2 In the embodiment of the present invention, when the transfer transistor 41A is turned on according to the distribution signal DIMIX_A, the charge generated by the photodiode 51 receiving the reflected light is transferred to the FD unit 42A, or when the transfer transistor 41B is turned on according to the distribution signal DIMIX_B, the charge generated by the photodiode 51 receiving the reflected light is transferred to the FD unit 42B. In this way, in a predetermined period in which irradiation with irradiation light is cyclically performed in the irradiation time T, the charge transferred via the transfer transistor 41A is successively accumulated in the FD unit 42A, and the charge transferred via the transfer transistor 41B is successively accumulated in the FD unit 42B.

[0069] Once the selection transistor 43A is turned on according to the selection signal ADDRESS DECODE_A after the period of charge accumulation ends, the charge accumulated in the FD unit 42A is read via the signal line 53A, and a detection signal A according to the amount of charge is output from the light receiving unit 15. Similarly, once the selection transistor 43B is turned on according to the selection signal ADDRESS DECODE_B, the charge accumulated in the FD unit 42B is read via the signal line 53B, and a detection signal B according to the amount of charge is output from the light receiving unit 15. Furthermore, when the reset transistor 44A is turned on according to the reset signal RST_A, the charge accumulated in the FD unit 42A is released, and when the reset transistor 44B is turned on according to the reset signal RST_B, the charge accumulated in the FD unit 42B is released.

[0070] In this manner, the pixel 31 distributes the charge generated by the reflected light received by the photodiode 51 to the tap 52A or the tap 52B according to the delay time ΔT and outputs the detection signal A and the detection signal B as pixel data.

[0071] The signal processing unit 16 calculates a depth value based on the detection signal A and the detection signal B supplied as pixel data from each pixel 31. Figure 7 Describes the calculation of depth values.

[0072] <Unit Pixel Structure>

[0073] Next, a specific structure of the pixels 31 arranged in a matrix shape in the pixel array unit 32 will be described.

[0074] Each pixel 31 includes a photodiode 51 (hereinafter referred to as PD 51) as a photoelectric conversion element and is configured so that the charge generated by the PD 51 is distributed to a tap 52A and a tap 52B. Of the charges generated by the PD 51, the charge distributed to the tap 52A is read out from the vertical signal line 53A and then output as a detection signal SIG1. Furthermore, the charge distributed to the tap 52B is read out from the vertical signal line 53B and then output as a detection signal SIG2.

[0075] The configurations of the tap 52A and the tap 52B are basically similar to each other. The tap 52A and the tap 52B both implement an FD type global shutter. Figure 4 In the example, the tap 52A of the pixel 31 in the pixel array unit 32 includes, for example, a transfer transistor (TG) 41A, a floating diffusion (FD) 42A serving as a charge retention unit and a charge-voltage conversion unit, a selection transistor (SEL) 43A, a reset transistor (RST) 44A, an amplifier transistor (AMP) 45A, a feedback enable transistor (FBEN) 46A, a discharge transistor (OFG) 47, a conversion efficiency switching transistor (FDG) 48A, and an additional capacitance unit 49A.

[0076] Similarly, the tap 52B is composed of the transfer transistor 41B, the FD 42B, the selection transistor 43B, the reset transistor 44B, the amplification transistor 45B, the FBEN 46B, the FDG 48B, and the additional capacitance unit 49B.

[0077] It should be noted that the Figure 4 The configuration in which the reset transistor 44 is provided in each of the FD 42A and the FD 42B is shown, or a configuration in which the reset transistor 44 is shared by the FD 42A and the FD 42B may be adopted.

[0078] In adopting Figure 4In the case of the configuration shown in which the reset transistors 44A and 44B are provided in the FD 42A and FD 42B, respectively, the reset timings of the FD 42A and FD 42B can be controlled independently, and thus fine control can be performed. When a configuration is adopted in which the reset transistor 44 is provided in common for the FD 42A and FD 42B, the reset timings of the FD 42A and FD 42B can be the same, and thus control can be simplified, and the circuit configuration can also be simplified.

[0079] In the following description, a configuration in which the reset transistor 44 is provided in each of the FD 42A and the FD 42B will be described as an example. Figure 4 In the following description, the tap 52A and the tap 52B basically have a similar configuration, and thus the tap 52A will be described as an example.

[0080] exist Figure 4 In the example shown, TG 41A, FD 42A, SEL 43A, RST 44A, AMP 45A, FBEN 46A, and OFG 47 are all N-type MOS transistors. A drive signal is supplied to each gate electrode of TG 41A, FD 42A, SEL 43A, RST 44A, AMP 45A, FBEN 46A, and OFG 47. Each drive signal is a pulse signal that corresponds to an active state (i.e., an on state) when in a high-level state and to an inactive state (i.e., an off state) when in a low-level state. In the following description, turning a drive signal into an active state is also referred to as turning on the drive signal, and turning a drive signal into an inactive state is also referred to as turning off the drive signal.

[0081] The PD 51 is a photoelectric conversion element composed of a PN junction photodiode, and functions as a photoelectric conversion unit that receives light from an object, generates charges according to the amount of received light through photoelectric conversion, and accumulates the charges.

[0082] The TG 41A is connected between the PD 51 and the FD 42A and functions as a transfer unit that transfers the charge accumulated in the PD 51 to the FD 42A according to a drive signal applied to the gate electrode of the TG 41A.

[0083] The FD 42A serves as a charge retention unit that temporarily holds the charge accumulated in the PD 51 to implement a global shutter function. Furthermore, the FD 42A also serves as a floating diffusion region that converts the charge transferred from the PD 51 via the TG 41A into an electrical signal (e.g., a voltage signal) and outputs the electrical signal. The RST 44A is connected to the FD 42A, and the VSL 53A is also connected to the FD 42A via the AMP 45A and the SEL 43A.

[0084] Furthermore, an additional capacitance unit 49A, which is a floating diffusion region (FD) that converts charge into an electrical signal (e.g., a voltage signal), is also connected to the FD 42A via the FDG 48A. Note that although the additional capacitance unit 49A is a floating diffusion region (FD), the additional capacitance unit 49A also operates as a capacitor in the same manner as the FD 42, and therefore, it is assumed that the additional capacitance unit 49A is expressed using a capacitor circuit symbol.

[0085] The FDG 48A switches the connection state of the FD 42A and the additional capacitance unit 49A between an electrically connected state and an electrically disconnected state by being turned on and off according to the drive signal FDG. The FDG 48A functions as an additional control unit that controls the addition of the additional capacitance unit 49A.

[0086] The drive signal FDG is supplied to the gate electrode constituting the FDG 48A, and once the drive signal FDG is turned on, the potential immediately below the FDG 48A becomes deeper, and electrical connection is established between the FD 42A and the additional capacitance unit 49A.

[0087] On the other hand, when the drive signal FDG is turned off, the potential directly below FDG 48A becomes shallower, electrically disconnecting FD 42A and additional capacitance unit 49A. Therefore, turning the drive signal FDG on and off adds capacitance to FD 42A, changing the pixel's sensitivity. Specifically, if the change in accumulated charge is ΔQ, the resulting voltage change is ΔV, and the capacitance is C, the relationship ΔV = ΔQ / C holds.

[0088] Now, assuming that the capacitance value of the FD 42A is defined as CFD and the capacitance value of the additional capacitance unit 49A is defined as CFD2, then when the drive signal FDG is turned on, the capacitance value C in the region of the pixel from which the signal level reading is performed is CFD+CFD2. On the other hand, if the drive signal FDG is turned off, the capacitance value C changes to CFD, and thus the sensitivity of the voltage in response to the amount of charge change (amount of voltage change: FD conversion efficiency) is enhanced.

[0089] In this manner, the sensitivity of the pixel is appropriately changed by turning the drive signal FDG on and off for the pixel 31. Once the drive signal FDG is turned on, for example, the additional capacitance unit 49A is electrically connected to the FD 42A, and a portion of the charge transferred from the PD 51 to the FD 42A is accumulated not only in the FD 42A but also in the additional capacitance unit 49A.

[0090] The RST 44A includes a drain connected to the FBEN 46A and a source connected to the FD 42A. The RST 44A functions as a reset unit that initializes (ie, resets) the FD 42A according to a drive signal applied to its gate electrode. Figure 4 As shown, the drain of RST44A forms a parasitic capacitance C_ST with the ground and forms a parasitic capacitance C_FB with the gate electrode of AMP 45A.

[0091] The FBEN 46A functions as a reset voltage control unit that controls the reset voltage applied to the RST 44A.

[0092] OFG 47 includes a drain connected to power supply VDD and a source connected to PD 51. The cathode of PD 51 is commonly connected to the source of OFG 47 and the source of TG 41A. OFG 47 is initialized according to the drive signal applied to its gate electrode, that is, PD 51 is reset. Resetting PD 51 means depletion of PD 51.

[0093] The AMP 45A includes a gate electrode connected to the FD 42A and a drain connected to the power supply VDD, and functions as an input unit of a source follower circuit that reads the charge obtained by photoelectric conversion at the PD 51. In other words, the AMP 45A constitutes a source follower circuit together with a constant current source connected to one end of the VSL 53A through a source connected to the VSL 53A via the SEL 43A.

[0094] The SEL 43A is connected between the source of the AMP 45A and the VSL 53A, and a selection signal is supplied to the gate electrode of the SEL 43A. When the selection signal of the SEL 43A is turned on, the SEL 43A enters the power distribution state, and the tap 52A of the pixel 31 for which the SEL 43A is set enters the selection state. Once the tap 52A of the pixel 31 enters the selection state, the pixel signal output from the AMP 45A is read by the column signal processing unit 23 via the VSL 53A.

[0095] Furthermore, for example, a plurality of pixel driving lines (not shown) are arranged for each pixel row in the pixel array unit 32. Furthermore, each driving signal is supplied from the vertical driving unit 2 to the selected pixel 31 through the plurality of pixel driving lines.

[0096] Each component constituting the tap 52B is also constructed and operates in the same manner as each component constituting the above-described tap 52A.

[0097] It should be noted that in Figure 4 The pixel circuit shown in is an example of a pixel circuit that can be used in the pixel array unit 32 and can also be used in a pixel circuit having another configuration.

[0098] <Example of Pixel Plane Composition>

[0099] Figure 5 Shown in Figure 4 The circuit configuration example shown in is a planar configuration example of each pixel 31 .

[0100] like Figure 5 As shown, the PD 51 is provided in a region near the center of the rectangular pixel 31. The TG 41A and TG 41B are provided on the upper side (top side) of the PD 51 in the figure. The TG 41A is the gate portion of the transfer transistor 41A, and the TG 41B is the gate portion of the transfer transistor 41B.

[0101] Each of the TG 41A and the TG 41B is disposed adjacent to one of the four sides of the PD 51. Figure 5 In the illustrated example, the TG 41A and the TG 41B are arranged side by side in the X-axis direction on the top side of the PD 51 .

[0102] An FD 42A-1 is provided on the upper side of the TG 41A. The FD 42A-1 configures a portion of the FD 42A included in the tap 52A.

[0103] The FD 42A included in the tap 52A is composed of an FD 42A-1 and an FD 42A-2. The FD 42A-1 and the FD 42A-2 are formed in different regions. The FD 42A-1 is formed on the upper side of the TG 41A in the figure, and the FD 42A-2 is formed at a position separated from the FD 42A-1 and formed at a position diagonally above and to the right of the FD 42A-1. As will be described later, the FD 42A-1 and the FD 42A-2 are connected to the wiring in the wiring layer and are configured so as to be treated as a single region.

[0104] FDG 48A is formed on the upper side of FD 42A-2 in the figure. In addition, additional capacitance unit 49A is formed on the upper side of FDG 48A in the figure. Once FDG 48A is turned on, a state in which three regions (i.e., FD 42A-1, FD 42A-2, and additional capacitance unit 49A) are connected is achieved.

[0105] The amplifying transistor 45A included in the tap 52A (the gate portion thereof) is formed on the left side of the TG 41A in the drawing. Furthermore, the selecting transistor 43A (the gate portion thereof) is formed above the TG 41A in the drawing. Furthermore, the tap 52A is also provided with an FBEN 46A, which is formed above the reset transistor 44A in the drawing.

[0106] In this manner, the FDs 42A are dispersed across two regions, namely, FD 42A-1 and FD 42A-2. The RST 44A is connected to the FD 42A-1, and the FBEN 46A is connected to the RST 44A. The FDG 48A is connected to the FD 42A-2. By arranging the FDs 42A in two separate regions (i.e., FD 42A-1 and FD 42A-2), the FBEN 46A can be connected to one of the two regions via the RST 44A, and the FDG 48A can be connected to the other of the two regions.

[0107] Each portion forming the tap 52B is provided on the right side of the tap 52A in the figure. The tap 52B also has a similar configuration to that of the tap 52A.

[0108] The TG 41B included in the tap 52B is formed on the right side of the PD 51 in the figure. The FD 42B-1 is arranged above the TG 41B in the figure. The FD 42B included in the tap 52B is composed of the FD 42B-1 and the FD 42B-2. The FD 42B-1 is formed above the TG 41B in the figure, and the FD 42B-2 is formed at a position separated from the FD 42B-1 and formed at a position above and to the left of the FD 42B-1. As will be described later, the FD 42B-1 and the FD 42B-2 are connected to the wiring in the wiring layer and are configured so as to be considered as one area.

[0109] FDG 48B is formed on the upper side of FD 42B-2 in the figure. Moreover, additional capacitance unit 49B is formed on the upper side of FDG 48B in the figure. Once FDG 48B is turned on, a state in which three regions (i.e., FD 42B-1, FD 42B-2, and additional capacitance unit 49B) are connected is achieved.

[0110] The amplifying transistor 45B included in the tap 52B (the gate portion thereof) is formed on the right side of the TG 41B in the drawing. The selecting transistor 43B (the gate portion thereof) is formed on the upper side of the TG 41B in the drawing. In addition, the tap 52B is further provided with the FBEN 46B, and the FBEN 46B is formed on the upper side of the reset transistor 44B in the drawing.

[0111] The well contact 54 is provided on the upper side of the PD 51. The (gate portion) of the discharge transistor (OFG) 47 is provided on the lower side of the PD 51. The discharge transistor 47 is an overflow gate for preventing overflow and is configured to be shared by the tap 52A and the tap 52B, and thus Figure 5 As shown, one OFD 47 is formed in the pixel 31 .

[0112] Figure 5The arrangements shown below are examples and are not intended to be limiting. Figure 5 In the examples shown below, a configuration in which the discharge transistor 47 is provided is described, but a configuration in which the discharge transistor 47 is not provided may also be adopted.

[0113] exist Figure 5 In the example shown in FIG. 5 , each portion constituting the tap 52A and each portion constituting the tap 52B are arranged linearly symmetrically with respect to the center line L1 of the pixel 31 (the line L1 shown by a dotted line in the figure).

[0114] In other words, TG 41A, FD 42A-1, FD 42A-2, reset transistor 44A, FBEN 46A, amplifying transistor 45A, selecting transistor 43A, FDG 48A and additional capacitance unit 49A constituting tap 52A and TG 41B, FD 42B-1, FD 42B-2, reset transistor 44B, FBEN 46B, amplifying transistor 45B, selecting transistor 43B, FDG 48B and additional capacitance unit 49B constituting tap 52B are arranged linearly symmetrically.

[0115] Although Figure 5 Although wiring is not shown, the FD 42A-1 and the amplifier transistor 45A are connected and configured so that the signal amount from the FD 42A-1 is supplied to the amplifier transistor 45A. In addition, the FD 42B-1 and the amplifier transistor 45B are also connected and configured so that the signal amount from the FD 42B-1 is supplied to the amplifier transistor 45B.

[0116] By adopting the linear symmetric arrangement as described above, the length of the wiring between FD 42A-1 and the amplifier transistor 45A and the length of the wiring between FD 42B-1 and the amplifier transistor 45B can be set to be substantially the same. In addition, by using left and right object wirings, another wiring of the same length can be obtained.

[0117] <Example of Cross-Sectional Structure of Pixel>

[0118] Figure 6 It is shown that the Figure 4 and Figure 5 1 is a diagram showing an example of a cross-sectional configuration of each pixel 31 of two taps 52 shown in FIG.

[0119] The pixel 31 includes a semiconductor substrate 141 and a multilayer wiring layer 142 formed on the front surface side (lower side in the drawing).

[0120] The semiconductor substrate 141 is formed of, for example, silicon (Si) and has a thickness of, for example, approximately several μm. For example, in the semiconductor substrate 141, an N-type (second conductivity type) semiconductor region 152 is formed on a pixel-by-pixel basis within the P-type (first conductivity type) semiconductor region 151, and thus a photodiode 51 is formed on a pixel-by-pixel basis. The P-type semiconductor regions 151 provided on the front and rear surfaces of the semiconductor substrate 141 also function as hole charge accumulation regions for suppressing dark current.

[0121] exist Figure 6 The upper surface of the semiconductor substrate 141 on the upper middle side is the rear surface of the semiconductor substrate 141 and is a light incident surface on which light is incident. On the rear surface side, an anti-reflection film 143 is formed on the upper surface of the semiconductor substrate 141.

[0122] The anti-reflection film 143 has a laminated structure in which a fixed charge film and an oxide film are laminated, and for example, an insulating film having a high dielectric constant (high-k) obtained by an atomic layer deposition (ALD) method can be used. Specifically, hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium oxide (STO), etc. can be used. Figure 6 In the example of , the anti-reflection film 143 is structured such that a hafnium oxide film 153 , an aluminum oxide film 154 , and a silicon oxide film 155 are laminated.

[0123] An inter-pixel light-shielding film 145 that prevents incident light from being incident on adjacent pixels is formed on the upper surface of the anti-reflection film 143 at a boundary portion 144 (hereinafter, also referred to as a pixel boundary portion 144) between adjacent pixels 31 on the semiconductor substrate 141. The material of the inter-pixel light-shielding film 145 only needs to be a material that blocks light, and for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu) can be used.

[0124] The planarization film 146 is formed on the upper surfaces of the antireflection film 143 and the inter-pixel light shielding film 145 by an insulating film of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or an organic material such as resin.

[0125] Then, on-chip lenses 147 are formed on the upper surface of the planarization film 146 in units of pixels. The on-chip lenses 147 are formed of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin. Light collected by the on-chip lenses 147 is effectively incident on the PD 51.

[0126] Furthermore, an inter-pixel separator 161 that separates adjacent pixels is formed at the pixel boundary 144 on the rear surface side of the semiconductor substrate 141 to a predetermined depth in the substrate depth direction from the rear surface side (on-chip lens 147 side) of the semiconductor substrate 141. The outer periphery of the inter-pixel separator 161, including the bottom and side walls, is covered with a hafnium oxide film 153 that is part of the anti-reflection film 143. The inter-pixel separator 161 prevents incident light from penetrating the next pixel 31, thereby confining the incident light to its own pixel, and prevents leakage of incident light from adjacent pixels 31.

[0127] exist Figure 6 In the example of FIG, the silicon oxide film 155 and the pixel separator 161 are formed simultaneously by embedding the silicon oxide film 155 in a groove (recess) dug out from the rear surface side. This is the material of the uppermost layer of the anti-reflection film 143. Therefore, the silicon oxide film 155, which is part of the laminated film of the anti-reflection film 143, and the pixel separator 161 are formed of the same material, but their materials do not necessarily need to be the same. The material embedded in the groove (recess) dug out from the rear surface side as the pixel separator 161 can be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN).

[0128] On the other hand, for one PD 51 formed in each pixel 31, two transfer transistors TRG1 and TRG2 are formed on the front surface side of the semiconductor substrate 141 forming the multilayer wiring layer 142. For example, the transfer transistor TRG1 corresponds to the TG 41A ( Figure 5 ), and the transfer transistor TRG2 corresponds to TG 41B ( Figure 5 ).

[0129] Furthermore, the floating diffusion regions FD1 and FD2 serving as charge accumulation units that temporarily hold the charges transferred from the PD 51 are formed of a high-concentration N-type semiconductor region (N-type diffusion region) on the front surface side of the semiconductor substrate 141. For example, the floating diffusion region FD1 corresponds to (FD 42A-1 or FD 42A-2 ( Figure 5 ) constitutes the FD 42A, and the floating diffusion region FD2 corresponds to the FD 42B-1 or the FD 42B-2 ( Figure 5 ) constitutes) FD 42B.

[0130] The multilayer wiring layer 142 is composed of a plurality of wiring layers M and an interlayer insulating film 162 therebetween. Figure 6 An example is shown in which the multilayer wiring layer 142 is composed of four layers (ie, wiring layers M1 to M4 ).

[0131] Wirings 171-174 are formed in each of the plurality of wiring layers M in multilayer wiring layer 142. Wirings 171-174 are formed from a metal film such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or titanium nitride (TiN). Here, wiring provided in wiring layer M1 is referred to as wiring 171, wiring provided in wiring layer M2 is referred to as wiring 172, wiring provided in wiring layer M3 is referred to as wiring 173, and wiring provided in wiring layer M4 is referred to as wiring 174.

[0132] The wirings 171 to 174 provided in the wiring layers M1 to M4 are connected at necessary positions using vias 166 provided in the vertical direction.

[0133] As described above, the pixel 31 has a back-illuminated structure in which the semiconductor substrate 141 as a semiconductor layer is provided between the on-chip lens 147 and the multilayer wiring layer 142, and incident light is incident on the PD 51 from the rear surface side on which the on-chip lens 147 is formed.

[0134] Furthermore, the pixel 31 includes two transfer transistors TRG1 and TRG2 for the PD 51 provided in each pixel and is configured to be able to distribute charges (electrons) generated by the PD 51 through photoelectric conversion to the floating diffusion region FD1 or FD2 .

[0135] <About the method used to calculate depth values>

[0136] A method for calculating a depth value from a signal obtained by a pixel including the above two taps will be described. As schemes for calculating a depth value, there are a two-phase scheme using detection signals of two types of phases and a four-phase scheme using detection signals of four types of phases.

[0137] A two-phase scheme and a four-phase scheme will be described.

[0138] In the four-phase scheme, if Figure 7 As shown, the light receiving unit 15 receives the reflected light at the light receiving timing obtained by shifting the phase by 0°, 90°, 180°, and 270° with reference to the irradiation timing of the irradiation light. More specifically, the light receiving unit 15 receives the reflected light by changing the phase in a time-division manner, and for example, the light receiving unit 15 receives the reflected light when the phase is set to 0° with respect to the irradiation timing of the irradiation light in a certain frame period, receives the reflected light when the phase is set to 90° in the next frame period, receives the light when the phase is set to 180° in the next frame period, and receives the light when the phase is set to 270° in the next frame period.

[0139] Note that, unless otherwise specified, a phase of 0°, 90°, 180°, or 270° represents the phase in the tap 52A of the pixel 31. Since the tap 52B has a phase inverted from the one tap 52A, when the tap 52A has a phase at 0°, 90°, 180°, or 270°, the tap 52B has a phase of 180°, 270°, 0°, or 90°.

[0140] Figure 8 : is a diagram showing the exposure period of the tap 52A of the pixel 31 in the aligned phase of 0°, 90°, 180°, or 270°, in order to facilitate understanding of the phase difference.

[0141] like Figure 8 As shown, in tap 52A, the detection signal A obtained by receiving light at the same phase as the phase of the irradiated light (phase of 0°) will be referred to as detection signal A0, the detection signal A obtained by receiving light at a phase obtained by being shifted by 90 degrees from the phase of the irradiated light (phase of 90°) will be referred to as detection signal A90, the detection signal A obtained by receiving light at a phase obtained by being shifted by 180 degrees from the phase of the irradiated light (phase of 180°) will be referred to as detection signal A180, and the detection signal A obtained by receiving light at a phase obtained by being shifted by 270 degrees from the phase of the irradiated light (phase of 270°) will be referred to as detection signal A270.

[0142] Although not shown, in tap 52B, the detection signal B obtained by receiving light at the same phase as the phase of the irradiation light (phase of 0°) will be referred to as detection signal B0, the detection signal B obtained by receiving light at a phase shifted by 90 degrees from the phase of the irradiation light (phase of 90°) will be referred to as detection signal B90, the detection signal B obtained by receiving light at a phase shifted by 180 degrees from the phase of the irradiation light (phase of 180°) will be referred to as detection signal B180, and the detection signal B obtained by receiving light at a phase shifted by 270 degrees from the phase of the irradiation light (phase of 270°) will be referred to as detection signal B270.

[0143] Figure 9 is a diagram for explaining a method for calculating depth values ​​and reliability in a two-phase scheme and a four-phase scheme.

[0144] In the indirect ToF method, the depth value d can be obtained by the following expression (1).

[0145] [Expression 1]

[0146]

[0147]

[0148] In Expression (1), c is the speed of light, ΔT is the delay time, and f represents the modulation frequency of light. In addition, φ in Expression (1) represents the phase shift amount [rad] of the reflected light and is represented by the following Expression (2).

[0149] [Expression 2]

[0150]

[0151] In the four-phase scheme, I and Q in Expression (2) are calculated by the following Expression (3) using detection signals A0 to A270 and detection signals B0 to B270 obtained by setting the phases to 0°, 90°, 180°, and 270°. I and Q are signals obtained by assuming that the brightness change of the irradiated light is a sine wave and converting the phase of the sine wave from the polar coordinate system to the orthogonal coordinate system (IQ plane).

[0152] I=c0-c180=(A0-B0)-(A180-B180)

[0153] Q=c90-c270=(A90-B90)-(A270-B270)... (3)

[0154] In a four-phase scheme, for example, the variation in properties between taps, that is, the difference in sensitivity between taps in each pixel, can be removed by obtaining the difference in detection signals of opposite phases in the same pixel at "A0-A180" and "A90-A270" in expression (3).

[0155] On the other hand, in the two-phase scheme, I and Q in Expression (2) can be calculated using detection signals in two phases (i.e., the phase at 0° and the phase at 90°). In other words, I and Q in Expression (2) in the two-phase scheme are expressed by the following Expression (4).

[0156] I=c0-c180=(A0-B0)

[0157] Q=c90-c270=(A90-B90)... (4)

[0158] In the two-phase scheme, although it is impossible to remove the variation in properties between the taps present in each pixel, it is possible to obtain the depth value d to the object using only the detection signals in the two phases, thereby performing distance measurement at a frame rate twice that of the four-phase scheme. For example, the variation in properties between the taps can be adjusted by a correction parameter (e.g., gain or offset).

[0159] In the two-phase scheme and the four-phase scheme, the reliability cnf can be obtained by the following expression (5).

[0160]

[0161] As can be recognized from Expression (5), the reliability cnf corresponds to how large the reflected light has been received by the pixel 31, that is, luminance information (luminance value).

[0162] It should be noted that the output of pixel data (detection signal) by each pixel 31 in the pixel array unit 32 in units of one phase of 0°, 90°, 180°, 270°, etc. will be referred to as one frame (cycle) hereinafter. In the four-phase scheme, one depth map is generated in four frames consisting of four phases, while in the case of the two-phase scheme, one depth map is generated in two frames consisting of two phases.

[0163] <Problems with simultaneous full-pixel driving>

[0164] If the above-described basic pixel driving is performed at the same timing for all pixels 31 in the pixel array unit 32 , the following problem may occur.

[0165] (1) Occurrence of IR drop

[0166] The drive control circuit 33 controls the distribution of the charge generated by the photodiode 51 to the tap 52A or the tap 52B based on the distribution signals DIMIX_A and DIMIX_B. If all pixels 31 in the pixel array unit 32 are driven at the same timing when the number of pixels in the pixel array unit 32 is large, the drive current is concentrated, the strong charging and discharging current may cause an IR drop, and the distribution signals DIMIX_A and DIMIX_B become distorted signals, and it may happen that the charge distribution cannot be accurately controlled. For example, in the case of a VGA with a number of pixels (resolution) greater than 640×480, and if all pixels in the pixel array unit 32 are driven simultaneously, the IR drop has a large impact.

[0167] (2) EMC / EMI degradation

[0168] If all the pixels 31 in the pixel array unit 32 are driven at the same timing, the peak current increases, the electromagnetic waves generated from the distance measuring sensor 13 also increase, and electromagnetic compatibility (EMC) and electromagnetic interference (EMI) deteriorate.

[0169] Therefore, it is desirable to perform such driving that driving of all pixels in the pixel array unit 32 is dispersed to disperse the peak current.

[0170] (3) Occurrence of cyclic error

[0171] As described above, although the depth value d is calculated based on the assumption that the brightness variation of the illumination light is a sine wave, the light actually emitted from the light emitting unit 12 is as follows. Figure 3 The rectangular wave shown in FIG. 1 is a sine wave, and a periodic error (hereinafter, referred to as a cyclic error) occurs in the depth value d by processing the rectangular wave into a sine wave.

[0172] The light receiving unit 15 according to the present disclosure achieves driving that disperses driving of all pixels in the pixel array unit 32, disperses peak current, and thereby reduces cycle error. Hereinafter, driving of the light receiving unit 15 will be described in detail.

[0173] <Detailed Configuration Example of Light Receiving Unit>

[0174] <Example of Phase Control Division Number of Two>

[0175] Figure 10 2 is a block diagram showing a more detailed configuration example of the light receiving unit 15 .

[0176] The light receiving unit 15 includes a pixel array unit 32 in which pixels 31 are two-dimensionally arranged and a pixel array unit 32 in which pixels 31 are two-dimensionally arranged. Figure 2 The drive control circuit 33 described in FIG. Figure 10 in Figure 2 The tap 52A and the tap 52B of the pixel 31 shown in FIG are shown in a simplified manner as “A” and “B”.

[0177] In the pixel array unit 32, N (N>1) pixel arrays are defined as one block BL, and all pixels 31 arranged two-dimensionally are divided into a plurality of blocks BL. Figure 10 The example in FIG. 1 shows an example in which N=3 and three pixel arrays are defined as one block BL.

[0178] Each block BL in the pixel array unit 32 is further classified as any unit (phase control unit block) for controlling two types of phases. If each of the two types of phase control unit blocks is defined as a block BL_X or a block BL_Y, then Figure 10 As shown, blocks BL_X and blocks BL_Y are alternately arranged in the horizontal direction (row direction).

[0179] The light receiving unit 15 includes a pulse generating circuit 71 and a controller (control circuit) 72 in addition to the pixel array unit 32 and the drive control circuit 33 .

[0180] The drive control circuit 33 includes two phase shift circuits 81 and two or more block drive units 82. Note that both or one of the pulse generation circuit 71 and the controller 72 may be configured as part of the drive control circuit 33.

[0181] exist Figure 10, among the two phase shift circuits 81, the phase shift circuit 81 corresponding to the block BL_X is represented as a phase shift circuit 81X, and the phase shift circuit 81 corresponding to the block BL_Y is represented as a phase shift circuit 81Y. Similarly, among the two or more block driving units 82, the block driving unit 82 corresponding to the block BL_X is represented as a block driving unit 82X, and the block driving unit 82 corresponding to the block BL_Y is represented as a block driving unit 82Y.

[0182] The pulse generation circuit 71 generates a drive pulse signal based on a light emission control signal of a predetermined frequency (for example, 200 MHz) supplied from the light emission control unit 14 , and supplies the drive pulse signal to the phase shift circuits 81X and 81Y.

[0183] More specifically, the pulse generation circuit 71 generates a drive pulse signal that is frequency-synchronized with the light emission control signal from the light emission control unit 14. In addition, the pulse generation circuit 71 performs reference to the drive pulse signal after frequency synchronization. Figure 10 The driving pulse signal output from the pulse generating circuit 71 corresponds to the phase shift of the irradiation timing of the irradiation light described in Figure 7 etc. The distribution signals DIMIX_A and DIMIX_B are described in

[14] .

[0184] The controller 72 controls the phase change timing of the phase shift circuits 81X and 81Y. In other words, the controller 72 provides instructions on the timing of changing the phase to the phase shift circuits 81X and 81Y.

[0185] The phase shift circuits 81X and 81Y perform phase shift processing on the drive pulse signal supplied from the pulse generating circuit 71 as needed, and supply the drive pulse signal after the phase shift (phase-shifted drive pulse signal) to the block driving unit 82. The phase shift circuits 81X and 81Y approximate the irradiation light emitted as a rectangular wave to a sine wave (create a pseudo-sine wave) by generating the drive pulse signal shifted to a plurality of phases in a time-division manner within one frame period.

[0186] Specifically, the phase shift circuits 81X and 81Y perform a process of shifting the phase of the drive pulse signal supplied from the pulse generating circuit 71 by 0°, 45°, or 90° in a predetermined order within one frame period, and supply the drive pulse signal after the shift to the block driving unit 82. Note that, in the case of a shift of 0°, the drive pulse signal supplied from the pulse generating circuit 71 can be supplied to the block driving unit 82 as it is.

[0187] The phase shift circuits 81X, 81Y are respectively given instructions on the timing of shifting the phase from the controller 72. The phase shift circuits 81X and 81Y change the phase to be shifted at the timing indicated by the instruction from the controller 72.

[0188] The block driving unit 82X performs control of supplying the driving pulse signal supplied from the phase shift circuit 81X (ie, the distributed signals DIMIX_A and DIMIX_B after phase shift) to each pixel 31 in the corresponding block BL_X and distributing the charge generated by the photodiode 51 to the tap 52A or the tap 52B.

[0189] The block driving unit 82Y performs the following control: the driving pulse signal provided from the phase shift circuit 81Y (i.e., the distribution signals DIMIX_A and DIMIX_B after phase shift) is provided to each pixel 31 in the corresponding block BL_Y, and the charge generated by the photodiode 51 is distributed to the tap 52A or the tap 52B.

[0190] Figure 11 81X and 81Y are diagrams for explaining the phase shift processing performed by each of the phase shift circuits 81X and 81Y.

[0191] Figure 11 The vertical direction of the blocks BL_X and BL_Y in represents the time axis in one frame period.

[0192] The phase shift circuit 81X starts at a phase of 0°, follows the timing indicated by the controller 72, and shifts and outputs the phase in the order of 45° and 90° every time a predetermined time has passed. After the phase of 90°, the process returns to the phase of 0°, and the phase shift process is repeated in the order of 0°, 45°, and 90° until the end of exposure.

[0193] On the other hand, the phase shift circuit 81Y starts at a phase of 90°, follows the timing indicated by the instruction from the controller 72, and shifts and outputs the phase in the order of 0° and 45° every time a predetermined time has passed. After the phase of 45°, the process returns to the phase of 90°, and the phase shift process is repeated in the order of 90°, 0°, and 45° until the end of exposure.

[0194] Figure 12 The charge accumulation time (integration time) in each phase of 0°, 45°, and 90° is shown.

[0195] like Figure 12 As shown in FIG. 1A , the controller 72 provides an instruction for changing the phase to the phase shift circuit 81 at the following timing: the ratio of the period during which the phase shift circuit 81 generates the drive pulse signal with a phase shift of 0°, the period during which the phase shift circuit 81 generates the drive pulse signal with a phase shift of 45°, and the period during which the phase shift circuit 81 generates the drive pulse signal with a phase shift of 90° becomes In this way, the ratio of the charge accumulation time in the phases of 0°, 45°, and 90° becomes

[0196] The ratio of the charge accumulation time in the phases of 0°, 45°, and 90° can be set to To approximate the waveform of the modulated wave to a sine wave, such as Figure 12 As shown in B. The amplification of the sine wave can be adjusted by adjusting the ratio of the charge accumulation time.

[0197] In order to approximate the light having a rectangular waveform output from the light emitting unit 12 to a sine wave, a phase shift of the light emission timing of the light source may be performed to create a pseudo sine wave as disclosed in PTL 1, or also by Figure 12 In this method, a phase shift of light reception timing is performed on the light reception side to generate a pseudo sine wave.

[0198] Figure 13 Phase shift control of each of the blocks BL_X and BL_Y is shown.

[0199] The driving control circuit 33 classifies all pixels in the pixel array unit 32 into two phase control unit blocks, ie, block BL_X and block BL_Y, and makes the block BL_X and the block BL_Y accumulate charges in different phases, as shown in FIG. Figure 13 In this way, the current for driving the pixel 31 is dispersed in the entire pixel array unit 32, and thus the reduction in IR drop can be suppressed and the deterioration of EMC and EMI can also be suppressed.

[0200] Furthermore, the phase shift circuit 81 can control the ratio of the charge accumulation time of the phases of 0°, 45°, and 90° to 0° by the timing control performed based on the controller 72. Approximate the modulated wave of the received light to a sine wave and reduce the cyclic error.

[0201] Since the integration results of the pixels arranged in block BL_X and block BL_Y are the same, the pixel data (detection signals A and B) output from the pixels do not require any special correction processing such as correction processing to eliminate offset in the plane (area) of the pixel array unit 32.

[0202] Therefore, according to the distance measuring sensor 13, it is possible to realize driving that reduces both the cycle error and the dispersion of the driving current. In addition, it is possible to acquire pixel data (detection signals A and B) similar to the case where no phase shift is performed.

[0203] <Detection based on IQ Mosaic>

[0204] As described above, the phase shift for generating a pseudo sine wave and the dispersion of drive timing in units of blocks performed by the plurality of phase shift circuits 81 and the plurality of block drive units 82 produce effects of dispersing the drive current and reducing the cycle error.

[0205] However, as described above, in order for the ranging sensor 13 to output one depth map, four frames are required in the four-phase scheme and two frames are required in the two-phase scheme. If the number of pixels in the ranging sensor 13 increases, there is a concern that the frame rate may deteriorate.

[0206] Will refer to Figure 14 Describes a driver that outputs a depth map in one frame by modifying a two-phase scheme.

[0207] In the two-phase scheme, Figure 14 In the first frame shown on the left side of , the tap 52A of each pixel 31 acquires a detection signal at a phase of 0°, and the tap 52B acquires a detection signal at a phase of 180°. Next, in the second frame, the tap 52A of each pixel 31 acquires a detection signal at a phase of 90°, and the tap 52B acquires a detection signal at a phase of 270°. Then, the four detection signals in the first and second frames are used to calculate I and Q in Expression (4) and the depth value d in Expression (1).

[0208] If it is assumed that the pixel data of each pixel 31 obtained in the first frame is called I pixel data of the same phase component as the modulated wave of light, and the pixel data of each pixel 31 obtained in the second frame is called Q pixel data of the orthogonal phase component relative to the modulated wave of light, in the two-phase scheme, I pixel data is acquired by all pixels in the first frame, and Q pixel data is acquired by all pixels in the second frame.

[0209] On the other hand, Figure 14 As shown on the right side of , by having the pixel 31 that acquires I pixel data (hereinafter referred to as I pixel) and the pixel 31 that acquires Q pixel data (hereinafter referred to as Q pixel) exist together, it is possible to acquire detection signals for all phases of 0°, 90°, 180°, and 270° for the modulated wave of light in one frame, thereby calculating I and Q in expression (4) and obtaining the depth value d. In this way, driving in which the I pixel and the Q pixel exist together in one frame will be referred to as IQ mosaic driving.

[0210] exist Figure 14 In the IQ mosaic drive shown in FIG, driving is performed so that I pixel, I pixel, Q pixel, and Q pixel are arranged in this order in the horizontal direction (row direction) in the drawing. Although the following description continues by exemplifying the case where driving is performed so that I pixel, I pixel, Q pixel, and Q pixel are arranged in this order, the present technology can also be applied to the case where driving is performed with other arrangements (for example, in the order of I pixel, Q pixel, I pixel, and Q pixel).

[0211] It should be noted that in Figure 14In the IQ mosaic driving in , similar to the above-mentioned two-phase scheme, it is impossible to remove the characteristic variation between the taps present in each pixel.

[0212] In the case where priority is given to removing the characteristic variation between the taps existing in each pixel, the drive control circuit 33 performs the same operation as in the first frame. Figure 14 The IQ mosaic driving in one frame is similar to the driving in FIG, and the IQ mosaic driving is performed with the phases of the taps 52A and 52B of each pixel 31 inverted from the phases of the first frame in the second frame, as shown in FIG. Figure 15 In this case, by obtaining the difference in detection signals of opposite phases within the same pixel using the pixel data in the first frame and the second frame, it is possible to remove attribute changes between taps present in each pixel similarly to the above-mentioned four-phase scheme, and obtain the depth value d with fewer frames (two frames) than in the four-phase scheme.

[0213] As a measure for reducing the frame rate as the number of pixels in the pixel array unit 32 increases, the above-described IQ mosaic drive may be employed.

[0214] By combining IQ mosaic drive, phase shifting for generating a pseudo sine wave performed by a plurality of phase shift circuits 81 and a plurality of block drive units 82, and drive timing dispersion in units of blocks BL, the effect of shortening the frame rate and the effect of dispersing the drive current and reducing the cyclic error can be simultaneously obtained.

[0215] <Example of IQ Mosaic Driving with Four Phase Control Divisions>

[0216] Next, IQ mosaic driving will be described, in which all pixels in the pixel array unit 32 are classified into four types of phase control unit blocks, and I pixels and Q pixels are arranged in units of pixel arrays, as shown in FIG. Figure 14 shown.

[0217] Figure 16 is a diagram showing a schematic configuration example of the pixel array unit 32 and the drive control circuit 33 in a case where the pixel array unit 32 is classified into four types of phase control unit blocks and IQ mosaic driving is performed.

[0218] Each block BL divided in units of N columns in the pixel array unit 32 is classified into four types, namely, blocks BL_XI, BL_YI, BL_XQ, and BL_YQ. Blocks BL_XI and BL_YI are blocks BL including pixels 31 driven as I pixels, and blocks BL_XQ and BL_YQ are blocks BL including pixels 31 driven as Q pixels.

[0219] The drive control circuit 33 includes four phase shift circuits 81 and four or more block drive units 82 .

[0220] In the four phase shift circuits 81, the phase shift circuits 81 corresponding to the blocks BL_XI, BL_YI, BL_XQ, and BL_YQ will be represented as phase shift circuits 81XI, 81YI, 81XQ, and 81YQ, respectively. Similarly, in the four or more block drive units 82, the block drive units 82 corresponding to the blocks BL_XI, BL_YI, BL_XQ, and BL_YQ will be represented as block drive units 82XI, 82YI, 82XQ, and 82YQ, respectively.

[0221] Figure 17 Phase shift control of each of the blocks BL_XI, BL_YI, BL_XQ and BL_YQ is shown.

[0222] Similar to the aforementioned example, the ratio of the charge accumulation time in the phases of 0°, 45°, and 90° in each pixel 31 is When the phase of the I pixel is 0°, 45°, or 90°, the phase of the Q pixel is 90°, 135°, or 180°, respectively, and the phase of the I pixel and the phase of the Q pixel are in an orthogonal relationship.

[0223] As from Figure 17 It can be appreciated that if it is assumed that the types of phase shifts for generating a pseudo sine wave are three types, i.e., 0°, 45°, and 90° (90°, 135°, and 180° for Q pixels), and the ratio of the charge accumulation time in the phases of 0°, 45°, and 90° is Then, the same phase is obtained in the two blocks BL in the partial period shown by the dotted line. In other words, although the phase of each block BL is different except for the partial period shown by the dotted line, it is impossible to completely disperse the phase so that the phase of each block BL is different throughout one frame period.

[0224] Therefore, the drive control circuit 33 can execute Figure 18 The phase shift control shown in FIG is used to fully distinguish the phase of each phase control unit block throughout one frame period.

[0225] Figure 18 is a diagram showing an example of phase shift control based on IQ mosaic driving, in which the pixel array unit 32 is classified into four types of phase control unit blocks and the phases of the phase control unit blocks are completely distinguished.

[0226] The drive control circuit 33 performs phase shift control by setting the type of phase shift used to generate a pseudo sine wave to five types, i.e., 0°, 22.5°, 45°, 67.5° and 90° every 22.5° (90°, 112.5°, 135°, 157.5° and 180° for Q pixels), and setting the ratio of the charge accumulation time in the phases of 0°, 22.5°, 45°, 67.5° and 90° to 1:2.6092:3.4071:2.6061:0.9964.

[0227] By performing such control, it is possible to achieve a state where the phase of each phase control unit block is different throughout all cycles. For example, the blocks BL_XI, BL_YI, BL_XQ, and BL_YQ are controlled to have phases of 0°, 45°, 90°, and 135° during the period 101 indicated by the dotted line, and are controlled to have phases of 45°, 90°, 135°, and 180° during the period 102 indicated by the dotted line.

[0228] Figure 19 The figure shows the comparison between the cycle error of the exposure control based on rectangular pulse and the Figure 18 Graph showing the results between the cyclic errors of the pseudo-sine wave based exposure control.

[0229] Figure 19 A is a graph showing a cycle error (CE) in exposure control of a rectangular pulse having a duty ratio of 50%, in which the ratio of the high time is 50%.

[0230] Figure 19 B is a graph showing a cycle error (CE) in exposure control of a rectangular pulse having a duty ratio of 33%, in which the ratio of the high time is 33%.

[0231] Figure 19 C is shown in Figure 18 Graph of the cyclic error (CE) in the pseudo-sine wave exposure control shown in FIG.

[0232] exist Figure 19 In all of A, B, and C in , the left graph represents the integrated waveform at the integration time of one frame period, and the right graph represents the cyclic error (vertical axis) in FFT for each frequency (horizontal axis).

[0233] In the exposure control based on the pseudo-sine wave, the cyclic error is substantially zero at frequencies other than 200 MHz, which is the modulation frequency of the light source. Figure 19 In the graph showing the results of FFT, the value obtained by multiplying the integer value on the horizontal axis by 100 corresponds to the frequency. Figure 19In the exposure control of the rectangular pulses in A and B, a cyclic error occurs at a frequency other than 200 MHz, which is the light source modulation frequency. Specifically, the cyclic error increases at a frequency that is an integer multiple of 200 MHz.

[0234] As mentioned above, according to Figure 18 The pseudo-sine wave based exposure control shown in can completely disperse the drive timing and essentially completely eliminate the cycle error.

[0235] <About Wiring>

[0236] like Figure 14 As shown, wiring in the case of performing IQ mosaic driving to obtain an arrangement of I pixel, I pixel, Q pixel, and Q pixel will be described.

[0237] Figure 20 52A and 52B are diagrams for explaining wiring related to the connection between the tap 52A and the tap 52B. More specifically, Figure 20 A diagram for explaining wiring related to the connection between the transfer transistor 41A included in the tap 52A and a signal line that supplies the distribution signal DIMIX_A to the transfer transistor 41A, and wiring related to the connection between the transfer transistor 41B included in the tap 52B and a signal line that supplies the distribution signal DIMIX_B to the transfer transistor 41B.

[0238] Figure 20 As an example, sixteen pixels 31 arranged in 4×4 in the pixel array unit 32 are shown. Figure 20 The arrangement of the sixteen pixels shown in Figure 14 . In other words, pixels 31-1, 31-5, 31-9, and 31-13 arranged in the first column on the left side of the figure are I pixels. In addition, pixels 31-2, 31-6, 31-10, and 31-14 arranged in the second column on the left side of the figure are I pixels.

[0239] Pixels 31-3, 31-7, 31-11, and 31-15 arranged in the third column on the left side of the figure are Q pixels. Pixels 31-4 and 31-8, 31-12, and 31-16 arranged in the fourth column on the left side of the figure are Q pixels.

[0240] Reference will be made to a row arranged on the upper side of the drawing. Tap 52A-1 of pixel 31-1, which is a 1-pixel, and tap 52A-2 of pixel 31-2, which is a 1-pixel, are connected. Furthermore, taps 52A-1 and 52A-2 are connected to signal line 211-1. Signal line 211-1 is formed in the column direction and is formed on pixels 31-1, 31-5, 31-9, and 31-13 arranged in the first column on the left side of the drawing.

[0241] The tap 52A-1 and the tap 52A-2 are taps for acquiring a detection signal at a phase of 0 degrees, and the signal line 211-1 is a signal line for transmitting a signal for driving the transfer transistor 41A included in each of the tap 52A-1 and the tap 52A-2 at a phase of 0 degrees.

[0242] The tap 52B-1 of the pixel 31-1, which is an I pixel, and the tap 52B-2 of the pixel 31-2, which is an I pixel, are connected. Furthermore, the taps 52B-1 and 52B-2 are connected to the signal line 211-3. The signal line 211-3 is formed in the column direction and is formed on the pixels 31-3, 31-7, 31-11, and 31-15 arranged in the third column from the left side in the figure.

[0243] The tap 52B-1 and the tap 52B-2 are taps for acquiring detection signals at a phase of 180 degrees, and the signal line 211-3 is a signal line for transmitting a signal for driving the transfer transistor 41B included in each of the tap 52B-1 and the tap 52B-2 at a phase of 180 degrees.

[0244] The tap 52A-3 of the pixel 31-3, which is a Q pixel, and the tap 52A-4 of the pixel 31-4, which is a Q pixel, are connected. Furthermore, the taps 52A-3 and 52A-4 are connected to the signal line 211-2. The signal line 211-2 is formed in the column direction and is formed on the pixels 31-2, 31-6, 31-10, and 31-14 arranged in the second column from the left in the figure.

[0245] The tap 52A-3 and the tap 52A-4 are taps for acquiring detection signals at a phase of 90 degrees, and the signal line 211-2 is a signal line for transmitting a signal for driving the transfer transistor 41A included in each of the tap 52A-3 and the tap 52A-4 at a phase of 90 degrees.

[0246] The tap 52B-3 of the pixel 31-3, which is a Q pixel, and the tap 52B-4 of the pixel 31-4, which is a Q pixel, are connected. Furthermore, the taps 52B-3 and 52B-4 are connected to the signal line 211-4. The signal line 211-4 is formed in the column direction and is formed on the pixel 31-4, pixels 31-8, 31-12, and 31-16 arranged in the fourth column from the left in the figure.

[0247] The tap 52B-3 and the tap 52B-4 are taps for acquiring a detection signal at a phase of 270 degrees, and the signal line 211-4 is a signal line for transmitting a signal for driving the transfer transistor 41B included in each of the tap 52B-3 and the tap 52B-4 at a phase of 270 degrees.

[0248] The pixels 31 in the second and subsequent rows are similarly connected to the pixels 31 in the first row. Such connection-related wiring is formed in the wiring layer 142 ( Figure 6 ). Hereinafter, the wiring in the wiring layer 142 will be described.

[0249] <About Wiring>

[0250] In the multilayer wiring layer 142 ( Figure 6 ) to form wiring. Figure 21 The wiring in the wiring layer M1 is added to Figure 5 Schematic diagram of a plan view of the pixel 31 shown in FIG. Figure 22 The wiring in the wiring layer M2 is added to Figure 5 Schematic diagram of a plan view of the pixel 31 shown in FIG.

[0251] Reference Figure 21 A through hole 311A ​​for connecting the TG 251A to a wiring formed in another wiring layer is formed on the lower side of the TG 41A. In addition, a contact point (not shown) connected to the through hole 311A ​​is also formed on the lower side of the TG 41A.

[0252] Note that in the above description and the following description, connection includes physical connection, and also includes a case where components are formed so that charge or a signal can be read even if a physical connection is not established between them.

[0253] Reference Figure 21 , FD 42A-2, FD 42A-1, and AMP 45A are connected to the wiring 331A. Contact 312A, contact 313A, and contact 315A are formed in FD 42A-2, FD 42A-1, and AMP 45A, respectively, and these contacts are connected to the wiring 331A.

[0254] The wiring 331A can also be used as a region for forming the FD 42A. By extending the wiring length of the wiring 331A, the capacity of the FD 42A can be increased. Figure 22 As shown, a wiring 341A constituting a part of the FD 42A is formed in the wiring layer M2. The wiring 341A is connected to the wiring 331A through the via 314A.

[0255] The through hole 314A is formed in Figure 21 and Figure 22 Between the TG 41A and the AMP 45A in the via 314A. The wiring 331A is formed in the wiring layer M1, and the wiring 341A is formed in the wiring layer M2 so that they are connected to the via 314A.

[0256] It should be noted that the wiring 341A is formed to increase the capacity of the FD 42A and is not a wiring for connection, as described above, and therefore the wiring 341A can be omitted. Although the description here will continue by exemplifying the case where the wiring 341A is formed in the wiring layer M2, the wiring 341A can be formed in the wiring layer M3 or the wiring layer M4 in addition to the wiring layer M2.

[0257] Reference Figure 21 , wiring 332A is formed in a region corresponding to the lower side of AMP 45A and SEL 43A. Wiring 332A is connected to contact 317A formed between via 316A formed in SEL 43A and one side of RST 44A and FBEN 46A (a region corresponding to the drain of reset transistor 44A).

[0258] Wiring 332A is connected to Figure 7 The part corresponding to the parasitic capacitor C_ST in the circuit diagram shown in FIG. By increasing the capacity of the parasitic capacitor C_ST, the KTC noise can be further reduced. Therefore, as Figure 21 As shown, the wiring 333A is provided in the wiring layer M1, and as shown in FIG. Figure 22 As shown, the wiring 342A is provided in the wiring layer M2 as a region corresponding to the parasitic capacitance C_ST. The portion corresponding to the parasitic capacitance C_ST is composed of the wiring 332A, the wiring 333A, and the wiring 342A.

[0259] Wiring 332A formed in wiring layer M1 is connected to via 316A. Furthermore, wiring 333A formed in wiring layer M1 is connected to via 318A. Wiring 342A formed in wiring layer M2 is connected to via 316A and via 318A. Thus, wiring 332A, via 316A, wiring 342A, via 318A, and wiring 333A are connected, forming parasitic capacitance C_ST.

[0260] Reference Figure 21 The wiring 333A is formed as a wiring extending from the area on the right side of the FD 42A- 2 in the figure through the well contact 54 and the lower side of the PD 51 to the OFD 47 .

[0261] The wiring associated with the tap 52A is formed to have a linear symmetric relationship with the wiring associated with the tap 52B. Figure 21 and Figure 22 The wiring associated with the tap 52B will be described.

[0262] Reference Figure 21 A through hole 311B for connecting the TG 251B to a wiring formed in another wiring layer is formed on the lower side of the TG 41B. A contact (not shown) connected to the through hole 311B is also formed on the lower side of the TG 41B.

[0263] refer to Figure 21 , FD 42B-1, FD 42B-2, and AMP 45B are connected to the wiring 331B. Contact 312B, contact 313B, and contact 315B are formed in FD 42B-1, FD 42B-2, and AMP 45B, respectively, and these contacts are connected to the wiring 331B.

[0264] like Figure 22 As shown in FIG4 , a wiring 341B constituting a part of the FD 42B is also formed in the wiring layer M2. The wiring 341B is connected to the wiring 331B through a via 314B.

[0265] refer to Figure 21 , wiring 332B is formed in a region corresponding to the lower side of AMP 45B and SEL 43B. Wiring 332B is connected to contact 317B formed between via 316B formed in SEL 43B and one side of RST 44B and FBEN 46B (a region corresponding to the drain of reset transistor 44B).

[0266] Wiring 332B formed in wiring layer M1 is connected to via 316B. Furthermore, wiring 333B formed in wiring layer M1 is connected to via 318B. Wiring 342B formed in wiring layer M2 is connected to via 316B and via 318B. Thus, wiring 332B, via 316B, wiring 342B, via 318B, and wiring 333B are connected, forming parasitic capacitance C_ST.

[0267] Reference Figure 21 The wiring 333B is formed as a wiring extending from the area on the left side of the FD 42B- 2 in the figure through the well contact 54 and the lower side of the PD 51 to the OFD 47 .

[0268] In this manner, the wiring associated with the tap 52B is formed in a linearly symmetrical relationship with the wiring associated with the tap 52A.

[0269] The transistors, wirings, and the like included in the tap 52A in the pixel 31 and the transistors, wirings, and the like included in the tap 52B in the pixel 31 are arranged line-symmetrically with respect to the center line L1 in the pixel 31 .

[0270] Therefore, for example, variations in the length of wiring that contributes to noise cancellation, such as the length of wiring 332, wiring 333, etc. corresponding to parasitic capacitance C_ST, can be suppressed. Therefore, a difference in performance related to noise reduction between tap 52A and tap 52B can be prevented and the ranging rule can be improved.

[0271] Figure 233 is a diagram for explaining wiring in the wiring layer M3. Figure 24 3 is a diagram for explaining wiring in the wiring layer M4. Figure 25 4 is a diagram for explaining signal lines connected to contacts provided in the wiring layer M4 .

[0272] Since the wiring in the wiring layers M3 and M4 is arranged across a plurality of pixels 31, Figures 23 to 25 The pixel 31 is shown with a simplified configuration, and only portions necessary for the description are shown and described.

[0273] Figure 23 and Figure 24 Pixels 31-1 to 31-4 arranged in a row direction are shown. Contact 361A-1 is formed in a region corresponding to the region where TG 45A-1 is formed in pixel 31-1 within wiring layer M3. Contact 361A-1 is connected to via 311A ​​formed in wiring layer M1 and wiring layer M2.

[0274] The via 311A ​​is provided directly below the TG 45, is formed in a straight line (a shape close to a straight line), and is configured to connect to the contact 361A formed in the wiring layer M3. By shortening the wiring connected to the TG 45, an increase in wiring capacity can be prevented (wiring capacity can be reduced).

[0275] Similarly, a contact 361B-1 is formed in a region within the wiring layer M3 corresponding to a region where the TG 45B-1 is formed in the pixel 31-1. The contact 361B-1 is connected to a via 311B formed in the wiring layer M1 and the wiring layer M2.

[0276] Similarly, contact 361A-2 is formed in a region within the wiring layer M3 corresponding to a region where TG 45A-2 is formed in the pixel 31-2, and contact 361B-2 is formed in a region within the wiring layer M3 corresponding to a region where TG 45B-2 is formed, and contacts 361A-2 and 361B-2 are connected to corresponding through-holes 311A ​​and 311B, respectively.

[0277] Similarly, contact 361A-3 is formed in a region within the wiring layer M3 corresponding to a region where TG 45A-3 is formed in the pixel 31-3, and contact 361B-3 is formed in a region within the wiring layer M3 corresponding to a region where TG 45B-3 is formed, and contacts 361A-3 and 361B-3 are connected to corresponding through-holes 311A ​​and 311B, respectively.

[0278] Similarly, contact 361A-4 is formed in a region within wiring layer M3 corresponding to a region where TG 45A-4 is formed in pixel 31-4, and contact 361B-4 is formed in a region within wiring layer M3 corresponding to a region where TG 45B-4 is formed, and contacts 361A-4 and 361B-4 are connected to corresponding through-holes 311A ​​and 311B, respectively.

[0279] The wiring formed in the wiring M3 is used for the above reference Figure 20 The wiring for establishing connections between the taps 52 is described above. Figure 20 As described, the tap 52A-1 of the pixel 31-1 and the tap 52A-2 of the pixel 31-2 are connected. Figure 23 As shown, this connection is achieved by connecting the wiring 371 in the wiring layer M3 to the contact 361A-1 of the TG 45A-1 constituting the tap 52A-1 of the pixel 31-1 and the contact 361A-2 of the TG 45A-2 constituting the tap 52A-2 of the pixel 31-2.

[0280] The wiring 371 is also connected to the via 363-1. The via 363-1 is formed in a region corresponding to the region where the PD 51-1 is formed within the wiring layer M3. Figure 24 The contact 381-1 is connected to the signal line 211-1, as shown in FIG. Figure 25 shown.

[0281] Reference Figure 23 , the contact 361B-1 of the TG 45B-1 constituting the tap 52B-1 of the pixel 31-1 and the contact 361B-2 of the TG 45B-2 constituting the tap 52B-2 of the pixel 31-2 are connected to the wiring 372. The wiring 372 is also connected to a through-hole 363-3 formed in a region corresponding to the region where the PD 51-3 is formed within the wiring layer M3.

[0282] Through hole 363-3 is connected to the Figure 24 The contact 381-3 is connected to the signal line 211-3, as shown in FIG. Figure 25 shown.

[0283] Reference Figure 23 , the contact 361A-3 of the TG 45A-3 constituting the tap 52A-3 of the pixel 31-3 and the contact 361A-4 of the TG 45A-4 constituting the tap 52A-4 of the pixel 31-4 are connected to the wiring 373. The wiring 373 is also connected to a through-hole 363-2 formed in the wiring layer M3 corresponding to the region where the PD 51-2 is formed.

[0284] Through hole 363-2 is connected to the Figure 24The contact 381-2 is connected to the signal line 211-2, as shown in FIG. Figure 25 shown.

[0285] Reference Figure 23 , the contact 361B-3 of the TG 45B-3 constituting the tap 52B-3 of the pixel 31-3 and the contact 361B-4 of the TG 45B-4 constituting the tap 52B-4 of the pixel 31-4 are connected to the wiring 374. The wiring 374 is also connected to a via 363-4 formed in a region corresponding to the region where the PD 51-4 is formed within the wiring layer M3.

[0286] Through hole 363-4 is connected to the Figure 24 The contact 381-4 is connected to the signal line 211-4, as shown in FIG. Figure 25 shown.

[0287] Will refer to Figure 25 The signal line 211-1 shown in FIG is described. The signal line 211-1 is a signal line provided across the pixels 31-1, 31-5, 31-9, and 31-13 arranged in the column direction, and is the same as the signal line provided in the above reference. Figure 20 The case described is similar. In addition, the signal line 211 - 1 is a signal line that transmits a signal for controlling the transfer transistor 41A to obtain a detection result of a phase of 0 degrees.

[0288] The signal line 211-1 is connected to a contact 381-1 provided in a region corresponding to the pixel 31-1, as shown in FIG. Figure 25 As shown. Via 363-1 is connected to contact 381-1, as shown Figure 24 Furthermore, the wiring 371 is connected to the through hole 363-1, as shown in FIG. Figure 23 As shown in .

[0289] The wiring 371 is connected to the contact 361A-1, and the contact 361A-1 is connected to the via 311A ​​( Figure 21 and Figure 22 Finally, the via 311A ​​is connected to the contact (gate of the transfer transistor 41A) formed in the TG 41A. Therefore, the TG 41A is connected to the signal line 211-1, and the driving is controlled by the signal from the signal line 211-1.

[0290] Each signal line 211-2 to 211-4 is also connected to the corresponding TG 41 and is configured to transmit a signal for controlling driving to the corresponding TG 41. The wiring connecting the signal lines 211-1 to 211-4 to the TG 41 is as described above with reference to FIG. Figure 23 Here, we will refer to Figure 23 .

[0291] The wiring 371 connects the contact 361A-1 included in the tap 52A-1 to the contact 361A-2 included in the tap 52A-2. In addition, the wiring 371 is connected to the via 363-1 in the tap 52A-1. The length of the wiring 371 is set to a length L1.

[0292] The wiring 372 connects the contact 361B-1 included in the tap 52B-1 to the contact 361B-2 included in the tap 52B-2. In addition, the wiring 372 is also connected to the through-hole 363-3 included in the pixel 31-3. The length of the wiring 372 is set to a length L2.

[0293] The wiring 373 connects the contact 361A-3 included in the tap 52A-3 to the contact 361A-4 included in the tap 52A-4. In addition, the wiring 373 is also connected to the through-hole 363-2 included in the pixel 31-2. The length of the wiring 373 is set to a length L3.

[0294] The wiring 374 connects the contact 361B-3 included in the tap 52B-3 to the contact 361B-4 included in the tap 52B-4. In addition, the wiring 371 is connected to the via 363-4 in the tap 52A-4. The length of the wiring 374 is set to a length L4.

[0295] Length L1 and length L4 are substantially the same length. Length L1 and length L2 are the lengths of the wiring connecting the taps (TG 45) of adjacent pixels. Furthermore, length L2 and length L3 are substantially the same length. Length L2 and length L3 are the lengths of the wiring connecting the taps (TG 45) of adjacent pixels and the length of the extended wiring extending to the through-hole of the adjacent pixel.

[0296] However, length L1 (length L4) and length L2 (length L3) are different lengths. Due to the different wiring lengths, there is a possibility that parasitic capacitance may vary. To prevent this parasitic capacitance from varying, it is possible to consider setting lengths L1 to L4 to be the same.

[0297] Since the length L1 of the wiring 371 is shorter than the length L3 of the wiring 373, a redundant wiring 375 is added to the wiring 371. When the length L5 obtained by adding the wiring 371 and the redundant wiring 375 is set as the length L5, the length L5 is substantially the same as the length L3 of the wiring 373.

[0298] Note that here, an exemplary case will be described in which the parasitic capacitance is adjusted to be the same by adjusting the length of the wiring to be the same. Furthermore, the description will be given assuming that the parasitic capacitance is the same if the wiring length is the same. However, parasitic capacitance is determined not only by the length of the wiring but also by factors such as the distance from other wirings and the size of the wiring.

[0299] Therefore, in the case of more accurately adjusting the parasitic capacitance, not only by setting the length L5 of both the wiring 371 and the redundant wiring 375 to be the same as the length L3 , but also by setting the length of the redundant wiring 375 in consideration of other elements.

[0300] The length of length L5 is set to achieve a parasitic capacitance substantially the same as that of length L3. That is, redundant wiring 375 is a wiring added to wiring 371 to achieve a parasitic capacitance equivalent to that generated by wiring 373 having a length of L3. For example, the length of redundant wiring 375 is set to a length to achieve a parasitic capacitance equivalent to that generated by wiring 373 having a length of L3.

[0301] Note that although redundant wiring is described here, this includes wiring used to adjust parasitic capacitance and wiring added to the predetermined wiring as described above. Redundant wiring is wiring formed for purposes other than connection to contacts, vias, etc., and is separate from wiring formed for the purpose of connection to contacts, vias, etc.

[0302] Similarly, because the length L4 of wiring 374 is shorter than the length L2 of wiring 373, redundant wiring 376 is added to wiring 374. Redundant wiring 376 is a wiring added to wiring 374 in order to achieve the same parasitic capacitance as that generated by wiring 372 having a length of L2. For example, the length of redundant wiring 376 is set to a length that can achieve the same parasitic capacitance as that generated by wiring 372 having a length of L2.

[0303] Redundant wiring 375 and redundant wiring 376 may be provided in a layer different from the layer in which wirings 371 to 374 are formed. For example, a configuration may be employed in which redundant wiring 375 and redundant wiring 376 are formed in wiring layers M2 and M4 that are different from wiring layer M3 in which wirings 371 to 374 are formed and are connected to vias.

[0304] Furthermore, the redundant wiring 375 and the redundant wiring 376 may be formed to have a thickness different from that of the wirings 371 to 374. Figure 23 The one wiring shown may be formed into a plurality of wirings. Moreover, the redundant wiring 375 and the redundant wiring 376 may be formed into a linear shape, such as Figure 23 As shown, or may be formed in a shape other than a linear shape, for example, a shape having a curve or a loop.

[0305] Note that the above embodiment is a case of connecting a transfer transistor in a tap, and an exemplary case has been described where redundant wiring is provided in a wiring connected to the transfer transistor. This technology can also be applied to wiring connecting transistors other than the transfer transistor in a tap.

[0306] Furthermore, this technology can be applied to imaging elements other than dual-tap structures. For example, this technology can be applied to imaging elements that include one transfer transistor per pixel. In such imaging elements, a structure can be employed that uses redundant wiring to connect predetermined transistors in adjacent pixels.

[0307] In this way, redundant wiring for adjusting parasitic capacitance is provided. Therefore, it is possible to suppress variations in parasitic capacitance. When a pixel to which this technology is applied is applied to a pixel that performs distance measurement, distance measurement can be performed with enhanced accuracy.

[0308] Although examples in which the arrangement, size, and the like of transistors are changed have been described as embodiments, the arrangement and size are merely examples, and the present technology can also be applied to arrangements and sizes other than those described herein.

[0309] As described above, pixels employing this technology are constructed such that the region constituting the FD (floating diffusion region) is arranged in a dispersed manner as two regions, and the two regions are connected so as to be considered as a single FD. By distributing the FD in two dispersed regions, the degree of freedom in arrangement is increased. By distributing the FD in two dispersed regions, the FD can also be formed into a larger area than when the FD is provided as a single region.

[0310] Note that in the above-described embodiments, the FD may be provided by being divided into two areas or two or more areas.

[0311] As described above, pixels employing this technology are constructed to further increase the capacity of the FD by providing a conversion efficiency switching transistor (FDG) that converts the capacity of the FD and an additional capacitance unit. Furthermore, by also providing wiring that forms part of the FD in the laminated wiring layer, a structure capable of further increasing the capacity of the FD is achieved. In this way, pixels employing this technology can achieve a pixel with increased FD capacity.

[0312] As described above, since the pixel to which the present technology is applied is configured to be provided with the feedback enable transistor (FBEN), so that the parasitic capacitance C_ST and the parasitic capacitance C_FB can be further ensured by wiring, noise such as KTC noise can be reduced.

[0313] As described above, when this technology is applied to a pixel with a two-tap structure, the transistors and the wiring in the taps are arranged linearly and symmetrically within the pixel, thus eliminating variations in wiring length. Although there is a possibility that if wiring lengths vary, the wiring capacity may vary and it may be impossible to properly suppress noise, the application of this technology can reduce the possibility of this happening.

[0314] Since redundant wiring for adjusting parasitic capacitance is provided, variation in parasitic capacitance can be suppressed. In the case where a pixel to which the present technology is applied is applied to a pixel that performs distance measurement, distance measurement can be performed with enhanced accuracy.

[0315] Note that this technology can be applied to a so-called continuous wave scheme in an indirect ToF scheme, in which light projected onto an object is amplified and modulated. As the structure of the photodiode 51 in the light receiving unit 15, this technology can be applied to a distance measuring sensor having a structure in which charge is distributed to two charge accumulation units, such as a distance measuring sensor with a current-assisted photon demodulator (CAPD) and a distance measuring sensor based on a gate scheme in which the charge of the photodiode is alternately applied between two gates.

[0316] Although the above embodiment has described a case in which the pixel 31 has a two-tap structure in which the charge generated by the photodiode 51 is distributed to two taps (i.e., tap 52A and tap 52B), the present technology can also be applied to pixel structures having other numbers of taps, such as a one-tap structure and a four-tap structure.

[0317] <Example of Distance Measuring Sensor Chip Configuration>

[0318] Figure 26 : is a perspective view showing an example of the chip configuration of the distance measuring sensor 13 .

[0319] For example, the distance measuring sensor 13 may be constituted by one chip in which a sensor die 651 and a logic die 652 as a plurality of dies (substrates) are laminated, as shown in FIG. Figure 26 As shown in A.

[0320] The sensor die 651 includes (a circuit as) a sensor unit 661 , and the logic die 652 includes a logic unit 662 .

[0321] For example, the pixel array unit 32 and the drive control circuit 33 may be formed in the sensor unit 661. For example, the pulse generation circuit 71, the controller 72, an AD conversion unit that performs AD conversion on the detection signal, the signal processing unit 16, and the input / output terminals are formed in the logic unit 662.

[0322] Furthermore, the distance measuring sensor 13 may be composed of three layers, wherein another logic die is laminated in addition to the sensor die 651 and the logic die 652. Of course, the distance measuring sensor 13 may also be composed of four or more layers of die (substrates).

[0323] Alternatively, the distance measuring sensor 13 may be constituted by, for example, a first chip 671 and a second chip 672 and a relay substrate (interposer substrate) 653 on which they are mounted, as shown in FIG. Figure 26 As shown in B.

[0324] For example, the pixel array unit 32 and the drive control circuit 33 are formed on the first chip 671. The pulse generation circuit 71, the controller 72, an AD conversion unit that performs AD conversion on the detection signal, the signal processing unit 16, etc. are formed on the second chip 672.

[0325] Note that the above Figure 26 The circuit configuration of the sensor die 651 and the logic die 652 in A and Figure 26 The circuit configuration of the first chip 671 and the second chip 672 in FIG. 6 is merely an example, and the present invention is not limited thereto. For example, the signal processing unit 16 that performs processing such as generating a depth map may be provided outside the ranging sensor 13 (on another chip).

[0326] <Configuration Example of Electronic Device>

[0327] For example, the distance measuring module 11 may be installed in an electronic device such as a smartphone, a tablet terminal, a mobile phone, a personal computer, a game device, a television receiver, a wearable terminal, a digital still camera, or a digital video camera.

[0328] Figure 27 : is a block diagram showing a configuration example of a smartphone as an electronic device equipped with a distance measurement module.

[0329] like Figure 27 As shown, a smartphone 701 is composed of a distance measuring module 702, an imaging device 703, a display 704, a speaker 705, a microphone 706, a communication module 707, a sensor unit 708, a touch panel 709, and a control unit 710, which are connected to each other via a bus 711. In addition, the control unit 710 functions as an application processing unit 721 and an operating system processing unit 722 by causing the CPU to execute a program.

[0330] Figure 1The ranging module 11 shown in FIG. 1 is applied to the ranging module 702. For example, the ranging module 702 is provided on the front surface of the smartphone 701 and can output a depth value of the surface shape of the face, hand, finger, etc. of the user of the smartphone 701 as a ranging result by performing ranging on the user of the smartphone 701.

[0331] The imaging device 703 is provided on the front surface of the smartphone 701, and acquires an image of the user photographing the smartphone 701 by imaging the user as a subject. Note that although not shown in the figure, a configuration may be adopted in which the imaging device 703 is also provided on the rear surface of the smartphone 701.

[0332] The display 704 displays an operation screen for processing performed by the application processing unit 721 and the operating system processing unit 722, an image captured by the imaging device 703, etc. When making a call using the smartphone 701, the speaker 705 and the microphone 706 perform operations such as outputting the other party's voice and collecting the user's voice.

[0333] The communication module 707 performs communication via a communication network. The sensor unit 708 senses speed, acceleration, proximity, and the like, and the touch panel 709 acquires a touch operation of a user on an operation screen displayed on the display 704 .

[0334] The application processing unit 721 performs processing for providing various services through the smartphone 701. For example, the application processing unit 721 may perform processing for creating a face based on computer graphics that virtually reproduces the user's facial expression based on the depth provided by the ranging module 702, and displaying the created face on the display 704. In addition, the application processing unit 721 may perform processing for creating three-dimensional shape data of, for example, an arbitrary three-dimensional object based on the depth provided by the ranging module 702.

[0335] The operating system processing unit 722 performs processing for implementing basic functions and operations of the smartphone 701. For example, the operating system processing unit 722 can perform processing for authenticating the user's face and unlocking the smartphone 701 based on the depth value provided from the ranging module 702. In addition, for example, the operating system processing unit 722 can perform processing for recognizing user gestures based on the depth value provided from the ranging module 702, and can perform processing for inputting various operations according to the gestures.

[0336] According to the smartphone 701 configured in this manner, a depth map with high accuracy can be generated at high speed, for example, by applying the aforementioned distance measurement module 11. The smartphone 701 can therefore detect distance measurement information more accurately.

[0337] <Example of Application in Mobile Objects>

[0338] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, a robot, etc.).

[0339] Figure 28 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0340] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Figure 28 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0341] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force; a drive force transmission mechanism that transmits the drive force to the wheels; a steering mechanism that adjusts the vehicle's steering angle; and a braking device that generates the vehicle's braking force.

[0342] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and other functions.

[0343] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the vehicle exterior and receive the captured images. Furthermore, the vehicle exterior information detection unit 12030 can also perform object detection and distance detection on the road, such as people, vehicles, obstacles, signs, and text, based on the received images.

[0344] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal based on the intensity of the received light. Imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by imaging unit 12031 can be visible light or invisible light such as infrared.

[0345] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is dozing off.

[0346] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on the vehicle exterior and interior information acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement advanced driver assistance system (ADAS) functions such as vehicle collision avoidance and impact mitigation after driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0347] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 to perform collaborative control such as automatic driving that allows autonomous driving without relying on the driver's operation.

[0348] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for glare prevention, such as switching high beam to low beam, by controlling the headlights according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0349] The audio / image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or auditorily notifying the occupants of the vehicle or the outside of the vehicle of information. Figure 28 In the illustrated example, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0350] Figure 29 12031 is a diagram illustrating an example of an installation position of the imaging unit 12031.

[0351] exist Figure 29 , vehicle 12100 includes imaging units 12101 , 12102 , 12103 , 12104 , and 12105 as imaging unit 12031 .

[0352] Imaging units 12101, 12102, 12103, 12104, and 12105 can be located in locations such as the front nose, sideview mirrors, rear bumper, rear door, and the upper portion of the windshield inside the vehicle 12100. Imaging unit 12101 located at the front nose and imaging unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture front-facing images of vehicle 12100. Imaging units 12102 and 12103 located on the sideview mirrors primarily capture images of the sides of vehicle 12100. Imaging unit 12104 located on the rear bumper or rear door primarily captures images of the rear of vehicle 12100. The front-facing images captured by imaging units 12101 and 12105 are primarily used to detect leading vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0353] Here, Figure 29The figure shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located at the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located at the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 as viewed from above can be obtained.

[0354] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0355] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 determines the distance to each three-dimensional object in imaging ranges 12111 to 12114, as well as the change in distance over time (relative speed relative to vehicle 12100). Specifically, it can extract a three-dimensional object traveling at a predetermined speed (e.g., 0 km / h or greater) in a direction substantially identical to vehicle 12100 (i.e., the closest three-dimensional object on the travel path of vehicle 12100) as a preceding vehicle. Furthermore, microcomputer 12051 can pre-set a distance to be maintained between the vehicle and the preceding vehicle, and execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this manner, cooperative control for autonomous driving can be implemented, wherein autonomous driving is performed without the driver's input.

[0356] For example, the microcomputer 12051 can classify and extract three-dimensional object data related to three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as utility poles) based on the distance information obtained from the imaging units 12101 to 12104, and use this three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles near the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that are difficult to visually recognize. The microcomputer 12051 can then determine a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk value is equal to or greater than a set value and there is a possibility of collision, the microcomputer 12051 can perform driving assistance for collision avoidance by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062 and executing forced deceleration or evasive steering through the drive system control unit 12010.

[0357] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify pedestrians by determining whether a pedestrian exists in images captured by the imaging units 12101 to 12104. This pedestrian identification is performed by, for example, extracting feature points from images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the subject's outline to determine whether the subject is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to overlay and display the identified pedestrian with a square outline for emphasis. Furthermore, the audio / image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian, etc., at a desired location.

[0358] The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present technology.

[0359] The present technology described in various modes in this specification can be implemented independently as long as no contradiction arises. Of course, any number of modes of the present technology can be used in combination. For example, part or all of the present technology described in any embodiment can be implemented in combination with part or all of the present technology described in other embodiments. In addition, part or all of the above-described present technology can be implemented in combination with other technologies not described above.

[0360] In addition, for example, a configuration described as one device (or one processing unit) may be divided to be configured as a plurality of devices (or processing units). On the other hand, the configuration described as a plurality of devices (or processing units) may be collected and configured as one device (or processing unit). A configuration other than the above configuration may be added to the configuration of each device (or each processing unit). In addition, when the configuration or operation is substantially the same throughout the system, a portion of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or another processing unit).

[0361] In addition, in this specification, a system means a group of multiple components (devices, modules (components), etc.), regardless of whether all components are arranged in a single housing. Therefore, multiple devices housed in separate housings and connected via a network, as well as a device in which multiple modules are housed in a single housing, are both systems.

[0362] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0363] The present technology can adopt the following configurations.

[0364] (1) An imaging element comprising: a first wiring connecting a predetermined transistor in a first adjacent pixel to a through-hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring connecting a predetermined transistor in a second adjacent pixel to a through-hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, wherein the first wiring is connected to a redundant wiring.

[0365] (2) The imaging element according to (1), wherein a layer in which the predetermined transistor is provided and a layer in which the first wiring and the second wiring are provided are different layers.

[0366] (3) The imaging element according to (1) or (2), wherein each through-hole is formed in a substantially linear shape.

[0367] (4) An imaging element according to any one of (1) to (3), wherein the pixel includes a photoelectric conversion unit that performs photoelectric conversion, a plurality of charge accumulation units that accumulate charges obtained by the photoelectric conversion unit, and a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units, and the predetermined transistor is the transfer unit.

[0368] (5) An imaging element according to (4), wherein the pixel further includes: a plurality of reset units that reset each of the plurality of charge accumulation units; a plurality of reset voltage control units that control a voltage to be applied to each of the plurality of reset units; and a plurality of additional control units that control the addition of capacity to each of the plurality of charge accumulation units, and each of the plurality of charge accumulation units is composed of a plurality of regions.

[0369] (6) An imaging element according to (5), wherein a plurality of regions constituting a charge accumulation unit are provided in a substrate provided with a photoelectric conversion unit, wiring connecting the plurality of regions is provided in a wiring layer laminated on the substrate, and the first wiring and the second wiring are provided in a wiring layer different from the wiring layer.

[0370] (7) The imaging element according to (5) or (6), wherein the plurality of charge accumulation units, the plurality of transfer units, the plurality of reset units, the plurality of reset voltage control units, and the plurality of additional control units are arranged linearly symmetrically.

[0371] (8) The imaging element according to any one of (1) to (7), further includes: a phase shift circuit that generates a phase-shifted drive pulse signal, wherein the phase-shifted drive pulse signal is obtained by shifting a drive pulse signal generated corresponding to a light-emitting control signal to multiple phases in a time-division manner in one frame period, and the light-emitting control signal represents the irradiation timing of the light-emitting source, wherein the pixel accumulates an electric charge obtained by photoelectric conversion of reflected light based on the phase-shifted drive pulse signal, and the reflected light is obtained by reflecting light emitted from the light-emitting source by a predetermined object, and outputs a detection signal based on the accumulated electric charge.

[0372] (9) An imaging element according to (8), wherein the plurality of charge accumulation units include a first charge accumulation unit and a second charge accumulation unit, the first charge accumulation unit accumulates the charge based on the phase-shifted drive pulse signal, and the second charge accumulation unit accumulates the charge based on a signal inverted relative to the phase-shifted drive pulse signal.

[0373] (10) A ranging module comprising: a light-emitting unit that emits irradiation light; and a light-receiving element that receives reflected light obtained by reflecting the light from the light-emitting unit by an object, wherein the light-receiving element includes a photoelectric conversion unit that performs photoelectric conversion; a plurality of charge accumulation units that accumulate charges obtained by the photoelectric conversion unit; a plurality of transfer units that transfer charges from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring that connects the transfer unit in a first adjacent pixel to a through hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring that connects the transfer unit in a second adjacent pixel to a through hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer, and the first wiring is connected to a redundant wiring.

[0374] [Reference Number List]

[0375] 11 Distance measurement module

[0376] 12 light-emitting units

[0377] 13 Distance sensor

[0378] 14 Lighting control unit

[0379] 15 Light receiving unit

[0380] 16 signal processing units

[0381] 21 pixel array unit

[0382] 23 columns of signal processing units

[0383] 26 pixel drive lines

[0384] 31 pixels

[0385] 32 pixel array unit

[0386] 33 Drive control circuit

[0387] 41 pass transistor

[0388] 42 FD units

[0389] 43 Select transistor

[0390] 44 Reset transistor

[0391] 45 Amplifier Transistor

[0392] 47 Discharge transistor

[0393] 49 Additional capacitor unit

[0394] 51 Photodiode

[0395] 52 taps

[0396] 53 vertical signal lines

[0397] 54 well contact

[0398] 71 Pulse Generation Circuit

[0399] 72 Controller

[0400] 81 Phase Shift Circuit

[0401] 82 driver units

[0402] 101 Time

[0403] 102 Time Period

[0404] 141 Semiconductor Substrate

[0405] 142 multi-layer wiring layers

[0406] 143 Anti-reflective film

[0407] 144 pixel border

[0408] 145 pixel inter-shading film

[0409] 146 planarization film

[0410] 147 On-chip lens

[0411] 151 Semiconductor Region

[0412] 152 Semiconductor Region

[0413] 153 Hafnium oxide film

[0414] 154 Aluminum Oxide Film

[0415] 155 silicon oxide film

[0416] 161 pixel separation

[0417] 162 interlayer insulating film

[0418] 166 through holes

[0419] 211 through hole

[0420] 311 through hole

[0421] 312, 313 Contact

[0422] 314 through hole

[0423] 315 Contact

[0424] 316 through hole

[0425] 317 Contact

[0426] 318 through hole

[0427] 331, 332, 333, 341 wiring

[0428] 361 Contact

[0429] 363 through-hole

[0430] 371, 372, 373, 374 wiring

[0431] 375, 376 redundant wiring

[0432] 381 Contact

Claims

1. An imaging element, comprising: a phase shift circuit that generates a phase-shifted drive pulse signal obtained by shifting a drive pulse signal generated corresponding to a light-emission control signal to a plurality of phases in a time-division manner during one frame period, the light-emission control signal indicating an illumination timing of a light-emitting source; a pixel for accumulating charges obtained by photoelectric conversion of reflected light obtained by reflection of light emitted from the light emitting source by a predetermined object based on the phase-shifted drive pulse signal, and outputting a detection signal according to the accumulated charges, a first wiring connecting a predetermined transistor in a first adjacent pixel to a through-hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring connecting a predetermined transistor in a second adjacent pixel to a through-hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer; The first wiring is connected to a redundant wiring for adjusting parasitic capacitance, and the redundant wiring is added to a predetermined wiring.

2. The imaging element according to claim 1, wherein A layer in which the predetermined transistor is provided is a different layer from a layer in which the first wiring and the second wiring are provided.

3. The imaging element according to claim 1, wherein Each of the through holes is formed in a substantially linear shape.

4. The imaging element according to claim 1, wherein The pixels include: a photoelectric conversion unit, performing photoelectric conversion; a plurality of charge accumulation units that accumulate charges obtained by the photoelectric conversion units; and a plurality of transfer units that transfer the charge from the photoelectric conversion unit to each of the plurality of charge accumulation units; and The predetermined transistor is the transmission unit.

5. The imaging element according to claim 4, wherein The pixel further comprises: a plurality of reset units that reset each of the plurality of charge accumulation units; a plurality of reset voltage control units that control a voltage to be applied to each of the plurality of reset units; and a plurality of addition control units that control addition of capacity to each of the plurality of charge accumulation units; and Each of the plurality of charge accumulation units is composed of a plurality of regions.

6. The imaging element according to claim 5, in, A plurality of regions constituting the charge accumulation unit are provided in a substrate provided with the photoelectric conversion unit; Wiring connecting the plurality of regions is provided in a wiring layer laminated on the substrate; and The first wiring and the second wiring are provided in a wiring layer different from the wiring layer.

7. The imaging element according to claim 5, wherein The plurality of charge accumulation units, the plurality of transfer units, the plurality of reset units, the plurality of reset voltage control units, and the plurality of additional control units are linearly symmetrically arranged.

8. The imaging element according to claim 1, wherein The plurality of charge accumulation units include a first charge accumulation unit that accumulates the charge based on the phase-shifted drive pulse signal and a second charge accumulation unit that accumulates the charge based on a signal inverted in phase with respect to the phase-shifted drive pulse signal.

9. A ranging module, comprising: a light emitting unit for emitting irradiation light; a phase shift circuit that generates a phase-shifted drive pulse signal obtained by shifting a drive pulse signal generated corresponding to a light-emission control signal to a plurality of phases in a time-division manner in one frame period, the light-emission control signal indicating an illumination timing of the light-emitting unit; and a light receiving element that receives reflected light obtained by reflecting the light from the light emitting unit by an object; Wherein, the light receiving element includes: a photoelectric conversion unit that performs photoelectric conversion on the reflected light; a plurality of charge accumulation units that accumulate the charges obtained by the photoelectric conversion units based on the phase-shifted drive pulse signal; a plurality of transfer units that transfer the charge from the photoelectric conversion unit to each of the plurality of charge accumulation units; a first wiring connecting the transfer unit in a first adjacent pixel to a through-hole formed in one of the first adjacent pixels and to a wiring formed in another layer; and a second wiring connecting the transfer unit in a second adjacent pixel to a through-hole formed in a pixel adjacent to one of the second adjacent pixels and to a wiring formed in another layer; and The first wiring is connected to a redundant wiring for adjusting parasitic capacitance, the redundant wiring being added to a predetermined wiring.

Images