A manufacturing process method for a TFT device with an ESL-to-BCE architecture

Abstract

A manufacturing process method for a TFT device of an ESL-to-BCE architecture includes: sequentially forming a metal gate and a gate insulating layer on a glass substrate; depositing an active layer on the gate insulating layer; coating a first positive photoresist on the upper surface of the active layer, performing an exposure and development process, developing and removing the first positive photoresist not blocked by the mask, and performing a hard bake to remove the solvent in the PR and completely harden to form a protective film; patterning an active layer SE; continuing to coat a second positive photoresist, performing a DC process exposure and development; developing away the second positive photoresist illuminated by the ES mask; etching a DC hole by dry etching; performing a photoresist stripping process, at which time the DC hole is completely opened and the active layer is not etched; patterning a source and drain electrode; depositing a passivation insulating layer to form a TFT device. The present invention solves the process problem of active layer back channel damage encountered in the existing ESL-to-BCE architecture.

Description

Technical Field

[0001] The present invention belongs to the technical field of display transistors, and specifically refers to a manufacturing process method of a TFT device with an ESL-to-BCE architecture. Background Art

[0002] Indium gallium zinc thin film transistor (IGZO-TFT) is a special type of metal oxide semiconductor field effect transistor (MOSFET). IGZO is an amorphous oxide containing indium, gallium and zinc. The carrier mobility is 20 to 30 times that of amorphous silicon. It can greatly improve the charging and discharging rate of TFT to pixel electrode, improve the response speed of pixels, have a faster panel refresh rate, and realize ultra-high resolution TFT-LCD. At the same time, the existing amorphous silicon production line only needs a slight modification to be compatible with the IGZO process, so it is more competitive in terms of cost than low temperature polycrystalline silicon (LTPS). There are two common structures of traditional a-Si or IGZO TFT: ESL (etch stop layer) and BCE (Back channel etch).

[0003] In the existing IGZO array process technology, the ESL architecture is often used. Under this architecture, due to the presence of an etching barrier layer, the electrical performance of the TFT device is more stable and the product yield is relatively higher. However, an extra mask also means a reduction in factory production capacity. The increase in the number of process pep increases the process cost to a certain extent. For this reason, based on the existing IGZO array process technology—ESL architecture, if the ESL architecture can be directly converted to BCE architecture products for production without changing the original mask, the benefits can be maximized. However, this direct conversion will inevitably encounter some technical difficulties, such as process problems, such as Figure 1 As shown, the original ES mask will open ES holes at the channel of the TFT device to facilitate the connection between the source and drain electrodes SD and the active layer IGZO. However, after removing the ES layer, the ES hole position is not protected by the ES etching barrier layer, and the active layer IGZO will inevitably be bombarded by the dry etching gas at the ES hole position, causing damage to the IGZO back channel. The increase in defects makes the TFT device unstable. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a manufacturing process method for a TFT device of an ESL-to-BCE architecture, which solves the process problem of active layer back channel damage encountered in the current ESL-to-BCE architecture.

[0005] The present invention is achieved in that:

[0006] A manufacturing process method of a TFT device of an ESL to BCE architecture comprises the following steps:

[0007] Step 1: Patterning a metal gate and a gate insulating layer on a glass substrate in sequence;

[0008] Step 2: depositing an active layer on the gate insulating layer by using a physical vapor deposition method;

[0009] Step 3: coating a first positive photoresist on the upper surface of the active layer, wherein the first positive photoresist dissolves in a developer when exposed to light;

[0010] Step 4: performing an exposure and development process to remove the first positive photoresist that is not blocked by the mask, and performing hard baking to remove the solvent in the PR and completely harden it to form a protective film;

[0011] Step 5: Patterning the active layer; no thin film process is performed here, that is, the first positive photoresist is not removed;

[0012] Step 6: Then continue to apply a second positive photoresist layer, and use the original ES mask for DC process exposure and development;

[0013] Step 7: Develop the second positive photoresist illuminated by the ES mask light;

[0014] Step 8: A DC hole is etched out by dry etching, while the original ES hole position is not etched because it is protected by the first positive photoresist;

[0015] Step 9: Perform a photoresist stripping process, at which point the DC hole is completely opened and the active layer SE is not etched;

[0016] Step 10: Pattern the source and drain;

[0017] Step 11: A passivation insulating layer is then deposited using chemical vapor deposition to form a TFT device.

[0018] Furthermore, the metal gate is a Mo / Al / Mo structure.

[0019] Furthermore, the gate insulating layer is SiOx.

[0020] Furthermore, the active layer is a semiconductor layer of a TFT device, including: a-Si, MOx or LTPS.

[0021] Furthermore, the active layer is IGZO SE.

[0022] Furthermore, the source and drain are of Mo / Al / Mo structure.

[0023] Furthermore, the insulating layer is SiOx.

[0024] The advantages of the present invention are: in order to solve the process problem of active layer back channel damage encountered in the current ESL to BCE architecture, the present invention is based on the existing process technology and mask, utilizes the characteristics of the existing process, does not perform a film stripping process after IGZO exposure and development, utilizes the retained photoresist as an etching barrier layer, and in the DC opening process, the IGZO surface is protected by a layer of photoresist during exposure / etching, thereby avoiding the IGZO back channel from being bombarded by ES hole dry etching gas, making the TFT device more stable, thereby ensuring the normal display of the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of SE over-corrosion risk in the ESL-to-BCE architecture of the prior art.

[0027] Figure 2 It is a structural schematic diagram of the first step of the process of the present invention.

[0028] Figure 3 It is a schematic structural diagram of the second step of the process of the present invention.

[0029] Figure 4 It is a schematic structural diagram of the third step of the process of the present invention.

[0030] Figure 5 It is a schematic structural diagram of the fourth step of the process of the present invention.

[0031] Figure 6 It is a schematic structural diagram of the fifth step of the process of the present invention.

[0032] Figure 7 It is a schematic structural diagram of the sixth step of the process of the present invention.

[0033] Figure 8 It is a schematic structural diagram of the seventh step of the process of the present invention.

[0034] Fig. 9 It is a schematic structural diagram of the eighth step of the process of the present invention.

[0035] Fig.10 It is a schematic structural diagram of the ninth step of the process of the present invention.

[0036] Fig.11 It is a schematic structural diagram of the tenth step of the process of the present invention.

[0037] Fig.12 It is a schematic structural diagram of the eleventh step of the process of the present invention. DETAILED DESCRIPTION

[0038] like Figures 2 to 12 As shown, a method for manufacturing an array from an ESL to a BCE architecture includes the following steps:

[0039] Step 1: sequentially forming a metal gate GE-2 and a gate insulating layer GI-3 on a glass substrate Glass;

[0040] Step 2: Deposit the active layer IGZO SE-4 on the GI-3 layer using physical vapor deposition;

[0041] Step 3: Coat a layer of positive photoresist PR①-5 on the upper surface of IGZO, which dissolves in the developer when exposed to light;

[0042] Step 4: Perform exposure and development process to remove the photoresist PR①-5 that is not blocked by the mask, and perform hard baking to remove the solvent in the PR and completely harden it to form a protective film;

[0043] Step 5: Patterning the active layer SE-4. No thin film process is performed here, that is, PR①-5 is not removed. This means that after the active layer SE-4 is etched, the invention does not perform the final film stripping process. The photoresist PR①-5 on the patterned active layer SE-4 is retained. The photoresist PR①-5 plays a key role in the subsequent process.

[0044] Step 6: Then continue to apply a layer of positive photoresist PR②-6, and use the original ES mask-9 for DC process exposure and development;

[0045] Step 7: Develop the photoresist PR② illuminated by the ES mask light;

[0046] Step 8: Use dry etching to etch out the DC hole, while the original ES hole position is protected by the photoresist PR①, and the active layer SE-4 is not etched;

[0047] Step 9: Perform photoresist stripping process, at this time the DC hole is completely opened and the active layer SE-4 is not over-etched;

[0048] Step 10: Pattern out the source and drain SD-7;

[0049] Step 11: A passivation insulating layer PV-8 is then deposited using chemical vapor deposition to form a TFT device.

[0050] The professional names are explained as follows:

[0051] Glass: Array side substrate glass, the basic component of the display device, on which active devices such as TFT are formed in sequence;

[0052] Pattern: Patterning, the main process of Array is film formation / exposure / development / etching / stripping. After the photoresist is developed, the corresponding pattern will be formed, and the etching process will etch the film layer without photoresist protection, and the final design pattern will be retained after the stripping process;

[0053] GE: Gate, Metal 1 metal layer, Mo / Al / Mo can be selected here;

[0054] GI: Gate insulation layer, an insulating layer with a large dielectric constant. SiOx can be selected for this design.

[0055] SE: Active layer, semiconductor layer of TFT devices, such as a-Si, MOx and LTPS, etc. IGZO can be selected for this design;

[0056] PR①: positive photoresist PR in SE process, which will dissolve in the developer after exposure to light;

[0057] PR②: Positive photoresist PR in DC process, which will dissolve in the developer after exposure to light;

[0058] SD: source and drain, Metal 2 metal layer, here is Mo / Al / Mo;

[0059] PV: Insulating layer, an insulating layer with a large dielectric constant. SiOx can be selected for this design, which is mainly used to block water and oxygen to prevent them from affecting the stability of TFT devices.

[0060] The present invention solves the process problem of active layer back channel damage encountered in the existing ESL to BCE architecture. Based on the existing process technology and mask, the present invention utilizes the characteristics of the existing process. After the IGZO is exposed and developed, no film stripping process is performed, and the retained photoresist is used as an etching barrier layer. During the DC hole opening process, the IGZO surface is protected by a layer of photoresist during exposure / etching, thereby avoiding the IGZO back channel from being bombarded by the ES hole dry etching gas, making the TFT device more stable, thereby ensuring the normal display of the display screen.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A manufacturing process for a TFT device with an ESL-to-BCE architecture, characterized in that: The steps include: The first step: patterning a metal gate and a gate insulating layer on a glass substrate in sequence; Step 2: depositing an active layer on the gate insulating layer by using a physical vapor deposition method; Step 3: coating a first positive photoresist on the upper surface of the active layer, wherein the first positive photoresist dissolves in a developer when exposed to light; Step 4: performing an exposure and development process to remove the first positive photoresist that is not blocked by the mask, and performing hard baking to remove the solvent in the PR and completely harden it to form a protective film; Step 5: patterning to form an active layer; no thin film process is performed here, that is, the first positive photoresist is not removed; Step 6: Then continue to apply a second positive photoresist layer, and use the original ES mask for DC process exposure and development; Step 7: Develop the second positive photoresist illuminated by the ES mask light; Step 8: A DC hole is etched out by dry etching, while the original ES hole position is not etched because it is protected by the first positive photoresist; Step 9: Perform a photoresist stripping process, at which point the DC hole is completely opened and the active layer SE is not etched; Step 10: Patterning to form source and drain electrodes; Step 11: A passivation insulating layer is then deposited using chemical vapor deposition to form a TFT device.

2. The manufacturing process of a TFT device with an ESL-to-BCE architecture as claimed in claim 1, characterized in that: The metal gate has a Mo / Al / Mo structure.

3. The manufacturing process of a TFT device with an ESL-to-BCE architecture as claimed in claim 1, characterized in that: The gate insulating layer is SiOx.

4. The manufacturing process of a TFT device with an ESL-to-BCE architecture as claimed in claim 1, characterized in that: The active layer is a semiconductor layer of a TFT device, and includes: a-Si, MOx or LTPS.

5. The manufacturing process of a TFT device with an ESL-to-BCE architecture as claimed in claim 1, characterized in that: The active layer is IGZO SE.

6. The manufacturing process of the TFT device of ESL to BCE architecture as claimed in claim 1, characterized in that: The source and drain are of Mo / Al / Mo structure.

7. The manufacturing process of the TFT device of ESL to BCE architecture as claimed in claim 1, characterized in that: The insulating layer is SiOx.

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