Epitaxial structure, p-type transistor, integrated circuit, and power management chip

Abstract

The application discloses an epitaxial structure, a P-type transistor, an integrated circuit and a power management chip, wherein the epitaxial structure comprises a substrate and a vertical stacked structure formed on the substrate, the vertical stacked structure comprises a first P-type region, a P-type channel region and a second P-type region which are sequentially stacked, and a side surface of the second P-type region is in contact with a side surface of the substrate; in the epitaxial structure of the vertical stacked first P-type region, P-type channel region and second P-type region, the P-type channel region can be sharply reduced to the nanometer range without being limited by a photolithography process. In addition, the threshold voltage of the normally-off P-type transistor with the epitaxial structure can be freely adjusted by adjusting the P-type channel region doping concentration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an epitaxial structure, a P-type transistor, an integrated circuit and application and a power management chip. BACKGROUND

[0002] Gallium nitride (GaN) material has a very narrow depletion region due to its larger band gap than traditional silicon material, so it can develop a very high carrier concentration device structure, which shows a broad application prospect in the field of developing next-generation high-frequency high-voltage electronic power devices. However, with the continuous development of gallium nitride power device technology, the silicon-based peripheral circuit in the power system (such as driving, sensing and control circuit, etc.) begins to limit the potential of gallium nitride power devices. On the one hand, the heterogeneous integration of silicon-based peripheral circuit and gallium nitride power device through packaging requires metal line interconnection, which causes the generation of interconnection parasitic inductance, causing circuit instability. For example, in the driving circuit, the parasitic inductance L GS between the gate and the source will cause gate voltage oscillation when the current changes greatly, which may cause mis-conduction in the switching transient process. With the increase of the working frequency of the power system, the parasitic effect becomes more and more significant. On the other hand, although the heterogeneous monolithic integration process can minimize parasitic parameters, in addition to the limited heterogeneity, high process complexity and cost increase, it is still difficult to get rid of the limitations of silicon devices. The limited thermal stability of silicon devices limits the excellent performance of gallium nitride power devices in high-temperature working conditions; in addition, due to poor radiation resistance, silicon devices also limit the application of switching power supplies in radiation environments. In order to break through the limitations of the existing silicon-based peripheral circuit, fully release the potential of gallium nitride power devices and power systems, all-gallium nitride monolithic power integrated circuits are important development directions and research hotspots. As a necessary component of complementary logic circuits, gallium nitride-based P-type transistor devices are the key to realizing power integrated circuits. In addition, P-type transistor devices can also expand the functionality of power device platforms to improve the performance of gallium nitride power devices.

[0003] However, P-type transistor devices on traditional commercial silicon substrate gallium nitride platforms face the problem of being difficult to achieve both normally-off operation and reasonable on-state current. Therefore, new threshold control technology is needed to achieve normally-off operation of P-type transistor devices, break through the limited threshold voltage control ability and channel on-resistance degradation, and realize the maximum potential of P-type transistor devices in P-type gate high electron mobility transistor (HEMT) power platforms. SUMMARY

[0004] Therefore, in order to improve the threshold voltage control ability of normally-off devices and reduce the on-resistance of the devices, it is necessary to provide an epitaxial structure, a P-type transistor, an integrated circuit and application and a power management chip.

[0005] The present application provides an epitaxial structure, comprising a substrate and a vertical stack structure formed on the substrate, the vertical stack structure comprising a first P-type region, a P-type channel region and a second P-type region stacked in sequence, one side surface of the first P-type region being in contact with one side surface of the substrate;

[0006] wherein the first P-type region comprises at least one first P-type layer, the P-type channel region comprises at least one P-type channel layer, and the second P-type region comprises at least one second P-type layer.

[0007] In one embodiment, the doping elements in the first P-type layer and the second P-type layer are each independently selected from at least one of magnesium and oxygen, and the doping elements in the P-type channel layer are selected from at least one of silicon, germanium, iron, carbon and oxygen; and / or

[0008] the doping concentration of the first P-type layer is 10 12 cm -3 ~ 10 22 cm -3 , the doping concentration of the P-type channel layer is 0 ~ 10 22 cm -3 , and the doping concentration of the second P-type layer is 10 12 cm -3 ~ 10 22 cm -3 ; and / or

[0009] the host material of the first P-type layer and the host material of the second P-type layer are each independently selected from at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, aluminum nitride, indium aluminum gallium nitride, zinc oxide, indium oxide, stannous oxide, tin oxide, copper oxide and nickel oxide, and the host material of the P-type channel layer is selected from at least one of gallium nitride, aluminum gallium nitride, aluminum nitride, indium gallium nitride and indium aluminum gallium nitride.

[0010] In one embodiment, the substrate comprises a substrate, a stress buffer layer, a channel layer and a barrier layer stacked in sequence, and one side surface of the barrier layer is in contact with one side surface of the first P-type region.

[0011] In one embodiment, a two-dimensional electron gas is formed between the barrier layer and the channel layer by introducing at least one of spontaneous polarization and piezoelectric polarization.

[0012] The present application also provides a P-type transistor, comprising a gate dielectric layer, a first gate, a first electrode, a second electrode and an epitaxial structure as described above, one of the first electrode and the second electrode being a first source electrode, and the other being a first drain electrode.

[0013] The gate dielectric layer is in contact with the first P-type region, the P-type channel region and the second P-type region in the epitaxial structure, and the first gate is in contact with the gate dielectric layer.

[0014] The first electrode is in contact with the first P-type region, and the second electrode is in contact with the second P-type region.

[0015] In one of the embodiments, a third electrode is further included, and a material of the third electrode forms an ohmic contact or a Schottky contact with a material of the P-type channel region.

[0016] The application further provides an integrated circuit including the P-type transistor as described above.

[0017] In one of the embodiments, an N-type transistor is further included, wherein a substrate of the P-type transistor and a substrate of the N-type transistor are the same substrate, and the N-type transistor further includes a third P-type region disposed on the substrate, and the third P-type region has the same thickness, doping concentration, bulk material and doping element as the first P-type region.

[0018] In one of the embodiments, the N-type transistor further includes a second source, a second drain and a second gate, wherein the second gate is in contact with the third P-type region, the second source is in contact with the substrate, and the second drain is in contact with the substrate.

[0019] Further, the application provides a power management chip including the P-type transistor as described above.

[0020] In the epitaxial structure of the vertically stacked first P-type region, P-type channel region and second P-type region, the P-type channel region can be reduced to the nanometer range without being limited by the photolithography process. In addition, the threshold voltage of the normally-off P-type transistor with the epitaxial structure can be freely adjusted by adjusting the doping concentration of the P-type channel region.

[0021] Further, the gate channel width of the transistor structure with the epitaxial structure is determined by the thickness of the P-type channel region. The channel width can be controlled to tens of nanometers by the epitaxial thickness without the need for high-cost and inefficient electron beam lithography process, greatly reducing the on-resistance of the channel. In addition, compared with the traditional planar P-type transistor device structure, the vertical P-type transistor device sidewall is less affected by the directional etching bombardment, and the introduced defects are less, and the P-type channel region can achieve better on characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 A cross-sectional structure diagram of the epitaxial structure of the application is shown in the figure;

[0023] Figure 2 FIG. 2 is a schematic diagram of a cross-sectional structure of a P-type transistor according to an embodiment of the present application;

[0024] Figure 3 FIG. 2 is a schematic diagram of a cross-sectional structure of a P-type transistor according to an embodiment of the present application;

[0025] Figure 4 FIG. 3 is a schematic diagram of a cross-sectional structure of an integrated P-type transistor and N-type transistor according to an embodiment of the present application;

[0026] Figure 5 FIG. 4 is a transfer output characteristic curve of a P-type transistor according to Embodiment 1 of the present application;

[0027] BRIEF DESCRIPTION OF DRAWINGS: 10: epitaxial structure, 110: substrate, 111: substrate, 112: stress buffer layer, 113: channel layer, 114: barrier layer, 115: two-dimensional electron gas, 120: first P-type region, 130: P-type channel region, 140: second P-type region, 20: P-type transistor, 150: gate dielectric layer, 160: first gate, 170: first electrode, 180: second electrode, 190: third electrode, 30: integrated P-type transistor and N-type transistor, 210: third P-type region, 220: first N-type region, 230: second gate, 240: second source, 250: second drain. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description and the accompanying drawings. The figures included in the application generally represent exemplary embodiments of the application. It should be noted, however, that the application can be practiced in many different forms and should not be considered limited to the embodiments set forth in the application. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0029] In describing a position relationship, unless otherwise stated, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or an intervening film layer can also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under the other layer, with one or more intervening layers also being present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] like Figure 1 As shown, the present invention provides an epitaxial structure 10, including a substrate 110 and a vertically stacked structure formed on the substrate 110. The vertically stacked structure includes a first P-type region 120, a P-type channel region 130 and a second P-type region 140 sequentially stacked on the substrate 110. One side surface of the first P-type region 140 is in contact with one side surface of the substrate 110.

[0034] The first P-type region 120 includes at least one first P-type layer, the P-type channel region 130 includes at least one P-type channel layer, and the second P-type region 140 includes at least one second P-type layer.

[0035] In one specific example, the doping elements in the first P-type layer and the second P-type layer are each independently selected from at least one of magnesium and oxygen, and the doping elements in the P-type channel layer are selected from at least one of silicon, germanium, iron, carbon and oxygen.

[0036] In one specific example, the doping concentration of the first P-type layer is 10 12 cm -3 ~ 10 22 cm -3 , the doping concentration of the P-type channel layer is 0 ~ 10 22 cm -3 , and the doping concentration of the second P-type layer is 10 12 cm -3 ~ 10 22 cm -3 .

[0037] In one specific example, the bulk material of the first P-type layer and the bulk material of the second P-type layer are each independently selected from at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, aluminum nitride, indium aluminum gallium nitride, zinc oxide, indium oxide, stannous oxide, tin oxide, copper oxide and nickel oxide, and the bulk material of the P-type channel layer is selected from at least one of gallium nitride, aluminum gallium nitride, aluminum nitride, indium gallium nitride and indium aluminum gallium nitride.

[0038] It can be understood that the selection of the doping elements, the doping concentrations and the bulk materials in each first P-type layer in the first P-type region 120 are independent of each other; the selection of the doping elements, the doping concentrations and the bulk materials in each P-type channel layer in the P-type channel region 130 are independent of each other; and the selection of the doping elements, the doping concentrations and the bulk materials in each second P-type layer in the second P-type region 140 are independent of each other.

[0039] Further, the thickness of the first P-type region 120 is 10 nm ~ 300 nm, the thickness of the P-type channel region 130 is 10 nm ~ 200 nm, and the thickness of the second P-type region 140 is 10 nm ~ 300 nm.

[0040] In one specific example, the substrate 110 includes a substrate 111, a stress buffer layer 112, a channel layer 113 and a barrier layer 114 stacked in sequence, and one side surface of the barrier layer 114 is in contact with one side surface of the first P-type region 120.

[0041] The substrate 111 can be, but is not limited to, silicon, silicon carbide, gallium nitride, aluminum nitride, sapphire or diamond, and the thickness of the substrate 111 is 0.1 mm ~ 1 mm.

[0042] Further, the stress buffer layer 112 has a thickness of 1 μm to 10 μm, and the material of the stress buffer layer 112 is selected from nitrides, and it can be understood that the material of the stress buffer layer 112 can be, but is not limited to, at least one of gallium nitride and aluminum gallium nitride.

[0043] The channel layer 113 has a thickness of 100 nm to 600 nm, and the material of the channel layer 113 is selected from at least one of gallium nitride, aluminum nitride, aluminum gallium nitride, and indium gallium nitride.

[0044] The barrier layer 114 has a thickness of 1 nm to 100 nm, and the material of the barrier layer 114 is selected from at least one of aluminum gallium nitride, gallium nitride, aluminum nitride, and indium gallium nitride.

[0045] In one specific example, the two-dimensional electron gas 115 is formed between the barrier layer 114 and the channel layer 113 by introducing at least one of spontaneous polarization and piezoelectric polarization.

[0046] It can be understood that the channel layer 113 material and the barrier layer 114 material have different band gaps, so that there is a band step difference between the conduction band bottoms of the two, and the band step difference of the conduction band and a large number of positive charges at the interface cause the conduction band bottom to bend, and the bending of the energy band causes a two-dimensional potential well to be formed at the heterojunction interface. The two-dimensional potential well will confine the polarization-induced electrons therein, and these electrons can only move in two dimensions in the plane parallel to the abrupt junction interface in the potential well to form a two-dimensional electron gas 115. The two-dimensional electron gas 115 can be used as a back electrode to enhance the control of the gate of the P-type transistor, and in addition, the range of control of the threshold voltage of the epitaxial structure having the above structure can be further widened.

[0047] The method for forming the epitaxial structure 10 described above includes the following steps S10 to S90:

[0048] Step S10: providing a substrate 111, and preferably, the substrate 111 is gallium nitride.

[0049] Step S20: forming a stress buffer layer 112 on the substrate 111, and the method for forming the stress buffer layer 112 can be, but is not limited to, at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating, and magnetron sputtering.

[0050] Step S30: forming a channel layer 113 on the stress buffer layer 112, and the method for forming the channel layer 113 can be, but is not limited to, at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating, and magnetron sputtering.

[0051] Step S40: Forming a barrier layer 114 on the channel layer 113, the forming method of the barrier layer 114 can be but not limited to at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating and magnetron sputtering.

[0052] Step S50: Forming a first P-type region 120 on the barrier layer 114, the forming method of the first P-type region 120 can be but not limited to preparing a first P-type layer main material by at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating and magnetron sputtering, and doping elements by ion implantation and high-temperature annealing activation or low-energy electron radiation activation.

[0053] Step S60: Forming a P-type channel region 130 on the first P-type region 120, the forming method of the P-type channel region 130 can be but not limited to preparing a P-type channel layer main material by at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating and magnetron sputtering, and doping elements by ion implantation and high-temperature annealing activation or low-energy electron radiation activation.

[0054] Step S70: Forming a second P-type region 140 on the P-type channel region 130, the forming method of the second P-type region 140 can be but not limited to preparing a first P-type layer main material by at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating and magnetron sputtering, and doping elements by ion implantation and high-temperature annealing activation or low-energy electron radiation activation.

[0055] Step S80: Etching part of the first P-type region 120, the P-type channel region 130 and the second P-type region 140 to a required width;

[0056] Step S90: Introducing a two-dimensional electron gas 115 between the channel layer 113 and the barrier layer 114 by introducing at least one of spontaneous polarization and piezoelectric polarization.

[0057] It can be understood that the above step S80 can be adjusted according to the width requirement of the first P-type region 120, the P-type channel region 130 and the second P-type region 140, for example, if the required widths of the layers are the same, the etching step S80 is not required.

[0058] The P-type channel region 130 can be reduced to nanometer scale without the limitation of photolithography process. The threshold voltage of the P-type transistor with the epitaxial structure 10 can be freely adjusted by adjusting the doping concentration of the P-type channel region 130.

[0059] Further, the gate-channel width of the transistor structure with the epitaxial structure 10 is determined by the thickness of the P-type channel region 130. The channel width can be controlled to tens of nanometers by the epitaxial thickness without the high cost and low efficiency of electron beam lithography process, which greatly reduces the on-resistance of the channel. In addition, compared with the traditional planar P-type transistor device structure, the sidewall of the vertical P-type transistor device is less affected by the directional etching bombardment, and the introduced defects are less, and the P-type channel region 130 channel can achieve better on-state characteristics.

[0060] The present application also provides a P-type transistor 20, comprising a gate dielectric layer 150, a first gate 160 and the epitaxial structure 10 as described above, wherein the gate dielectric layer 150 is in contact with the first P-type region 120, the P-type channel region 130 and the second P-type region 140, and the first gate 160 is in contact with the gate dielectric layer 150.

[0061] It can be understood that the material of the gate dielectric layer 150 can be but is not limited to at least one of aluminum oxide, aluminum nitride, aluminum oxynitride, silicon oxide, silicon nitride, silicon oxynitride and zirconium oxide, and the material of the first gate 160 can be but is not limited to at least one of titanium, aluminum, nickel, gold, chromium, titanium nitride, tungsten and nickel oxide.

[0062] Further, the material of the first gate 160 forms an ohmic contact or a Schottky contact with the material of the gate dielectric layer 150.

[0063] In one specific example, a first electrode 170 and a second electrode 180 are further included, the first electrode 170 is in contact with the first P-type region 120, and the second electrode 180 is in contact with the second P-type region 140, wherein the first electrode 170 is a first source electrode, and the second electrode 180 is a first drain electrode, or the first electrode 170 is a first drain electrode, and the second electrode 180 is a first source electrode.

[0064] Further, the material of the first electrode 170 forms an ohmic contact or a Schottky contact with the material of the first P-type region 120, and the material of the second electrode 180 forms an ohmic contact or a Schottky contact with the material of the second P-type region 140.

[0065] Preferably, the material of the first electrode 170 forms an ohmic contact with the material of the first P-type region 120, and the material of the second electrode 180 forms an ohmic contact with the material of the second P-type region 140.

[0066] In one embodiment, a third electrode 190 is further included, and the material of the third electrode 190 forms an ohmic contact or a Schottky contact with the material of the P-type channel region 130.

[0067] It is appreciated that the first electrode 170, the second electrode 180 and the third electrode 190 are each independently selected from at least one of titanium, aluminum, nickel, gold, chromium, titanium nitride, tungsten, and nickel oxide.

[0068] Further, the threshold voltage of the transistor can be adjusted by grounding or applying a bias to the third electrode 190 to the P-type channel region 130.

[0069] The method of forming the P-type transistor 20 as shown in FIG. 1 includes the following steps S110-S150: Figure 2

[0070] Step S110: providing the epitaxial structure 10 with the same width of each layer, and removing part of the P-type channel region 130 and the second P-type region 140.

[0071] Step S120: forming a gate dielectric layer 150 on the first P-type region 120, and the method of forming the gate dielectric layer 150 can be but is not limited to at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating, and magnetron sputtering.

[0072] Step S130: forming a first gate 160 on the gate dielectric layer 150, and the method of forming the first gate 160 can be but is not limited to at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating, and magnetron sputtering.

[0073] Step S140: forming a first electrode 170 on the first P-type region 120 and a second electrode 180 on the second P-type region 140, and the method of forming the first electrode 170 and the second electrode 180 can be but is not limited to at least one of metal evaporation, chemical vapor deposition, and magnetron sputtering.

[0074] The method of forming the P-type transistor 20 as shown in FIG. 2 further includes steps S150-S190. Figure 3

[0075] Step S150: providing the epitaxial structure 10 with the same width of each layer, and removing part of the P-type channel region 130 and the second P-type region 140.

[0076] Step S160: forming a gate dielectric layer 150 on the first P-type region 120, and the method of forming the gate dielectric layer 150 can be but is not limited to at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating, and magnetron sputtering.​​

[0077] Step S170: forming a first gate 160 on the gate dielectric layer 150, the method of forming the first gate 160 can be but not limited to at least one of chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, vacuum ion plating and magnetron sputtering.

[0078] Step S180: forming a first electrode 170 on the first P-type region 120 and forming a second electrode 180 on the second P-type region 140, the method of forming the first electrode 170 and the second electrode 180 can be but not limited to at least one of metal evaporation, chemical vapor deposition and magnetron sputtering.

[0079] Step S190: forming a third electrode 190 on the P-type channel region 130, the method of forming the third electrode 190 can be but not limited to at least one of metal evaporation, chemical vapor deposition and magnetron sputtering.

[0080] The present application also provides an integrated circuit comprising the P-type transistor 20 as described above.

[0081] In one specific example, the integrated circuit further comprises an N-type transistor, wherein the base 110 of the P-type transistor 20 and the base 110 of the N-type transistor are the same base 110, and the N-type transistor further comprises a third P-type region 210 disposed on the base 110, the third P-type region 210 having the same thickness, doping concentration, body material and doping element as the first P-type region 120.

[0082] In one specific example, the N-type transistor further comprises a second source 240, a second drain 250 and a second gate 230, wherein the second gate 230 is in contact with the third P-type region 210, the second source 240 is in contact with the base 110, and the second drain 250 is in contact with the base 110.

[0083] The second gate 230, the second source 240 and the second drain 250 are each independently selected from at least one of titanium, aluminum, nickel, gold, chromium, titanium nitride, tungsten and nickel oxide.

[0084] It can be understood that the material of the third P-type region 210 forms ohmic contact or Schottky contact with the material of the second gate 230, and the second source 240 and the second drain 250 are respectively located on two sides of the third P-type region 210.

[0085] In one specific example, the third P-type region 210 comprises at least one third P-type layer, and the doping element in the third P-type layer is independently selected from at least one of magnesium and oxygen; the doping concentration of the third P-type layer is 10 12 cm -3 ~ 10 22 cm -3The host material of the third P-type layer is selected from at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, aluminum nitride, indium aluminum gallium nitride, zinc oxide, indium oxide, stannous oxide, tin oxide, copper oxide, and nickel oxide.

[0086] Furthermore, the aforementioned N-type transistor also includes a first N-type region 220, which is located between the third P-type region 210 and the substrate 110. The material of the first N-type region 220 forms an ohmic contact or a Schottky contact with the material of the second gate 230. The thickness, doping concentration, host material, and doping elements of the first N-type region 220 are the same as those of the P-type channel region 130.

[0087] In one specific example, the first N-type region 220 includes at least one first N-type layer, wherein the doping element in the first N-type layer is selected from at least one of silicon, germanium, iron, carbon, and oxygen, and the doping concentration of the first N-type layer is 0 to 10. 22 cm -3 And the doping concentration is not 0; the host material of the first N-type layer is selected from at least one of gallium nitride, aluminum gallium nitride, aluminum nitride, indium gallium nitride, and indium aluminum gallium nitride.

[0088] The third P-type region 210 can also form a PN junction gate structure with the first N-type region 220 on the same substrate N-type transistor device, providing lower gate leakage current and larger gate voltage swing for the integrated P-type transistor and N-type transistor 30.

[0089] Because the annealing step in the above transistor fabrication process causes the metal materials of the second source 240 and the second drain 250 to enter the barrier layer 114 from the dislocations present in the barrier layer 114 material, some of the metal materials of the second source 240 and the second drain 250 that have entered the barrier layer 114 will form ohmic contacts with the two-dimensional electron gas 115 respectively.

[0090] like Figure 4 As shown, the method for forming the integrated P-type transistor and N-type transistor 30 includes the following steps S210 to S220:

[0091] Step S210: Provide an epitaxial structure 10 with the same width for each layer; etch away portions of the first P-type region 120, the P-type channel region 130, and the second P-type region 140, as well as portions of the first N-type region 220 and the third P-type region 210; and form on the first P-type region 120, the P-type channel region 130, and the second P-type region 140... Figure 2 P-type transistor.

[0092] Step S220: forming a second gate 230 on the first N-type region 220, and forming a second source 240 and a second drain 250 on both sides of the first N-type region 220 and the third P-type region 210, the forming method of the second gate 230, the second source 240 and the second drain 250 can be, but is not limited to, at least one of metal evaporation, chemical vapor deposition and magnetron sputtering.

[0093] The integrated circuit fully utilizes the epitaxial structure to simultaneously manufacture the N-type transistor and the P-type transistor on the substrate 110, and in particular, the first P-type region and the P-type channel region in the epitaxial structure only need to remove the excess material by etching to reserve the third P-type region or the third P-type region and the first N-type region, the first P-type region not etched in the preset third P-type region is the third P-type region of the N-type transistor, and the P-type channel region not etched in the preset first N-type region is the first N-type region of the N-type transistor, without the need of additional manufacturing steps to manufacture the third P-type region and the first N-type region of the N-type transistor again.

[0094] The application further provides a power management chip comprising the P-type transistor or the integrated circuit.

[0095] It can be understood that the power management chip can be widely applied to various electronic products such as electronic components.

[0096] The following specific examples are provided to further illustrate the epitaxial structure, the P-type transistor and the integrated circuit. The raw materials involved in the following specific embodiments can be sourced from the market if not otherwise specified.

[0097] Example 1

[0098] The embodiment provides a P-type transistor, which comprises an epitaxial structure, a first gate, a gate dielectric layer, a first source and a first drain,

[0099] The epitaxial structure comprises a silicon material with a thickness of 0.5 mm as a substrate, an AlGaN / GaN superlattice with a thickness of 4 μm as a stress buffer layer, a GaN with a thickness of 400 nm as a channel layer, an AlGaN with a thickness of 15 nm as a barrier layer, the channel layer and the barrier layer being in contact with a two-dimensional electron gas structure, a Mg-doped GaN with a thickness of 80 nm and a doping concentration of 3×10 19 cm -3 -3 as a first P-type layer, a Si-doped GaN with a thickness of 50 nm and a doping concentration of 1×10 18 cm -3 -3 as a P-type channel layer, and a Mg-doped GaN with a thickness of 50 nm and a doping concentration of 3×10 19 cm -3 as a first N-type layer.-3 Mg-doped GaN is used as the second P-type layer, i.e., the second P-type region.

[0100] Ni / Au serves as the first drain, the first source, and the first gate. Aluminum oxide is used as the gate dielectric layer. The material of the first drain forms an ohmic contact with the material of the first P-type region, and the material of the first source forms an ohmic contact with the material of the second P-type region.

[0101] like Figure 5 As shown, the transfer output characteristic curves of Example 1, which uses P-type channel layers with different silicon doping concentrations as P-type channel regions, obtained by finite element simulation, are provided.

[0102] Example 2

[0103] This embodiment provides a P-type transistor and an N-type transistor integrated on the same substrate, including an epitaxial structure, a first gate, a gate dielectric layer, a first source, a first drain, a first N-type region, a third P-type region, a second gate, a second source, and a second drain.

[0104] The epitaxial structure comprises a 0.5 mm thick silicon substrate, a 4 μm thick AlGaN / GaN superlattice as a stress buffer layer, a 400 nm thick GaN channel layer, and a 15 nm thick AlGaN barrier layer. A two-dimensional electron gas structure is present at the contact between the channel layer and the barrier layer. The channel layer is 80 nm thick and has a doping concentration of 3 × 10⁻⁶. 19 cm -3 Mg-doped GaN is used as the first P-type layer, i.e., the first P-type region, with a thickness of 50 nm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 Si-doped GaN is used as the P-type channel layer, i.e., the P-type channel region, with a thickness of 50 nm and a doping concentration of 3 × 10⁻⁶. 20 cm -3 Oxygen-doped nickel oxide serves as the second P-type layer, i.e., the second P-type region, with a thickness of 80 nm and a doping concentration of 3 × 10⁻⁶. 19 cm -3 Mg-doped GaN is used as the third P-type layer, i.e., the third P-type region, with a thickness of 50 nm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 Si-doped GaN is used as the first N-type layer, i.e., the first N-type region.

[0105] Ni / Au as the first drain electrode, Ni / Au as the first source electrode, Ni / Au as the first gate electrode, aluminum oxide as the gate dielectric layer, Ti / Al / Ni / Au as the second drain electrode, Ti / Al / Ni / Au as the second source electrode, Ni / Au as the second gate electrode, the material of the first drain electrode and the material of the first P-type region form an ohmic contact, the material of the first source electrode and the material of the second P-type region form an ohmic contact, the material of the second drain electrode and the two-dimensional electron gas form an ohmic contact, and the material of the second source electrode and the two-dimensional electron gas form an ohmic contact.

[0106] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present disclosure.

[0107] The above-described embodiments only express several implementation manners of the present application, facilitate understanding of the technical solutions of the present application in detail, but should not be understood as a limitation on the scope of patent protection of the present application. It should be pointed out that, for ordinary skilled persons in the art, a number of modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. It should be understood that, on the basis of the technical solutions provided by the present application, the technical solutions obtained by ordinary skilled persons in the art through logical analysis, reasoning or limited experiments all belong to the protection scope of the appended claims of the present application. Therefore, the protection scope of the present patent of the present application should be subject to the contents of the appended claims, and the description and drawings can be used to explain the contents of the claims.

Claims

1. An epitaxial structure, characterized by, The vertical stack structure includes a first P-type region, a P-type channel region and a second P-type region which are sequentially stacked, and a side surface of the first P-type region is in contact with a side surface of the substrate; The first P-type region includes at least one first P-type layer, the P-type channel region includes at least one P-type channel layer, and the second P-type region includes at least one second P-type layer; The substrate includes a substrate, a stress buffer layer, a channel layer and a barrier layer which are sequentially stacked, and a side surface of the barrier layer is in contact with a side surface of the first P-type region.

2. The epitaxial structure of claim 1, wherein, The doping elements in the first P-type layer and the second P-type layer are each independently selected from at least one of magnesium and oxygen, and the doping elements in the P-type channel layer are selected from at least one of silicon, germanium, iron, carbon and oxygen; and / or The first P-type layer has a doping concentration of 10 12 cm -3 ~10 22 cm -3 , the P-type channel layer has a doping concentration of 0~10 22 cm -3 , and the second P-type layer has a doping concentration of 10 12 cm -3 ~10 22 cm -3 ; and / or The host materials of the first P-type layer and the second P-type layer are each independently selected from at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, aluminum nitride, indium aluminum gallium nitride, zinc oxide, indium oxide, stannous oxide, tin oxide, copper oxide and nickel oxide, and the host material of the P-type channel layer is selected from at least one of gallium nitride, aluminum gallium nitride, aluminum nitride, indium gallium nitride and indium aluminum gallium nitride.

3. The epitaxial structure of claim 1, wherein, A two-dimensional electron gas is formed between the barrier layer and the channel layer by introducing at least one of spontaneous polarization and piezoelectric polarization.

4. A P-type transistor, characterized by The epitaxial structure includes a gate dielectric layer, a first gate, a first electrode, a second electrode and a P-type transistor as claimed in any one of claims 1-3, one of the first electrode and the second electrode is a first source electrode, and the other is a first drain electrode; The gate dielectric layer is in contact with the first P-type region, the P-type channel region and the second P-type region in the epitaxial structure, and the first gate is in contact with the gate dielectric layer; The first electrode is in contact with the first P-type region, and the second electrode is in contact with the second P-type region.

5. The P-type transistor of claim 4, wherein, A third electrode is further included, and a material of the third electrode forms an ohmic contact or a Schottky contact with a material of the P-type channel region.

6. An integrated circuit, characterized by A P-type transistor as claimed in claim 4 or 5 is included.

7. The integrated circuit of claim 6, wherein, An N-type transistor is further included, wherein a substrate of the P-type transistor and a substrate of the N-type transistor are the same substrate, the N-type transistor further includes a third P-type region which is disposed on the substrate, and the third P-type region has the same thickness, doping concentration, host material and doping elements as the first P-type region.

8. The integrated circuit of claim 7, wherein, The N-type transistor further includes a second source electrode, a second drain electrode and a second gate electrode, wherein the second gate electrode is in contact with the third P-type region, the second source electrode is in contact with the substrate, and the second drain electrode is in contact with the substrate.

9. A power management chip, characterized by, A P-type transistor as claimed in claim 4 or 5 is included.

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