A manufacturing method of a vertical structure light emitting diode

Abstract

A manufacturing method of a vertical structure light-emitting diode is disclosed, including: forming an epitaxial layer on the surface of a patterned growth substrate, the epitaxial layer including an etching stop layer, a first semiconductor layer, a multi-quantum well layer, a carrier blocking layer, and a second semiconductor layer that are sequentially stacked on the growth substrate, wherein the doping types of the first semiconductor layer and the second semiconductor layer are opposite to each other; forming a first metal bonding layer on the epitaxial layer; providing a bonding substrate, and bonding the bonding substrate and the epitaxial layer through the first metal bonding layer; stripping the growth substrate, and exposing the surface of the etching stop layer with a concavo-convex pattern; planarizing at least a part of the etching stop layer. In the present invention, an etching stop layer is added between the growth substrate and the first semiconductor layer, and the high-selectivity etching process is combined to improve the uniformity and stability of the etching process. At the same time, the crystal quality of the epitaxial layer and the stress of the epitaxial layer can be improved, and the optoelectronic parameter performance and uniformity of the epitaxial wafer can be enhanced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a vertical structure light emitting diode. Background Art

[0002] Compared with the upright and inverted structure light-emitting diodes, the vertical structure light-emitting diode has significant advantages. On the one hand, the vertical structure light-emitting diode transfers the epitaxial layer from the sapphire substrate with poor insulation and heat dissipation to the bonding substrate with excellent electrical and thermal conductivity. The light-emitting diode can withstand a higher operating current and thus obtain a higher brightness. On the other hand, the vertical structure light-emitting diode can easily perform micro-nano processing on the surface of the N-type semiconductor layer, which is thicker than the P-type semiconductor layer, thereby reducing the total reflection of the interface between the N-type semiconductor layer and the air to increase the light extraction efficiency of the light-emitting diode, which is of great help in improving the brightness and light efficiency.

[0003] At present, there are generally three types of surface micro-nano processing technology solutions for vertical structure light-emitting diodes: the first is to use alkaline hot solution to perform wet etching to process the surface of the N-type semiconductor layer, so that the surface of the N-type semiconductor layer forms a pyramid-shaped protrusion structure with a characteristic size ranging from hundreds of nanometers to several microns, thereby improving the problem of low light extraction efficiency of vertical structure light-emitting diodes caused by total reflection effect; the second is to use high-precision lithography technology to prepare a photonic crystal structure with a scale precisely related to the emission wavelength on the surface of the N-type semiconductor layer to improve the light extraction efficiency, but there will be a certain size difference between the pattern designed by theoretical calculation and the pattern obtained after etching, which makes this solution difficult to be adopted on a large scale; the third is to use a PSS substrate to grow an epitaxial layer, which can not only improve the quality of the epitaxial crystal, but also the PSS pattern can be transferred to the surface of the N-type semiconductor layer after peeling, and then combined with chemical wet roughening to form a secondary roughening effect, a better light extraction effect can be obtained.

[0004] After the PSS pattern is transferred to the surface of the peeled N-type semiconductor layer, it is necessary to completely remove the semiconductor layer in the dicing channel area, which will face new process challenges brought about by the height difference of the PSS transferred pattern. The main reasons for this problem are as follows: First, there is a thickness difference in the epitaxial layer. There will be a height difference of about 0.3 - 0.5 um between the epitaxial layers at the center and edge of the wafer. Second, since the height of the PSS pattern is about 2 um, the height difference of the semiconductor layer formed after the pattern transfer after peeling will also be in the range of 1.5 um - 2.0 um. Currently, the methods to solve the above problems are to use the SiO2 / GaN low etching selectivity etching technology and the dry etching endpoint detection technology. In the SiO2 / GaN low etching selectivity etching technology, it is necessary to form a SiO2 dielectric layer between the semiconductor layer and the bonding metal layer, and at the same time, combine dry etching and wet etching to remove the semiconductor layer in the dicing channel area. Since the silicon oxide (SiO2) layer has good resistance to dry etching and wet corrosion, the etching and corrosion selectivity is improved, which can reduce the etching planarization non-uniformity caused by the height difference of the PSS pattern and the thickness difference of the epitaxial layer itself to a certain extent. However, the etching selectivity between GaN and SiO2 is generally in the range of 3:1 - 4:1, while the PSS height difference is in the range of 1.5 um - 2.0 um. At the same time, to ensure that the SiO2 layer has enough etching process window, a relatively thick SiO2 layer needs to be prepared. The too thick SiO2 layer will also bring new process challenges and heat dissipation problems of the light-emitting diode. Further, if wet etching is used, it is easy to cause the risk of lateral over-etching to the light-emitting area or the metal layer, and the process control requirements are also extremely strict. The dry etching endpoint detection technology is to use an endpoint detection module to monitor the semiconductor layer interface, and distinguish the etching interruption and etching process parameters according to the monitoring results. However, the height difference of the PSS pattern is 1.5 um - 2.0 um, and the feature size is only a few micrometers. The different monitoring positions and the limitation of the control ability make the monitoring results often unsatisfactory; or use an etching component spectral analysis module to monitor the etching depth, but its price is expensive, increasing the fixed cost investment. Finally, due to the large difference in the lattice constants between the nitride material and the sapphire substrate, as the size of the epitaxial wafer increases, the wafer warpage also increases, bringing new technical challenges to processes such as lithography, wafer bonding, and epitaxial layer transfer. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a manufacturing method for a vertical structure light-emitting diode, adding an etching barrier layer between the growth substrate and the first semiconductor layer, and combining the Al2O3 / GaN extremely high selectivity etching process to reduce the etching process uniformity problem, and at the same time, can improve the crystal quality and stress of the epitaxial layer, and improve the optoelectronic parameter performance and uniformity of the epitaxial wafer.

[0006] The present invention provides a manufacturing method for a vertical structure light-emitting diode, including:

[0007] An epitaxial layer is formed on the surface of a patterned growth substrate, and the epitaxial layer includes an etching stop layer, a first semiconductor layer, a multi-quantum well layer, a carrier blocking layer, and a second semiconductor layer that are sequentially stacked on the growth substrate. Among them, the doping types of the first semiconductor layer and the second semiconductor layer are opposite to each other;

[0008] A first metal bonding layer is formed on the epitaxial layer;

[0009] A bonding substrate is provided, and the bonding substrate is bonded to the epitaxial layer through the first metal bonding layer;

[0010] The growth substrate is peeled off, and the surface of the etching stop layer with a concavo-convex pattern is exposed;

[0011] At least a part of the etching stop layer is planarized.

[0012] Preferably, the etching stop layer is Al x Ga 1-x N / GaN superlattice material layer.

[0013] Preferably, the Al x Ga 1-x composition of the N layer in the etching stop layer is fixed, or in the direction from the growth substrate to the first semiconductor layer, the Al x Ga 1-x composition of the N layer in the etching stop layer gradually changes from high to low, and the range x of the Al composition is 0.01 to 0.2.

[0014] Preferably, the range of the number of Al x Ga 1-x N / GaN stack pairs in the etching stop layer is 10 to 30.

[0015] Preferably, the single-layer thickness of the Al x Ga 1-x N / GaN superlattice material layer is 2 nm to 5 nm.

[0016] Preferably, the epitaxial layer further includes a buffer layer on the growth substrate and an unintentionally doped layer on the buffer layer, and the etching stop layer, the first semiconductor layer, the multi-quantum well layer, the carrier blocking layer, and the second semiconductor layer are sequentially stacked on the unintentionally doped layer.

[0017] Preferably, the method of peeling off the growth substrate and exposing the surface of the etching stop layer with a concavo-convex pattern includes:

[0018] The growth substrate is removed by using a substrate transfer technique to expose the surface of the unintentionally doped layer with a concavo-convex pattern;

[0019] Using a dry etching process, the unintentionally doped layer is etched to the surface of the etch stop layer, and the uneven pattern on the surface of the unintentionally doped layer is transferred to the surface of the etch stop layer.

[0020] Preferably, before forming the first metal bonding layer on the epitaxial layer, it further includes: sequentially forming a second ohmic contact layer and a mirror layer on the second semiconductor layer.

[0021] Preferably, planarizing at least a part of the etch stop layer includes: using dry etching to planarize at least the etch stop layer in the dicing lane area.

[0022] Preferably, planarizing at least a part of the etch stop layer includes: using dry etching to planarize the entire etch stop layer.

[0023] Preferably, the etching gas includes a main etching gas and an auxiliary etching gas. The main etching gas includes a Cl-based gas, and the auxiliary etching gas includes at least one of an O-based etching gas and an F-based etching gas.

[0024] Preferably, the proportion of the auxiliary etching gas in the total etching gas is 10% - 50%.

[0025] Preferably, after planarizing at least a part of the etch stop layer, it further includes:

[0026] Roughening the surface of the etch stop layer to form a light extraction structure.

[0027] Preferably, after planarizing at least a part of the etch stop layer, it further includes:

[0028] Performing dry etching on the planarized etch stop layer to expose the surface of the first semiconductor layer;

[0029] Roughening the surface of the first semiconductor layer to form a light extraction structure.

[0030] Preferably, the characteristic size of the light extraction structure is 300 nm - 3 μm.

[0031] Preferably, after forming the epitaxial layer, it further includes:

[0032] Forming an isolation groove penetrating from the mirror layer to the unintentionally doped layer, and forming an insulating layer in the isolation groove, and the insulating layer extends from the unintentionally doped layer into the mirror layer;

[0033] Before forming the light extraction structure, it further includes: removing the insulating layer to form a step structure around the epitaxial layer.

[0034] Preferably, before forming the light extraction structure, it further includes:

[0035] In the scribing lane region, the first semiconductor layer, the multiple quantum well layer, the carrier blocking layer, the second semiconductor layer, the second ohmic contact layer, and the mirror layer are sequentially etched to expose the surface of the first metal bonding layer, so as to form a stepped structure around the epitaxial layer. The surface of the first semiconductor layer is the upper stepped surface of the stepped structure, and the surface of the first metal bonding layer is the lower stepped surface of the stepped structure.

[0036] Preferably, after forming the light extraction structure, it further includes:

[0037] Forming a first electrode on the surface of the first semiconductor layer;

[0038] Forming a protective layer on the surface of the first semiconductor layer, the sidewalls of the stepped structure, and the surface of the first metal bonding layer, and the protective layer exposes the first electrode;

[0039] Forming a second electrode on the surface of the bonding substrate away from the epitaxial layer.

[0040] Preferably, before sequentially forming the second ohmic contact layer and the mirror layer on the second semiconductor layer, it further includes:

[0041] Etching the second semiconductor layer, the carrier blocking layer, and the multiple quantum well layer to form a plurality of contact through holes distributed in an array, and the bottom of the contact through hole exposes the surface of the first semiconductor layer;

[0042] Forming a first ohmic contact layer on the surface of the first semiconductor layer at the bottom of the contact through hole;

[0043] Forming a dielectric layer on the sidewalls of the contact through holes, the sidewalls of the second ohmic contact layer, and the surface and sidewalls of the mirror layer, and exposing the first ohmic contact layer;

[0044] Forming the first metal bonding layer on the surface of the dielectric layer, and the first metal bonding layer contacts the first ohmic contact layer and fills the contact through hole.

[0045] Preferably, before forming the light extraction structure, it further includes:

[0046] In the scribing lane region, dry-etching the epitaxial layer and the second ohmic contact layer to expose the surface of the mirror layer, so as to form a stepped structure around the epitaxial layer. The upper stepped surface of the stepped structure is the surface of the etching stop layer, and the lower stepped surface of the stepped structure is the surface of the mirror layer;

[0047] After forming the light extraction structure, it further includes: forming a second electrode on the mirror layer on the lower surface of the step structure;

[0048] forming a protective layer on the upper step surface and the side wall of the step structure;

[0049] forming a first electrode on the surface of the bonding substrate away from the epitaxial layer.

[0050] Preferably, before bonding the bonding substrate and the epitaxial layer through the first metal bonding layer, it further includes:

[0051] forming a second metal bonding layer on the bonding substrate, and bonding the bonding substrate and the epitaxial layer through the second metal bonding layer and the first metal bonding layer.

[0052] Preferably, it further includes: in the dicing lane area, cutting the bonding substrate by using a wafer cutting technology to form a single vertical structure light emitting diode.

[0053] In the manufacturing method of the vertical structure light emitting diode provided by the present invention, an etching stop layer is added between the growth substrate and the first semiconductor layer, and in combination with a highly selective etching process, the patterned epitaxial layer is etched to achieve planarization of the dicing lane area of the patterned epitaxial layer with a large height difference, eliminating the influence of non-uniform dry etching caused by the thickness difference of the epitaxial layer and the height difference of the epitaxial layer pattern.

[0054] Furthermore, the manufacturing method of the vertical structure light emitting diode provided by the present invention improves the uniformity and stability of the dry etching process. At the same time, growing the epitaxial layer on the patterned growth substrate can improve the crystal quality and stress of the epitaxial layer, reduce the warpage degree, and improve the optoelectronic parameter performance and uniformity of the epitaxial wafer.

[0055] In a preferred embodiment, the dicing lane area is etched with a high selectivity ratio by using the etching stop layer, achieving a good planarization etching effect in the dicing lane area and significantly improving the yield problem of the vertical chip process.

[0056] Furthermore, the manufacturing method of the vertical structure light emitting diode provided by the present invention can achieve low-cost large-scale production through structural design and process optimization under existing equipment conditions. The method is simple and has great significance for industrial implementation. Description of the Drawings

[0057] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0058] Figure 1Shows a schematic structural diagram of a vertical - structure light - emitting diode according to the first embodiment of the present invention;

[0059] Figures 2a to 2l Respectively show cross - sectional schematic diagrams of a vertical - structure light - emitting diode at various stages during the manufacturing process according to the first embodiment of the present invention;

[0060] Figure 3 Shows a schematic structural diagram of a vertical - structure light - emitting diode according to the second embodiment of the present invention;

[0061] Figures 4a to 4j Respectively show cross - sectional schematic diagrams of a vertical - structure light - emitting diode at various stages during the manufacturing process according to the second embodiment of the present invention. Detailed implementation manners

[0062] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well - known parts may not be shown.

[0063] The present invention can be presented in various forms, and some examples will be described below.

[0064] Figure 1 Shows a schematic structural diagram of a vertical - structure light - emitting diode according to the first embodiment of the present invention. In this embodiment, the vertical - structure light - emitting diode is an anti - polarity vertical - structure light - emitting diode. As Figure 1 shown, the anti - polarity vertical - structure light - emitting diode includes: a bonding substrate 200, a second electrode 108, a metal bonding layer 106, a mirror layer 104, a second ohmic contact layer 103, an epitaxial layer 101, and a first electrode 109.

[0065] The second electrode 108 is located on the first surface of the bonding substrate 200; the metal bonding layer 106 is located on the second surface of the bonding substrate 200, and the mirror layer 104 is located on the metal bonding layer 106; the metal bonding layer 106 includes a first metal bonding layer 1061 and a second metal bonding layer 1062, and the first metal bonding layer 1061 and the second metal bonding layer 1062 are stacked in sequence between the mirror layer 104 and the bonding substrate 200. The second ohmic contact layer 103 is located on the mirror layer 104; the epitaxial layer 101 is located on the second ohmic contact layer 103; the first electrode 109 is located on the epitaxial layer 101, specifically on the surface of the epitaxial layer 101 having a light extraction structure.

[0066] Among them, the epitaxial layer 101 includes a second semiconductor layer 17, a carrier blocking layer 16, a multi-quantum well layer 15, and a first semiconductor layer 14 that are sequentially stacked on the surface of the second ohmic contact layer 103. A light extraction structure is formed on the surface of the first semiconductor layer 14, so as to improve the light extraction efficiency of the vertical structure light-emitting diode. The light extraction structure is a concave-convex structure, and the concave-convex structure is a rough light-emitting surface with a feature size ranging from several hundred nanometers to several micrometers. In a specific embodiment, the feature size of the light extraction structure is, for example, 300 nm to 3 μm.

[0067] Furthermore, the vertical structure light-emitting diode further includes a step structure and a protective layer 105. The periphery of the light-emitting diode has a step structure. The step structure penetrates through the first semiconductor layer 14, the multi-quantum well layer 15, the carrier blocking layer 16, the second semiconductor layer 17, the second ohmic contact layer 103, and the mirror layer 104 and exposes the surface of a part of the first metal bonding layer 1061. The surface of the epitaxial layer 101 (the surface of the first semiconductor layer 14) serves as the upper step surface of the step structure, and the surface of the first metal bonding layer 1061 serves as the lower step surface of the step structure; the protective layer 105 is located on the surface and side walls of the step structure and exposes the first electrode 109.

[0068] Figures 2a to 2k Cross-sectional schematic views of each stage in the manufacturing process of the vertical structure light-emitting diode according to the first embodiment of the present invention are respectively shown. In this embodiment, the vertical structure light-emitting diode is an inverse-polarity vertical structure light-emitting diode. The following combines Figures 2a to 2k to introduce the manufacturing method of the vertical structure light-emitting diode of the first embodiment of the present application.

[0069] As Figure 2a shown, an epitaxial layer is formed on the surface of the patterned growth substrate.

[0070] In this step, first, the growth of the epitaxial layer is completed on the patterned hetero-substrate. This hetero-substrate is a growth substrate and serves as the substrate for the growth of the epitaxial layer. This step specifically includes: providing a patterned growth substrate 100, that is, the surface of the substrate has a concave-convex pattern; sequentially growing a buffer layer 11, an unintentionally doped layer 12, an etch stop layer 13, a first semiconductor layer 14, a multi-quantum well layer 15, a carrier blocking layer 16, and a second semiconductor layer 17 on the surface of the growth substrate 100.

[0071] Specifically, a micron-scale patterned sapphire substrate with a feature size of 3 μm, namely the growth substrate 100, is provided. Then, an epitaxial layer 101 is prepared thereon by an epitaxial growth method, and the total thickness of the epitaxial layer 101 is controlled within 5 μm to 10 μm. The epitaxial layer 101 includes a buffer layer 11, an unintentionally doped layer 12, an etch stop layer 13, a first semiconductor layer 14 (such as n-GaN), a multi-quantum well layer 15, a carrier blocking layer 16 (such as p-AlGaN), and a second semiconductor layer 17 (such as p-GaN) formed in sequence on the surface of the growth substrate 100. Further, the multi-quantum well layer 15 is a GaN / InGaN material, corresponding to a wavelength range of 360 nm to 600 nm.

[0072] The epitaxial growth method can be metal organic chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The epitaxial layer 101 includes one of the reciprocating continuous progressive epitaxial structures composed of a GaN / InGaN material system, and its preferred embodiment is an InGaN structure with different In components.

[0073] The patterned growth substrate 100 has uneven patterns, and the uneven patterns on the growth substrate 100 can be prepared by lithography using bulk materials, single or multiple dielectric materials. The feature size range is several micrometers to hundreds of micrometers, and the pattern array mode is one of linear or curved strip, quadrilateral, and triangular arrangements. The material of the growth substrate 100 includes single crystal substrates such as Ga2O3, SiC, sapphire, ZnO, and LiGaO2. Further, a pre-deposited AlN film can be formed on the surface of the growth substrate 100. The thickness of the growth substrate 100 is 300 μm to 2 mm.

[0074] Since the growth substrate 100 has uneven patterns, the epitaxial layer 101 grown thereon will be conformal with the growth substrate 100. For example, uneven patterns corresponding to the uneven patterns on the growth substrate 100 will be formed on the surfaces of the buffer layer 11 and the unintentionally doped layer 12 facing the growth substrate 100.

[0075] The etch stop layer 13 is an Al x Ga 1-x N / GaN superlattice material layer. The Al x Ga 1-x content in the N layer of the N / GaN superlattice material layer is fixed, or in the direction from the growth substrate 100 to the first semiconductor layer 14, the Al x Gacontent in the N layer of the superlattice material layer gradually changes from high to low to effectively block the dislocations extending from the buffer layer 11. The Al 1-x x Ga 1-x content in the N layer of the superlattice material layer gradually changes from high to low to effectively block the dislocations extending from the buffer layer 11. The Al xGa 1-x The range of the Al component x in the AlGaN layer is 0.01 to 0.2. Further, Al in the etching stop layer 13 x Ga 1-x The number of AlGaN / GaN stack pairs ranges from 10 to 30, and Al x Ga 1-x The single-layer thickness of the AlGaN / GaN superlattice material layer is 2 nm to 5 nm.

[0076] Further, an insulating layer 18 is formed. Continuing to refer to Figure 2a , an insulating layer 18 penetrating the epitaxial layer 101 is formed in the scribing lane region. For example, the epitaxial layer 101 is etched using photolithography and etching techniques to form isolation grooves, and the insulating layer 18 is formed in the isolation grooves using chemical vapor deposition techniques. The region surrounded by the insulating layer 18 forms a MESA mesa unit region (step structure). The plurality of insulating layers 18 divide the epitaxial layer 101 into multiple units, and each unit subsequently forms a single vertical structure light-emitting diode. The insulating layer 18 extends from the unintentionally doped layer 12 into the second semiconductor layer 17.

[0077] In this embodiment, the insulating layer 18 is provided. In other embodiments, the insulating layer 18 can also be omitted. During the subsequent removal of the insulating layer 18, the epitaxial layer 101 and the subsequently formed second ohmic contact layer 103 and mirror layer 104 are directly etched to form a step structure, and this embodiment does not limit this.

[0078] As Figure 2b shown, a second ohmic contact layer, a mirror layer, and a metal bonding layer are sequentially formed on the surface of the epitaxial layer to form an epitaxial wafer.

[0079] The second ohmic contact layer 103 and the mirror layer 104 are sequentially prepared on the second semiconductor layer 17 using photolithography and physical vapor deposition techniques, and an insulating layer 18 is formed in the second ohmic contact layer 103 and the mirror layer 104, that is, the insulating layer 18 extends from the unintentionally doped layer 12 into the mirror layer 104. In other embodiments, the insulating layer 18 can also be formed at one time after the formation of the epitaxial layer 101, the second ohmic contact layer 103, and the mirror layer 104.

[0080] The material of the second ohmic contact layer 103 is, for example, ITO, and the thickness is, for example, 10 nm; the material of the mirror layer 104 is, for example, AgTiWTi, and the thickness is, for example, 200 nm, but is not limited thereto. Then, a first metal bonding layer 1061 is prepared on the surface of the mirror layer 104 by PVD (physical vapor deposition) method. The first metal bonding layer 1061 is, for example, TiPtAuSn. The obtained semiconductor structure is an epitaxial wafer 10, which is used for subsequent bonding with a bonding substrate.

[0081] As shown Figure 2c in the figure, a bonding substrate is provided, and a metal bonding layer is formed on the surface of the bonding substrate.

[0082] A bonding substrate 200 is provided, and a second metal bonding layer 1062 made of the same material as the first metal bonding layer 1061 is prepared thereon by PVD method. The bonding substrate 200 is, for example, a silicon substrate with a thickness of 800 um.

[0083] As shown Figure 2d in the figure, the bonding substrate is bonded to the epitaxial wafer through the metal bonding layer.

[0084] In this step, using the wafer bonding process, for example, at 300 °C and a pressure of 3000 kgf, the epitaxial wafer 10 and the bonding substrate 200 are bonded together. Specifically, the first metal bonding layer 1061 and the second metal bonding layer 1062 are bonded to each other, so that the bonding substrate 200 is bonded to the epitaxial wafer 10.

[0085] In this embodiment, the bonding substrate 200 is, for example, one of Si, Cu, Mo, W, CuW, CuMo, and AlSi substrates, and the thickness of the bonding substrate 200 is 100 um to 1 um. The metal bonding layer 106 is one of a binary eutectic bonding metal composed of high melting point metals such as Au, Ni, Cu, and Ag and low melting point metals such as Sn and In, or a structure formed by direct Au - Au metal bonding. A adhesion layer (not shown in the figure) can be formed separately before forming the first metal bonding layer 1061 and the second metal bonding layer 1062. The adhesion layer is, for example, Ti.

[0086] As shown Figure 2e in the figure, the growth substrate is peeled off to expose the surface of the epitaxial layer with the concave - convex pattern.

[0087] In this step, the substrate transfer technology is mainly used to remove the growth substrate 100, exposing the surface of the epitaxial layer 101 with the concave - convex pattern. In this embodiment, while removing the growth substrate 100, the buffer layer 11 is also decomposed and removed synchronously, and the surface of the unintentionally doped layer 12 is exposed. The surface of the unintentionally doped layer 12 has a concave - convex pattern.

[0088] The substrate transfer technology is, for example, one or a combination of processes such as laser lift - off, chemical wet etching, and electrochemical etching.

[0089] Specifically, a DPSS laser is used to provide a small, circular positive light spot with a Gaussian energy distribution (spot diameter is about 20 μm). The patterned sapphire substrate (growth substrate 100) and the epitaxial layer 101 are separated by means of spiral or linear scanning and peeling, exposing the surface of the unintentionally doped layer 12 with a concavo-convex pattern. Since the thickness of the buffer layer 11 is relatively thin, the shape of the unintentionally doped layer 12 is conformal to that of the buffer layer 11. After the buffer layer 11 is decomposed, the concavo-convex pattern on the surface of the unintentionally doped layer 12 is exposed; or it can be understood that the concavo-convex pattern on the sapphire substrate (buffer layer 11) is transferred to the unintentionally doped layer 12, and the concavo-convex pattern corresponds to the concavo-convex pattern on the patterned growth substrate 100.

[0090] As Figure 2f shown, using the dry etching process parameters with physical etching characteristics, the unintentionally doped layer 12 is etched to the surface of the etch stop layer 13. Due to the physical etching characteristics, the concavo-convex pattern on the surface of the unintentionally doped layer 12 is transferred to the surface of the etch stop layer 13. That is, the exposed surface of the current epitaxial layer 101 is the surface of the etch stop layer 13, and the surface of the etch stop layer 13 has a concavo-convex pattern.

[0091] As Figure 2g shown, the dry etching is continued to etch the etch stop layer 13 to planarize the etch stop layer 13.

[0092] In this step, for example, the etch stop layer 13 is etched by dry etching. The etching gas includes a main etching gas and an auxiliary etching gas. The main etching gas includes a Cl-based gas, such as Cl2, SiCl4, BCl3, and the auxiliary etching gas includes at least one of an O-based etching gas and an F-based etching gas. Among them, the auxiliary etching gas accounts for 10-50% of the total etching gas.

[0093] In this embodiment, the etching gas is, for example, chlorine gas (Cl2) and oxygen gas (O2). O2 in the etching gas reacts with Al in the etch stop layer 13 (Al x Ga 1-x N / GaN superlattice) to form an Al2O3 film, achieving a highly selective etching effect and planarizing the concavo-convex pattern on the surface of the etch stop layer 13. In this embodiment, the etching gas is set in a ratio of Cl2:O2 = 3:1.

[0094] As Figure 2h shown, the etch stop layer 13 is removed, exposing the surface of the first semiconductor layer 14.

[0095] In this step, for example, dry etching is used to continue etching the planarized etch stop layer 13 to remove the etch stop layer 13 to expose the first semiconductor layer 14. In this embodiment, the etching gas is, for example, boron trichloride gas (BCl3) and chlorine gas (Cl2).

[0096] In this embodiment, since the etch stop layer 13 is planarized in the above step, the first semiconductor layer 14 obtained in this step also has a flat surface.

[0097] As Figure 2i shown, the insulating layer is removed.

[0098] In this step, for example, a mask layer is formed on the surface of the first semiconductor layer 14. The mask layer is, for example, a photoresist layer with an opening. The insulating layer 18 is etched through the mask layer to remove the insulating layer 18 to expose the first metal bonding layer 1061 below the insulating layer 18. After removing the insulating layer 18, a step structure is formed around the periphery of the vertical structure light-emitting diode unit. The step structure penetrates through the first semiconductor layer 14, the multiple quantum well layer 15, the carrier blocking layer 16, the second semiconductor layer 17, the second ohmic contact layer 103, and the mirror layer 104 and exposes a part of the surface of the first metal bonding layer 1061. The surface of the epitaxial layer 101 (the surface of the first semiconductor layer 14) serves as the upper step surface of the step structure, and the surface of the first metal bonding layer 1061 serves as the lower step surface of the step structure. Adjacent vertical structure light-emitting diode units are separated, and individual vertical structure light-emitting diodes are formed subsequently.

[0099] Since the surfaces of the insulating layer 18 and the first semiconductor layer 14 have been planarized in the above step, the influence of the concave and convex pattern on the etching uniformity of the insulating layer 18 in the dicing channel region is eliminated, the planarized etching effect in the dicing channel region is achieved, and the vertical chip process yield problem is significantly improved.

[0100] As Figure 2j shown, a light extraction structure is formed on the surface of the first semiconductor layer 14.

[0101] In this step, for example, wet etching is used to roughen the surface of the first semiconductor layer 14 to obtain a rough light-emitting surface with a feature size ranging from several hundred nanometers to several micrometers, that is, the light extraction structure. In a specific embodiment, the feature size of the light extraction structure is, for example, 300 nm to 3 μm. Specifically, the entire wafer is placed in a heated KOH solution to roughen the surface of the first semiconductor layer 14.

[0102] As Figure 2k shown, a first electrode is formed.

[0103] In this step, for example, lithography and physical vapor deposition techniques are used to fabricate a first electrode 109 with a thickness of 800 nm on the first semiconductor layer 14. The first electrode 109 is an N electrode.

[0104] Such as Figure 2l , a protective layer and a second electrode are formed.

[0105] In this step, a SiO2 dielectric film with a thickness of 200 nm is fabricated as the protective layer 105 on the surface of the first semiconductor layer 14 (the upper step surface of the step structure) and the sidewalls and bottom wall of the step structure (the surface of the first metal bonding layer 1061) by using the CVD process. Then, the bonding substrate 200 is thinned (for example, thinned to 180 microns) by using a thinning device, and a second electrode 108 is fabricated on its surface away from the epitaxial layer 101. The second electrode 108 is made of, for example, TiPtAu material, and the second electrode 108 is a P electrode.

[0106] Furthermore, the vertical structure light-emitting diode is cut by using the wafer dicing technique.

[0107] Continue to refer to Figure 2l , as shown by the dashed line, the wafer dicing technique is used to separately cut the second electrode 108 and the bonding substrate 200 in the scribe lane area to complete chip scribing, and finally the reverse-polarity vertical structure light-emitting diode as shown in Figure 1 is obtained. The wafer dicing technique is one of water-guided laser, laser scribing or grinding wheel tool processing methods, and the cutting scheme is one of single-sided cutting or double-sided cutting.

[0108] Figure 3 shows a schematic structural diagram of the vertical structure light-emitting diode according to the second embodiment of the present invention. In this embodiment, the structure of the vertical structure light-emitting diode is the structure of a positive-polarity vertical structure light-emitting diode. As Figure 3 shown, the positive-polarity vertical structure light-emitting diode includes a bonding substrate 400, a first electrode 309, a metal bonding layer 306, a mirror layer 304, a first ohmic contact layer 302, a second ohmic contact layer 303, an epitaxial layer 301, a second electrode 308, a dielectric layer 305, and a protective layer 307.

[0109] The first electrode 309 is located on the first surface of the bonding substrate 400; the metal bonding layer 306 is located on the second surface of the bonding substrate 400, and the mirror layer 304 is located on the side of the metal bonding layer 306 away from the bonding substrate 400; the second ohmic contact layer 303 is located on the mirror layer 304; the epitaxial layer 301 is located on the second ohmic contact layer 303; the second electrode 308 is located on the surface of the mirror layer 304. The metal bonding layer 306 includes a first metal bonding layer 3061 and a second metal bonding layer 3062.

[0110] Among them, the epitaxial layer 301 includes a second semiconductor layer 37, a carrier blocking layer 36, a multi-quantum well layer 35, a first semiconductor layer 34, and an etching stop layer 33 that are sequentially stacked on the surface of the second ohmic contact layer 303. A light extraction structure is formed on the surface of the etching stop layer 33, which improves the light extraction efficiency of the vertical structure light-emitting diode. In this embodiment, the light extraction structure is formed on the surface of the etching stop layer 33 and is an uneven structure, and the characteristic size of the uneven structure is from several hundred nanometers to several micrometers. In a specific embodiment, the characteristic size of the light extraction structure is, for example, 300 nm to 3 μm. In this embodiment, the etching stop layer 33 is retained, and the light extraction structure is formed on the surface of the etching stop layer 33. In other embodiments, the etching stop layer 33 can also be removed, and the light extraction structure can also be formed on the surface of the first semiconductor layer 34.

[0111] The vertical structure light-emitting diode has a plurality of contact vias uniformly distributed in an array. The contact vias penetrate through the mirror layer 304, the second ohmic contact layer 303, and a part of the epitaxial layer 301 (the second semiconductor layer 37, the carrier blocking layer 36, the multi-quantum well layer 35) and expose the surface of the first semiconductor layer 34. The first ohmic contact layer 302 is located on the first semiconductor layer 34 at the bottom of the contact via. The dielectric layer 305 is located on the surface of the mirror layer 304 and the sidewalls of the contact vias, exposing the surface of the first ohmic contact layer 302. The first metal bonding layer 3061 is located on the surface of the dielectric layer 305 and fills the contact via, contacting the first ohmic contact layer 302, that is, the dielectric layer 305 separates the first metal bonding layer 3061 from the epitaxial layer 101, the second ohmic contact layer 303, and the mirror layer 304. The second bonding layer 3602 is located between the first bonding layer 3601 and the bonding substrate 400.

[0112] The periphery of the vertical structure light-emitting diode has a specific step structure. The step structure penetrates through the etching stop layer 33, the first semiconductor layer 34, the multi-quantum well layer 35, the carrier blocking layer 36, the second semiconductor layer 37, and the second ohmic contact layer 303 and exposes a part of the surface of the mirror layer 304. The surface of the epitaxial layer 301 (the surface of the etching stop layer 33) serves as the upper step surface of the step structure, and the surface of the mirror layer 304 serves as the lower step surface of the step structure. The protective layer 307 is located on the surface of the etching stop layer 33 (the upper step surface of the step structure) and the sidewalls of the step structure. The second electrode 308 is located on the mirror layer 304 of the lower step surface.

[0113] Figures 4a to 4j Cross-sectional schematic diagrams of each stage in the manufacturing process of the vertical structure light-emitting diode according to the second embodiment of the present invention are respectively shown. The vertical structure light-emitting diode of this embodiment is a positive-polarity vertical structure light-emitting diode.

[0114] As Figure 4aAs shown, an epitaxial layer is formed on the surface of the patterned growth substrate.

[0115] A sapphire substrate is provided, and patterned SiO2 (with a feature size of 2 μm) is formed on the sapphire substrate to form a growth substrate 300 with a concavo-convex pattern. The epitaxial layer 301 is prepared by an epitaxial growth method.

[0116] The total thickness of the epitaxial layer 301 is controlled to be 5 μm to 10 μm; the epitaxial layer 301 includes a buffer layer 31, an unintentionally doped layer 32, an etch stop layer 33, a first semiconductor layer 34 (such as n-GaN), a multi-quantum well layer 35, a carrier blocking layer 36 (such as p-AlGaN), and a second semiconductor layer 37 (such as p-GaN) formed in sequence on the surface of the growth substrate 300. The epitaxial growth method can be metal organic chemical vapor deposition, laser-assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy. The epitaxial layer 301 includes one of the reciprocating continuous progressive epitaxial structures composed of the GaN / InGaN material system, and its preferred solution is the InGaN structure with different In components.

[0117] The etch stop layer 33 is an Al x Ga 1-x N / GaN superlattice material layer. Al x Ga 1-x In the Al x Ga 1-x N layer of the N / GaN superlattice material layer, the Al component is fixed, or in the direction from the growth substrate 100 to the first semiconductor layer 14, the Al x Ga 1-x component in the N layer of the N / GaN superlattice material layer gradually changes from high to low to effectively block the dislocations extending from the buffer layer 11. The Al x Ga 1-x component range x of the N layer in the N / GaN superlattice material layer is 0.01 to 0.2. Further, the number of Al x Ga 1-x N / GaN stack pairs in the etch stop layer 33 ranges from 10 to 30, and the single layer thickness of the Al x Ga 1-x N / GaN superlattice material layer is 2 nm to 5 nm.

[0118] Further, contact vias 38 with an array distribution are defined on the epitaxial layer 301 by using photolithography and dry etching techniques. The contact vias 38 penetrate through the second semiconductor layer 37, the carrier blocking layer 36, and the multi-quantum well layer 35, exposing the surface of the first semiconductor layer 34. Further, a first ohmic contact layer 302 is formed on the surface of the first semiconductor layer 34 exposed by the contact vias 38 by using photolithography and physical vapor deposition techniques. The material of the first ohmic contact layer 302 is, for example, Al / Ti / Pt / Au, and the thickness is, for example, 800 nm.

[0119] As Figure 4b shown, a second ohmic contact layer, a mirror layer, and a dielectric layer are sequentially formed on the surface of the epitaxial layer.

[0120] In this step, a second ohmic contact layer 303 and a mirror layer 304 are prepared on the second semiconductor layer 37 by using photolithography, wet etching, and sputtering processes. The material of the second ohmic contact layer 303 is, for example, ITO, and the thickness is, for example, 100 nm. The material of the mirror layer 304 is, for example, AgTiWTiPtTi, and the thickness is, for example, 800 nm. Subsequently, a dielectric layer 305 is prepared on the surface of the mirror layer 304 by using CVD process. The dielectric layer 305 also fills the contact vias 38. The material of the dielectric layer 305 is, for example, an insulating material such as SiO2, and the thickness is, for example, 1 um. Then, an opening is prepared in the dielectric layer 305 by using photolithography and dry etching techniques. The opening exposes the surface of the first ohmic contact layer 302, that is, the dielectric layer 305 covers the surface of the mirror layer 304 and the sidewalls of the contact vias 38, and exposes the surface of the first ohmic contact layer 302.

[0121] In this embodiment, the first ohmic contact layer 302 is formed first, and then the dielectric layer 305 is formed. In other embodiments, the dielectric layer 305 may also be formed first, and then the first ohmic contact layer 302 is formed. This embodiment does not limit this.

[0122] As Figure 4c shown, a metal bonding layer is formed on the dielectric layer to form an epitaxial wafer.

[0123] Specifically, a first metal bonding layer 3061 is prepared on the surface of the dielectric layer 305 by using PVD method. The first metal bonding layer 3061 is, for example, a NiSn binary metal. A Ti adhesion layer (not shown in the figure) may also be prepared before preparing the first metal bonding layer 3061. The first metal bonding layer 3061 fills the opening 38 and contacts the first ohmic contact layer 302. The prepared semiconductor structure is the epitaxial wafer 20.

[0124] As Figure 4d shown, a bonding substrate is provided, and a metal bonding layer is formed on the surface of the bonding substrate.

[0125] In this step, a bonding substrate 400 is provided, and a second metal bonding layer 3062 made of the same material as the first metal bonding layer 3061 is prepared thereon by PVD method. Before preparing the second metal bonding layer 3062, an adhesion layer (not shown in the figure) can also be prepared first. The bonding substrate 400 is, for example, a CuW substrate with a thickness of 200um.

[0126] As Figure 4e shown, the bonding substrate is bonded to the epitaxial wafer through the metal bonding layer.

[0127] In this step, subsequently, an eutectic bonding process is used to bond the epitaxial wafer 20 and the bonding substrate 400 together, for example, under the conditions of 280°C and a bonding pressure of 12000 kgf. Specifically, the first metal bonding layer 3061 and the second metal bonding layer 3062 are bonded, so that the bonding substrate 400 is bonded to the epitaxial wafer 20.

[0128] As Figure 4f shown, the growth substrate is peeled off to expose the surface of the epitaxial layer with the concave-convex pattern.

[0129] In this embodiment, after the growth substrate 300 is peeled off and removed, the surface of the unintentionally doped layer 32 with the concave-convex pattern is exposed.

[0130] This step specifically includes: using a substrate transfer technique to separate the growth substrate 300 from the epitaxial layer 301, exposing the surface of the unintentionally doped layer 32 with the concave-convex pattern.

[0131] A square small spot with a flat-top energy distribution (spot side length about 200um) is provided by a 248nm KrF excimer laser, and the patterned sapphire substrate (growth substrate 300) and the epitaxial layer 301 are separated by a spiral or linear scanning peeling method, exposing the surface of the unintentionally doped layer 32 with the concave-convex pattern. Since the buffer layer 31 is very thin, the shape of the unintentionally doped layer 32 is conformal to the buffer layer 31. During substrate transfer, the buffer layer 31 is simultaneously decomposed and removed, exposing the surface of the unintentionally doped layer 32 with the concave-convex pattern, and the concave-convex pattern corresponds to the concave-convex pattern on the patterned growth substrate 300.

[0132] As Figure 4g shown, using the dry etching process parameters with physical etching characteristics, the unintentionally doped layer 32 is etched to the surface of the etch stop layer 33. Since the etching characteristic is physical etching, the concave-convex pattern on the surface of the unintentionally doped layer 32 is transferred to the surface of the etch stop layer 33. That is, the exposed surface of the current epitaxial layer 301 is the surface of the etch stop layer 33, and the surface of the etch stop layer 33 has a concave-convex pattern.

[0133] As Figure 4hAs shown, dry etching is used to etch the etch stop layer 33 in the scribing lane region.

[0134] In this step, at least the etch stop layer 33 in the scribing lane region is planarized. Specifically, for example, a mask layer is formed on the etch stop layer 33, and the mask layer has an opening that exposes the etch stop layer 33 in the scribing lane region. The mask layer is, for example, a photoresist layer. Then, the etch stop layer 33 in the scribing lane region is etched through the opening of the mask layer to planarize the etch stop layer 33 in the scribing lane region.

[0135] Specifically, for example, dry etching is used to etch the etch stop layer 33. The etching gas is, for example, chlorine gas (Cl2), oxygen gas (O2), and carbon tetrafluoride gas (CF4). O2 in the etching gas and Al in the etch stop layer 33 (Al x Ga 1-x N / GaN superlattice) form an Al2O3 film, and carbon tetrafluoride gas (CF4) and Al in the etch stop layer 33 (Al x Ga 1-x N / GaN superlattice) form AlF3, achieving a highly selective etching effect and etching the uneven pattern on the surface of the etch stop layer 33 to planarize it. In this embodiment, the etching gas is set in the ratio of Cl2:O2:CF4 = 2:1:1.

[0136] In this embodiment, a part of the etch stop layer 33 in the scribing lane region is retained. In other embodiments, the etch stop layer 33 in the scribing lane region can also be completely removed. In another embodiment, the etch stop layer 33 in the non-scribing lane region can also be planarized.

[0137] As Figure 4i shown, etching of the scribing lane region is continued to finally expose the mirror layer 304 and form a light extraction structure on the surface of the etch stop layer 33.

[0138] In this step, etching of the scribing lane region is continued through the opening of the mask layer. In this embodiment, for example, dry etching is used to etch the etch stop layer 33, the first semiconductor layer 34, the multiple quantum well layer 35, the carrier blocking layer 36, the second semiconductor layer 37, and the second ohmic contact layer 303 in the scribing lane region to expose the surface of the mirror layer 304, forming a stepped structure around the light-emitting diode. The etching gas is, for example, silicon tetrachloride gas (SiCl4) and chlorine gas (Cl2).

[0139] Since the etch stop layer 33 in the scribing lane region has been planarized in the above steps, the influence of the concave-convex pattern on the etch uniformity of the scribing lane region is eliminated, the planarized etching effect of the scribing lane region is achieved, and the vertical chip process yield problem is significantly improved.

[0140] Further, for example, wet etching is used to treat the surface of the etch stop layer 33 to obtain a rough light-emitting surface with a feature size ranging from several hundred nanometers to several micrometers, that is, a light extraction structure. In a specific embodiment, the feature size of the light extraction structure is, for example, 300 nm to 3 μm. Specifically, the entire wafer is placed in a heated KOH solution to roughen the surface of the etch stop layer 33.

[0141] As Figure 4j shown, a protective layer, a first electrode, and a second electrode are formed.

[0142] Using photolithography and physical vapor deposition techniques, a second electrode 308 is prepared on the surface of the mirror layer 304 exposed on the lower step surface. The second electrode 308 is, for example, made of CrPtAu material, and the second electrode 308 is a P electrode.

[0143] Further, a 200-nm-thick SiO2 dielectric film is prepared as the protective layer 307 on the surface of the etch stop layer 33 and the sidewalls of the step structure by using the CVD process. Then, the bonding substrate 400 is thinned by using a thinning device, and a first electrode 309 is prepared on its surface away from the epitaxial layer 301. The first electrode 309 is, for example, made of TiPtAu material, and the first electrode 309 is an N electrode.

[0144] Further, the wafer cutting technology is used to complete the cutting of the vertical structure light-emitting diode.

[0145] For example, the water-guided laser cutting process is used to scribe the first electrode 309 and the bonding substrate 400 respectively to complete the chip scribing, and finally the positive-polarity vertical structure light-emitting diode as Figure 3 shown is obtained.

[0146] In the manufacturing method of the vertical structure light-emitting diode provided by the invention, an etch stop layer is added between the growth substrate and the first semiconductor layer, and combined with a highly selective etching process, the patterned epitaxial layer is etched to achieve the planarization of the scribing lane region of the patterned epitaxial layer with a large height difference, and the influence of the thickness difference of the epitaxial layer and the height difference of the epitaxial layer pattern on the non-uniform dry etching is eliminated.

[0147] Furthermore, the manufacturing method of the vertical structure light-emitting diode provided by the present invention improves the uniformity and stability of the dry etching process. At the same time, using a patterned growth substrate to grow the epitaxial layer can improve the crystal quality and stress of the epitaxial layer, reduce the warpage degree, and improve the optoelectronic parameter performance and uniformity of the epitaxial wafer.

[0148] In a preferred embodiment, a high selectivity etching is performed on the scribing lane region using an etching stop layer, achieving a good planarization etching effect in the scribing lane region and significantly improving the yield problem of the vertical chip process.

[0149] Furthermore, the manufacturing method of the vertical structure light-emitting diode provided by the present invention can achieve low-cost large-scale production through structure design and process optimization under the existing equipment conditions. The method is simple and has great significance for industrial implementation.

[0150] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A manufacturing method of a vertical structure light-emitting diode, characterized in that, Including: Forming an epitaxial layer on the surface of a patterned growth substrate, the epitaxial layer including an etching stop layer, a first semiconductor layer, a multi-quantum well layer, a carrier blocking layer, and a second semiconductor layer that are sequentially stacked on the growth substrate, wherein the doping types of the first semiconductor layer and the second semiconductor layer are opposite to each other; Forming a first metal bonding layer on the epitaxial layer; Providing a bonding substrate and bonding the bonding substrate to the epitaxial layer through the first metal bonding layer; Removing the growth substrate and exposing the surface of the etching stop layer having a concavo-convex pattern; Planarizing at least a part of the etching stop layer; and Etching the dicing street region to form a stepped structure; Wherein, planarizing at least a part of the etching stop layer includes: planarizing at least the etching stop layer in the dicing street region.

2. The manufacturing method according to claim 1, characterized in that, The etching stop layer is Al x Ga 1-x N / GaN superlattice material layer.

3. The manufacturing method according to claim 2, characterized in that, Al in the etching stop layer x Ga 1-x The Al component of the AlGaN layer is fixed, or in the direction from the growth substrate to the first semiconductor layer, the Al component of the AlGaN layer in the etching stop layer x Ga 1- x gradually changes from high to low, and the range x of the Al component is 0.01 to 0.

2.

4. The manufacturing method according to claim 2, characterized in that, Al in the etch stop layer x Ga 1-x The number of N / GaN stack pairs ranges from 10 to 30.

5. The manufacturing method according to claim 2, characterized in that, The Al x Ga 1-x The single layer thickness of the N / GaN superlattice material layer is 2 nm to 5 nm.

6. The manufacturing method according to claim 1, characterized in that, The epitaxial layer further includes a buffer layer on the growth substrate and an unintentionally doped layer on the buffer layer, and the etching stop layer, the first semiconductor layer, the multi-quantum well layer, the carrier blocking layer, and the second semiconductor layer are sequentially stacked on the unintentionally doped layer.

7. The manufacturing method according to claim 6, characterized in that, The method of removing the growth substrate and exposing the surface of the etching stop layer having a concavo-convex pattern includes: Using a substrate transfer technique to remove the growth substrate and expose the surface of the unintentionally doped layer with a concavo-convex pattern; Using a dry etching process to etch the unintentionally doped layer to the surface of the etching stop layer, and the concavo-convex pattern on the surface of the unintentionally doped layer is transferred to the surface of the etching stop layer.

8. The manufacturing method according to claim 7, characterized in that, Before forming the first metal bonding layer on the epitaxial layer, it further includes: sequentially forming a second ohmic contact layer and a mirror layer on the second semiconductor layer.

9. The manufacturing method according to claim 8, characterized in that, Planarizing at least a part of the etching stop layer includes: using dry etching to planarize at least the etching stop layer in the dicing street region.

10. The manufacturing method according to claim 8, characterized in that, Planarizing at least a part of the etching stop layer includes: using dry etching to planarize the entire etching stop layer.

11. The manufacturing method according to claim 9 or 10, characterized in that, The etching gas includes a main etching gas and an auxiliary etching gas, the main etching gas includes a Cl-based gas, and the auxiliary etching gas includes at least one of an O-based etching gas and an F-based etching gas.

12. The manufacturing method according to claim 11, characterized in that, The proportion of the auxiliary etching gas in the total etching gas is 10% - 50%.

13. The manufacturing method according to claim 9, characterized in that, After planarizing at least a part of the etching stop layer, it further includes: Roughening the surface of the etching stop layer to form a light extraction structure.

14. The manufacturing method according to claim 10, characterized in that, After planarizing at least a part of the etching stop layer, it further includes: Performing dry etching on the planarized etching stop layer to expose the surface of the first semiconductor layer; Roughening the surface of the first semiconductor layer to form a light extraction structure.

15. The manufacturing method according to claim 13 or 14, characterized in that, The characteristic dimension of the light extraction structure is 300 nm - 3 μm.

16. The manufacturing method according to claim 14, characterized in that, After forming the epitaxial layer, it further includes: Forming an isolation groove penetrating from the mirror layer to the unintentionally doped layer, and forming an insulating layer in the isolation groove, the insulating layer extending from the unintentionally doped layer into the mirror layer; Before forming the light extraction structure, it further includes: removing the insulating layer to form a stepped structure on the periphery of the epitaxial layer.

17. The manufacturing method according to claim 14, characterized in that, Before forming the light extraction structure, it further includes: In the dicing lane region, the first semiconductor layer, the multiple quantum well layer, the carrier blocking layer, the second semiconductor layer, the second ohmic contact layer, and the mirror layer are sequentially etched to expose the surface of the first metal bonding layer, so as to form a stepped structure around the epitaxial layer. The surface of the first semiconductor layer is the upper stepped surface of the stepped structure, and the surface of the first metal bonding layer is the lower stepped surface of the stepped structure.

18. The manufacturing method according to claim 16 or 17, characterized in that, After forming the light extraction structure, it further includes: Forming a first electrode on the surface of the first semiconductor layer; Forming a protective layer on the surface of the first semiconductor layer, the sidewalls of the stepped structure, and the surface of the first metal bonding layer, and the protective layer exposes the first electrode; Forming a second electrode on the surface of the bonding substrate away from the epitaxial layer.

19. The manufacturing method according to claim 13, characterized in that, Before sequentially forming the second ohmic contact layer and the mirror layer on the second semiconductor layer, it further includes: Etching the second semiconductor layer, the carrier blocking layer, and the multiple quantum well layer to form a plurality of contact through holes distributed in an array, and the bottom of the contact through hole exposes the surface of the first semiconductor layer; Forming a first ohmic contact layer on the surface of the first semiconductor layer at the bottom of the contact through hole; Forming a dielectric layer on the sidewalls of the contact through hole, the sidewalls of the second ohmic contact layer, and the surface and sidewalls of the mirror layer, and the dielectric layer exposes the first ohmic contact layer; Forming the first metal bonding layer on the surface of the dielectric layer, and the first metal bonding layer contacts the first ohmic contact layer and fills the contact through hole.

20. The manufacturing method according to claim 19, characterized in that, Before forming the light extraction structure, it further includes: In the dicing lane region, dry-etching the epitaxial layer and the second ohmic contact layer to expose the surface of the mirror layer, so as to form a stepped structure around the epitaxial layer. The upper stepped surface of the stepped structure is the surface of the etching stop layer, and the lower stepped surface of the stepped structure is the surface of the mirror layer; After forming the light extraction structure, it further includes: forming a second electrode on the mirror layer on the lower stepped surface of the stepped structure; Forming a protective layer on the upper stepped surface and the sidewalls of the stepped structure; Forming a first electrode on the surface of the bonding substrate away from the epitaxial layer.

21. The manufacturing method according to claim 1, characterized in that, Before bonding the bonding substrate and the epitaxial layer through the first metal bonding layer, it further includes: Forming a second metal bonding layer on the bonding substrate, and the bonding substrate is bonded to the epitaxial layer through the second metal bonding layer and the first metal bonding layer.

22. The manufacturing method according to claim 1, characterized in that, It further includes: In the dicing lane region, using a wafer cutting technique to cut the bonding substrate to form individual vertical structure light-emitting diodes.

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