Dynamic range compensation method for first-order error feedback mismatch error shaping

Abstract

The present invention discloses a dynamic range compensation method suitable for first-order error feedback mismatch error shaping. The method comprises: predicting an upper plate voltage sampled at time n based on a digital output result of a SAR ADC at time n-1; setting a predicted threshold voltage, comparing the predicted threshold voltage with the voltage of the SAR ADC at time n-1, and setting a predicted compensation amount according to the comparison result to adjust the range of the upper plate voltage at time n so that the voltage falls within the signal range processed by the SAR ADC. The method has the advantages of compensating for dynamic range loss and avoiding quantization errors.

Description

Technical Field

[0001] The present invention relates to the field of digital-analog hybrid integrated circuit design, and more particularly to a dynamic range compensation method suitable for first-order error feedback mismatch error shaping. Background Art

[0002] The linearity of a SAR ADC (successive approximation analog-to-digital converter) is also known as the ADC's accuracy. Accuracy refers to the closeness between the actual digital output and the theoretically expected digital output for a given analog input, or the accuracy of the ADC's conversion result relative to the actual value. In other words, ADC accuracy determines how many bits in the digital output codeword represent useful information about the input signal. Applications such as health monitoring and wearable devices require ADC linearity greater than 10 bits. Failure to meet these requirements can lead to inaccurate test results and compromise product performance. SAR ADC linearity primarily depends on the mismatch error of the capacitor array. To improve ADC linearity, calibration techniques can be used to compensate for mismatch, but this approach increases circuit complexity and incurs significant hardware costs. Alternatively, the linearity of oversampled SAR ADCs can be improved using dynamic element matching (DEM). However, the control overhead of this approach increases exponentially with the number of bits, so a limited number of bits is recommended. Error Feedback Mismatch Error Shaping (EF MES) technology can also effectively improve the linearity of SAR ADC. It regards the weight of the high-order capacitance (MSB) as the ideal weight and only considers the relative error of the low-order capacitance (LSB) relative to the MSB. EF MES technology can be used directly in SAR ADC without adding additional circuit structures. It only needs to convert the LSB switching result at time n-1 to D LSB (n-1) is kept in the lower plate of the capacitor and participates in the sampling and conversion at time n. Therefore, the mismatch error at time n-1 is reflected in the voltage of the upper plate, which is:

[0003] D out (n) = V in (n)+E(n)-E(n-1)

[0004] Where E is the mismatch error of the LSB portion relative to the MSB portion.

[0005] Performing z-transform on the above equation yields:

[0006] D out (z)=V in (z)+(1-z -1)E(z)

[0007] The first-order shaping of the mismatch error is achieved. For example, Chinese Patent Publication No. CN111371456A discloses a second-order mismatch error shaping technology in a full dynamic range NS SAR ADC, which uses a similar method to perform the second-order shaping of the mismatch error. However, during the shaping process of the above method, since the upper plate voltage of the capacitor array is the input signal V at time n, in (n) and n-1 time LSB part switching result - D LSB The sum of (n-1) may exceed the maximum quantization range of the ADC, resulting in a 6dB dynamic range loss, which makes it easy for ADC quantization errors to occur. Summary of the Invention

[0008] The technical problem to be solved by the present invention is that the existing EF MES technology suffers from dynamic range loss, which easily causes ADC quantization errors, resulting in inaccurate detection results of health monitoring and wearable devices in practical applications.

[0009] The present invention solves the above technical problems by the following technical means: a dynamic range compensation method applicable to first-order error feedback mismatch error shaping, the method comprising:

[0010] Step a: Based on the digital output of the SAR ADC at time n-1, predict the upper plate voltage sampled at time n;

[0011] Step b: Set the predicted threshold voltage, compare the predicted threshold voltage with the voltage at time n-1 of the SAR ADC, and set the predicted compensation amount according to the comparison result to adjust the range of the upper plate voltage at time n so that it is within the signal range processed by the SAR ADC.

[0012] The present invention analyzes the possible voltage range of the upper plate at time n, sets a predicted threshold voltage, compares the predicted threshold voltage with the voltage of the SAR ADC at time n-1, and sets a predicted compensation amount based on the comparison result to adjust the range of the upper plate voltage at time n. This achieves prediction and compensation of the upper plate voltage, prevents it from exceeding the SAR ADC signal processing range, compensates for dynamic range loss, and avoids quantization errors, thereby ensuring accurate health monitoring and wearable device detection results in practical applications.

[0013] Furthermore, the SAR ADC mainly includes a capacitor array and a comparator. The input end of the comparator is respectively connected to the upper plate of each capacitor in the capacitor array, and the lower plate of each capacitor is respectively connected to the voltage source via a switching switch. The output end of the comparator outputs the comparison result. The capacitor array is divided into two parts, one part is the low-order capacitor part, and the other part is the high-order capacitor part.

[0014] Furthermore, the step a includes:

[0015] The quantization result D of SAR ADC at time n-1 is out (n-1) is the input signal V at time n in (n) approximate value, according to the formula V TOP (n) = V in (n)+D LSB (n-1), predict the range of the plate voltage on the capacitor array at time n, where V TOP (n) is the voltage on the upper plate of the capacitor array at time n, D LSB (n-1) is the switching result of the low-order capacitor part.

[0016] Furthermore, the step b includes:

[0017] When V in (n-1)>V th1 Time D pre =1, then V in (n)>0.18;

[0018] When V th0 <V in (n-1)<V th1 Time D pre =0, then 0.073<V in (n)<0.927;

[0019] When V in (n-1)<V th0 Time D pre =-1, at this time, V in (n)<0.82;

[0020] Among them, V th0 is the first predicted threshold voltage, V th1 is the second predicted threshold voltage, D pre is the predicted compensation amount.

[0021] Furthermore, the first prediction threshold voltage V th0 =0.45, the second predicted threshold voltage V th1 =0.55.

[0022] Furthermore, the step b further includes:

[0023] For the input signal V in There is V in (n) = sin(2πnf in / f s ), considering the frequency range and complexity supported by the circuit, take (fin ) max ≈0.06f s , where f in is the input signal frequency, f s is the sampling frequency, (f in ) max is the maximum frequency of the input signal.

[0024] Furthermore, the method further comprises step c:

[0025] The upper plate of the capacitor array is connected to the input signal V by the gate voltage bootstrap switch. in (n) is sampled, and the lower plate of the capacitor of the low-bit capacitor part keeps the conversion result of time n-1 unchanged. When the conversion result D(n-1) of the corresponding bit is 1, the lower plate keeps the first reference voltage V refn When the conversion result D(n-1) of the corresponding bit is 0, the lower plate is kept at the second reference voltage V refp The high-order capacitor part is divided into 8 equal minimum unit capacitors, and the lower plates of six of the minimum unit capacitors are randomly selected to maintain the common mode voltage V cm remains unchanged, while the other two are compensated according to the predicted amount D pre Make changes if D pre = +1, then the lower plate and the second reference voltage V refp Connected; if D pre =-1, then the lower plate and the first reference voltage V refn connected.

[0026] Furthermore, the relationship between the common mode voltage and the second reference voltage is V cm =0.5V refp .

[0027] Furthermore, the method further comprises step d:

[0028] The upper plates of all capacitors in the capacitor array are disconnected from the input signal, and the lower plate voltage is switched to V cm , reset the upper plate voltage.

[0029] Furthermore, the method further comprises step e:

[0030] The upper plate voltage of the capacitor array is quantized by FLASH ADC and SAR ADC. After the FLASH ADC obtains the 8-bit thermometer code output, it is converted into binary output by the decoder and the tir-level switching scheme is used to simultaneously control the switching of the lower plate reference voltage of the first 3 bits of the capacitor array. The SAR conversion of the remaining capacitors in the capacitor array uses V cm-based switching scheme, and obtains 12.2-bit output in turn.

[0031] The advantages of the present invention are as follows: the present invention analyzes the possible voltage range of the upper plate at time n, sets a predicted threshold voltage, compares the predicted threshold voltage with the voltage of the SAR ADC at time n-1, sets a predicted compensation amount according to the comparison result, adjusts the range of the upper plate voltage at time n, realizes prediction and compensation of the upper plate voltage, prevents it from exceeding the SAR ADC signal processing range, compensates for dynamic range loss, and avoids quantization errors, thereby ensuring accurate health monitoring and wearable device detection results in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of a dynamic range compensation method for first-order error feedback mismatch error shaping disclosed in an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the possible range of the upper plate voltage of the capacitor array in the dynamic range compensation method for first-order error feedback mismatch error shaping disclosed in an embodiment of the present invention;

[0034] Figure 3 The performance comparison of the first-order error feedback mismatch error shaping method before and after using the dynamic range compensation method of the present invention is shown in FIG. Figure 3 (a) is a diagram showing the simulation results of the signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) at different input signal amplitudes when the method of the present invention is not used. Figure 3 (b) is a diagram showing the SNR and SFDR simulation results at different input signal amplitudes when using the method of the present invention;

[0035] Figure 4 is the variation of SNR and SFDR with input signal frequency fin before and after the first-order error feedback mismatch error shaping predicted by the present invention under full dynamic range, where: Figure 4 (a) shows the variation of SNR with input signal frequency fin before and after the first-order error feedback mismatch error shaping predicted by the present invention under full dynamic range. Figure 4 (b) shows the change of SFDR with input signal frequency fin before and after the first-order error feedback mismatch error shaping predicted by the present invention under full dynamic range. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] like Figure 1 As shown, the present invention provides a dynamic range compensation method applicable to first-order error feedback mismatch error shaping, the method comprising:

[0038] Data prediction stage: Figure 1 A single-ended architecture diagram of a 12-bit SAR ADC to which the compensation method of the present invention is applied is given. The SAR ADC mainly includes a capacitor array and a comparator. The input end of the comparator is respectively connected to the upper plate of each capacitor in the capacitor array, and the lower plate of each capacitor is respectively connected to the voltage source through a switching switch. The output end of the comparator outputs the comparison result, wherein the capacitor array is divided into two parts, one part is a low-order capacitor part, and the other part is a high-order capacitor part. According to the digital output result of the SAR ADC at time n-1, the upper plate voltage of the capacitor array sampled at time n is predicted; a predicted threshold voltage is set, and the predicted threshold voltage is compared with the voltage at time n-1 of the flexible piezoresistive pressure sensor or other analog device collected by the SAR ADC, and the range of the upper plate voltage at time n is adjusted according to the comparison result, so that it is within the signal range processed by the SAR ADC. The specific process is:

[0039] When the conversion at time n-1 is completed, the quantization result D out (n-1) as V in (n) is an approximate value, and the range of the plate voltage on the capacitor array at time n is predicted. Figure 2 As shown, the quantization range of SAR ADC is [0, 1]. in When the voltage range of (n) is [0.927, 1], the SAR ADC may be overloaded, V TOP The possible range of (n) is [0.854, 1.073], and the predicted compensation amount D pre = +1 to ensure the normal operation of SAR ADC, the voltage value corresponding to 1 is 0.106; when V in When the voltage range of (n) is [0.82-0.927], V TOP The possible range of (n) is [0.747-1], and the predicted compensation amount that satisfies the normal operation of SAR ADC is D pre = +1 / 0; when Vin When the voltage range of (n) is [0.18-0.82], V TOP The possible range of (n) is [0.107-0.893], and the predicted compensation amount that satisfies the normal operation of SAR ADC is D pre =+1 / 0 / -1; when V in When the voltage range of (n) is [0.073-0.18], V TOP The possible range of (n) is [0-0.253], and the predicted compensation amount that satisfies the normal operation of SAR ADC is D pre =0 / -1; when V in When the voltage range of (n) is [0-0.073], the SAR ADC may be overloaded, V TOP The possible range of (n) is [-0.073-0.146], and the predicted compensation amount D pre =-1 to ensure the normal operation of SAR ADC.

[0040] Therefore, in order for the SAR ADC to work properly, the threshold V th0 and V th1 Should satisfy: When V in (n-1)>V th1 Time D pre =1, then V in (n)>0.18; when V th0 <V in (n-1)<V th1 Time D pre =0, then 0.073<V in (n)<0.927; when V in (n-1)<V th0 Time D pre =-1, at this time, V in (n)<0.82. And for the input signal V in There is V in (n) = sin(2πnf in / f s ), considering the frequency range and complexity of the predicted circuit, V th0 =0.45 and V th1 =0.55, (f in ) max ≈0.06f s .

[0041] Sampling phase: The upper plate of the capacitor array is connected to the input signal V through the gate voltage bootstrap switch in(n) is sampled, and the lower plate of the capacitor of the low-bit capacitor part keeps the conversion result of time n-1 unchanged. When the conversion result D(n-1) of the corresponding bit is 1, the lower plate keeps the first reference voltage V refn When the conversion result D(n-1) of the corresponding bit is 0, the lower plate is kept at the second reference voltage V refp The high-order capacitor part is divided into 8 equal minimum unit capacitors, and the lower plates of six of the minimum unit capacitors are randomly selected to maintain the common mode voltage V cm remains unchanged, while the other two are compensated according to the predicted amount D pre Make changes if D pre = +1, then the lower plate and the second reference voltage V refp Connected; if D pre =-1, then the lower plate and the first reference voltage V refn In this embodiment, V refn =0, V refp =1.8V, V cm =0.9V.

[0042] Reset phase: The upper plates of all capacitors in the capacitor array are disconnected from the input signal, and the lower plate voltages are switched to V cm , reset the upper plate voltage.

[0043] Conversion stage: The upper plate voltage of the capacitor array is quantized by FLASH ADC and SAR ADC. After the FLASH ADC obtains the 8-bit thermometer code output, it is converted into binary output by the decoder and the tir-level switching scheme is used to simultaneously control the switching of the lower plate reference voltage of the first 3 bits of the capacitor array. The SAR conversion of the remaining capacitors in the capacitor array uses V cm -based switching scheme, and obtain 12.2-bit output in turn. cmThe -based switching scheme adopts the scheme recorded in the literature Zhu Y, Chan CH, Chio UF, et al. A 10-bit 100-MS / s reference-free SAR ADC in 90nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2010, 45(6): 1111-1121. The tir-level switching scheme adopts the scheme recorded in Shu YS, Kuo LT, Lo T Y. An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR Over 1kHzBW in 55nm CMOS.

[0044] The following simulation analysis verifies the effectiveness of the present invention. Figure 1 The oversampling SAR ADC proposed in [1] is modeled. The capacitance of the MSB (high capacitance) part is taken as an ideal value, the standard deviation of the capacitance mismatch of the LSB (low capacitance) part is taken as 1%, and the oversampling ratio (OSR) is 8. 200 Monte Carlo simulations are performed for different capacitance mismatch errors. Figure 3 To compare the performance of the first-order EF MES SAR ADC before and after using the present invention, we take f in =101f s / 4096. It can be seen from the figure that when the amplitude of the input signal is less than -1.4dB, whether or not the digital prediction technology proposed in the present invention is used has no effect on the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR). When the amplitude of the input signal is greater than -1.4dB, not using the digital prediction technology will cause the SAR ADC to be overloaded, and the SFDR and SNR will drop rapidly; and the dynamic scheme compensation scheme proposed in the present invention can support input signals with a full dynamic range. This shows that the present invention can solve the dynamic range loss problem caused by it without affecting the first-order EFMES shaping capability. The present invention adopts an 8-fold oversampling rate, so the bandwidth BW = f_s / (2*8)≈0.06f_s. Appendix Figure 4 Figure 3 shows the variation of SNR and SFDR with input signal frequency f_in before and after the first-order EF MES predicted by the present invention under the full dynamic range. The figure shows that the dynamic range compensation scheme proposed in the present invention is well suited for an 8x oversampling SAR ADC using a first-order EF MES. The oversampling SAR ADC using the dynamic range compensation scheme proposed in the present invention improves SNR by approximately 5 dB and SFDR by approximately 12 dB.

[0045] In summary, the first-order EF MES dynamic range compensation technology proposed in this invention can be used to compensate for the dynamic range of out (n-1) for a simple comparison, the dynamic range loss problem caused by the first-order EF MES technology is eliminated without sacrificing the shaping effect.

[0046] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A dynamic range compensation method suitable for first-order error feedback mismatch error shaping, characterized in that: The method comprises: Step a: predicting the upper plate voltage sampled at time n based on the digital output result of the SAR ADC at time n-1; the ADC includes a capacitor array and a comparator, the input end of the comparator is respectively connected to the upper plate of each capacitor in the capacitor array, the lower plate of each capacitor is respectively connected to the voltage source through a switch, and the output end of the comparator outputs the comparison result, wherein the capacitor array is divided into two parts, one part is a low-order capacitor part, and the other part is a high-order capacitor part; the quantization result of the SAR ADC at time n-1 is As the input signal at time n The approximate value of , predict the range of the plate voltage on the capacitor array at time n, where is the upper plate voltage of the capacitor array at time n, is the switching result of the low-position capacitor part; Step b: Set the predicted threshold voltage, compare the predicted threshold voltage with the voltage at time n-1 of the SAR ADC, and set the predicted compensation amount according to the comparison result to adjust the range of the upper plate voltage at time n so that it is within the signal range processed by the SAR ADC.

2. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 1, characterized in that: The step b comprises: when hour ,at this time ; when hour ,at this time ; when hour ,at this time, ; in, is the first predicted threshold voltage, is the second predicted threshold voltage, is the predicted compensation amount.

3. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 2, characterized in that: The first predicted threshold voltage , the second predicted threshold voltage .

4. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 3, characterized in that: The step b further comprises: For input signal have , considering the frequency range and complexity supported by the circuit, take ,in, is the input signal frequency, is the sampling frequency, is the maximum frequency of the input signal.

5. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 3, characterized in that: Also includes step c: The upper plate of the capacitor array switches the input signal through the gate voltage bootstrap switch Sampling is performed, and the lower plate of the capacitor of the low-bit capacitor part keeps the conversion result at time n-1 unchanged. When the conversion result of the corresponding bit When the lower plate maintains the first reference voltage Connected; when the conversion result of the corresponding bit When the lower plate maintains the second reference voltage The high-order capacitor part is divided into 8 equal minimum unit capacitors, and the lower plates of six of the minimum unit capacitors are randomly selected to maintain the common mode voltage. remains unchanged, while the other two are compensated according to the predicted amount Make changes if , then the lower plate and the second reference voltage connected; if , then the lower plate and the first reference voltage connected.

6. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 5, characterized in that: The relationship between the common mode voltage and the second reference voltage is: .

7. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 5, characterized in that: Also includes step d: The upper plates of all capacitors in the capacitor array are disconnected from the input signal, and the voltage of the lower plates is switched to , reset the upper plate voltage.

8. The dynamic range compensation method for first-order error feedback mismatch error shaping according to claim 7, characterized in that: Also includes step e: The upper plate voltage of the capacitor array is quantized by FLASH ADC and SAR ADC. After the FLASH ADC obtains the 8-bit thermometer code output, it is converted into binary output by the decoder and the tir-level switching scheme is used to simultaneously control the switching of the lower plate reference voltage of the first 3 bits of the capacitor array. The remaining SAR conversion is used. Switching schemes, 12.2-bit output is obtained in turn.

Images