Solid-state imaging device and imaging device

Abstract

A solid-state imaging device (200) is provided with: a plurality of photoelectric conversion elements (311); a plurality of current-voltage conversion circuits (320); a plurality of address event detection circuits (231); a first ground line (424); and a second ground line (421). The plurality of photoelectric conversion elements (311) are arranged side by side in a first region. The plurality of current-voltage conversion circuits (320) respectively convert currents output from the plurality of photoelectric conversion elements (311) into voltages. The address event detection circuit (231) detects a change in the voltage output from the current-voltage conversion circuit (320). The first ground wiring (424) is provided in a second region located outside the first region, and supplies a first ground potential to the photoelectric conversion element (311). The second ground wiring (421) is provided in the second region, and supplies a second ground potential having a voltage value different from that of the first ground potential to the current-voltage conversion circuit (320).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a solid-state imaging device and an imaging device. BACKGROUND

[0002] Recently, an asynchronous solid-state imaging device has been proposed in which an address event detection circuit that detects an address event in which the amount of light of a pixel exceeds a threshold value for each pixel address in real time is provided for each pixel (for example, refer to Patent Literature 1).

[0003] Further, in an asynchronous solid-state imaging device, a solid-state imaging device that supplies a predetermined potential lower than a reference potential to the anode of a photodiode and the back gate of an amplification transistor has been proposed (for example, refer to Patent Literature 2).

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Unexamined Patent Publication No. 2016-533140

[0007] Patent Literature 2: Japanese Patent Application Laid-Open No. 2019-195135 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] However, the above-described conventional technique does not disclose a more specific supply method of how to supply a predetermined potential having a value different from that of a reference potential to the anode of a photodiode, and there is a room for examination as to the method of supplying a predetermined potential.

[0010] Therefore, the present disclosure provides a solid-state imaging device and an imaging device that are capable of supplying a predetermined potential having a value different from that of a reference potential to a photodiode.

[0011] SOLUTION TO PROBLEM

[0012] According to the present disclosure, a solid-state imaging device is provided. The solid-state imaging device is provided with a plurality of photoelectric conversion elements, a plurality of current-voltage conversion circuits, a plurality of address event detection circuits, a first ground wiring, and a second ground wiring. The plurality of photoelectric conversion elements are arranged side by side in a first region. The plurality of current-voltage conversion circuits respectively convert a current output from the plurality of photoelectric conversion elements into a voltage. The plurality of address event detection circuits respectively detect a change in the voltage output from the plurality of current-voltage conversion circuits. The first ground wiring is provided in a second region outside the first region and supplies a first ground potential to the plurality of photoelectric conversion elements. The second ground wiring is provided in the second region and supplies a second ground potential having a voltage value different from that of the first ground potential to the plurality of current-voltage conversion circuits. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a configuration example of an imaging apparatus according to an embodiment of the present disclosure.

[0014] Figure 2 This is a view used to illustrate the stacked structure of a solid-state imaging element according to an embodiment of the present invention.

[0015] Figure 3 This is a view showing a planar configuration of a light-receiving substrate according to an embodiment of the present disclosure.

[0016] Figure 4 This is a view used to illustrate the planar configuration of a circuit board according to an embodiment of the present disclosure.

[0017] Figure 5 This is a diagram illustrating the configuration of effective pixels according to an embodiment of the present invention.

[0018] Figure 6 This is a view showing the circuit configuration of effective pixels according to an embodiment of the present disclosure.

[0019] Figure 7 This is a diagram illustrating another circuit configuration of a current-to-voltage conversion circuit according to an embodiment of the present disclosure.

[0020] Figure 8 This is a view showing a first grounding potential and a second grounding potential according to an embodiment of the present disclosure.

[0021] Figure 9 This is a view showing the layout configuration of an optical receiving unit according to an embodiment of the present disclosure.

[0022] Figure 10 This is a view showing the layout configuration of an optical receiving circuit according to an embodiment of the present disclosure.

[0023] Figure 11 It is along Figure 9 The cross-sectional view of the optical receiving unit taken by line A-A' in the figure.

[0024] Figure 12 This is a view showing a cross-sectional configuration of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0025] Figure 13 This is a view showing a planar configuration of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0026] Figure 14 This is a view showing a configuration example of an optical receiving circuit according to a first variation of an embodiment of the present disclosure.

[0027] Figure 15 FIG. 1 is a view showing a planar configuration of a solid-state imaging device according to an embodiment of the present disclosure.

[0028] Figure 16 FIG. 2 is a view showing an example of a light-receiving circuit according to a first modification of the embodiment of the present disclosure.

[0029] Figure 17 FIG. 3 is a view showing a planar configuration of a solid-state imaging device according to the first modification of the embodiment of the present disclosure.

[0030] Figure 18 FIG. 4 is a view showing a circuit configuration of an effective pixel according to a second modification of the embodiment of the present disclosure.

[0031] Figure 19 FIG. 5 is a block diagram showing a configuration example of an address event detection unit according to a fourth modification of the embodiment of the present disclosure.

[0032] Figure 20 FIG. 6 is a block diagram showing a configuration example of an imaging device in an imaging system according to a fifth modification of the embodiment of the present disclosure.

[0033] Figure 21 FIG. 7 is a schematic view showing an example of a configuration of a distance measurement system according to the embodiment of the present disclosure.

[0034] Figure 22 FIG. 8 is a block diagram showing an example of a circuit configuration according to the embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same function are denoted with the same reference numerals, and description thereof will not be repeated.

[0036] Further, in this specification and the drawings, the following cases are present: similar parts in different embodiments are distinguished from each other by different alphabets assigned after the same reference numerals. However, in a case where it is not necessary to particularly distinguish similar parts, only the same reference sign is assigned.

[0037] Further, the drawings referred to in the following description are drawings for illustrating embodiments of the present disclosure and for facilitating the understanding thereof, and the shapes, sizes, ratios, and the like in the drawings can be different from the actual ones for the sake of clarity. Further, the solid-state imaging element and the solid-state imaging device shown in the drawings can be appropriately changed in design in consideration of the following description and the known technology. Further, in the description using the cross-sectional view of the solid-state imaging element, the vertical direction of the stacked structure of the solid-state imaging element corresponds to the relative direction in the case where the incident surface on which light is incident on the solid-state imaging element is on the bottom, and this can be different from the vertical direction according to the actual acceleration of gravity.

[0038] Also, in the following description of the circuit configuration, unless otherwise specified, "electrically connected" means connecting a plurality of elements so as to conduct electricity. Further, in the following description, "electrically connected" includes not only the case where a plurality of elements are directly and electrically connected, but also the case where a plurality of elements are indirectly and electrically connected via another element.

[0039] Further, in the following description, "gate" refers to the gate electrode of a field effect transistor (FET). "Drain" refers to the drain or drain electrode of the FET, and "source" refers to the source or source electrode of the FET.

[0040] Further, in the following description, the description of a specific length (numerical value) and shape does not merely mean the same value as a mathematically defined numerical value or a geometrically defined shape. In detail, the description of a specific length (numerical value) and shape in the following description includes a case where there is an allowable difference (error / distortion) in the imaging device, the manufacturing steps thereof, and the use / operation thereof, and a shape similar to the shape.

[0041] Note that the description is made in the following order.

[0042] 1. Introduction

[0043] 2. Configuration example of imaging device

[0044] 3. Configuration example of solid-state imaging device

[0045] 4. Configuration example of effective pixel

[0046] 5. Configuration example of light-receiving unit

[0047] 5.1. Regarding layout configuration of light-receiving unit

[0048] 5.2. Regarding cross-sectional configuration of light-receiving unit

[0049] 6. Detailed configuration of solid-state imaging device

[0050] 7. First modification example

[0051] 8. Second modification example

[0052] 9. Third modification

[0053] 10. Fourth modification

[0054] 11. Fifth modification

[0055] 12. Application examples

[0056] 13. Conclusion

[0057] 1. Introduction

[0058] Conventionally, a synchronous solid-state imaging element that images image data (frame) in synchronization with a synchronization signal such as a vertical synchronization signal is used in an imaging device or the like. With this general synchronous solid-state imaging element, image data can be acquired only at each cycle of the synchronization signal (for example, 1 / 60 seconds), making it difficult to cope with cases where higher speed processing is required in fields relating to traffic, robots, and the like.

[0059] Therefore, an asynchronous solid-state imaging element has been proposed in which an address event detection circuit that detects in real time that the light amount of a pixel exceeds a threshold value for each pixel address as an address event is provided for each pixel. In this solid-state imaging element, a photodiode and a plurality of transistors for detecting an address event are arranged for each pixel.

[0060] However, in the above-described conventional technology, when the reverse bias of the photodiode decreases due to voltage fluctuation such as a decrease in the power supply potential or an increase in the ground voltage, the sensitivity of the photodiode can deteriorate. Therefore, there is a problem that the signal quality deteriorates due to the lack of sensitivity. When the area of the photodiode is increased, the sensitivity can be improved, but the number of pixels per unit area undesirably decreases. Furthermore, the sensitivity can also be improved by sufficiently increasing the power supply potential, but this undesirably increases the power consumption. That is, in the above-described conventional technology, it is difficult to improve the quality of the signal output from the effective pixels.

[0061] Therefore, it is desirable to achieve a technology that can overcome the above-described problems and improve the signal quality output from the effective pixels.

[0062] 2. Configuration example of imaging device

[0063] First, with reference to Figure 1 The configuration of the imaging device 100 according to the embodiment is described. Figure 1 is a block diagram illustrating a configuration example of the imaging device 100 according to the embodiment of the present disclosure.

[0064] The imaging device 100 according to the embodiment is provided with an imaging lens 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. As the imaging device 100, a camera mounted on a wearable device, a vehicle-mounted camera, or the like is assumed.

[0065] The imaging lens 110, which is an example of an optical system, captures incident light from an object to form an image on an imaging surface of the solid-state imaging device 200.

[0066] The solid-state imaging device 200, also called a DVS (Dynamic Vision Sensor), detects, for each of a plurality of pixels, an absolute value of a change in luminance exceeding a threshold value as an address event. The address event includes, for example, an ON event indicating an increase in luminance amount exceeding an upper threshold value and an OFF event indicating a decrease in luminance amount falling below a lower threshold value lower than the upper threshold value.

[0067] Then, the solid-state imaging device 200 generates a detection signal representing a detection result of the address event of each pixel. Each detection signal includes an ON event detection signal V CH (refer to Figure 6 ) indicating the presence or absence of the ON event and an OFF event detection signal V CL (refer to Figure 6 ) indicating the presence or absence of the OFF event.

[0068] The solid-state imaging device 200 performs predetermined signal processing (such as image recognition processing) on image data including the detection signal and outputs the processed data to the recording unit 120 via a signal line 209.

[0069] The recording unit 120 records data from the solid-state imaging device 200. The control unit 130 controls the solid-state imaging device 200 and allows such a solid-state imaging device 200 to image image data.

[0070] 3. Configuration Example of Solid-state Imaging Device

[0071] Next, with reference to Figures 2 to 10 , a configuration of the solid-state imaging device 200 according to the embodiment is described. Figure 2 is a view showing a stacked structure of the solid-state imaging device 200 according to the embodiment of the present disclosure.

[0072] The solid-state imaging device 200 according to the embodiment is provided with a circuit board 202 and a light-receiving substrate 201 stacked on the circuit board 202. The light-receiving substrate 201 and the circuit board 202 are electrically connected to each other via connection such as a via, a Cu-Cu joint, or a bump.

[0073] Figure 3is a diagram showing a planar configuration of a light-receiving substrate 201 according to an embodiment of the present disclosure. As shown in Figure 3 The light-receiving substrate 201 includes a light-receiving unit 210, a via arrangement unit 221, and a via arrangement unit 222.

[0074] In the light-receiving unit 210, a plurality of light-receiving circuits 211 are arranged in a two-dimensional lattice pattern. Such light-receiving circuits 211 photoelectrically convert incident light to generate a photoelectric current, and convert the photoelectric current into a voltage to output a voltage signal. A pixel address including a row address and a column address is assigned to each light-receiving circuit 211.

[0075] A via connected to a circuit board 202 (refer to Figure 4 ) is arranged in the via arrangement unit 221 and the via arrangement unit 222.

[0076] Figure 4 is a diagram for showing a planar configuration of the circuit board 202 according to an embodiment of the present disclosure. As shown in Figure 4 The circuit board 202 includes an address event detection unit 230, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, a via arrangement unit 261, and a via arrangement unit 262.

[0077] In the address event detection unit 230, a plurality of address event detection circuits 231 are arranged in a two-dimensional lattice pattern. The address event detection circuits 231 quantize voltage signals from the light-receiving circuits 211 and output such quantized voltage signals as detection signals.

[0078] Each address event detection circuit 231 to which a pixel address is assigned is electrically connected to a light-receiving circuit 211 having the same address. Further, in an embodiment, in a plan view, the light-receiving circuit 211 and the address event detection circuit 231 having the same address are arranged at the same position.

[0079] The signal processing circuit 240 performs predetermined signal processing on the detection signals from the address event detection unit 230. For example, the signal processing circuit 240 arranges such detection signals as pixel signals in a two-dimensional lattice pattern, and acquires image data having 2-bit information for each pixel. Then, the signal processing circuit 240 performs signal processing such as image recognition processing on the acquired image data.

[0080] The row drive circuit 251 selects a row address and allows the address event detection unit 230 to output a detection signal corresponding to the selected row address. The column drive circuit 252 selects a column address and allows the address event detection unit 230 to output a detection signal corresponding to the selected column address. A via connected to the light-receiving substrate 201 (refer to Figure 3The via of the effective pixel 310 is arranged in the via arrangement unit 261 and the via arrangement unit 262.

[0081]

[0082] Figure 5 A diagram for illustrating a configuration of the effective pixel 310 according to an embodiment of the present application is shown. As shown in Figure 5 each effective pixel 310 includes the light-receiving circuit 211 in the light-receiving substrate 201 and the address event detection circuit 231 in the circuit board 202 to which the same pixel address is assigned.

[0083] As described above, on the light-receiving substrate 201 and the circuit board 202, the plurality of light-receiving circuits 211 and the plurality of address event detection circuits 231 are respectively arranged in a two-dimensional lattice manner. Further, in a plan view, the light-receiving circuit 211 and the address event detection circuit 231 having the same address are arranged at the same position.

[0084] That is, in the solid-state imaging device 200 according to the embodiment, the effective pixel 310 including a pair of the light-receiving circuit 211 and the address event detection circuit 231 is arranged in a two-dimensional lattice manner. Then, the light-receiving circuit 211 and the address event detection circuit 231 are electrically connected to each other via a connection such as a via, a Cu-Cu joint, or a bump at the joint 203.

[0085] Figure 6 is a view showing a circuit configuration of the effective pixel 310 according to an embodiment of the present disclosure. As shown in Figure 6 the effective pixel 310 is provided with a photodiode 311, a current-voltage conversion circuit 320, a buffer 330, a subtracter 340, a quantizer 350, and a transmission circuit 360.

[0086] (effective pixel)

[0087] In the unit of such an effective pixel 310, in the light-receiving circuit 211, the LG transistor 321 (an example of a first transistor) and the amplification transistor 322 (an example of a second transistor) including the photodiode 311 and the current-voltage conversion circuit 320 are included in the unit of the effective pixel 310 in the embodiment of the present disclosure. Further, in the unit of the effective pixel 310, the buffer 330, the subtracter 340, the quantizer 350, and the transmission circuit 360 are included in the address event detection circuit 231.

[0088] That is, in the embodiment of the present disclosure, the effective pixel 310 includes the photodiode 311, the current-voltage conversion circuit 320, and the address event detection circuit 231.

[0089] ​The photodiode 311 photoelectrically converts incident light to generate a photoelectric current. Then, the photodiode 311 supplies the generated photoelectric current to the current-voltage conversion circuit 320.

[0090] The current-voltage conversion circuit 320 converts the photoelectric current from the photodiode 311 into a voltage signal of a logarithm thereof. Then, the current-voltage conversion circuit 320 supplies the converted voltage signal to the buffer 330.

[0091] The buffer 330 corrects the voltage signal transmitted from the current-voltage conversion circuit 320 and outputs the corrected signal to the subtracter 340. In the active pixel 310 according to the embodiment, it is possible to increase a driving force for driving a subsequent stage and to secure isolation of noise accompanying a switching operation of the subsequent stage by such a buffer 330.

[0092] The subtracter 340 obtains an amount of change of the corrected signal transmitted from the buffer 330 by a subtraction process. Then, the subtracter 340 supplies the obtained amount of change as a difference signal to the quantizer 350.

[0093] The quantizer 350 converts (i.e., quantizes) the analog difference signal into a digital detection signal by comparing the difference signal with a predetermined threshold value. The quantizer 350 according to the present embodiment compares the difference signal with each of an upper threshold value and a lower threshold value and supplies a comparison result as a 2-bit detection signal to the transmission circuit 360.

[0094] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 according to a column drive signal from the column drive circuit 252.

[0095] The specific circuit configuration of each unit is described below.

[0096] (Photodiode)

[0097] The cathode of the photodiode 311 is connected to the source of the LG transistor 321 of the current-voltage conversion circuit 320 described later. Further, the anode of the photodiode 311 is connected to a terminal of the first ground potential V NEG . In this way, the first ground potential V NEG is supplied to the photodiode 311. In addition, the first ground potential V NEG is described later.

[0098] (Current-voltage conversion circuit)

[0099] The current-to-voltage conversion circuit 320 includes an LG transistor 321, an amplifying transistor 322, and a constant current circuit 323. For example, N-type MOS (metal-oxide-semiconductor) transistors are used as the LG transistor 321 and the amplifying transistor 322. Furthermore, for example, a load MOS transistor such as a P-type MOS transistor is used as the constant current circuit 323.

[0100] The source and drain of LG transistor 321 are connected to the cathode of photodiode 311 and the power supply potential VDD terminal, respectively. The anode of photodiode 311 is connected to the ground potential terminal. Constant current circuit 323 and amplifying transistor 322 are connected in series in this order to the power supply potential VDD terminal and the second ground potential VDD terminal. SS Between the terminals. Note that the second ground potential V is described later. SS .

[0101] The connection point between the constant current circuit 323 and the amplifying transistor 322 is connected to the gate of the LG transistor 321 and the input terminal of the buffer 330. The connection point between the LG transistor 321 and the photodiode 311 is connected to the gate of the amplifying transistor 322. A predetermined bias voltage V... blog The current is applied to the gate of the constant current circuit 323.

[0102] Then, LG transistor 321 converts the photocurrent generated by photodiode 311 into a voltage between the gate and the source, and amplification transistor 322 amplifies the voltage between the gate at the potential corresponding to the photocurrent and the source at the ground potential, and outputs it from the drain.

[0103] In addition, the constant current circuit 323 is based on the bias voltage V blog A constant current is supplied to the amplifying transistor 322. With this structure, the current-to-voltage conversion circuit 320 converts the photocurrent from the photodiode 311 into a voltage signal.

[0104] In this way, the current-to-voltage conversion circuit 320 is a so-called source follower current-to-voltage conversion circuit equipped with an amplifying transistor 322, a constant current circuit 323, and a constant current circuit 323.

[0105] It should be noted that in the solid-state imaging device 200 according to the embodiment, the photodiode 311, the LG transistor 321 and the amplifying transistor 322 are arranged on the light receiving substrate 201, and the circuit following the constant current circuit 323 is arranged on the circuit board 202.

[0106] Here, refer to Figure 7 Describe another configuration example of the current-to-voltage conversion circuit 320. Figure 7 This is a view showing another circuit configuration of the current-to-voltage conversion circuit 320 according to an embodiment of the present disclosure. (See diagram below.)Figure 7 As shown, the current-voltage conversion circuit 320 can also be a so-called gain-boosted current-voltage conversion circuit provided with two LG transistors 321 and 324, two amplification transistors 322 and 325, and a constant current circuit 323.

[0107] In the case of gain-boosting, as Figure 7 shown, the source of the LG transistor 321 and the gate of the amplification transistor 322 are connected to, for example, the cathode of the photodiode 311. Further, the drain of the LG transistor 321 is connected to, for example, the source of the LG transistor 324 (an example of a third transistor) and the gate of the amplification transistor 325. The drain of the LG transistor 324 is connected to, for example, a terminal of the power supply potential VDD.

[0108] Further, for example, the source of the amplification transistor 325 (an example of a fourth transistor) is connected to the gate of the LG transistor 321 and the drain of the amplification transistor 322. For example, the drain of the amplification transistor 325 is connected to a terminal of the power supply potential VDD via the constant current circuit 323.

[0109] By having the current-voltage conversion circuit 320 have a connection relationship as Figure 6 or Figure 7 shown, a ring source follower circuit is formed. Thus, the photocurrent from the photodiode 311 is converted into a logarithmic voltage signal according to the amount of its charge. Note that each of the LG transistor 324 and the amplification transistor 325 can include, for example, an N-type MOS transistor.

[0110] (V NEG and V SS )

[0111] Next, the above-described first ground potential V NEG and the second ground potential V SS are described with reference to Figure 8 . Figure 8 is a view showing the first ground potential V NEG and the second ground potential V SS according to the embodiment of the present disclosure.

[0112] As described above, the first ground potential V NEG is applied to the anode of the photodiode 311, and the second ground potential V SS is applied to the source of the amplification transistor 322 of the current-voltage conversion circuit 320 (refer to Figure 6 ). The voltage value of the first ground potential V NEG is set to, for example, a negative bias voltage so as to be smaller than the voltage value of the second ground potential V SS . The voltage value of the second ground potential V SSthe voltage value of the first ground potential V NEG is set to, for example, approximately "-1 V".

[0113] In this way, by applying the first ground potential V NEG to the anode of the photodiode 311, the potential gradient of the photodiode 311 can increase, as Figure 8 indicated. Note that, in Figure 8 , the photodiode 311 is denoted by PD, and the LG transistor 321 is denoted by LGT. As Figure 8 indicated, as the potential gradient of the photodiode 311 increases, the electric charges (the "e-" in Figure 8 ) generated in the photodiode 311 easily transfer to the LG transistor 321. Thus, the sensitivity of the photodiode 311 can be improved, and the quality of the signal output from the effective pixel can be improved.

[0114] (buffer)

[0115] will be described again with reference to Figure 6 . The buffer 330 includes a P-type transistor 331 and a P-type transistor 332. As the P-type transistor 331 and the P-type transistor 332, MOS transistors are used, for example.

[0116] The P-type transistor 331 and the P-type transistor 332 are connected in series between a terminal of a power supply potential VDD and a terminal of a second ground potential V SS in that order. A predetermined bias voltage V bsf is applied to the gate of the P-type transistor 331. The gate of the P-type transistor 332 is connected to the output terminal of the current-voltage conversion circuit 320.

[0117] With this configuration, the buffer 330 outputs the corrected voltage signal from the connection point between the P-type transistor 331 and the P-type transistor 332 to the subtracter 340.

[0118] (subtracter)

[0119] The subtracter 340 includes a capacitor 341, a P-type transistor 342, a capacitor 343, a P-type transistor 344, and an N-type transistor 345. As the P-type transistor 342, the P-type transistor 344, and the N-type transistor 345, MOS transistors are used, for example.

[0120] The P-type transistor 344 and the N-type transistor 345 are connected in series between a terminal of the power supply potential VDD and a terminal of the second ground potential V SS in that order. A predetermined bias voltage V ba is applied to the gate of the N-type transistor 345.

[0121] P-type transistor 344 and N-type transistor 345 are used as an inverter that inverts the input signal to output when the gate of P-type transistor 344 is made into an input terminal and the connection point between P-type transistor 344 and N-type transistor 345 is made into an output terminal.

[0122] One end of capacitor 341 is connected to the output terminal of buffer 330, and the other end is connected to the input terminal of inverter (i.e., the gate of P-type transistor 344). One end of capacitor 343 is connected to the input terminal of inverter, and the other end is connected to the output terminal of inverter (i.e., the connection point between P-type transistor 344 and N-type transistor 345).

[0123] P-type transistor 342 opens and closes the path between the two ends of capacitor 343 according to the row drive signal output from row drive circuit 251.

[0124] When the P-type transistor 342 is turned on, the voltage signal V init The input is given to the buffer 330 side of capacitor 341, and the opposite side becomes a virtual ground terminal. For convenience, the potential of this virtual ground terminal is set to zero.

[0125] At this time, when the capacitance of capacitor 341 is set to C1, the charge Q stored in capacitor 341 will be... init It is expressed as equation (1). On the other hand, since the two ends of capacitor 343 are short-circuited, the stored charge is zero.

[0126] Q init =C1×V init ...(1)

[0127] Next, considering that P-type transistor 342 is turned off, the voltage on the buffer 330 side of capacitor 341 becomes V. after The charge Q stored in capacitor 341 after It is represented by the following formula (2).

[0128] Q after =C1×V after ...(2)

[0129] Conversely, when the capacitance of capacitor 343 is set to C2 and its output voltage is set to V... out At that time, the charge Q2 stored in capacitor 343 is represented by the following expression (3).

[0130] Q2=-C2×V out ...(3)

[0131] At this time, the total charge of capacitors 341 and 343 remains unchanged, making the following expression (4) true.

[0132] Q init = Q after + Q2... (4)

[0133] Then, by substituting the expressions (1) to (3) into the above expression (4) and transforming, the following expression (5) is obtained.

[0134] V out = -(C1 / C2) x (V after - V init )... (5)

[0135] The above expression (5) represents a subtraction operation of the voltage signals, and the gain of the subtraction result is C1 / C2. Since it is generally desirable to maximize the gain, the capacitance C1 is preferably designed to be large and the capacitance C2 is preferably designed to be small. In contrast, when the capacitance C2 is too small, the kTC noise increases and the noise characteristics can deteriorate, so that the reduction of the capacitance of the capacitance C2 is limited within a range that allows the noise.

[0136] Further, since the subtracter 340 is mounted on each of the effective pixels 310, there is a limit to the area of the capacitors C1 and C2. In view of this, for example, the capacitance C1 is set to a value of 20 to 200 femto Farad (fF), and the capacitance C2 is set to a value of 1 to 20 femto Farad (fF).

[0137] (Quantizer)

[0138] The quantizer 350 includes a P-type transistor 351, an N-type transistor 352, a P-type transistor 353, and an N-type transistor 354. As the P-type transistor 351, the N-type transistor 352, the P-type transistor 353, and the N-type transistor 354, MOS transistors are used, for example.

[0139] The P-type transistor 351 and the N-type transistor 352 are connected in series in that order between a terminal of a power supply potential VDD and a terminal of a second ground potential VSS. The P-type transistor 353 and the N-type transistor 354 are connected in series in that order between a terminal of the power supply potential VDD and a terminal of the second ground potential VSS. SS SS

[0140] Further, the gate of the P-type transistor 351 and the gate of the P-type transistor 353 are connected to the output terminal of the subtracter 340. A bias voltage VthH indicating an upper limit threshold value is applied to the gate of the N-type transistor 352, and a bias voltage VthL indicating a lower limit threshold value is applied to the gate of the N-type transistor 354. bon boff

[0141] ​​​​The connection point between the P-type transistor 351 and the N-type transistor 352 is connected to the transmission circuit 360. In the quantizer 350, the voltage at this connection point is output as an on-event detection signal V CH to the transmission circuit 360.

[0142] The connection point between the P-type transistor 353 and the N-type transistor 354 is connected to the transmission circuit 360. In the quantizer 350, the voltage at this connection point is output as an off-event detection signal V CL to the transmission circuit 360.

[0143] With this configuration, the quantizer 350 outputs a high-level on-event detection signal V CH in a case where the difference signal exceeds the upper limit threshold, and outputs a low-level off-event detection signal V CL in a case where the difference signal falls below the lower limit threshold. That is, the solid-state imaging device 200 according to the present embodiment can simultaneously detect the presence or absence of both the on-event and the off-event.

[0144] Note that the same second ground potential V SS as the second ground potential V SS of the current-voltage conversion circuit 320 is supplied to the buffer 330, the subtracter 340, and the quantizer 350, but is not limited thereto. As described above, the photodiode 311, the LG transistor 321, and the amplification transistor 322 are arranged on the light-receiving substrate 201, and the circuit subsequent to the constant current circuit 323 is arranged on the circuit board 202. Therefore, different ground potentials can be supplied to different substrates (the light-receiving substrate 201 and the circuit board 202).

[0145] 5. Configuration Example of Light-Receiving Unit

[0146] 5.1. Regarding Layout Configuration of Light-Receiving Unit

[0147] Figure 9 is a view that shows a layout configuration of the light-receiving unit 210 according to the embodiment of the present disclosure. Figure 9 is a plan view of the light-receiving unit 210 that shows a cross section obtained by cutting the light-receiving substrate 201 in a stacking direction of the light-receiving substrate 201.

[0148] The light-receiving unit 210 includes a plurality of light-receiving circuits 211 arranged in a matrix. In Figure 9 , 3 x 3 light-receiving circuits 211 are shown, but the number of light-receiving circuits 211 is not limited thereto, and can be less than 3 x 3 or can be greater than 3 x 3. The light-receiving circuits 211 are isolated by the pixel isolation unit 410.

[0149] Here, reference is made toFigure 10 A layout configuration of the light-receiving circuit 211 is described. Figure 10 is a view illustrating a layout configuration of the light-receiving circuit 211 according to an embodiment of the present disclosure. Figure 10 is a plan view of the light-receiving circuit 211 illustrating a cross section obtained by cutting the light-receiving substrate 201 in a stacking direction of the light-receiving substrate 201.

[0150] As Figure 10 illustrated, the source of the LG transistor 321 is connected to a substantially center of the side S1 of the photodiode 311. The side S1 is a side of the photodiode 311 that is farthest from the pixel isolation unit 410 among the multiple sides. The LG transistor 321 is formed to expand in a first direction (lateral direction) in the LG transistor 321. The first direction is, for example, a direction substantially perpendicular to the side S1. That is, the LG transistor 321 is formed so that the source is arranged closer to the side S1 than the drain. Figure 10

[0151] Further, the amplification transistor 322 is formed on the drain side of the LG transistor 321 in a region R11 (an example of a third region) closer to the pixel isolation unit 410 than the LG transistor 321. Further, the amplification transistor 322 is formed to expand in a second direction (vertical direction) in the amplification transistor 322 substantially perpendicular to the first direction. The second direction is, for example, a direction substantially parallel to the side S1. That is, this is formed so that a distance from the source of the amplification transistor 322 to the side S1 is substantially equal to a distance from the drain of the amplification transistor 322 to the side S1. Figure 10

[0152] The LG transistor 324 and the amplification transistor 325 are formed on the drain side of the LG transistor 321 in a region R12 (an example of a fourth region) different from the region R11 in which the amplification transistor 322 is formed. The region R12 is a region closer to the pixel isolation unit 410 than the LG transistor 321 on the drain side of the LG transistor 321. The region R12 is arranged at a position opposite to the region R11 with the LG transistor 321 interposed therebetween. In an example in the LG transistor 324, Figure 10

[0153] Further, similarly to the amplification transistor 322, the LG transistor 324 and the amplification transistor 325 are formed to expand in the second direction. That is, a distance between the source of the LG transistor 324 and the side S1 is substantially the same as a distance between the drain of the LG transistor 324 and the side S1. Further, a distance between the source of the amplification transistor 325 and the side S1 is substantially the same as a distance between the drain of the amplification transistor 325 and the side S1.

[0154] Further, the first ground potential V NEG ​​​The light-receiving circuit 211 is supplied with a signal from the photodiode 311 via a contact region R13 formed in a region R11 in which the amplification transistor 322 is formed. Further, a second ground potential V SS is applied to a source of the amplification transistor 322, and a power supply potential VDD is applied to a drain of the LG transistor 324.

[0155] By arranging the light-receiving circuit 211 as shown in FIG. 14, the circuit area of the light-receiving circuit 211 can be further reduced. Further, by arranging the LG transistor 321 adjacent to the photodiode 311, the charge can be more easily transferred from the photodiode 311. Figure 10 Figure 10 By arranging the LG transistor 321 adjacent to the photodiode 311, the charge can be more easily transferred from the photodiode 311.

[0156] Note that, Figure 10 Layout examples of the LG transistors 321 and 324 and the amplification transistors 322 and 325 of the gain-boosted current-voltage conversion circuit 320 are shown, but the layout configuration of the light-receiving circuit 211 is not limited to the examples in Figure 10 For example, the LG transistor 324 and the amplification transistor 325 in Figure 6 may be omitted. Such a layout example corresponds to the current-voltage conversion circuit 320 shown in Figure 10 In this case, for example, by arranging the contact region R13 to which V NEG is applied on the drain side of the LG transistor 321, the circuit area of the light-receiving circuit 211 can be further reduced in a region (e.g., the region R12 in Figure 10 ) different from the region R11 in which the amplification transistor 322 is formed.

[0157] Further, it is described that the LG transistor 324 and the amplification transistors 322 and 325 are formed to extend in the second direction, but there is no limitation. For example, the LG transistor 324 and the amplification transistors 322 and 325 can be formed to extend in the first direction. In this case, for example, by being formed such that the LG transistor 324 and the amplification transistor 325 are both arranged at substantially the same distance from the S1, the wiring length of each transistor can be shortened.

[0158] Further, in Figure 11 , it is shown that the source of the LG transistor 321 is connected to the substantially center of the side S1 of the photodiode 311, but it is not required that the substantially center be the physical center of the side S1. The LG transistor 321 only needs to be positioned between the region R11 in which the amplification transistor 322 is formed and the region R12 in which the LG transistor 324 and the amplification transistor 325 are formed, and the LG transistor 321 can be offset from the physical center of the side S1.​

[0159] <5.2. Cross-sectional configuration of light-receiving unit>

[0160] Figure 9 is a cross-sectional view of the light-receiving unit 210 taken along the line A-A' in Figure 11

[0161] As shown in Figure 12 , the light-receiving circuit 211 in which the photodiode 311 is embedded in the P-well region of the light-receiving substrate 201 is separated by the pixel isolation unit 410. Further, the back gates of the LG transistors 321 and 324 and the amplification transistor 322 are formed in the P-well region of the light-receiving substrate 201.

[0162] The power supply potential VDD is supplied to the drain of the LG transistor 324, and the second ground potential VSS is supplied to the source of the amplification transistor 322. Further, when the first ground potential VGL is applied to the P-well region of the light-receiving substrate 201, the first ground potential VGL is supplied to the anode of the photodiode 311, and the back gates of the LG transistors 321 and 324 and the amplification transistor 322. SS NEG NEG

[0163] 《6. Detailed configuration of solid-state imaging device》

[0164] Next, the detailed configuration of the solid-state imaging device 200 is described with reference to Figure 13 and Figure 12 . Figure 13 is a view showing a cross-sectional configuration of the solid-state imaging device 200 according to an embodiment of the present disclosure, mainly showing a cross-sectional structure of a peripheral portion of the solid-state imaging device 200. Figure 12 is a view showing a planar configuration of the solid-state imaging device 200 according to an embodiment of the present disclosure.

[0165] As shown in Figure 13 , the solid-state imaging device 200 includes an effective pixel region R1, a dummy pixel region R2, a power supply region R3, and a pad region R4.

[0166] The effective pixel region R1 is a region in which the light-receiving unit 210 and the address event detection unit 230 are stacked. In the effective pixel region R1, a plurality of effective pixels 310 are arranged in a two-dimensional lattice manner.

[0167] As shown in Figure 12 , the dummy pixel region R2 is a region provided to surround four sides of the effective pixel region R1.

[0168] Further, as shown in Figure 13 ​​​​As shown, multiple dummy pixels 310A are arranged side-by-side in the dummy pixel region R2. These dummy pixels 310A have essentially the same configuration as the effective pixels 310, but do not output signals to the outside.

[0169] In the solid-state imaging apparatus 200 according to the embodiment, by forming dummy pixel regions R2 around the four sides of the effective pixel region R1, process regularity from the center to the edge of the effective pixel region R1 can be ensured. Therefore, according to this embodiment, the manufacturing yield of the solid-state imaging apparatus 200 can be improved.

[0170] like Figure 1 As shown, the power supply region R3 is a region configured to surround the four sides of the dummy pixel region R2. The power supply region R3 includes a region to which a second ground potential V is applied. SS The second ground wiring 421, the power supply wiring 422 to which the power supply potential VDD is applied, and the substrate voltage V are applied. SUB The power supply wiring 423 and the first ground potential V applied NEG The first grounding wiring 424. For example, the second grounding wiring 421, the first grounding wiring 424, the power wiring 422 and the power wiring 423 are formed as a ring around the dummy pixel region R2.

[0171] The second grounding wiring 421 will connect the second grounding potential V SS Amplifying transistors 322, etc., are supplied to multiple effective pixels 310. Power supply wiring 422 supplies a power supply potential VDD to the multiple effective pixels 310, etc. Power supply wiring 423 transmits a substrate voltage V having the same potential as the power supply potential VDD. SUB The power supply is provided to areas other than the effective pixel region R1 and the dummy pixel region R2 of the solid-state imaging device 200. The first ground wiring 424 supplies a first ground potential V to the photodiodes 311 and other components of the plurality of effective pixels 310. NEG .

[0172] Each voltage is supplied from, for example, a power supply unit (not shown) disposed around circuit board 202 to second ground wiring 421, power supply wiring 422, power supply wiring 433 and first ground wiring 424. For example, the power supply unit includes a charge pump circuit (not shown), etc.

[0173] In the solid-state imaging apparatus 200 according to the embodiment, the first ground potential V NEG A first ground wiring 424 disposed in a power supply region R3 located outside the effective pixel region R1 forming the effective pixel 310 supplies power to the photodiodes 311 of the plurality of effective pixels 310. Furthermore, a second ground potential V SS Multiple current-to-voltage conversion circuits are supplied from the second ground wiring 421 located in the power supply area R3. Therefore, circuits with a second ground potential V can be connected to the second ground wiring.SS a different first ground potential V NEG is supplied to the photodiode 311 and can improve the sensitivity of the photodiode 311.

[0174] Further, in the solid-state imaging device 200 according to this embodiment, by providing the power supply wiring 423 separate from the power supply wiring 422, even in a case where the power supply potential VDD fluctuates and the like when the effective pixels 310 are operated, the substrate voltage V SUB is stably supplied to the peripheral portion of the solid-state imaging device 200. Thus, according to this embodiment, the solid-state imaging device 200 can be stably operated.

[0175] The pad region R4 is a region provided around the power supply region R3 and includes the contact hole 426 and the bonding pad 425. The contact hole 426 is formed from the surface on the light incident side of the light-receiving substrate 201 to the middle of the circuit board 202 in the thickness direction of the light-receiving substrate 201 and the circuit board 202.

[0176] The bonding pad 425 is provided at the bottom of the contact hole 426. In the embodiment, a wire bond or the like is connected to the bonding pad 425 via the contact hole 426, so that the recording unit 120 (refer to Figure 1 ) or the control unit 130 (refer to Figure 12 ) is electrically connected to each unit of the solid-state imaging device 200.

[0177] The configuration of the effective pixel 310 arranged in the effective pixel region R1 will be further described with reference to Figure 11 The solid-state imaging device 200 is obtained by stacking the light-receiving substrate 201 and the circuit board 202, and the joint 203 is provided at the interface between such light-receiving substrate 201 and circuit board 202.

[0178] The light-receiving substrate 201 includes a semiconductor layer 201a and an insulating layer 201b. The semiconductor layer 201a includes a semiconductor material such as silicon. In such semiconductor layer 201a, a photodiode 311, an LG transistor 321 (refer to Figure 11 ), an amplification transistor 322 (refer to Figure 6 ), and the like are formed for each effective pixel 310 and dummy pixel 310A.

[0179] Further, in the semiconductor layer 201a, a pixel isolation unit 410 is formed so that the adjacent effective pixel 310 and dummy pixel 310A are separated from each other. The pixel isolation unit 410 electrically and optically isolates the adjacent effective pixel 310 and dummy pixel 310A from each other.

[0180] For example, the pixel isolation unit 410 is formed in a manner of individually surrounding the effective pixel 310 and the dummy pixel 310A and penetrating the semiconductor layer 201a.

[0181] The planarization film 411 is formed on the surface of the semiconductor layer 201a on the light incident side, and the on-chip lens 412 is formed on the surface of such planarization film 411 on the light incident side. The planarization film 411 planarizes the surface on which the on-chip lens 412 is mounted.

[0182] The on-chip lens 412 is, for example, individually provided on the effective pixel 310 and the dummy pixel 310A, collects incident light, and guides it to the effective pixel 310 and the dummy pixel 310A.

[0183] The insulating layer 201b includes an insulating material such as silicon oxide (SiO x ), silicon nitride (SiN), or silicon oxynitride (SiON), and is provided on the surface of the semiconductor layer 201a on the side opposite to the light incident side.

[0184] Further, a wiring unit 401 including a wiring layer, a via, and the like is formed in the insulating layer 201b. Such wiring unit 401 is electrically connected to the photodiode 311, the PG transistor 321, and the amplification transistor 322 in the semiconductor layer 201a in the wiring configuration illustrated. Figure 6

[0185] The wiring unit 401 is electrically connected to the first pad 403 via the via 402. The first pad 403 is provided to be exposed on the surface (i.e., the interface with the circuit board 202) on the side opposite to the surface on the light incident side on the light-receiving substrate 201, and includes copper or a copper alloy.

[0186] Further, the insulating layer 202a includes the second pad 404. The second pad 404 is provided to be exposed on the surface (i.e., the interface with the light-receiving substrate 201) on the light incident side of the circuit board 202, and includes copper or a copper alloy.

[0187] The second pad 404 is electrically connected to the wiring unit 406 via the via 405. The wiring unit 406 is electrically connected to the gate of the P-type transistor 332 (refer to Figure 6 ) and the source of the P-type transistor 323 (refer to Figure 14 ). Then, in this embodiment, the first pad 403 and the second pad 404 are directly joined by Cu-Cu joining.

[0188] ​In this way, the solid-state imaging device 200 according to the embodiment is provided with the plurality of photodiodes 311 (an example of a photoelectric conversion element), the plurality of current-voltage conversion circuits 320, the address event detection unit 231, the first ground line 424, and the second ground line 421. The plurality of photodiodes 311 are arranged side by side in the effective pixel region R1. The plurality of current-voltage conversion circuits 320 respectively convert the current output from the plurality of photodiodes 311 into a voltage. The address event detection unit 231 detects a change in the voltage output from each of the plurality of current-voltage conversion circuits 320. The first ground wiring 424 is provided in a voltage supply region R3 (an example of a second region) located outside the effective pixel region R1 (an example of a first region), and supplies the first ground potential V NEG to the plurality of photodiodes 311. The second ground wiring 421 is provided in the voltage supply region R3, and supplies the second ground potential V NEG having a voltage value different from that of the first ground potential V SS to the plurality of current-voltage conversion circuits 320.

[0189] Thus, the first ground potential V SS different from the second ground potential V NEG (referential potential) can be supplied to the photodiode 311, and the sensitivity of the photodiode 311 can be improved.

[0190] 7. First Modification Example

[0191] In the above-described embodiment, each voltage is supplied to the power supply region R3 from a power supply unit (not shown) provided around the circuit board 202, but there is no limitation. For example, each voltage can be supplied to the power supply region R3 from the outside.

[0192] Figure 15 is a view that shows a configuration example of the light-receiving circuit 211 according to the first modification example of the embodiment of the present disclosure. Figure 14 is a view that shows a planar configuration of the solid-state imaging device 200 according to the first modification example of the embodiment of the present disclosure.

[0193] As shown in Figure 15 , the drain of the LG transistor 321 of the light-receiving circuit 211 is externally connected to a terminal of a power supply potential VDDP. Further, as shown in Figure 16 , an external power supply potential VDDP is supplied from a power supply wiring 422a to the drain of the LG transistor 321 and the like via the power supply wiring 422a of the power supply region R3.

[0194] In this way, by supplying the power supply potential VDDP from the outside of the solid-state imaging device 200, the power supply potential VDDP can be uniformly supplied to the light-receiving circuit 211 and the like.

[0195] Note that, in the above embodiment and the first modification example, the power supply region R3 is formed in a ring shape around the effective pixel region R1 and the dummy pixel region R2, but is not limited thereto. For example, the power supply region R3 can be provided to surround three sides of the dummy pixel region R2. Alternatively, for example, the power supply region R3 can be provided along two sides or one side of the dummy pixel region R2.

[0196] 8. Second Modification Example

[0197] In the above embodiment, the solid-state imaging device 200 detects address events, but is not limited thereto. For example, the solid-state imaging device 200 can acquire a gray scale image together with the detection of address events.

[0198] Figure 16 is a diagram illustrating an example of the light-receiving circuit 211 according to the second modification example of the embodiment of the present disclosure. As Figure 1 indicated, in a case where the solid-state imaging device 200 acquires a gray scale image, the drain of the LG transistor 321 is not connected to a terminal of the power supply potential VDD, but is connected to the read circuit 370.

[0199] The read circuit 370 generates a pixel signal based on a photoelectric current from the photodiode 311. The read circuit 370 includes a pixel transistor (not shown) including, for example, a transfer transistor, a reset transistor, a selection transistor, an amplification transistor, and the like. Further, although not shown, the solid-state imaging device 200 can include a drive circuit and an output circuit provided on the circuit board 202. The drive circuit includes a shift register, an address decoder, and the like, and drives each effective pixel 310. Further, the output circuit includes a column AD, and the like, and outputs a pixel signal read by the read circuit 370 to the recording unit 120 (refer to Figure 17 ).

[0200] Figure 17 is a diagram illustrating a planar configuration of the solid-state imaging device 200 according to the second modification example of the embodiment of the present disclosure.

[0201] In the present modification example, the drain of the LG transistor 321 is not connected to a terminal of the power supply potential VDD, but is connected to the read circuit 370. Therefore, as Figure 18 indicated, the power supply wiring 422 of the power supply region R3 can be omitted.

[0202] 9. Third Modification Example

[0203] Figure 19 is a diagram illustrating a circuit configuration of the effective pixel 310 according to the third modification example of the embodiment of the present disclosure, and illustrates the quantizer 350 that detects presence or absence of either one of a selected ON event or an OFF event.

[0204] The quantizer 350 according to the third modification example includes a P-type transistor 351, an N-type transistor 352, and a switch 355. The P-type transistor 351 and the N-type transistor 352 are connected in series between a terminal of a power supply potential VDD and a terminal of a ground potential in this order.

[0205] Further, a gate of the P-type transistor 351 is connected to an output terminal of the subtracter 340. A gate of the N-type transistor 352 is connected to the switch 355.

[0206] Then, the control unit 130 can apply a bias voltage V bon or a bias voltage V boff indicating the lower limit threshold to the gate of the N-type transistor 352 by switching the switch 355. A connection point 356 between the P-type transistor 351 and the N-type transistor 352 is connected to the transmission circuit 360.

[0207] Then, in a case where the bias voltage V bon is applied to the gate of the N-type transistor 352, in the quantizer 350 according to the third modification example, a voltage at the connection point 356 is output as the ON event detection signal V CH to the transmission circuit 360.

[0208] On the contrary, in a case where the bias voltage V boff is applied to the gate of the N-type transistor 352, in the quantizer 350 according to the third modification example, a voltage at the connection point 356 is output as the OFF event detection signal V CL to the transmission circuit 360.

[0209] By such a configuration, in a case where the ON event is selected by the control unit 130, when the difference signal exceeds the upper limit threshold, the quantizer 350 according to the third modification example outputs the ON event detection signal V CH at a high level.

[0210] On the contrary, in a case where the OFF event is selected by the control unit 130, when the difference signal falls below the lower limit threshold, the quantizer 350 according to the third modification example outputs the OFF event detection signal V CL at a low level.

[0211] For example, in the solid-state imaging device 200 according to the third modification example, when a light source not shown is turned on by a command or the like of the control unit 130, the control unit 130 can select the ON event so that the ON event detection signal V CH can be effectively output.

[0212] Furthermore, in the solid-state imaging element 200 according to the third modification, when a light source (not shown) is disconnected via a command from the control unit 130, the control unit 130 can select a disconnection event, thereby effectively outputting a disconnection event detection signal V. CL .

[0213] In the third variation described above, the chip area of ​​the solid-state imaging element 200 can be reduced, and the power consumption of the solid-state imaging element 200 can be reduced, since the number of transistors forming the quantizer 350 can be reduced.

[0214] Example 10. Fourth Variation

[0215] In addition to the address event detection unit 231 described in the above embodiments, the solid-state imaging device 200 may be provided with a device having, for example, Figure 19 The address event detection unit 1000 configuration shown in the figure. Figure 19 This is a block diagram illustrating a configuration example of an address event detection unit 1000 according to a fourth variation of an embodiment of the present disclosure. Figure 20 As shown, in addition to the current-to-voltage conversion unit 1331, buffer 1332, subtractor 1333, quantizer 1334 and transmission unit 1335, the address event detection unit 1000 according to this configuration example also includes a storage unit 1336 and a control unit 1337.

[0216] Storage unit 1336 is disposed between quantizer 1334 and transmission unit 1335, and accumulates the output of quantizer 1334 (i.e., the comparison result of comparator 1334a) based on the sampled signal provided from control unit 1337. Storage unit 1336 may be a sampling circuit such as a switch, plastic or capacitor, or may be a digital memory circuit such as a latch or flip-flop.

[0217] Control unit 1337 supplies a predetermined threshold voltage Vth to the inverting (-) input of comparator 1334a. The threshold voltage Vth supplied from control unit 1337 to comparator 1334a can have different voltage values ​​in a time-division manner. For example, control unit 1337 provides a threshold voltage Vth1 corresponding to an on-event where the change in indicated photocurrent exceeds an upper threshold and a threshold voltage Vth2 corresponding to an off-event where the change in indicated photocurrent falls below a lower threshold at different timings, so that a comparator 1334a can detect multiple types of address events.

[0218] For example, the storage unit 1336 can accumulate the comparison result of the comparator 1334a using the threshold voltage Vth1 corresponding to the on event in a period in which the threshold voltage Vth2 corresponding to the off event is supplied from the control unit 1337 to the inverting (-) input terminal of the comparator 1334a. Note that the storage unit 1336 can be located inside the pixel 2030 (refer to Figure 20 ) or outside the pixel 2030. Furthermore, the storage unit 1336 is not a necessary component of the address event detection unit 1000. That is, the storage unit 1336 can be omitted.

[0219] 11. Fifth Modification

[0220] The imaging device 100 described in the above embodiment is an asynchronous imaging device that reads events by an asynchronous reading method. Note that the event reading method is not limited to the asynchronous reading method, and can be a synchronous reading method. An imaging device that applies the synchronous reading method is a scanning-type imaging device that is the same as a normal imaging device that performs imaging at a predetermined frame rate.

[0221] Figure 20 is a block diagram illustrating an example of a configuration of the imaging device 2000 in the imaging system according to the fifth modification of the embodiment of the present disclosure.

[0222] As Figure 20 indicated, the imaging device 2000 is provided with a pixel array unit 2021, a drive unit 2022, a signal processing unit 2025, a read region selection unit 2027, and a signal generation unit 2028.

[0223] The pixel array unit 2021 includes a plurality of pixels 2030. The plurality of pixels 2030 outputs an output signal in response to a selection signal output of the read region selection unit 2027. Each of the plurality of pixels 2030 can have a quantizer comparator in the pixel. The plurality of pixels 2030 outputs an output signal corresponding to an amount of change in intensity of light. As Figure 21 indicated, the plurality of pixels 2030 can be arranged in a matrix in two dimensions.

[0224] The drive unit 2022 drives each of the plurality of pixels 2030 to output a pixel signal generated in each of the pixels 2030 to the signal processing unit 2025. Note that the drive unit 2022 and the signal processing unit 2025 are circuit units for acquiring grayscale information. Therefore, in a case where only event information is acquired, the drive unit 2022 and the signal processing unit 2025 can be omitted.

[0225] The read region selection unit 2027 selects some of the plurality of pixels 2030 included in the pixel array unit 2021. Specifically, the read region selection unit 2027 determines the selected region in response to a request from each pixel 2030 of the pixel array unit 2021. For example, the read region selection unit 2027 selects any one or a plurality of rows in a row included in a structure corresponding to a two-dimensional matrix of the pixel array unit 2021. The read region selection unit 2027 sequentially selects one or a plurality of rows according to a pre-set period. In addition, the read region selection unit 2027 can determine the selected region in response to a request from each pixel 2030 of the pixel array unit 2021.

[0226] Based on the output signal of the pixel selected by the read region selection unit 2027, the signal generation unit 2028 generates an event signal corresponding to an active pixel in which an event is detected in the selected pixel. The event is an event in which the light intensity changes. The active pixel is a pixel in which the amount of change in the light intensity corresponding to the output signal exceeds or falls below a pre-set threshold value. For example, the signal generation unit 2028 compares the output signal of the pixel with a reference signal, detects an active pixel that outputs the output signal in a case where the output signal is greater than or less than the reference signal, and generates an event signal corresponding to the active pixel.

[0227] The signal generation unit 2028 can include, for example, a column selection circuit that arbitrates signals entering the signal generation unit 2028. In addition, the signal generation unit 2028 can be configured to output not only information of the active pixel in which the event is detected but also information of an inactive pixel in which the event is not detected.

[0228] The address information and the time stamp information of the active pixel in which the event is detected (for example, (X, Y, T)) are output from the signal generation unit 2028 through the output line 2015. Note that the data output from the signal generation unit 2028 can be not only the address information and the time stamp information but also frame format information (for example, (0, 0, 1, 0,...).

[0229] 12. Application Example

[0230] For example, the technology of the present disclosure can be applied to a structured light distance measurement system. The distance measurement system according to the application example of the present disclosure is a system for measuring a distance to an object using a structured light method technique. In addition, the distance measurement system according to the present application example can also be used as a system for acquiring a three-dimensional (3D) image, and in this case, this can be referred to as a three-dimensional image acquisition system. In the structured light method, distance measurement is performed by identifying a point image and by pattern matching from the coordinates of a light source (so-called point light source) from which a point image is projected.

[0231] Figure 22To show a schematic diagram of an example of a configuration of a distance measurement system according to an embodiment of the present disclosure, and ​ To show a block diagram of an example of a circuit configuration according to an embodiment of the present disclosure.

[0232] The distance measurement system 3000 according to the present embodiment uses a surface emitting semiconductor laser (for example, a vertical cavity surface emitting laser (VCSEL) 3010) as a light source unit, and uses an event detection sensor 3020 called DVS as a light receiving unit. The vertical cavity surface emitting laser (VCSEL) 3010 projects light of a predetermined pattern onto a subject. The distance measurement system 3000 according to the present embodiment is provided with a system control unit 3030, a light source driving unit 3040, a sensor control unit 3050, a light source side optical system 3060, and a camera side optical system 3070 in addition to the vertical cavity surface emitting laser 3010 and the event detection sensor 3020.

[0233] The system control unit 3030 includes, for example, a processor (CPU), drives the vertical cavity surface emitting laser 3010 via the light source driving unit 3040, and drives the event detection sensor 3020 via the sensor control unit 3050. More specifically, the system control unit 3030 controls the vertical cavity surface emitting laser 3010 and the event detection sensor 3020 synchronously.

[0234] In the distance measurement system 3000 according to the present embodiment having the above-described structure, light of a predetermined pattern emitted from the vertical cavity surface emitting laser 3010 is projected onto an object (measurement target) 3100 by the light source side optical system 3060. The projected light is reflected by the object 3100. Then, the light reflected by the object 3100 is incident on the event detection sensor 3020 by the camera side optical system 3070. The event detection sensor 3020 receives the light reflected by the object 3100, and detects a change in luminance of a pixel exceeding a predetermined threshold as an event. The event information detected by the event detection sensor 3020 is supplied to an application processor 3200 outside the distance measurement system 3000. The application processor 3200 performs predetermined processing on the event information detected by the event detection sensor 3020.

[0235]

[0236] In each of the above-described embodiments of the present disclosure, a solid-state imaging device 100 in which the first conductivity type is P type, the second conductivity type is N type, and an electron is used as a signal charge is described, but embodiments of the present disclosure are not limited to such an example. For example, each of the embodiments can be applied to a solid-state imaging device 100 in which the first conductivity type is N type, the second conductivity type is P type, and a hole is used as a signal charge. In this case, the first ground potential V​NEG a second ground potential V SS .

[0237] While the preferred embodiments of the present disclosure have been described above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is apparent that various modifications and changes can be made to the present application by those skilled in the technical field of the present application within the scope of the technical idea described in the claims, and the present application embraces all such modifications and changes.

[0238] Furthermore, the effects described in this specification are merely illustrative or exemplary, and the effects are not limited thereto. That is, it is apparent that, according to the description of this specification, the technology according to the present disclosure can exhibit other effects in addition to or instead of the effects described above to those skilled in the art.

[0239] Note that the following configurations also belong to the technical scope of the present disclosure. (1)

[0241] A solid-state imaging device is provided with:

[0242] a plurality of photoelectric conversion elements arranged side by side in a first region;

[0243] a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of photoelectric conversion elements into voltages;

[0244] a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits;

[0245] a first ground wiring provided in a second region located outside the first region and supplying a first ground potential to the plurality of photoelectric conversion elements; and

[0246] a second ground wiring provided in the second region and supplying a second ground potential having a voltage value different from that of the first ground potential to the plurality of current-voltage conversion circuits. (2)

[0248] The solid-state imaging device according to (1), wherein the voltage value of the first ground potential is smaller than the voltage value of the second ground potential. (3)

[0250] The solid-state imaging device according to (1) or (2), further provided with a power supply wiring provided in the second region and supplying a power supply potential to the current-voltage conversion circuits. (4)

[0252] The solid-state imaging device according to (1) or (2), further provided with a reading circuit that reads the current output from the plurality of photoelectric conversion elements and outputs a pixel signal corresponding to the current, respectively. (5)

[0254] The solid-state imaging device according to any one of (1) to (4), wherein

[0255] The current-voltage conversion circuit includes a ring source follower circuit.

[0256] The source follower circuit includes:

[0257] a first transistor whose source is connected to the photoelectric conversion element; and

[0258] a second transistor whose gate is connected to the photoelectric conversion element and whose drain is connected to the gate of the first transistor.

[0259] The source of the first transistor is arranged to be connected to a substantially center of the photoelectric conversion element in a cross section obtained by cutting the stacked substrate in a stacking direction of a stacked substrate on which the plurality of photoelectric conversion elements are formed. (6)

[0261] The solid-state imaging device according to (5), wherein, in the cross section, the source of the first transistor is arranged to be closer to the photoelectric conversion element than the drain of the first transistor. (7)

[0263] The solid-state imaging device according to (5) or (6), wherein, in the cross section, a distance between the source of the second transistor and the photoelectric conversion element is substantially the same as a distance between the drain of the second transistor and the photoelectric conversion element. (8)

[0265] The solid-state imaging device according to any one of (5) to (7), wherein

[0266] The source follower circuit further includes:

[0267] a third transistor whose source is connected to the drain of the first transistor; and

[0268] a fourth transistor whose source is connected to the gate of the first transistor and the drain of the second transistor, and whose gate is connected to the drain of the first transistor and the source of the third transistor.

[0269] In the cross section, the third transistor and the fourth transistor are disposed in a fourth region, and the second transistor is disposed in a third region, the fourth region being opposite the third region with the first transistor interposed therebetween. (9)

[0271] The solid-state imaging device according to (8), wherein

[0272] In the cross section, a distance between the source of the third transistor and the photoelectric conversion element is substantially the same as an interval between the drain of the third transistor and the photoelectric conversion element; and

[0273] In the cross section, a distance between the source of the fourth transistor and the photoelectric conversion element is substantially the same as an interval between the drain of the fourth transistor and the photoelectric conversion element. (10)

[0275] The solid-state imaging device according to (8) or (9), wherein a first ground potential is applied to the stacked substrate via a contact region, the contact region being disposed in a second region at a position farther from a photoelectric conversion element than the second transistor in the cross section. (11)

[0277] An imaging device is provided with:

[0278] a solid-state imaging device;

[0279] an optical system that captures incident light from an object to form an image on an imaging surface of the solid-state imaging element; and

[0280] a control unit that controls the solid-state imaging element;

[0281] The solid-state imaging device is provided with:

[0282] a plurality of photoelectric conversion elements arranged side by side in a first region;

[0283] a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of photoelectric conversion elements into voltages;

[0284] a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits;

[0285] a first ground wiring disposed in a second region outside the first region and supplying a first ground potential to the plurality of photoelectric conversion elements; and

[0286] A second ground wiring is provided in the second region to supply a second ground potential having a voltage value different from that of the first ground potential to the plurality of current-voltage conversion circuits.

[0287] Symbol explanation

[0288] 100 imaging device

[0289] 110 imaging lens

[0290] 130 control unit

[0291] 200 solid-state imaging device

[0292] 231, 231A address event detection circuit

[0293] 310 effective pixel

[0294] 310A dummy pixel

[0295] 311, 311A photodiode

[0296] 320, 320A current-voltage conversion circuit

[0297] 421, 424 ground wiring

[0298] 422, 423 power supply wiring

[0299] R1 effective pixel region

[0300] R2 dummy pixel region

[0301] R3 power supply region

Claims

1. A solid-state imaging device comprising: a plurality of photoelectric conversion elements arranged side by side in a first region; a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of photoelectric conversion elements into voltages; a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits; a first ground wiring provided in a second region outside the first region and supplying a first ground potential to the plurality of photoelectric conversion elements; and a second ground wiring provided in the second region and supplying a second ground potential having a voltage value different from that of the first ground potential to the plurality of current-voltage conversion circuits, wherein the current-voltage conversion circuit includes a ring source follower circuit; the source follower circuit includes: a first transistor whose source is connected to the photoelectric conversion element; and a second transistor whose gate is connected to the photoelectric conversion element and whose drain is connected to the gate of the first transistor; the source of the first transistor is arranged to be connected to the center of the photoelectric conversion element in a cross section obtained by cutting a stacked substrate in a stacking direction of the stacked substrate on which the plurality of photoelectric conversion elements are formed. the voltage value of the first ground potential is smaller than the voltage value of the second ground potential.

2. The solid-state imaging device according to claim 1, wherein 3. The solid-state imaging device according to claim 1, further comprising a power supply wiring provided in the second region and supplying a power supply potential to the current-voltage conversion circuit.

4. The solid-state imaging device according to claim 1, further comprising a reading circuit that reads the currents output from the plurality of photoelectric conversion elements and respectively outputs pixel signals corresponding to the currents. in the cross section, the source of the first transistor is arranged closer to the photoelectric conversion element than the drain of the first transistor.

5. The solid-state imaging device according to claim 1, wherein in the cross section, the distance between the source of the second transistor and the photoelectric conversion element is the same as the interval between the drain of the second transistor and the photoelectric conversion element.

6. The solid-state imaging device according to claim 1, wherein 7. The solid-state imaging device according to claim 1, wherein the source follower circuit further includes: a third transistor whose source is connected to the drain of the first transistor; and a fourth transistor whose source is connected to the gate of the first transistor and the drain of the second transistor, and whose gate is connected to the drain of the first transistor and the source of the third transistor; in the cross section, the third transistor and the fourth transistor are provided in a fourth region, the second transistor is provided in a third region, and the fourth region is opposite the third region across the first transistor.

8. The solid-state imaging device according to claim 7, wherein in the cross section, the distance between the source of the third transistor and the photoelectric conversion element is the same as the interval between the drain of the third transistor and the photoelectric conversion element, and ​ In the cross section, a distance between the source of the fourth transistor and the photoelectric conversion element is the same as a distance between the drain of the fourth transistor and the photoelectric conversion element.

9. The solid-state imaging device according to claim 7, wherein The first ground potential is applied to the stacked substrate via a contact region, the contact region being disposed, in the cross section, at a position farther from the photoelectric conversion element than the second transistor.

10. An imaging apparatus comprising: a solid-state imaging device; an optical system that captures incident light from an object to form an image on an imaging surface of the solid-state imaging device; and a control unit that controls the solid-state imaging device; the solid-state imaging device is provided with: a plurality of photoelectric conversion elements arranged side by side in a first region; a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of photoelectric conversion elements into voltages; a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits; a first ground wiring disposed in a second region outside the first region and supplying a first ground potential to the plurality of photoelectric conversion elements; and a second ground wiring disposed in the second region and supplying a second ground potential having a voltage value different from that of the first ground potential to the plurality of current-voltage conversion circuits, wherein the current-voltage conversion circuit includes a ring-shaped source follower circuit; the source follower circuit includes: a first transistor whose source is connected to the photoelectric conversion element; and a second transistor whose gate is connected to the photoelectric conversion element and whose drain is connected to the gate of the first transistor; the source of the first transistor is arranged to be connected to the center of the photoelectric conversion element in a cross section obtained by cutting a stacked substrate in a stacking direction of the stacked substrate on which the plurality of photoelectric conversion elements are formed. ​

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