A circuit, method and electronic device for efficiently implementing pseudo DDR signal cross-clock domain

Abstract

The present invention discloses a circuit, method and electronic device for efficiently implementing pseudo DDR signal cross-clock domain, relating to the technical field of circuit design. The circuit comprises: a chip-side high-frequency clock domain module, multiple cross-clock domain modules arranged on the chip-side high-frequency clock domain module, and a host-side low-frequency clock domain module connected to the multiple cross-clock domain modules; each cross-clock module comprises a low-frequency to high-frequency transmission submodule and a high-frequency to low-frequency transmission submodule; one end of the low-frequency to high-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; one end of the high-frequency to low-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; the circuit can simultaneously process scenarios with high timing requirements, such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals, avoid multi-domain propagation of metastable states, and improve the stability and reliability of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a circuit, method and electronic device for efficiently implementing pseudo DDR signal crossing clock domains. Background Art

[0002] Simple digital integrated circuits are synchronous logic circuits driven by a single clock. The flip-flops in these circuits flip under the control of a unified clock, resulting in simple timing constraints and easy clock system design. However, a single clock constraint is no longer suitable for the rapidly growing scale of integrated circuits. The design of large-scale digital circuits with complex functions often involves multiple clock domains. Managing signal propagation across clock domains (CDCs), enabling output drive and input sampling, and minimizing or preventing metastable states have become key issues in determining the success of digital integrated circuit design.

[0003] Currently, the most common approach to cross-clock domain synchronization is to use a synchronizer to sample asynchronous input signals, ensuring that the generated output signal meets the setup and hold time requirements of the synchronization system, thereby suppressing the adverse effects of metastability on the circuit. There are two common synchronization methods: the two-stage trigger method and the lock method.

[0004] The essence of the two-stage flip-flop method is to reduce the probability of metastable states. By cascading two stages of flip-flops, when the signal from the previous clock domain reaches the first flip-flop in the next clock domain, it is likely that the setup / hold time will not be met, causing the output of that stage to remain in a metastable state for a long time. If the state of the second stage lasts for less than one cycle, the metastable state can be eliminated by adding a stage of flip-flops, so that the output of the second stage flip-flop meets the requirements of the synchronization signal. However, adding just one stage of D flip-flops will increase the input signal's delay by one stage. This method is typically used for circuit synchronization with low timing requirements and is suitable for synchronizing a small number of signals from a slow clock to a fast clock. However, it cannot achieve bidirectional synchronization of a large number of signals between fast and slow clock domains, which has strict timing requirements.

[0005] The locking method primarily addresses the issue of two-stage trigger synchronization: when signals transition from a fast to a slow clock, the slow clock may not be able to sample the fast clock in time if the signal changes too quickly. While a complementary approach to the two-stage trigger method, locking synchronizers still cannot meet the stringent timing requirements for the synchronous cross-domain propagation of numerous control and data signals between the fast and slow clock domains. This can lead to metastable multi-domain propagation, reducing system stability and reliability. Summary of the Invention

[0006] The purpose of the present invention is to provide a circuit, method and electronic device for efficiently implementing pseudo DDR signal cross-clock domain, so as to solve the problem that the existing cross-clock domain solution cannot meet the high timing requirements of synchronous cross-domain propagation of a large number of control signals and data signals between fast and slow clock domains, resulting in metastable multi-domain propagation and reducing the stability and reliability of the system.

[0007] In a first aspect, the present invention provides a circuit for efficiently implementing pseudo DDR signal cross-clock domain, the circuit comprising:

[0008] A chip-side high-frequency clock domain module, multiple cross-clock domain modules arranged on the chip-side high-frequency clock domain module, and a host-side low-frequency clock domain module connected to the multiple cross-clock domain modules;

[0009] Each of the cross-clock domain modules includes a low-frequency to high-frequency transmission submodule and a high-frequency to low-frequency transmission submodule, one end of the low-frequency to high-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module, one end of the high-frequency to low-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module;

[0010] The low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module;

[0011] The high-frequency to low-frequency transmission submodule is used to complete the reading of corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction issued by the host-side low-frequency clock domain module.

[0012] In the case of adopting the above technical solution, the circuit for efficiently implementing pseudo DDR signal cross-clock domains provided by the embodiment of the present invention, the low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the synchronized write control signal and the write data signal to the chip-side high-frequency clock domain module; the high-frequency to low-frequency transmission submodule is used to, upon receiving a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, complete the reading of the corresponding data based on the read data signal. It can simultaneously handle scenarios with high timing requirements, such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals. It has a wide range of application scenarios and can be applied to bidirectional cross-clock domain propagation of a large number of signals from the low-frequency domain to the high-frequency domain or vice versa, avoiding metastable multi-domain propagation and improving the stability and reliability of the circuit.

[0013] In a possible implementation, the low-frequency to high-frequency transmission submodule includes an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit, one end of the asynchronous first-in-first-out control signal transmission unit is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; one end of the data signal transmission unit is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module;

[0014] The low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module, including:

[0015] The asynchronous first-in first-out control signal transmission unit is used to adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0016] The data signal transmission unit is configured to adjust the write data signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0017] The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit are also used to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module.

[0018] In a possible implementation, the circuit further includes a plurality of memory modules, which are arranged on the chip-side high-frequency clock domain module, and the plurality of memory modules are respectively connected to each of the cross-clock domain modules in a one-to-one correspondence.

[0019] In a possible implementation, the asynchronous first-in-first-out control signal transmission unit is configured to, upon receiving a write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain, including:

[0020] The asynchronous first-in-first-out control signal transmission unit is configured to, upon receiving the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, write the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and upon detecting that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state;

[0021] The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

[0022] In a possible implementation, the data signal transmission unit is configured to, upon receiving a write data signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, adjust the write data signal from the low-frequency clock domain to the high-frequency clock domain, including:

[0023] The data signal transmission unit is used to, upon receiving the write data signal sent by the host-side low-frequency clock domain module, determine the write data transmission signal corresponding to each transmission based on a pre-set second transmission depth value, store the write data transmission signal in the corresponding memory module until the number of transmissions reaches the second transmission depth value, and read all the write data transmission signals out from the data transmission unit in sequence according to the order in which they are stored and written.

[0024] In a second aspect, the present invention further provides a method for efficiently implementing pseudo DDR signal cross-clock domain, which is applied to any circuit for efficiently implementing pseudo DDR signal cross-clock domain as described in the first aspect, and the method comprises:

[0025] Upon receiving a write control signal and a write data signal corresponding to a write operation instruction from the low-frequency clock domain module on the host side, the low-frequency to high-frequency transmission submodule adjusts the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, performs synchronization alignment processing on the adjusted write control signal and the write data signal, and sends the write control signal and the write data signal after the synchronization alignment processing to the high-frequency clock domain module on the chip side;

[0026] When the high-frequency to low-frequency transmission submodule receives a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, the high-frequency to low-frequency transmission submodule completes reading of corresponding data based on the read data signal.

[0027] In one possible implementation, the low-frequency to high-frequency transmission submodule includes an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit. When the low-frequency to high-frequency transmission submodule receives a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, the low-frequency to high-frequency transmission submodule adjusts the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, performs synchronization alignment processing on the adjusted write control signal and the write data signal, and sends the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module, including:

[0028] The asynchronous first-in-first-out control signal transmission unit adjusts the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0029] The data signal transmission unit adjusts the write data signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0030] The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the synchronously aligned write control signal and the write data signal to the chip-side high-frequency clock domain module.

[0031] In a possible implementation, the asynchronous first-in-first-out control signal transmission unit adjusts the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end, including:

[0032] The asynchronous first-in-first-out control signal transmission unit, upon receiving the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, writes the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and upon detecting that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state;

[0033] The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

[0034] In a possible implementation, the data signal transmission unit adjusts the write data signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end, including:

[0035] When the data signal transmission unit receives the write data signal sent by the host-side low-frequency clock domain module, it determines the write data transmission signal corresponding to each transmission based on a preset second transmission depth value, stores the write data transmission signal in the corresponding memory module until the number of transmissions reaches the second transmission depth value, and reads all the write data transmission signals from the data transmission unit in sequence according to the order in which they are stored and written.

[0036] The beneficial effects of the method for efficiently implementing pseudo DDR signal crossing clock domains provided by the second aspect are the same as the beneficial effects of the circuit for efficiently implementing pseudo DDR signal crossing clock domains described in the first aspect or any possible implementation of the first aspect, and are not repeated here.

[0037] In a third aspect, the present invention also provides an electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, enables the device to execute the method for efficiently implementing pseudo DDR signal crossing clock domains as described in any possible implementation of the second aspect.

[0038] The beneficial effects of the electronic device provided in the third aspect are the same as the beneficial effects of the method for efficiently implementing pseudo DDR signal crossing clock domains described in the second aspect or any possible implementation of the second aspect, and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0040] Figure 1A schematic diagram of the structure of a circuit for efficiently implementing pseudo DDR signal crossing clock domains provided by an embodiment of the present application is shown;

[0041] Figure 2 An operation timing diagram of a write operation signal provided by an embodiment of the present application is shown;

[0042] Figure 3 An operation timing diagram of a read operation signal provided by an embodiment of the present application is shown;

[0043] Figure 4 A schematic diagram of waveforms before and after clock domain crossing from a host-side low-frequency clock domain module to a chip-side high-frequency clock domain module provided by an embodiment of the present application is shown;

[0044] Figure 5 A schematic diagram of waveforms before and after a clock domain is crossed from a high-frequency clock domain module on a chip to a low-frequency clock domain module on a host, provided in an embodiment of the present application;

[0045] Figure 6 A flow chart of a method for efficiently implementing pseudo DDR signal cross-clock domain transmission provided by an embodiment of the present application is shown;

[0046] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention;

[0047] Figure 8 A schematic diagram of the structure of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0049] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0050] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0051] Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a common type of memory used as RAM for most modern processors. To meet actual application requirements, pseudo-DDR signals convert the dual-edge transmission characteristics of standard DDR into a single-edge transmission characteristic and simplify non-essential DDR specifications based on the application scenario, such as fixing the burst length and eliminating uncommon DDR signals. However, considering that pseudo-DDR still has bidirectional cross-domain propagation signals and the problem of synchronous cross-domain propagation between specific read / write commands and the data they transmit, an invention that can efficiently solve the above-mentioned key cross-clock domain propagation problem, avoid the propagation of metastable states between different clock domains while achieving basic system functions, and reduce system level disturbances to achieve improved system stability and reliability has broad application prospects in the future era of increasingly complex ultra-large-scale integrated circuits.

[0052] Figure 1 FIG. 1 shows a schematic diagram of a circuit structure for efficiently implementing pseudo DDR signal cross-clock domains provided by an embodiment of the present application. Figure 1 As shown, the circuit for efficiently implementing pseudo DDR signal crossing clock domains includes:

[0053] A chip-side high-frequency clock domain module 101, multiple cross-clock domain modules 102 arranged on the chip-side high-frequency clock domain module 101, and a host-side low-frequency clock domain module 103 connected to the multiple cross-clock domain modules 102;

[0054] Each of the cross-clock domain modules 102 includes a low-frequency to high-frequency transmission sub-module 1021 and a high-frequency to low-frequency transmission sub-module 1022. One end of the low-frequency to high-frequency transmission sub-module 1021 is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the host-side low-frequency clock domain module 103. One end of the high-frequency to low-frequency transmission sub-module 1022 is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the host-side low-frequency clock domain module 103.

[0055] The low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module;

[0056] The high-frequency to low-frequency transmission submodule is used to complete the reading of corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction issued by the host-side low-frequency clock domain module.

[0057] In the present application, the high-frequency to low-frequency transmission submodule 1022 includes a first-in-first-out queue (QUEUE) 1022A.

[0058] An embodiment of the present invention provides a circuit for efficiently implementing pseudo-DDR signal cross-clock domains. The low-frequency to high-frequency transmission submodule is configured to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the synchronized write control signal and the write data signal to the chip-side high-frequency clock domain module. The high-frequency to low-frequency transmission submodule is configured to, upon receiving a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, complete reading of corresponding data based on the read data signal. This circuit can simultaneously handle scenarios with high timing requirements, such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals. It has a wide range of application scenarios and can be applied to bidirectional cross-clock domain propagation of a large number of signals from the low-frequency domain to the high-frequency domain or vice versa, avoiding metastable multi-domain propagation and improving the stability and reliability of the circuit.

[0059] Optional, see Figure 1The circuit further includes a plurality of memory modules 104 , which are arranged on the chip-side high-frequency clock domain module 101 , and the plurality of memory modules 104 are respectively connected to each of the cross-clock domain modules 102 in a one-to-one correspondence.

[0060] Optional, see Figure 1 The low-frequency to high-frequency transmission submodule 1021 includes an asynchronous first-in-first-out control signal transmission unit 1021A and a data signal transmission unit 1021B. One end of the asynchronous first-in-first-out control signal transmission unit 1021A is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the host-side low-frequency clock domain module 103. One end of the data signal transmission unit 1021B is connected to the chip-side high-frequency clock domain module 101, and the other end is connected to the host-side low-frequency clock domain module 103.

[0061] The asynchronous first-in first-out control signal transmission unit is used to adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0062] The data signal transmission unit is configured to adjust the write data signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end;

[0063] The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit are also used to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module.

[0064] The host-side low-frequency clock domain module may be HOST, where HOST is a low-frequency clock of 100 MHz, and the chip-side high-frequency clock domain module may be DEVICE, where DEVICE is a high-frequency clock of 400 MHz.

[0065] When the host-side low-frequency clock domain module performs a write operation, the host sends a control (WRITE) signal to the device, and synchronizes the data (DATA) signal and the non-read, non-write (NOP) signal. When a read operation is performed, the device only sends a data signal to the host.

[0066] Optional, Figure 2 FIG. 4 shows an operation timing diagram of a write operation signal provided by an embodiment of the present application. Figure 2As shown in the figure, the CTRL signal lasts for one clock cycle, followed by several cycles of NOP operations. When a write operation is performed, the HOST end sends a WRITE signal, and at the same time as the WRITE instruction is sent, 8 cycles of DATA data will be synchronously sent to the DEVICE end. No other instructions except the NOP instruction will be issued before the DATA data is sent. The signal odt=1 indicates that DATA is written from the HOST to the DEVICE.

[0067] Optional, Figure 3 FIG. 4 shows an operation timing diagram of a read operation signal provided by an embodiment of the present application. Figure 3 As shown, there are only 8 consecutive cycles of DATA signal transmission from the DEVICE to the HOST, and there is no CTRL signal transmission in this direction. The read valid signal rdvalid=1 indicates that DATA is read from the DEVICE to the HOST.

[0068] It should be noted that the basic requirements across time domains may include: the signal period before and after the CDC remains unchanged, the clocks of the WRITE instruction and the transmitted DATA signal are aligned before and after the CDC, and the DATA data of the WRITE and READ processes are controlled by the odt and rdvalid signals respectively.

[0069] The signals that cross the clock domain from the HOST to the DEVICE may include: ddr4_cke, ddr4_cs_n, ddr4_act_n, ddr4_adr[16:0], ddr4_bg[2:0], ddr4_c[2:0], ddr4_ba[1:0], ddr4_odt, ddr4_dq[7:0], ddr4_dm_n, and ddr4_dqs.

[0070] The signals that cross the clock domain from DEVICE to HOST may include: ddr4_dq[7:0], ddr4_dm_n, ddr4_dqs, and rd_valid.

[0071] Optionally, the asynchronous first-in, first-out control signal transmission unit in this application is also an asynchronous FIFO (First Input First Output). An asynchronous FIFO is a first-in, first-out circuit that can store, buffer, and synchronize data between two different clock domains. An asynchronous FIFO has two completely independent clock domains: a write clock domain and a read clock domain. The clock signal for the write clock domain is wclk, and the asynchronous reset signal is reset_n. The winc signal is the enable signal that controls whether wdata is written to the FIFO.

[0072] When the FIFO is full, the wfull signal is pulled high. It remains active until data in the FIFO is read from the read clock domain, making the FIFO non-empty. The signal definition in the read clock domain is similar to that in the write clock domain. If the rempty signal is pulled high, it indicates that the FIFO has been completely emptied. The rempty signal remains active until the write clock domain writes data to the FIFO again. The awfull and arempty signals in asynchronous FIFOs indicate that the FIFO is full or empty only when the value is less than one value of size. These signals are also active high.

[0073] When HOST issues a write operation (ddr4adr=10000), see Figure 2 , the HOST end will send a cycle of write control signal to the DEVICE end, and at this time there will be 8 cycles of write data signal sent synchronously with it. The write control signal and write data signal can be processed from the low frequency domain to the high frequency domain across the clock domain, and then the two can be synchronized.

[0074] Optionally, the asynchronous first-in-first-out control signal transmission unit is configured to, upon receiving the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, write the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and upon detecting that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state;

[0075] The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

[0076] Specifically, the CTRL (control) signal has a certain degree of continuity, unlike the DATA signal, which has burst transmission. Therefore, by setting an appropriate FIFO depth, when it is detected that the FIFO is not full and is not in the NOP state, the winc signal is set to 1, allowing wdata to be written to the FIFO from the write clock domain. The rinc signal is set to 1 as long as it detects that the FIFO is not empty, and the rinc signal can only remain valid for one cycle, so that real-time processing of the CTRL signal across clock domains can be achieved. In other words, as long as a non-NOP instruction of one cycle is written into the FIFO, the instruction in the FIFO will be read out, and the read instruction will also remain valid for one cycle. Since the clock frequency changes before and after crossing the clock domain, in order to ensure that rinc is only valid for one cycle, on the basis of setting rinc to 1 when detecting that the FIFO is not empty, a level pulse conversion (rising edge detection) circuit can be added to control rinc to be high and valid for only one cycle.

[0077] Optionally, the data signal transmission unit is used to, when receiving the write data signal emitted by the low-frequency clock domain module on the host side, determine the write data transmission signal corresponding to each transmission based on a pre-set second transmission depth value, store the write data transmission signal in the corresponding memory module until the number of transmissions reaches the second transmission depth value, and read out all the write data transmission signals from the data transmission unit in sequence according to the order in which they are stored and written.

[0078] In this application, the data transmission unit may be a QUEUE.

[0079] Specifically, when odt=1, DATA is transmitted from the HOST to the DEVICE. The DATA signal is characterized by burstiness. Data transmission occurs only when the HOST sends a specific WRITE command, and the length of each burst transmission is fixed at 8. When using the FIFO as a QUEUE, the FIFO depth is first set to the burst length, which can be a fixed value of 8, that is, the second transmission depth value can be 8. The 8 units of DATA transmitted in each burst are stored stably in the FIFO. After all 8 units of data enter the QUEUE, the QUEUE is marked as full (wfull=1), and the DATA is then read from the QUEUE in the order previously written from the write clock domain.

[0080] After completing the CDC transmission of the CTRL signal and the DATA signal respectively, a specific 1-cycle WRITE instruction is aligned with the 8-cycle DATA signal to achieve the coordinated transmission of the CTRL signal and the DATA signal. Since the temporary storage of the DATA signal in the QUEUE will cause a certain delay, it has a certain delay characteristic. Therefore, the DATA signal cannot be transmitted in advance at the same cycle as each WRITE instruction. Based on this, the WRITE instruction can be delayed to the same cycle as the DATA before transmission. Since the reading of the DATA signal is based on rinc = 1, rinc = 1 can be used as the reading condition of the CTRL signal to synchronize the CTRL and DATA signals, completing the cross-clock domain processing from the host to the device.

[0081] The high-frequency to low-frequency transmission submodule is used to complete the reading of corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction issued by the host-side low-frequency clock domain module.

[0082] In the present application, the high-frequency to low-frequency transmission submodule may include a QUEUE. When a read operation occurs, it is a cross-clock domain process from the DEVICE high-frequency domain to the HOST low-frequency domain. The data transmission from the DEVICE end to the HOST end has a certain degree of burstiness. When the DEVICE continuously bursts 8 cycles of DATA data to the HOST, the FIFO is used as the function of the QUEUE to temporarily store all the data in the QUEUE, and then the data in the QUEUE is read out sequentially from the DEVICE end. Because the clock frequency of the DEVICE end is higher than that of the HOST end, the speed at which the QUEUE is filled is faster than the speed at which it is read out. Therefore, it is necessary to read all the data in the previous QUEUE before writing the next DATA data. The interval between the 8 units of data in the two burst read operations cannot be too small to avoid data loss caused by the previous data not being read out and the next written data arriving, thereby completing the cross-clock domain processing from the DEVICE end to the HOST end.

[0083] The circuit of the present application efficiently implements pseudo DDR signal cross-clock domain, has good configurability, can simultaneously handle scenarios with high timing requirements such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals, and has a wide range of application scenarios. It can be applied to the bidirectional cross-clock domain propagation of a large number of signals from the low-frequency domain to the high-frequency domain or vice versa, avoiding the multi-domain propagation of metastable states and improving the stability and reliability of the system.

[0084] Figure 4 The figure shows a waveform diagram of the cross-clock domain from a host-side low-frequency clock domain module to a chip-side high-frequency clock domain module provided by an embodiment of the present application. In the HOST to DEVICE cross-clock domain mode, after completing the CDC transmission of the CTRL signal and the DATA signal respectively, a specific 1-cycle WRITE instruction and an 8-cycle DATA signal are aligned to achieve the coordinated transmission of the CTRL signal and the DATA signal. Since the temporary storage of the DATA signal in the QUEUE will cause a certain delay, it has a certain delay characteristic. Therefore, the DATA signal cannot be transmitted in advance at the same cycle as each WRITE instruction. Based on this, the WRITE instruction can be delayed to the same cycle as the DATA before transmission. Since the reading of the DATA signal is based on rinc=1, the CTRL and DATA signals can be synchronized with rinc=1 as the reading condition of the CTRL signal to complete the cross-clock domain processing from the HOST to the DEVICE.

[0085] Figure 5A waveform diagram of the clock domain before and after the high-frequency clock domain module on the chip side to the low-frequency clock domain module on the host side provided by an embodiment of the present application is shown. In the clock domain cross-over mode from DEVICE to HOST, when a read operation occurs, it is a cross-clock domain process from the high-frequency domain of DEVICE to the low-frequency domain of HOST. The data transmission from the DEVICE end to the HOST end has a certain degree of burstiness. When the DEVICE transmits 8 cycles of DATA data to the HOST continuously in burst, the FIFO is used as the QUEUE function to temporarily store all data in the QUEUE, and then the data in the QUEUE is read out sequentially from the DEVICE end. Because the clock frequency of the DEVICE end is higher than that of the HOST end, the speed of filling the QUEUE is faster than the speed of reading. Therefore, the next DATA data needs to be written after all the data in the previous QUEUE is read out. The interval between the 8 units of data in the two burst read operations cannot be too small, that is, before the next written data arrives, it is guaranteed that the currently written data has been read out. The embodiment of the present application does not limit the specific setting value of the interval, and can be adjusted according to the actual application scenario. It can avoid data loss caused by the previous data not being read out and the next written data arriving, and complete the cross-clock domain processing from the DEVICE end to the HOST end.

[0086] An embodiment of the present invention provides a circuit for efficiently implementing pseudo-DDR signal cross-clock domains. The low-frequency to high-frequency transmission submodule is configured to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the synchronized write control signal and the write data signal to the chip-side high-frequency clock domain module. The high-frequency to low-frequency transmission submodule is configured to, upon receiving a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, complete reading of corresponding data based on the read data signal. This circuit can simultaneously handle scenarios with high timing requirements, such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals. It has a wide range of application scenarios and can be applied to bidirectional cross-clock domain propagation of a large number of signals from the low-frequency domain to the high-frequency domain or vice versa, avoiding metastable multi-domain propagation and improving the stability and reliability of the circuit.

[0087] Figure 6 A schematic diagram of a method for efficiently implementing a pseudo DDR signal crossing clock domain provided by an embodiment of the present application is shown, which is applied to Figure 1 In the circuit for efficiently implementing pseudo DDR signal crossing clock domains, as shown in FIG. Figure 6 As shown, the method for efficiently implementing pseudo DDR signal crossing clock domains includes:

[0088] Step 201: When the low-frequency to high-frequency transmission submodule receives the write control signal and the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module on the host side, the write control signal and the write data signal are adjusted from the low-frequency clock domain to the high-frequency clock domain respectively, and the adjusted write control signal and the write data signal are synchronously aligned, and the write control signal and the write data signal after the synchronous alignment are sent to the high-frequency clock domain module on the chip side.

[0089] Optionally, the specific implementation of step 201 may include the following sub-steps:

[0090] Sub-step S1: upon receiving a write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host, the asynchronous first-in-first-out control signal transmission unit adjusts the write control signal from the low-frequency clock domain to the high-frequency clock domain;

[0091] Optionally, when the asynchronous first-in-first-out control signal transmission unit receives the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, the asynchronous first-in-first-out control signal transmission unit writes the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and when it is detected that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state;

[0092] The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

[0093] Sub-step S2: upon receiving the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host, the data signal transmission unit adjusts the write data signal from the low-frequency clock domain to the high-frequency clock domain;

[0094] When the data signal transmission unit receives the write data signal sent by the host-side low-frequency clock domain module, it determines the write data transmission signal corresponding to each transmission based on a preset second transmission depth value, stores the write data transmission signal in the corresponding memory module until the number of transmissions reaches the second transmission depth value, and reads all the write data transmission signals from the data transmission unit in sequence according to the order in which they are stored and written.

[0095] Sub-step S3: The asynchronous first-in first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the synchronously aligned write control signal and the write data signal to the chip-end high-frequency clock domain module.

[0096] Step 202: upon receiving a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, the high-frequency to low-frequency transmission submodule completes reading of corresponding data based on the read data signal.

[0097] An embodiment of the present invention provides a method for efficiently implementing pseudo-DDR signal cross-clock domains. Upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by a host-side low-frequency clock domain module, the low-frequency to high-frequency transmission submodule adjusts the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, performs synchronization alignment on the adjusted write control signal and the write data signal, and sends the synchronized write control signal and the write data signal to the chip-side high-frequency clock domain module. Upon receiving a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, the high-frequency to low-frequency transmission submodule completes reading of corresponding data based on the read data signal. This method can simultaneously handle scenarios with high timing requirements, such as synchronous cross-clock domain propagation between single-cycle and multi-cycle signals. It has a wide range of applications and can be applied to bidirectional cross-clock domain propagation of a large number of signals from a low-frequency domain to a high-frequency domain, or vice versa. This avoids metastable multi-domain propagation and improves circuit stability and reliability.

[0098] The present invention provides a method for efficiently implementing pseudo DDR signal cross-clock domain, which is applied to Figure 1 The circuit shown in the figure for efficiently implementing pseudo DDR signal crossing clock domains is not described here in detail to avoid repetition.

[0099] The electronic device in the embodiments of the present invention may be a device, or a component, integrated circuit, or chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device may be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. The non-mobile electronic device may be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc., and the embodiments of the present invention do not specifically limit this.

[0100] The electronic device in the embodiment of the present invention may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present invention.

[0101] Figure 7 FIG1 shows a hardware structure diagram of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device 300 includes a processor 310 .

[0102] like Figure 7 As shown, the processor 310 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention.

[0103] like Figure 7 As shown, the electronic device 300 may further include a communication line 340. The communication line 340 may include a path for transmitting information between the components.

[0104] Optional, such as Figure 7 As shown, the electronic device may further include a communication interface 320. There may be one or more communication interfaces 320. The communication interface 320 may be any transceiver or similar device for communicating with other devices or a communication network.

[0105] Optional, such as Figure 7 As shown, the electronic device may further include a memory 330. The memory 330 is used to store computer-executable instructions for executing the solution of the present invention, and is controlled by the processor to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0106] like Figure 7As shown, the memory 330 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these. The memory 330 can exist independently and be connected to the processor 310 via a communication line 340. The memory 330 can also be integrated with the processor 310.

[0107] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0108] In a specific implementation, as an embodiment, Figure 7 As shown, the processor 310 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 in.

[0109] In a specific implementation, as an embodiment, Figure 7 As shown, the terminal device may include multiple processors, such as Figure 7 The first processor 3101 and the second processor 3102 in the embodiment of the present invention are shown in FIG. Each of these processors can be a single-core processor or a multi-core processor.

[0110] Figure 8 FIG. 1 is a schematic diagram of the structure of the chip provided by an embodiment of the present invention. Figure 8 As shown, the chip 400 includes one or more (including two) processors 310 .

[0111] Optional, such as Figure 8 As shown, the chip also includes a communication interface 320 and a memory 330. The memory 330 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory (NVRAM).

[0112] In some embodiments, as Figure 8 As shown, the memory 330 stores the following elements, execution modules or data structures, or a subset thereof, or an extended set thereof.

[0113] In the embodiment of the present invention, Figure 8 As shown, corresponding operations are performed by calling an operation instruction stored in a memory (the operation instruction may be stored in an operating system).

[0114] like Figure 8 As shown, the processor 310 controls the processing operations of any terminal device, and the processor 310 can also be called a central processing unit (CPU).

[0115] like Figure 8 As shown, the memory 330 may include a read-only memory and a random access memory, and provides instructions and data to the processor. A portion of the memory 330 may also include NVRAM. For example, in an application, the memory, the communication interface, and the memory are coupled together through a bus system, wherein the bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, the following are not used in the following text: Figure 8 Various buses are labeled as bus system 450 .

[0116] like Figure 8As shown, the methods disclosed in the above embodiments of the present invention can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor may be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods, steps, and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in conjunction with the embodiments of the present invention can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in a memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0117] On the one hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed, the functions performed by the terminal device in the above embodiment are implemented.

[0118] On the one hand, a chip is provided, which is used in a terminal device. The chip includes at least one processor and a communication interface. The communication interface is coupled to the at least one processor, and the processor is used to run instructions to implement the functions performed by the circuit for efficiently implementing pseudo DDR signal crossing clock domains in the above embodiment.

[0119] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disc (DVD); or a semiconductor medium, such as a solid-state drive (SSD).

[0120] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0121] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A circuit for efficiently implementing pseudo DDR signal cross-clock domain, characterized in that: The circuit comprises: A chip-side high-frequency clock domain module, a plurality of cross-clock domain modules arranged on the chip-side high-frequency clock domain module, a host-side low-frequency clock domain module connected to the plurality of cross-clock domain modules, and a plurality of memory modules; The memory module is arranged on the chip-side high-frequency clock domain module, and a plurality of the memory modules are respectively connected to each of the cross-clock domain modules in a one-to-one correspondence; Each of the cross-clock domain modules includes a low-frequency to high-frequency transmission submodule and a high-frequency to low-frequency transmission submodule, one end of the low-frequency to high-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module, one end of the high-frequency to low-frequency transmission submodule is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; The low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module; The low-frequency to high-frequency transmission submodule includes an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit, one end of the asynchronous first-in-first-out control signal transmission unit is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; one end of the data signal transmission unit is connected to the chip-side high-frequency clock domain module, and the other end is connected to the host-side low-frequency clock domain module; The data signal transmission unit is configured to, upon receiving a write data signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, determine, based on a preset second transmission depth value, a write data transmission signal corresponding to each transmission, store the write data transmission signal in the corresponding memory module until the number of transmissions reaches the second transmission depth value, and sequentially read out all the write data transmission signals from the data transmission unit in the order in which they are stored and written; The high-frequency to low-frequency transmission submodule is used to complete the reading of corresponding data based on the read data signal when receiving the read data signal corresponding to the read operation instruction issued by the host-side low-frequency clock domain module.

2. The circuit for efficiently implementing pseudo DDR signal cross-clock domain according to claim 1, characterized in that: The low-frequency to high-frequency transmission submodule is used to, upon receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, adjust the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, perform synchronization alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module, including: The asynchronous first-in first-out control signal transmission unit is used to adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end; The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit are also used to perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the write control signal and the write data signal after the synchronous alignment processing to the chip-side high-frequency clock domain module.

3. The circuit for efficiently implementing pseudo DDR signal cross-clock domain according to claim 2, characterized in that: The asynchronous first-in-first-out control signal transmission unit is configured to adjust the write control signal from the low-frequency clock domain to the high-frequency clock domain upon receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host side, including: The asynchronous first-in-first-out control signal transmission unit is configured to, upon receiving the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, write the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and upon detecting that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state; The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

4. A method for efficiently implementing pseudo DDR signal cross-clock domain, characterized in that: The method applied to the circuit for efficiently implementing pseudo DDR signal crossing clock domains as claimed in any one of claims 1 to 3 comprises: Upon receiving a write control signal and a write data signal corresponding to a write operation instruction from the low-frequency clock domain module on the host side, the low-frequency to high-frequency transmission submodule adjusts the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, performs synchronization alignment processing on the adjusted write control signal and the write data signal, and sends the write control signal and the write data signal after the synchronization alignment processing to the high-frequency clock domain module on the chip side; When the high-frequency to low-frequency transmission submodule receives a read data signal corresponding to a read operation instruction issued by the host-side low-frequency clock domain module, the high-frequency to low-frequency transmission submodule completes reading of corresponding data based on the read data signal.

5. The method for efficiently implementing pseudo DDR signal cross-clock domain according to claim 4, characterized in that: The low-frequency to high-frequency transmission submodule includes an asynchronous first-in-first-out control signal transmission unit and a data signal transmission unit. When receiving a write control signal and a write data signal corresponding to a write operation instruction issued by the host-side low-frequency clock domain module, the low-frequency to high-frequency transmission submodule adjusts the write control signal and the write data signal from the low-frequency clock domain to the high-frequency clock domain, performs synchronization alignment processing on the adjusted write control signal and the write data signal, and sends the write control signal and the write data signal after the synchronization alignment processing to the chip-side high-frequency clock domain module, including: The asynchronous first-in-first-out control signal transmission unit adjusts the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end; When the data signal transmission unit receives the write data signal corresponding to the write operation instruction issued by the low-frequency clock domain module on the host side, the data signal transmission unit determines, according to a preset second transmission depth value, a write data transmission signal corresponding to each transmission, stores the write data transmission signal in a corresponding memory module until the number of transmissions reaches the second transmission depth value, sequentially reads all the write data transmission signals from the data transmission unit in the order of storage and writing, and adjusts the write data signal from the low-frequency clock domain to the high-frequency clock domain; The asynchronous first-in-first-out control signal transmission unit and the data signal transmission unit perform synchronous alignment processing on the adjusted write control signal and the write data signal, and send the synchronously aligned write control signal and the write data signal to the chip-side high-frequency clock domain module.

6. The method for efficiently implementing pseudo DDR signal cross-clock domain according to claim 5, characterized in that: The asynchronous first-in-first-out control signal transmission unit adjusts the write control signal from the low-frequency clock domain to the high-frequency clock domain when receiving the write control signal corresponding to the write operation instruction issued by the low-frequency clock domain module of the host end, including: The asynchronous first-in-first-out control signal transmission unit, upon receiving the write control signal corresponding to the write operation instruction issued by the host-side low-frequency clock domain module, writes the write control signal into the asynchronous first-in-first-out control signal transmission unit according to a preset first transmission depth value and upon detecting that the asynchronous first-in-first-out control signal transmission unit is in a preset normal state; The preset normal state means that the asynchronous first-in first-out control signal transmission unit is not full and is not in a non-reading and non-writing state.

7. An electronic device, characterized in that: include: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, enable the electronic device to execute the method for efficiently implementing pseudo DDR signal crossing clock domains as described in any one of claims 4-6.

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