Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and a method for fabricating the same. The method for fabricating a semiconductor structure includes the following steps: providing a substrate and forming a first trench within the substrate; forming a protective layer within the first trench, the protective layer covering the sidewalls and bottom of the first trench; etching the protective layer and the substrate at the bottom of the first trench to form a second trench; forming a passivation layer at the bottom of the second trench; and etching the sidewalls of the second trench to form a groove, within which a dielectric layer is formed. This method for fabricating the semiconductor structure eliminates the bit line contact structure process, thereby reducing the resistance of the bit lines and simplifying the bit line fabrication process.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source, and a drain. The gate of the transistor is used to electrically connect to the word line. The source of the transistor forms a bit line contact region to electrically connect to the bit line through a bit line contact structure. The drain of the transistor forms a memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0003] In memory devices employing Vertical Gate All Around (VGAA) transistors, buried word lines and buried bit lines can simplify the structure between the array device and the capacitor (e.g., bit line contact structure). However, current buried bit lines still suffer from high resistance and complex fabrication processes for bit line contact structures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems of high resistance and complex fabrication process of embedded bit lines in existing technologies.

[0005] A method for fabricating a semiconductor structure includes the following steps: providing a substrate and forming a first trench within the substrate; forming a protective layer within the first trench, the protective layer covering the sidewalls and bottom of the first trench; etching the protective layer and the substrate at the bottom of the first trench to form a second trench; forming a passivation layer at the bottom of the second trench; etching the sidewalls of the second trench to form a groove, and forming a dielectric layer within the groove.

[0006] In some embodiments, the groove connects to an adjacent second trench.

[0007] In some embodiments, the dielectric layer includes a metal layer; forming the dielectric layer in the groove includes filling the groove with a metal layer.

[0008] In some embodiments, the dielectric layer includes a metal silicide layer and a metal layer; forming the dielectric layer in the groove includes: forming a metal silicide layer covering the sidewalls and bottom of the groove; and forming a metal layer covering the metal silicide layer.

[0009] In some embodiments, forming a passivation layer at the bottom of the second trench includes: performing plasma injection on a substrate exposed at the bottom of the second trench to convert a portion of the substrate into a passivation layer.

[0010] In some embodiments, the sidewalls of the second trench are etched using an anisotropic etching process.

[0011] In some embodiments, the etching dimension of the sidewall of the second trench in a first direction is greater than its etching dimension in a second direction; wherein the first direction is a direction perpendicular to the sidewall of the second trench, and the second direction is a direction perpendicular to the substrate.

[0012] In some embodiments, the etching dimension of the sidewall of the second trench in the first direction is greater than the height of the second trench in the second direction; wherein the first direction is perpendicular to the sidewall of the second trench, and the second direction is perpendicular to the substrate.

[0013] In some embodiments, the groove includes a bit line trench; forming a dielectric layer within the groove includes forming a bit line within the groove.

[0014] In some embodiments, the preparation method further includes: filling the first trench with insulating material; etching back the substrate after filling with insulating material to form a word line trench; and forming word lines in the word line trench.

[0015] Based on the same inventive concept, this disclosure also provides a semiconductor structure that can be prepared by the preparation methods described in some of the foregoing embodiments.

[0016] The semiconductor structure includes a substrate, a protective layer, and a dielectric layer. A first trench and a recess located below the first trench are formed within the substrate. The protective layer covers the sidewalls of the first trench. The dielectric layer fills the recess.

[0017] In some embodiments, the semiconductor structure further includes a passivation layer located at the bottom of the groove. The dielectric layer also covers the passivation layer.

[0018] In some embodiments, the groove includes a bit line trench; the dielectric layer includes a bit line.

[0019] In some embodiments, the bit line includes a metal line; or, the bit line includes a metal silicide layer covering the sidewalls and bottom of the recess, and a metal layer covering the metal silicide layer.

[0020] In some embodiments, the lower surface of the bit line extends in a wavy shape along a first direction.

[0021] In some embodiments, the semiconductor structure further includes: an insulating layer disposed within a first trench, and a plurality of word lines disposed in parallel and spaced apart. The bit lines extend along a first direction; the word lines are located above the bit lines and extend along a third direction; the third direction intersects the first direction. Adjacent word lines are insulated by the insulating layer, and word lines and bit lines are insulated from each other by the insulating layer.

[0022] In this embodiment, a first trench can be formed within a substrate, and a protective layer covering the sidewalls and bottom of the first trench can be formed within the first trench. Next, the protective layer at the bottom of the first trench and the substrate can be etched to form a second trench. Then, before etching the sidewalls of the second trench to form a groove and before forming a dielectric layer within the groove, a passivation layer can be formed at the bottom of the second trench. This allows the passivation layer to effectively protect the substrate at the bottom of the second trench during groove formation and helps ensure that the groove is formed in a direction perpendicular to the sidewalls of the second trench.

[0023] Therefore, this disclosure provides a method for conveniently fabricating other layer structures (i.e., dielectric layers) at the bottom of a trench. The method involves controlling the depth of the second trench to ensure the structural dimensions of the dielectric layer, and obtaining the dielectric layer by etching the sidewalls of the second trench to form a groove followed by filling, so that the dielectric layer is located at the bottom of the first trench and in direct contact with the portion enclosed by the first trench. Furthermore, during the fabrication of the dielectric layer, a protective layer can effectively protect the sidewalls of the first trench, and a passivation layer can effectively protect the substrate portion at the bottom of the second trench, thereby preventing the fabrication of the dielectric layer from having other effects on the substrate and the sidewalls of the first trench.

[0024] Based on this, after applying the above-described fabrication method provided in this embodiment to DRAM, the dielectric layer can be fabricated as an embedded bit line. The portion enclosed by the sidewall of the first trench includes the active portion of the VGAA, and the groove is a bit line trench. Thus, after forming the groove, a dielectric layer can be formed within the groove to form the bit line, ensuring that the bit line is located below and connected to the active portion of the VGAA, thereby eliminating the need to fabricate a bit line contact structure; that is, the bit line contact structure process can be eliminated from the DRAM fabrication process, simplifying the DRAM fabrication process. Furthermore, in the above-described fabrication method, the bit line can be formed by filling the groove with dielectric material, facilitating the selection of the bit line forming material to form a bit line with lower resistance, thereby improving the electrical performance of the DRAM. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a storage unit provided in one embodiment;

[0027] Figure 2 This is a schematic diagram showing the distribution of bit lines and word lines in a semiconductor structure provided in one embodiment;

[0028] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure as provided in one embodiment;

[0029] Figures 4 to 20 These are cross-sectional views along the A-A' and B-B' directions of the structure obtained in each step of the fabrication method of a semiconductor structure provided in one embodiment; and, Figure 19 and Figure 20 This is also a schematic diagram of a semiconductor structure in one embodiment.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100 - Memory cell; 11 - Substrate; 111 - Shallow trench isolation structure; 12 - First trench;

[0032] 13-Protective layer; 14-Second trench; 15-Passivation layer; 16-Groove; 17-Dielectric layer;

[0033] 10 - Bit line; 20 - Columnar structure; 201 - Source; 202 - Conductive channel; 203 - Drain;

[0034] 30 - Letter bar; 31 - Insulation layer; 310 - Insulation material; G - Letter bar groove; 40 - Storage capacitor. Detailed Implementation

[0035] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0041] Gate-all-around transistors (GABOTs) offer advantages in miniaturization, high performance, and low power consumption, and are considered a key core technology for next-generation integrated circuits. Taking the vertical GABOT transistor as an example, this transistor offers greater integration freedom in the vertical direction, effectively reducing its planar area, facilitating vertical stacking of multi-layer devices, and further increasing integration density through novel wiring methods.

[0042] Please see Figure 1 This disclosure provides a semiconductor structure, such as a memory cell 100 in a DRAM. The memory cell 100 includes a vertical-all-around gate transistor (VAG) and a storage capacitor 40 located above and connected to the VGA. The VGA can be a pillar structure 20, which includes a source 201, a conductive channel 202, and a drain 203 arranged from bottom to top. The source 201 is connected to a bit line 10. The drain 203 is connected to the storage capacitor 40. A word line 30 is disposed around the conductive channel 202, and a gate dielectric layer is disposed between the conductive channel 202 and the word line 30. Figure 1 (Not shown in the image). The portion of word line 30 located on the periphery of conductive channel 202 can be used as the gate of a vertical all-around gate transistor.

[0043] It should be added that, please combine, Figure 1 and Figure 2 As described above, the memory cells 100 can be arranged in an array on a substrate, with each row of memory cells 100 connected to a word line 30, and each column of memory cells 100 connected to a bit line 10, to form a semiconductor structure. Multiple bit lines 10 are distributed in parallel at intervals, and each bit line 10 is along a first direction (e.g., ...). Figure 2 Extending in the X direction, multiple character lines 30 are distributed in parallel at intervals, and each character line 30 is along a third direction (e.g., in the X direction). Figure 2 (Extends in the Y direction).

[0044] In memory devices employing vertical gate-all-around (VGAA) transistors, buried word lines and buried bit lines can simplify the structure between the array device and the capacitor (e.g., bit line contact structure). However, current buried bit lines still suffer from high resistance and complex fabrication processes for bit line contact structures.

[0045] This disclosure provides a method for fabricating a semiconductor structure, which can be applied to the fabrication of DRAM. Furthermore, the semiconductor structure fabrication method described in this disclosure can solve the problems of high resistance and complex bit line contact structure fabrication processes in current embedded bit lines.

[0046] Please see Figure 3 The method for preparing a semiconductor structure provided in this embodiment includes steps S10 to S50.

[0047] S10 provides a substrate in which a first trench is formed.

[0048] S20, a protective layer is formed in the first trench, the protective layer covering the sidewalls and bottom of the first trench.

[0049] S30, etch the protective layer and substrate at the bottom of the first trench to form the second trench.

[0050] S40, a passivation layer is formed at the bottom of the second trench.

[0051] S50, the sidewalls of the second trench are etched to form a groove, and a dielectric layer is formed in the groove.

[0052] In some examples, the trench can be a bit line trench in a DRAM, and the dielectric layer can be a conductive layer. Forming a dielectric layer within the trench can be equivalent to forming a bit line within the trench. However, it is not limited to this; the dielectric layer can also be used to form other conductive structures.

[0053] In other examples, grooves can be used to form other types of bottom linear structures besides conductive structures. For example, the dielectric layer can be an insulating layer, and forming a dielectric layer in a groove can be seen as forming a bottom isolation structure in the groove.

[0054] In this embodiment, a first trench can be formed within a substrate, and a protective layer covering the sidewalls and bottom of the first trench can be formed within the first trench. Next, the protective layer at the bottom of the first trench and the substrate can be etched to form a second trench. Then, before etching the sidewalls of the second trench to form a groove and before forming a dielectric layer within the groove, a passivation layer can be formed at the bottom of the second trench. This allows the passivation layer to effectively protect the substrate at the bottom of the second trench during groove formation and helps ensure that the groove is formed in a direction perpendicular to the sidewalls of the second trench.

[0055] Therefore, this disclosure provides a method for conveniently fabricating other layer structures (i.e., dielectric layers) at the bottom of a trench. The method involves controlling the depth of the second trench to ensure the structural dimensions of the dielectric layer, and obtaining the dielectric layer by etching the sidewalls of the second trench to form a groove followed by filling, so that the dielectric layer is located at the bottom of the first trench and in direct contact with the portion enclosed by the first trench. Furthermore, during the fabrication of the dielectric layer, a protective layer can effectively protect the sidewalls of the first trench, and a passivation layer can effectively protect the substrate portion at the bottom of the second trench, thereby preventing the fabrication of the dielectric layer from having other effects on the substrate and the sidewalls of the first trench.

[0056] Based on this, after applying the above-described fabrication method provided in this embodiment to a DRAM, the dielectric layer can be fabricated as an embedded bit line, for example. For instance, the exposed portion of the first trench sidewall includes the active portion of the VGAA (i.e., the columnar structure 20), and the groove is a bit line trench. Thus, after forming the groove, a dielectric layer can be formed within the groove to form the bit line, ensuring that the bit line is located below and connected to the active portion of the VGAA, thereby eliminating the need to fabricate a bit line contact structure; that is, the bit line contact structure process can be eliminated from the DRAM fabrication process, simplifying the DRAM fabrication process. Furthermore, in the above-described fabrication method, the bit line can be formed by filling the groove with dielectric material, facilitating the selection of the bit line forming material to form a bit line with lower resistance, thereby improving the electrical performance of the DRAM.

[0057] The following combination Figures 4 to 17 The application of the semiconductor structure fabrication method in DRAM according to the embodiments of this disclosure is described in detail.

[0058] In step S10, please refer to Figure 4 and Figure 5 A substrate 11 is provided, and a first trench 12 is formed in the substrate 11.

[0059] It is understood that before forming the first trench 12 within the substrate 11, a shallow trench can be formed within the substrate 11, and a shallow trench isolation structure 111 can be formed within the shallow trench; that is, the provided substrate 11 may include the shallow trench isolation structure 111. The shallow trench isolation structure 111 can isolate multiple active regions on the substrate 11. Next, a portion of the material located within the active regions of the substrate 11 and a portion of the shallow trench isolation structure 111 can be removed to form the first trench 12 within the substrate 11. The first trench 12 extends, for example, along a third direction, such as the Y direction.

[0060] For example, substrate 11 includes, but is not limited to, silicon substrate, germanium substrate, silicon-germanium substrate or silicon nitride substrate.

[0061] For example, the shallow trench isolation structure 111 includes, but is not limited to, oxides, such as silicon oxide.

[0062] In this embodiment of the disclosure, when the first trench 12 is formed, a portion of the sidewall of the columnar structure 20 in the VGAA may be exposed within the first trench 12. For example, the depth of the first trench 12 is equal to the height of the columnar structure 20. That is, the formation depth of the first trench 12 can be limited by the height of the columnar structure 20.

[0063] After forming the first trench 12, the method for fabricating the semiconductor structure further includes: performing ion implantation on the lower and upper portions of the columnar structure 20 respectively to form a source, a drain, and a conductive channel located between the source and the drain. The source is located in the lower portion of the columnar structure 20, and the drain is located in the upper portion of the columnar structure 20. The types of ions implanted to form the source and drain are different, and this embodiment does not specifically limit this. Furthermore, the depth of ion implantation required to form the source and drain can be selected and set according to actual needs.

[0064] In step S20, please refer to Figure 6 and Figure 7 A protective layer 13 is formed in the first trench 12, and the protective layer 13 covers the sidewalls and bottom of the first trench 12.

[0065] For example, the protective layer 13 includes, but is not limited to, nitrides, such as silicon nitride.

[0066] For example, the protective layer 13 also covers the top of the columnar structure 20 and the shallow trench isolation structure 111, as well as the sidewalls exposed within the first trench 12. That is to say, the protective layer 13 can be deposited directly on one side of the resulting structure after the first trench 12 has been formed.

[0067] Optionally, the protective layer 13 may be deposited by, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0068] In this embodiment of the disclosure, by forming a protective layer 13, structures on the substrate 11 that do not need to be etched can be protected during subsequent etching processes, such as protecting the sidewalls of the first trench 12, so as to avoid damage to these structures during the etching process.

[0069] In step S30, please refer to Figure 8 and Figure 9 The protective layer 13 and the substrate 11 at the bottom of the first trench 12 are etched to form the second trench 14.

[0070] After the first trench 12 and the protective layer 13 are formed, the protective layer 13 located at the bottom of the first trench 12 can be removed to expose the substrate 11 located below the first trench 12. Then, the substrate 11 can be etched on the basis of the first trench 12 to form the second trench 14.

[0071] For example, the protective layer 13 located at the bottom of the first trench 12 can be removed by dry etching, which can precisely control the etching area and etching direction to avoid the protective layer 13 covering the sidewall of the first trench 12 being etched simultaneously.

[0072] Alternatively, during the process of removing the protective layer 13 located at the bottom of the first trench 12, the portion of the protective layer 13 covering the top of the columnar structure 20 can also be simultaneously etched away.

[0073] For example, the second trench 14 is formed by removing a portion of the substrate 11 located at the bottom of the first trench 12, and the formation depth of the second trench 14 can be matched to the height of the dielectric layer to be formed. Optionally, the sum of the depths of the first trench 12 and the second trench 14 is less than the height of the shallow trench isolation structure 111. This facilitates effective isolation of adjacent dielectric layers using the shallow trench isolation structure 111 after the dielectric layer is formed. For example, when the dielectric layer is used to form bit lines, the shallow trench isolation structure 111 can also be used to isolate adjacent bit lines to avoid electrical coupling between adjacent bit lines.

[0074] In step S40, please refer to Figure 10 and Figure 11 A passivation layer 15 is formed at the bottom of the second trench 14.

[0075] In some embodiments, forming a passivation layer 15 at the bottom of the second trench 14 includes: performing plasma injection on a substrate 11 exposed at the bottom of the second trench 14 to convert a portion of the substrate 11 into the passivation layer 15.

[0076] For example, boron ions can be used to plasma implant the substrate 11 to transform a portion of the substrate 11 into a passivation layer 15. It should be understood that the passivation layer 15 is a structure formed jointly by the implanted ions and the substrate 11. For example, when the substrate 11 is a silicon substrate, the passivation layer 15 is a structure formed jointly by boron and silicon, that is, a structure formed by doping boron in silicon.

[0077] For example, the thickness of the passivation layer 15 can be selected according to actual needs. For instance, the thickness of the passivation layer 15 may be less than or equal to one-fifth of the height of the second trench 14.

[0078] In step S50, please refer to Figures 12-15 The sidewall of the second trench 14 is etched to form a groove 16, and a dielectric layer 17 is formed in the groove 16.

[0079] like Figure 12 and Figure 13 As shown, after the passivation layer 15 is formed, the sidewalls of the second trench 12 can be etched to connect adjacent second trenches 12 along a first direction (e.g., the X direction), such as a column direction, thereby forming a groove 16 located below a plurality of columnar structures 20 in the same column.

[0080] For example, the groove 16 connects to the adjacent second groove 14 and extends along a first direction (e.g., the X direction). This creates an extending channel beneath the columnar structure 20 to facilitate the formation of a bitline groove in the groove 16, thereby forming an embedded bitline by filling the groove 16 with a dielectric layer 17.

[0081] For example, the sidewalls of the second trench 14 are etched using an anisotropic etching process. Anisotropic etching refers to etching that occurs at different rates in different directions. For the process of forming the trench in this embodiment, the etching rate of the sidewalls of the second trench 14 along a first direction (e.g., the X direction) is greater than the etching rate of the sidewalls of the second trench 14 along a second direction (e.g., the Z direction). Here, the etching rates of the second trench 14 along different directions can be selected and determined based on the structure of the dielectric layer 17 to be formed.

[0082] In this embodiment of the disclosure, the anisotropic etching process has high etching precision. Therefore, using the anisotropic etching process to etch the sidewall of the second trench 14 can achieve fine control over the forming contour of the groove 16.

[0083] Alternatively, please continue reading Figure 12The etching dimension d1 of the sidewall of the second trench 14 in the first direction (e.g., the X direction) is greater than its etching dimension d2 in the second direction (e.g., the Z direction); wherein the first direction (e.g., the X direction) is perpendicular to the sidewall of the second trench 14, and the second direction (e.g., the Z direction) is perpendicular to the substrate 11.

[0084] Alternatively, please continue reading Figure 12 The etching dimension d1 of the sidewall of the second trench 14 in the first direction (e.g., the X direction) is greater than the height h of the second trench 14 in the second direction (e.g., the Z direction); wherein the first direction (X direction) is perpendicular to the sidewall of the second trench 14, and the second direction (Z direction) is perpendicular to the substrate 11.

[0085] In this embodiment of the disclosure, by controlling the etching dimension d1 of the sidewall of the second trench 14 in the first direction (e.g., the X direction) to be greater than its etching dimension d2 in the second direction (e.g., the Z direction), and controlling the etching dimension d1 of the sidewall of the second trench 14 in the first direction (e.g., the X direction) to be greater than the height h of the second trench 14 in the second direction (e.g., the Z direction) (i.e., controlling the etching degree of the sidewall of the second trench 14 in the first direction to be greater than its etching degree in the second direction), the groove 16 can extend along a direction perpendicular to the sidewall of the second trench 14 to form a channel, while reducing the etching of the substrate 11 below the second trench 14, thereby avoiding the excessive depth of the groove 16 and causing over-etching.

[0086] For example, a portion of the lower surface of the groove 16 may be lower than the surface of the passivation layer 15. This means that during etching, the portion of the substrate 11 not covered by the passivation layer 15 can be easily etched away, resulting in a curved lower surface of the groove 16. For instance, the lower surface of the groove 16 may extend in a wavy pattern along a first direction. However, this is not a limitation; for example, the passivation layer 15 may be removed simultaneously with the formation of the groove 16, or removed after the formation of the groove 16.

[0087] like Figure 14 and Figure 15 As shown, after the groove 16 is formed, a dielectric layer 17 can be formed inside the groove 16.

[0088] For example, the lower surface of the dielectric layer 17 matches the lower surface of the groove 16 and extends in a wavy shape along a first direction (e.g., the X direction).

[0089] For example, the dielectric layer 17 can be deposited along the first trench 12 into the groove 16.

[0090] Optionally, the deposition method of the dielectric layer 17 includes, but is not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0091] For example, dielectric layer 17 includes a conductive layer or an insulating layer. When dielectric layer 17 is a conductive layer, it can be used, for example, to form bit lines. When dielectric layer 17 is an insulating layer, it can be used, for example, to form a bottom isolation structure.

[0092] It should be understood that the dielectric layer 17 can be a single-layer structure or a multilayer structure.

[0093] In some examples, the dielectric layer 17 includes a metal layer; forming the dielectric layer 17 within the groove 16 includes filling the groove 16 with a metal layer.

[0094] Optionally, the material of the metal layer includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), or tantalum (Ta).

[0095] In this embodiment of the disclosure, by filling the groove 16 with a metal layer to form a dielectric layer 17, the resistance of the dielectric layer 17 can be reduced, thereby improving the electrical performance of the semiconductor structure.

[0096] In other examples, the dielectric layer 17 includes a metal silicide layer and a metal layer. Forming the dielectric layer 17 within the recess 16 includes: forming a metal silicide layer covering the sidewalls and bottom of the recess 16; and forming a metal layer covering the metal silicide layer.

[0097] Optionally, the substrate 11 is a silicon substrate, and the metal silicide includes, but is not limited to, tantalum silicide (Ta5Si3), cobalt silicide (CoSi2) or tungsten silicide (WSi2).

[0098] In this embodiment of the disclosure, forming a metal silicide layer before forming a metal layer can further reduce the resistance of the dielectric layer 17, thereby helping to further improve the electrical performance of the semiconductor structure.

[0099] In some embodiments, the groove 16 includes a bit line trench; forming a dielectric layer 17 within the groove 16 includes forming a bit line within the groove 16.

[0100] The metal layer or the stacked structure formed by the metal layer and the metal silicide layer in some of the foregoing embodiments can be used as a bit line.

[0101] In some embodiments, please refer to Figures 16-20 The preparation method in this embodiment further includes the following steps.

[0102] like Figure 16 As shown, the first trench 12 is filled with insulating material 310.

[0103] like Figure 17 and Figure 18 As shown, the substrate 11 after being etched back to fill the insulating material 310 forms word line trenches G.

[0104] Here, the word line trench G can be formed by removing part of the insulating material 310 and part of the shallow trench isolation structure 111. Furthermore, after forming the word line trench G, the remaining insulating material 310 can form an insulating layer 31 located within the first trench 12.

[0105] like Figure 19 and Figure 20 As shown, a word line 30 is formed within the word line groove G. The word line 30 extends in a third direction (e.g., the Y direction).

[0106] It is understood that in this embodiment of the present disclosure, the word line 30 is located below the surface of the substrate 11, that is, the word line 30 is a buried word line. Furthermore, adjacent word lines 30 can be insulated from each other by an insulating layer 31.

[0107] For example, word line 30 includes a gate word line, and the portion of word line 30 located on the periphery of the conductive channel can be used as the gate of a vertical all-around gate transistor. Furthermore, a gate dielectric layer (not shown) can be formed between word line 30 and the conductive channel of pillar structure 20.

[0108] For example, the material of insulating layer 31 includes, but is not limited to, oxides, such as silicon oxide.

[0109] For example, the forming material of the word line 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof.

[0110] In this embodiment, bit lines can be directly formed by forming a dielectric layer 17 within the groove 16, i.e., forming embedded bit lines located below the columnar structure 20. This ensures that the bit line is connected to the columnar structure 20, thus eliminating the need to fabricate bit line contact structures; that is, the bit line contact structure process can be eliminated from the DRAM fabrication process, simplifying the DRAM fabrication process. Furthermore, in this embodiment, the size of the groove 16 can be used to constrain the structure of the bit lines, thereby simplifying the bit line fabrication process while precisely controlling the size of the bit lines to avoid electrical coupling between adjacent bit lines.

[0111] Furthermore, it is understood that the formation height of the word line 30 can be selected and set according to requirements. Optionally, an isolation structure can also be formed above the word line 30 to insulate the word line 30 from other conductive structures on the surface of the substrate 11. Optionally, the protective layer 13 located at the top of the pillar structure 20 can be etched away to expose the top of the pillar structure 20, thereby facilitating the formation of storage node contact structures or storage capacitors, etc., on the top of the pillar structure 20.

[0112] Based on the same inventive concept, this disclosure also provides a semiconductor structure that can be prepared by the preparation methods described in some of the foregoing embodiments.

[0113] Please see Figure 19 and Figure 20 The semiconductor structure includes a substrate 11, a protective layer 13, and a dielectric layer 17. The substrate 11 has a first trench 12 and a recess 16 located below the first trench 12. The protective layer 13 covers the sidewalls of the first trench 12. The dielectric layer 17 fills the recess 16.

[0114] In some examples, the semiconductor structure also includes a passivation layer 15 located at the bottom of the recess 16. A dielectric layer 17 also covers the passivation layer 15.

[0115] In some examples, the recess 16 can be a bit line trench in a DRAM, and the dielectric layer 17 can be formed of a conductive material; the dielectric layer 17 includes bit lines. In other examples, the dielectric layer 17 can be formed of a composite material; the dielectric layer 17 includes, for example, a bottom isolation structure formed of an insulating material and a bit line conductive structure formed of a conductive material.

[0116] For example, substrate 11 includes, but is not limited to, silicon substrate, germanium substrate, silicon-germanium substrate or silicon nitride substrate.

[0117] Optionally, the substrate 11 includes a shallow trench isolation structure 11. The shallow trench isolation structure 111 can isolate multiple active regions on the substrate 11. The first trench 12 can be formed by removing a portion of the material located in the active region of the substrate 11 and a portion of the shallow trench isolation structure 111.

[0118] For example, the substrate 11 also includes a plurality of pillar structures 20. The pillar structures 20 are located within the active region, and the first trench 12 exposes at least a portion of the sidewalls of the pillar structures 20 and the shallow trench isolation structure 111. Optionally, the pillar structure 20 includes a source, a conductive channel, and a drain disposed from bottom to top.

[0119] The aforementioned protective layer 13 also covers the shallow trench isolation structure 111 and the sidewalls of the columnar structure 20 exposed within the first trench 12. Optionally, the shallow trench isolation structure 111 includes, but is not limited to, oxides, such as silicon oxide. Optionally, the protective layer 13 includes, but is not limited to, nitrides, such as silicon nitride.

[0120] In this embodiment of the disclosure, the semiconductor structure includes a substrate 11, wherein a first trench 12 and a recess 16 located below the first trench 12 are provided in the substrate 11. In some embodiments, the recess 16 includes bit line trenches; the dielectric layer 17 includes bit lines. The bit lines here are buried bit lines located at the bottom of the substrate 11. Furthermore, the bottom surface of the dielectric layer 17 is typically higher than the bottom surface of the shallow trench isolation structure 11, so that the shallow trench isolation structure 111 can effectively isolate adjacent dielectric layers 17 to avoid electrical coupling between adjacent bit lines.

[0121] In some embodiments, the bit line includes a metal line; or, the bit line includes a metal silicide layer covering the sidewalls and bottom of the recess 16, and a metal layer covering the metal silicide layer.

[0122] For example, the materials of the metal wire include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), or tantalum (Ta).

[0123] For example, substrate 11 is a silicon substrate, and the metal silicide includes, but is not limited to, tantalum silicide (Ta5Si3), cobalt silicide (CoSi2) or tungsten silicide (WSi2).

[0124] In this embodiment of the disclosure, using metal lines as bit lines, or using a stacked structure of metal silicide layers and metal layers as bit lines, is beneficial to reduce the resistance of the bit lines, thereby effectively improving the electrical performance of the semiconductor structure.

[0125] In some embodiments, please refer to Figure 19 The lower surface of the bit line extends in a wavy shape along a first direction (e.g., the X direction).

[0126] In some embodiments, please refer to Figure 19 and Figure 20 The semiconductor structure further includes an insulating layer 31 disposed within the first trench 12, and a plurality of parallel-spaced word lines 30. The bit lines extend along a first direction (e.g., the X direction); the word lines 30 are located above the bit lines and extend along a third direction (e.g., the Y direction); the third direction (e.g., the Y direction) intersects the first direction (e.g., the X direction), for example, perpendicularly. Adjacent word lines 30 are insulated from each other by the insulating layer 31. Furthermore, word lines 30 and bit lines are also insulated from each other by the insulating layer 31.

[0127] Understandably, in this embodiment of the disclosure, the bit lines are embedded bit lines and the word lines are embedded word lines.

[0128] For example, the material of word line 30 includes, but is not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof.

[0129] For example, word line 30 includes a gate word line, and the portion of word line 30 located on the periphery of the conductive channel can be used as the gate of a vertical all-around gate transistor. Furthermore, a gate dielectric layer (not shown) is disposed between word line 30 and the conductive channel of pillar structure 20.

[0130] In some embodiments, the passivation layer 15 is located directly below the first trench 12, and the orthographic projection of the passivation layer 15 onto the substrate 11 may partially overlap with the orthographic projection of the first trench 12 onto the substrate 11. The passivation layer 15 may be formed, for example, by implanting boron ions into the substrate 11. The passivation layer 15 covers a portion of the bottom surface of the groove 16.

[0131] For example, the thickness of the passivation layer 15 can be selected and set according to actual needs. Optionally, the thickness of the passivation layer 15 is less than one-fifth of the maximum thickness of the dielectric layer 17 (e.g., bit line).

[0132] The semiconductor structure provided in this embodiment is formed using the fabrication methods described in some of the foregoing embodiments. The groove 16 is, for example, a bit line trench, and the dielectric layer 17 is, for example, a buried bit line. The bit line can be located below and connected to the pillar structure 20, thus eliminating the need for bit line contact structures. That is, the bit line contact structure process can be eliminated during DRAM fabrication, simplifying the DRAM fabrication process. Furthermore, in the above fabrication method, the bit line can be formed by filling the groove 16 with dielectric material, facilitating the selection of the bit line forming material to form bit lines with lower resistance, thereby improving the electrical performance of the DRAM.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first trench is formed within the substrate; A protective layer is formed within the first trench, the protective layer covering the sidewalls and bottom of the first trench; The protective layer and substrate at the bottom of the first trench are etched to form the second trench; A passivation layer is formed at the bottom of the second trench; The sidewalls of the second trench are etched to form a groove, and a conductive layer or an insulating layer is formed in the groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The groove connects to the adjacent second groove.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The conductive layer includes a metal layer; forming the conductive layer in the groove includes filling the groove with the metal layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The conductive layer includes a metal silicide layer and a metal layer; The conductive layer is formed within the groove, comprising: A metal silicide layer is formed covering the sidewalls and bottom of the groove; A metal layer is formed covering the metal silicide layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, A passivation layer is formed at the bottom of the second trench, including: Plasma injection is performed on the substrate exposed at the bottom of the second trench to transform a portion of the substrate into the passivation layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sidewalls of the second trench are etched using an anisotropic etching process.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The etching dimension of the sidewall of the second trench in the first direction is greater than its etching dimension in the second direction; wherein the first direction is perpendicular to the sidewall of the second trench, and the second direction is perpendicular to the substrate.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The etching dimension of the sidewall of the second trench in the first direction is greater than the height of the second trench in the second direction; wherein, the first direction is perpendicular to the sidewall of the second trench, and the second direction is perpendicular to the substrate.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 8, characterized in that, The groove includes a bit line trench; forming the conductive layer in the groove includes forming a bit line in the groove.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The preparation method further includes: Fill the first trench with insulating material; The substrate after being filled with the insulating material is etched back to form word line trenches; Character lines are formed within the character line groove.

11. A semiconductor structure, said semiconductor structure being prepared by the preparation method according to any one of claims 1-10, characterized in that, include: A substrate having a first trench and a groove located below the first trench; A protective layer covering the sidewalls of the first trench; And a conductive or insulating layer, filling the groove.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure further includes: a passivation layer located at the bottom of the groove; the conductive layer or the insulating layer further covers the passivation layer.

13. The semiconductor structure according to claim 11, characterized in that, The groove includes bit line trenches; the conductive layer is used to form bit lines.

14. The semiconductor structure according to claim 13, characterized in that, The bit line includes a metal layer; Alternatively, the bit line may include a metal silicide layer covering the sidewalls and bottom of the groove, and a metal layer covering the metal silicide layer.

15. The semiconductor structure according to claim 13 or 14, characterized in that, The semiconductor structure further includes: an insulating layer disposed in the first trench, and a plurality of word lines disposed in parallel and spaced apart; Wherein, the bit line extends along a first direction; the word line is located above the bit line and extends along a third direction; the third direction intersects with the first direction; Adjacent word lines are insulated by the insulating layer, and the word lines and bit lines are insulated from each other by the insulating layer.

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