An RC-LIGBT device integrating four MOSFETs

Abstract

The present invention relates to an RC-LIGBT device integrating four MOSFETs, belonging to the field of semiconductor technology. The device comprises a cathode P+ region, a cathode N+ region, a cathode P-well region, a drift region, a buried oxide layer, a substrate, an anode P+ region, an anode P-well region, an anode N-buffer region, a common MOS metal gate, a common MOS gate oxide layer, an anode N+ region, an anode floating N+ region, a channel MOS metal gate, an anode auxiliary MOS metal gate, an anode floating MOS metal gate, a channel MOS gate oxide layer, an anode auxiliary MOS gate oxide layer and an anode floating MOS gate oxide layer. The present invention improves the reverse recovery performance and reverse conduction performance of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to an RC-LIGBT device integrating four MOSFETs. Background Art

[0002] LIGBT (Lateral Insulated Gate Bipolar Transistor) is a bipolar semiconductor power device that combines MOSFET and BJT tubes. It has the advantages of low on-state voltage, low driving power consumption and high operating frequency. It is widely used in communication technology, new energy equipment and various consumer electronics fields. It is a core device of electronic power systems. LIGBT is easy to integrate on Si substrate and is usually used in SOI-based power intelligent systems.

[0003] Since LIGBT does not have the ability to conduct in the reverse direction, a reverse freewheeling diode is usually connected in parallel next to the LIGBT for protection in actual use. At the same time, in order to improve the integration of devices and reduce manufacturing costs, people began to try to integrate the protective freewheeling diode inside the LIGBT, forming RC-LIGBT (Reverse-Conducting Lateral Insulated Gate Bipolar Transistor). The emergence of RC-LIGBT significantly simplifies the topology of intelligent power circuits, reduces parasitic parameters and reduces chip area, but there are also some disadvantages that cannot be ignored.

[0004] Taking SA-LIGBT as an example of traditional RC-LIGBT, the anode N+ region and P+ region of SA-LIGBT (Short-Anode-LIGBT, anode short-circuited insulated gate bipolar transistor) are short-circuited together by the anode electrode, and a parasitic diode is introduced into the device body, which has the ability of reverse conduction. During the device shutdown process, the anode N+ region can directly extract electrons in the drift region, increase the switching speed of the device, and reduce the shutdown loss of the device. However, due to the introduction of the anode N+ region, the injection efficiency of holes in the on state is reduced, resulting in an increase in the on-state voltage drop, and more seriously, there is a snapback voltage foldback phenomenon. When the on-current is small, the electrons injected by NMOS flow directly out from the anode N+ region, the P+ / N-buffer junction is not turned on, the device is in unipolar mode, and the on-resistance is high; as the on-current gradually increases, the voltage drop caused by the electrons flowing through the N-buffer region below the P+ region gradually increases. When the voltage drop is greater than the built-in potential of the P+ / N-buffer junction, the P+ region begins to inject holes into the drift region to produce a conductivity modulation effect, the device enters the bipolar mode, and the resistance is greatly reduced, causing the Snapback phenomenon. This will introduce electromagnetic oscillations in the circuit system and affect the stability of the system.

[0005] In order to alleviate the snapback phenomenon, researchers proposed SSA-LIGBT (Separated-Shorted-Anode LIGBT). This structure separates the P+ region and the N+ region to a sufficient distance, which is equivalent to introducing a large resistor between the P+ region and the N+ region. The device can work in bipolar mode at a smaller on-current. Although the snapback phenomenon is alleviated, a large amount of chip area is wasted. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide an RC-LIGBT device integrating four MOSFETs. Based on the structure of a traditional LIGBT device, an ordinary MOSFET is used to control the opening and closing of the device; a channel MOSFET is used to adjust the ratio of majority electrons and minority holes injected into the device when the device is reversed, thereby greatly improving the reverse recovery performance of the device; an anode-assisted MOSFET is used to eliminate the Snapback voltage foldback phenomenon in the traditional RC-LIGBT, thereby further improving the reverse conduction performance of the device.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] An RC-LIGBT device integrating four MOSFETs includes a cathode P+ region 1, a cathode N+ region 2, a cathode P-well region 3, a drift region 4, a buried oxide layer 5, a substrate 6, an anode P+ region 7, an anode P-well region 8, an anode N-buffer region 9, a common MOS metal gate 12, and a common MOS gate oxide layer 16. It also includes an anode N+ region 10, an anode floating N+ region 11, a channel MOS metal gate 13, an anode auxiliary MOS metal gate 14, an anode floating MOS metal gate 15, a channel MOS gate oxide layer 17, an anode auxiliary MOS gate oxide layer 18, and an anode floating MOS gate oxide layer 19.

[0009] The reverse conducting region is composed of an anode N-buffer region 9, an anode P-well region 8, an anode N+ region 10, an anode auxiliary MOS metal gate 14, an anode auxiliary MOS gate oxide layer 18, an anode floating N+ region 11, an anode floating MOS metal gate 15 and an anode floating MOS gate oxide layer 19; the anode N+ region 10 is located directly behind the anode P+ region 7, and the anode N+ region 10 and the anode P+ region 7 are wrapped by the anode P-well region 8 on the upper right side; the anode P-well region 8 is completely wrapped by the anode N-buffer region 9 on the upper right side; the anode floating N+ region 11 is located above and behind the anode N-buffer region 9, and is in the same horizontal direction as the anode P+ region 7 and the anode N+ region 10; the anode P+ region 7 and the anode N+ region 10 are in direct contact with the anode electrode; the anode auxiliary MOS metal gate 14 and the anode auxiliary MOS gate oxide layer 18 are located in the anode P-well region 8-anode N+ region 10 sandwich. ell region 8; the lower side of the anode auxiliary MOS gate oxide layer 18 is in direct contact with the upper side of the anode P-well region 8, and the upper side of the anode auxiliary MOS gate oxide layer 18 is in direct contact with the lower side of the anode auxiliary MOS metal gate 14; the electrode of the anode auxiliary MOS metal gate 14 is connected to the anode electrode; the anode floating MOS metal gate 15 is located in the anode N+ region 10-anode P-well region 8-anode N-buffer region 9-anode floating N+ region 11 sandwich, directly above the anode P-well region 8, the anode N-buffer region 9 and the anode floating N+ region 11; the lower side of the anode floating MOS metal gate oxide layer 19 is in direct contact with the upper side of the anode P-well region 8 and the anode N-buffer region 9, and the upper side of the anode floating MOS metal gate oxide layer 19 is in direct contact with the lower left side of the anode floating MOS metal gate 15; the anode floating MOS metal gate 15 is in direct contact with the anode floating MOS gate oxide layer 19 and the anode floating N+ region 11;

[0010] The channel diode region is composed of a cathode N+ region 2, a cathode P-well region 3, a drift region 4, a channel MOS metal gate 13 and a channel MOS gate oxide layer 17; the cathode N+ region 2 is located on the right side of the cathode P+ region 1 and is completely wrapped by the cathode P-well region 3; the drift region 4 is located on the lower side and right side of the cathode P-well region 3; the channel MOS metal gate 13 is located directly above the cathode P-well region 3 in the sandwich of the cathode N+ region 2-cathode P-well region 3-drift region 4; the lower side of the channel MOS gate oxide layer 17 is in direct contact with the upper side of the cathode P-well region 3 and the left part of the upper side of the drift region 4, and the upper side of the channel MOS gate oxide layer 17 is in direct contact with the lower side of the channel MOS metal gate 13; the electrode of the channel MOS metal gate 13 is connected to the cathode electrode;

[0011] The bottom of the device is composed of a buried oxide layer 5 and a substrate 6 ; the buried oxide layer 5 is located at the lower side of the drift region 4 and at the upper side of the substrate 6 .

[0012] Furthermore, the source of the common MOSFET is the cathode N+ region 2, the drain is the (N-drift) drift region 4, the gate is a common MOS metal gate 12, and the gate oxide layer is a common MOS gate oxide layer 16;

[0013] The source of the channel MOSFET is the (N-drift) drift region 4, the drain is the cathode N+ region 2, the gate is the channel MOS metal gate 13, and the gate oxide layer is the channel MOS gate oxide layer 17;

[0014] The source of the anode-assisted MOSFET is the anode N-buffer region 9, the drain is the anode N+10, the gate is the anode-assisted MOS metal gate 14, and the gate oxide layer is the anode-assisted MOS gate oxide layer 18;

[0015] The source of the anode floating MOSFET is the anode floating N+ region 10 , the drain is the anode floating N+ region 11 , the gate is the anode floating MOS metal gate 15 , and the gate oxide layer is the anode floating MOS gate oxide layer 19 .

[0016] The structures and functions of the above four MOSFETs are shown in Table 1:

[0017] Table 1 Structure and function of four MOSFETs

[0018]

[0019] Furthermore, the ordinary MOSFET is used to control the injection of cathode electrons; the trench MOSFET is used to turn on before the parasitic diode in the body during reverse conduction; and the anode auxiliary MOSFET is used to ensure that the device provides an additional channel for electrons under the premise of bipolar mode.

[0020] Furthermore, ordinary MOSFET is used to control the opening and closing of the device; the channel MOSFET is used to adjust the ratio of majority electrons and minority holes injected into the device when the device is reversely conducted; the anode auxiliary MOSFET is used to eliminate the snapback voltage foldback phenomenon in the traditional RC-LIGBT, and further improve the reverse conduction performance of the device.

[0021] Furthermore, the thickness of the channel MOS gate oxide layer 17, the anode-assisted MOS gate oxide layer 18 or the anode-floating MOS gate oxide layer 19 can be adjusted as needed.

[0022] Furthermore, the material of the anode floating MOS metal gate 15 includes doped polysilicon or aluminum.

[0023] The beneficial effect of the present invention is that, based on the traditional LIGBT device, the present invention introduces a reverse conduction region at the anode and a channel diode region at the cathode. When the device is operating in forward conduction and the anode voltage is low, the electrons in the drift region will not flow directly to the anode N+ region short-circuited with the anode P+ region due to the blocking of the anode P-well layer. As the anode voltage gradually increases, the auxiliary gate located at the anode is turned on, and the electrons can flow through the anode N+ region as well as the anode P+ region. At this time, the device is in a bipolar operating mode, eliminating the Snapback voltage foldback phenomenon. When the device is turned off, the anode auxiliary gate can also assist in extracting electrons in the drift region, reducing the turn-off loss of the device. When the device is operating in reverse conduction, the channel diode located at the cathode can be turned on in advance before the PN junction formed by the cathode P+ and the drift region N-drift is turned on, reducing the number of minority holes injected during reverse conduction, thereby greatly improving the reverse recovery performance of the device. When the device operates in reverse conduction, the floating gate located in the anode reverse conduction region is automatically turned on by the voltage applied to the reverse biased PN junction formed by the anode N-buffer and the anode P-well, thereby improving the reverse conduction performance.

[0024] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 This is a schematic structural diagram of a new structure RC-LIGBT device according to Embodiment 1 of the present invention;

[0027] Figure 2 for Figure 1 Cross-sectional views of the device at three different cross sections a, b, and c;

[0028] Figure 3 for Figure 1 Equivalent circuit diagram of

[0029] Figure 4 (a) is a schematic diagram of the structure of a traditional LIGBT device, and (b) is a schematic diagram of the structure of a traditional PIN diode;

[0030] Figure 5 1 is a potential distribution diagram of Example 1 of the present invention and a conventional LIGBT in an avalanche breakdown state;

[0031] Figure 6 The drift region length L of the embodiment 1 of the present invention and the conventional LIGBT D Comparison of blocking characteristics at 18μm;

[0032] Figure 7 It is a comparison diagram of characteristic curves of latch-up effect occurring in the forward conduction state between the first embodiment of the present invention and the conventional LIGBT;

[0033] Figure 8 A comparison diagram of the forward conduction characteristics of Example 1 of the present invention and a conventional LIGBT, and a comparison diagram of the electron concentration near each gate in Example 1;

[0034] Fig. 9 1 is a reverse conduction characteristic diagram of Example 1 of the present invention, and a comparison diagram of electron concentration near each gate in Example 1;

[0035] Fig.10 The inductive load test circuit of Example 1 of the present invention and the traditional LIGBT and the turn-off characteristic curve under the same on-state voltage drop, and the electron concentration comparison diagram near each gate in Example 1;

[0036] Fig.11 A reverse recovery test circuit and reverse recovery performance characteristic comparison diagram of Example 1 of the present invention and a conventional PIN diode, and a comparison diagram of electron concentration near each gate in Example 1;

[0037] Fig.12 A schematic diagram of the main process flow of the new structure RC-LIGBT device provided by the present invention;

[0038] Figure markings: 1-cathode P+ region, 2-cathode N+ region, 3-cathode P-well region, 4-(N-drift) drift region, 5-buried oxide layer, 6-substrate, 7-anode P+ region, 8-anode P-well region, 9-anode N-buffer region, 10-anode N+ region, 11-anode floating N+ region, 12-ordinary MOS metal gate, 13-channel MOS metal gate, 14-anode auxiliary MOS metal gate, 15-anode floating MOS metal gate, 16-ordinary MOS gate oxide layer, 17-channel MOS gate oxide layer, 18-anode auxiliary MOS gate oxide layer, 19-anode floating MOS gate oxide layer. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0040] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0041] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0042] like Figure 4As shown, the conventional LIGBT device is mainly composed of a cathode P+ region 1, a cathode N+ region 2, a cathode P-well region 3, a drift region 4, an anode P+ region 7, an anode P-well region 8, an anode N-buffer region 9, a common MOS metal gate 12, and a common MOS gate oxide layer 16. From left to right, they are the cathode P+ region 1, the cathode N+ region 2, the common MOS metal gate 12, the common MOS gate oxide layer 16, the cathode P-well region 3, the (N-drift) drift region 4, the anode P+ region 7, the anode P-well region 8, and the anode N-buffer region 9. The right side of the cathode P+ region 1 is adjacent to the cathode N+ region 2, and the cathode P+ region 1 and the cathode N+ region 2 are connected to the cathode electrode. The cathode P-well region 3 is located at the lower side of the cathode P+ region 1 and the cathode N+ region 2, and completely wraps the cathode P+ region 1 and the cathode N+ region 2. The (N-drift) drift region 4 is adjacent to the cathode P-well region 3 and the anode N-buffer region 9. The anode P+ 7, the anode P-well region 8, and the anode N-buffer region 9 form a sandwich-like structure. The anode P+ region 7 is completely wrapped by the anode P-well region 8. The anode P-well region 8 is completely wrapped by the anode N-buffer region 9. The anode P+ region 7 is in contact with the anode electrode. The ordinary MOS metal gate 12 is located directly above the cathode P-well region 3 in the cathode N+ region 2-cathode P-well region 3-N-drift region 4 sandwich, and the ordinary MOS gate oxide layer 16 is in direct contact with the cathode P-well region 3.

[0043] Embodiment 1:

[0044] like Figure 1 As shown, improvements are made on the traditional LIGBT device. This embodiment provides a new RC-LIGBT device integrating four MOSFETs, mainly including a cathode P+ region 1, a cathode N+ region 2, a cathode P-well region 3, a (N-drift) drift region 4, a buried oxide layer 5, a substrate 6, an anode P+ region 7, an anode P-well region 8, an anode N-buffer region 9, an anode N+ region 10, an anode floating N+ region 11, a normal MOS metal gate 12, a channel MOS metal gate 13, an anode auxiliary MOS metal gate 14, an anode floating MOS metal gate 15, a normal MOS gate oxide layer 16, a channel MOS gate oxide layer 17, an anode auxiliary MOS gate oxide layer 18, and an anode floating MOS gate oxide layer 19.

[0045] The reverse conducting region is composed of the anode N-buffer region 9, the anode P-well region 8, the anode N+ region 10, the anode auxiliary MOS metal gate 14, the anode auxiliary MOS gate oxide layer 18, the anode floating N+ region 11, the anode floating MOS metal gate 15, and the anode floating MOS gate oxide layer 19. From left to right, they are the anode N-buffer region 9, the anode P-well region 8, the anode N+ region 10, the anode auxiliary MOS metal gate 14, the anode auxiliary MOS gate oxide layer 18, the anode floating N+ region 11, the anode floating MOS metal gate 15, and the anode floating MOS gate oxide layer 19. The anode N+ region 10 is located directly behind the anode P+ region 7, and the anode N+ region 10 and the anode P+ region 7 are wrapped in the anode P-well region 8. The anode P-well region 8 is completely wrapped by the anode N-buffer region 9. The anode floating N+ region 11 is located in the upper back of the anode N-buffer region 9, and is in the same horizontal direction as the anode P+ region 7 and the anode N+ region 10. The anode P+ region 7 and the anode N+ region 10 are in direct contact with the anode electrode. The anode auxiliary MOS metal gate 14 is located directly above the anode P-well region 8 in the sandwich of the anode N-buffer region 9—the anode P-well region 8—the anode N+ region 10, and the anode auxiliary MOS gate oxide layer 18 is in direct contact with the anode P-well region 8. The electrode of the anode auxiliary MOS metal gate 14 is connected to the anode electrode. The anode floating MOS metal gate 15 is located directly above the anode P-well region 8, the anode N-buffer region 9 and the anode floating N+ region 11 in the sandwich of the anode N+ region 10—the anode P-well region 8—the anode N-buffer region 9—the anode floating N+ region 11. The anode floating MOS metal gate oxide layer 19 is in direct contact with the anode P-well region 8 and the anode N-buffer region 9. The anode floating MOS metal gate 15 is in direct contact with the anode floating MOS gate oxide layer 19 and the anode floating N+ region 11.

[0046] The channel diode region is mainly composed of the cathode N+ region 2, the cathode P-well region 3, the (N-drift) drift region 4, the channel MOS metal gate 13, and the channel MOS gate oxide layer 17. From left to right, they are the cathode N+ region 2, the cathode P-well region 3, the (N-drift) drift region 4, the channel MOS metal gate 13, and the channel MOS gate oxide layer 17. The cathode N+ region 2 is located on the right side of the cathode P+ region 1 and is completely wrapped by the cathode P-well region 3. The (N-drift) drift region 4 is located on the lower side and right side of the cathode P-well region 3. The channel MOS metal gate 13 is located directly above the cathode P-well region 3 in the sandwich of the cathode N+ region 2-cathode P-well region 3-(N-drift) drift region 4. The channel MOS gate oxide layer 17 is in direct contact with the cathode P-well region 3. The electrode of the channel MOS metal gate 13 is connected to the cathode electrode.

[0047] The bottom of the device is composed of a buried oxide layer 5 and a substrate 6; the buried oxide layer 5 is located below the (N-drift) drift region 4 and above the substrate 6. The substrate 6 is located below the buried oxide layer 5.

[0048] The length (Y-axis direction) of the drift region 4 is 18 μm, the width (Z-axis direction) is 5 μm, and the thickness (X-axis direction) is 4 μm. The doping concentration of this region is 2×10 15 cm -3 The length of cathode P+ region 1 is 1 μm, the width is 5 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of cathode N+ region 2 is 1 μm, the width is 5 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of cathode P-well region 3 is 3 μm, the width is 5 μm, the thickness is 2 μm, and the doping concentration is 1×10 17 cm -3 The length of the anode P+ region 7 is 1 μm, the width is 1 μm, the height is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of the anode P-well region 8 is 2 μm, the width is 3 μm, the thickness is 2 μm, and the doping concentration is 1×10 17 cm -3 The length of the anode N-buffer region 9 is 3 μm, the width is 5 μm, the thickness is 3 μm, and the doping concentration is 8×10 16 cm -3 The length of the anode N+ region 10 is 1 μm, the width is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3The length of the anode floating N+ region 11 is 1 μm, the width is 1 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 . The length of the ordinary MOS metal gate 12 is 1μm, the width is 3μm, and the thickness is 0.1μm. The length of the ordinary MOS gate oxide layer 16 is 1μm, the width is 3μm, and the thickness is 0.1μm. The length of the channel MOS metal gate 13 is 1μm, the width is 2μm, and the thickness is 0.1μm. The length of the channel MOS gate oxide layer 17 is 1μm, the width is 2μm, and the thickness is 0.01μm. The length of the anode auxiliary MOS metal gate 14 is 1μm, the width is 1μm, and the thickness is 0.1μm. The length of the anode auxiliary MOS gate oxide layer 18 is 1μm, the width is 1μm, and the thickness is 0.1μm. The length of the anode floating MOS metal gate 15 is 1μm, the width is 3μm, and the thickness is 0.01μm. The length of the anode floating MOS gate oxide layer 19 is 1μm, the width is 3μm, and the thickness is 0.01μm. The buried oxide layer 5 has a length of 24 μm, a width of 5 μm, and a thickness of 3 μm. The substrate 6 has a length of 24 μm, a width of 5 μm, a thickness of 1 μm, and a doping concentration of 1×10 16 cm -3 .

[0049] When the device is working in forward conduction and the anode voltage is low, due to the obstruction of the anode P-well layer, the electrons in the drift region will not be directly extracted by the anode N+ region short-circuited by the anode P+ region. As the anode voltage gradually increases, the auxiliary MOS gate located at the anode is turned on, and the electrons can flow through the anode N+ region as well as the anode P+ region. At this time, the device is in bipolar working mode, eliminating the snapback voltage foldback phenomenon. When the device is turned off, the anode auxiliary gate can also assist in extracting electrons in the drift region, reducing the turn-off loss of the device. When the device is working in reverse conduction, the channel diode located at the cathode can be turned on in advance before the PN junction formed by the cathode P+ and the (N-drift) drift region is turned on, reducing the number of minority holes injected during reverse conduction, thereby greatly improving the reverse recovery performance of the device. When the device is working in reverse conduction, the floating gate located in the anode reverse conduction region is automatically turned on using the voltage applied to the reverse biased PN junction formed by the anode N-buffer and the anode P-well, thereby improving the reverse conduction performance.

[0050] Using SENTAURUS simulation software, the LIGBT device of the proposed embodiment 1 is Figure 1-2The structure shown in the figure is subjected to performance simulation analysis, its mechanism is analyzed, and electrical simulation is performed. During the simulation process, the simulation parameters of the device in Example 1 are consistent with those of the traditional LIGBT, wherein the thickness of the (N-drift) drift region is 4 μm, the carrier lifetime is 10 μs, and the ambient temperature is 300K.

[0051] Figure 3 The equivalent circuit diagram of the RC-LIGBT device of Example 1 is shown, in which the LIGBT region is equivalent to a PNP transistor controlled by NMOS. The reverse conduction region is equivalent to two NMOS tubes located at the anode, wherein the anode auxiliary gate is equivalent to an NMOS tube with the drain and the gate shorted together, and the anode floating electrode is equivalent to an NMOS tube with the source and the gate shorted together during forward conduction. The channel diode region is equivalent to a PN diode located at the cathode in parallel with an NMOS tube with the gate and the source shorted together. At the turn-off moment, the two NMOS tubes located at the anode can be turned on to assist in extracting electrons located in the (N-drift) drift region, thereby increasing the turn-off speed of the device and reducing the turn-off loss of the device. At the reverse recovery moment, since the threshold voltage of the NMOS located at the cathode is lower than the turn-on voltage of the PN diode, the NMOS is turned on ahead of the PN diode, reducing the minority holes injected into the device during reverse conduction, greatly improving the reverse recovery characteristics of the device.

[0052] Figure 5 The blocking characteristics of Example 1 and the conventional LIGBT are compared when the drift region length (Y-axis direction) is 18 μm. 15 cm -3 The breakdown voltage is 276V; the concentration of conventional LIGBT in the drift region is 2×10 15 cm -3 The breakdown voltage is 273V, and the two are at the same withstand voltage level.

[0053] Figure 6 For Example 1 and the conventional LIGBT, the drift region length (Y-axis direction) is 18 μm and the concentration is 2×10 15 cm -3 Comparison of avalanche breakdown characteristic curves below.

[0054] Figure 7 For Example 1 and the conventional LIGBT, the drift region length (Y-axis direction) is 18 μm and the concentration is 2×10 15 cm -3 As shown in the latch-up effect characteristic curve comparison diagram below, since the area of ​​the common MOS gate of Example 1 is smaller than that of the common MOS gate of the traditional LIGBT, the saturation current of Example 1 is much smaller than that of the traditional LIGBT, and the anti-latch-up effect performance of Example 1 is far superior to that of the traditional LIGBT.

[0055] Figure 8 middle Figure 8 (a) is a comparison of the forward conduction characteristic curves of Example 1 and the traditional LIGBT. When forward-conducting, the cathode is grounded and a positive voltage of 10V is applied to the gate. In the forward conduction stage, the on-state voltage drop of the traditional LIGBT is relatively small, at 0.97V; the on-state voltage drop of Example 1 is 1.35V. In the forward conduction stage, the cathode control gate in the drift region of Example 1 is smaller than that of the traditional LIGBT, and the efficiency of emitting holes is reduced due to the smaller area of ​​the cathode control gate and the smaller anode P+ region. Therefore, the on-state voltage drop of the device in Example 1 is slightly higher than that of the traditional LIGBT. Figure 8 (b) is the electron concentration distribution diagram near the ordinary MOS gate. At the forward conduction moment, the ordinary MOS gate controls the injection of cathode electrons. It can be seen that an inversion layer appears in the MOS channel, and a large number of electrons are injected from the cathode to the drift region. Figure 8 (c) is the electron concentration distribution diagram near the channel MOS gate. At the forward conduction moment, the channel MOS gate is in the off state and no inversion layer appears in the channel. Figure 8 (d) is the electron concentration distribution diagram near the anode floating MOS gate. At the forward conduction moment, the anode floating MOS gate is in the open state, and an inversion layer appears in the channel, providing an additional channel for electrons in the drift region. A large number of electrons flow into the anode through the channel. Figure 8 (e) is the electron concentration distribution diagram near the anode-assisted MOS gate. At the forward conduction moment, the anode-assisted MOS gate is in the off state. Due to the small on-voltage, an obvious inversion layer appears in the channel, but a large number of electrons are attracted to gather at the bottom.

[0056] Fig. 9 middle Fig. 9 (a) is the reverse conduction characteristic curve of Example 1. When conducting in reverse, the anode is grounded and a gradually increasing positive voltage is applied to the cathode. Thanks to the introduction of the channel diode region and the reverse conduction region, the device can conduct in reverse. The reverse conduction voltage drop of the device in Example 1 is 1.29V. Fig. 9 (b) is the electron concentration distribution diagram near the ordinary MOS gate. At the reverse conduction moment, the ordinary MOS gate is closed and no inversion layer appears in the channel. Fig. 9 (c) is the electron concentration distribution diagram near the channel MOS gate. At the reverse conduction moment, the channel MOS gate is in the open state, an inversion layer appears in the channel, and a large number of electrons are injected from the cathode into the drift region. Fig. 9 (d) is the electron concentration distribution diagram near the anode floating MOS gate. At the forward conduction moment, the anode floating MOS gate is in the open state, and an inversion layer appears in the channel, providing a channel for electrons in the drift region. A large number of electrons flow into the anode through the channel, allowing the device to obtain reverse conduction capability. Fig. 9(e) is the electron concentration distribution diagram near the anode-assisted MOS gate. At the reverse conduction moment, the anode-assisted MOS gate is in the off state, no inversion layer appears in the channel, and the electron current under the channel is very small.

[0057] Fig.10 middle Fig.10 (a) with Fig.10 (b) are the topological structure of the test circuit and the turn-off characteristic curves of Example 1 and the traditional LIGBT under the same conduction voltage drop, respectively, where the load in the test circuit is an inductive load. The turn-off time refers to the time taken for the collector current to drop from 90% to 10%. Since the device of Example 1 has two more NMOS electron extraction channels compared with the traditional LIGBT device. At the moment of turn-off, electrons can flow directly out through the two NMOS located at the anode, reducing the number of electrons flowing out through the anode P+ and emitting holes, and the turn-off loss of Example 1 is greatly reduced. Fig.10 (c) is the electron concentration distribution diagram near the ordinary MOS gate. The ordinary MOS gate is closed when the device is turned off. Fig.10 (d) is the electron concentration distribution diagram near the channel MOS gate. The channel MOS gate is in the off state when the device is turned off. Fig.10 (e) is the electron concentration distribution diagram near the anode floating MOS gate. When the device is turned off, the anode floating MOS gate is in the open state, and an inversion layer appears in the channel, providing an additional extraction channel for electrons in the drift region. At the end of the shutdown period, a small amount of electrons gather under the channel. Fig.10 (f) is the electron concentration distribution diagram near the anode-assisted MOS gate. When the device is turned off, the anode-assisted MOS gate is in the open state. Since the anode voltage is very large at the end of the shutdown period, the voltage applied to the anode-assisted MOS gate is also very large, the channel is completely inverted, and the electrons near the channel are completely extracted.

[0058] Fig.11 middle Fig.11 (a) with Fig.11 (b) are the topological structure diagram of the test circuit and the reverse recovery characteristic curves of Example 1 and the traditional PIN diode at the same conduction current. Compared with the traditional LIGBT device, the channel diode at the cathode of the device of Example 1 is turned on earlier than the PN junction diode to inject electrons, reducing the number of minority holes injected into the drift region. At the reverse recovery moment, the number of holes that need to be extracted from the device is greatly reduced, thereby greatly improving the reverse recovery characteristics of the device of Example 1. Fig.11 (c) is the electron concentration distribution diagram near the ordinary MOS gate. At the reverse recovery moment, the ordinary MOS gate is in the off state. Fig.11 (d) is the electron concentration distribution diagram near the trench MOS gate. The trench MOS gate is in the off state at the reverse recovery moment. Fig.11 (e) is the electron concentration distribution diagram near the anode floating MOS gate. At the reverse recovery moment, the anode floating MOS gate is in the open state, and an inversion layer appears in the channel, providing an additional extraction channel for electrons in the drift region. At the end of the reverse recovery, there are still a small number of electrons gathered under the channel. Fig.11 (f) is the electron concentration distribution diagram near the anode-assisted MOS gate. During the reverse recovery moment, the anode-assisted MOS gate is in a closed state most of the time. Under the action of the external inductor, it will be briefly opened for a short time to assist in extracting some electrons.

[0059] The present invention proposes a LIGBT device integrating four MOSFETs, as shown in FIG. Figure 1 For example, its main process flow is as follows Fig.12 As shown. The main processes include: ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling and annealing to form the common LIGBT area, reverse conduction area and channel diode area. Finally, metal electrodes are deposited to form the source, gate and drain.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An RC-LIGBT device integrating four MOSFETs, comprising a cathode P+ region (1), a cathode N+ region (2), a cathode P-well region (3), a drift region (4), a buried oxide layer (5), a substrate (6), an anode P+ region (7), an anode P-well region (8), an anode N-buffer region (9), a common MOS metal gate (12), and a common MOS gate oxide layer (16), It is characterized in that The device also includes an anode N+ region (10), an anode floating N+ region (11), a channel MOS metal gate (13), an anode auxiliary MOS metal gate (14), an anode floating MOS metal gate (15), a channel MOS gate oxide layer (17), an anode auxiliary MOS gate oxide layer (18) and an anode floating MOS gate oxide layer (19); The reverse conducting region is composed of an anode N-buffer region (9), an anode P-well region (8), an anode N+ region (10), an anode auxiliary MOS metal gate (14), an anode auxiliary MOS gate oxide layer (18), an anode floating N+ region (11), an anode floating MOS metal gate (15) and an anode floating MOS gate oxide layer (19); the anode N+ region (10) is located directly behind the anode P+ region (7), and the anode N+ region (10) and the anode P+ region (7) are jointly protected by the anode P-well region ( 8) is wrapped on the upper right side; the anode P-well region (8) is completely wrapped on the upper right side by the anode N-buffer region (9); the anode floating N+ region (11) is located above and behind the anode N-buffer region (9) and is in the same horizontal direction as the anode P+ region (7) and the anode N+ region (10); the anode auxiliary MOS metal gate (14) and the anode auxiliary MOS gate oxide layer (18) are located in the anode N-buffer region (9) - anode P-well region (8) - anode N+ region (10) sandwich The anode P-well region (8) is directly above the anode; the lower side of the anode auxiliary MOS gate oxide layer (18) is in direct contact with the upper side of the anode P-well region (8); the upper side of the anode auxiliary MOS gate oxide layer (18) is in direct contact with the lower side of the anode auxiliary MOS metal gate (14); the anode floating MOS metal gate (15) is located in the anode P-well region (8) in the sandwich of the anode N+ region (10) - the anode P-well region (8) - the anode N-buffer region (9) - the anode floating N+ region (11). , directly above the anode N-buffer region (9) and the anode floating N+ region (11); the lower side of the anode floating MOS gate oxide layer (19) is in direct contact with the upper side of the anode P-well region (8) and the anode N-buffer region (9); the upper side of the anode floating MOS gate oxide layer (19) is in direct contact with the lower left side of the anode floating MOS metal gate (15); the anode floating MOS metal gate (15) is in direct contact with the anode floating MOS gate oxide layer (19) and the anode floating N+ region (11); The channel diode region is composed of a cathode N+ region (2), a cathode P-well region (3), a drift region (4), a channel MOS metal gate (13) and a channel MOS gate oxide layer (17); the cathode N+ region (2) is located on the right side of the cathode P+ region (1) and is completely wrapped by the cathode P-well region (3); the drift region (4) is located on the lower side and right side of the cathode P-well region (3); the channel MOS metal gate (13) is located directly above the cathode P-well region (3) in the cathode N+ region (2) - cathode P-well region (3) - drift region (4) sandwich; the lower side of the channel MOS gate oxide layer (17) is in direct contact with the upper side of the cathode P-well region (3) and the left part of the upper side of the drift region (4), and the upper side of the channel MOS gate oxide layer (17) is in direct contact with the lower side of the channel MOS metal gate (13); The bottom of the device is composed of a buried oxide layer (5) and a substrate (6); the buried oxide layer (5) is located on the lower side of the drift region (4) and at the same time on the upper side of the substrate (6).

2. The RC-LIGBT device integrating four MOSFETs according to claim 1, It is characterized in that The anode P+ region (7) and the anode N+ region (10) are in direct contact with the anode electrode; the electrode of the anode auxiliary MOS metal gate (14) is connected to the anode electrode; and the electrode of the channel MOS metal gate (13) is connected to the cathode electrode.

3. The RC-LIGBT device integrating four MOSFETs according to claim 1 or 2, It is characterized in that The source of a common MOSFET is a cathode N+ region (2), the drain is a drift region (4), the gate is a common MOS metal gate (12), and the gate oxide layer is a common MOS gate oxide layer (16); The source of the channel MOSFET is a drift region (4), the drain is a cathode N+ region (2), the gate is a channel MOS metal gate (13), and the gate oxide layer is a channel MOS gate oxide layer (17); The source of the anode-assisted MOSFET is an anode N-buffer region (9), the drain is an anode N+ (10), the gate is an anode-assisted MOS metal gate (14), and the gate oxide layer is an anode-assisted MOS gate oxide layer (18); The source of the anode floating MOSFET is an anode N+ region (10), the drain is an anode floating N+ region (11), the gate is an anode floating MOS metal gate (15), and the gate oxide layer is an anode floating MOS gate oxide layer (19).

4. The RC-LIGBT device integrating four MOSFETs according to claim 3, It is characterized in that The common MOSFET is used to control the injection of cathode electrons; the channel MOSFET is used to turn on before the internal parasitic diode during reverse conduction; and the anode auxiliary MOSFET is used to ensure that the device provides an additional channel for electrons under the premise of bipolar mode.

5. The RC-LIGBT device integrating four MOSFETs according to claim 3, It is characterized in that The common MOSFET is used to control the opening and closing of the device; the channel MOSFET is used to adjust the ratio of majority electrons and minority holes injected into the device when the device is reversely conducted; the anode auxiliary MOSFET is used to eliminate the snapback voltage foldback phenomenon in the traditional RC-LIGBT.

6. The RC-LIGBT device integrating four MOSFETs according to claim 1, It is characterized in that The thickness of the channel MOS gate oxide layer (17), the anode-assisted MOS gate oxide layer (18) or the anode-floating MOS gate oxide layer (19) is adjusted as required.

7. The RC-LIGBT device integrating four MOSFETs according to claim 1, It is characterized in that The material of the anode floating MOS metal gate (15) includes doped polysilicon or aluminum.

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