Integrated memory with capacitor connection re-distribution and method of forming integrated memory

Abstract

This application relates to an integrated memory with capacitor connection redistribution, and a method of forming the same. Some embodiments include an integrated assembly having a digit line contact region between a plurality of pairs of capacitor contact regions. The capacitor contact regions are arranged with six adjacent capacitor contact regions in a substantially rectangular configuration. A conductive plug is coupled with the capacitor contact regions. A conductive redistribution material is coupled with the conductive plug. An upper surface of the conductive redistribution material is arranged in a substantially hexagonal close packed configuration. A digit line is over the digit line contact region. An insulating region is between the digit line and the conductive plug. The insulating region contains voids and / or low-k dielectric material. A capacitor is coupled with the upper surface of the conductive redistribution material.

Description

TECHNICAL FIELD

[0001] Integrated assembly. Integrated memory (e.g., DRAM). Integrated memory with capacitor connection redistribution. Method of forming integrated memory. BACKGROUND

[0002] Memory is a type of integrated circuit and is used in computer systems to store data. An example memory is DRAM (dynamic random access memory). DRAM cells can each include a transistor in combination with a capacitor. DRAM cells can be arranged in an array; where word lines extend along rows of the array, and digit lines extend along columns of the array. Word lines can be coupled with transistors of memory cells. Each memory cell can be uniquely addressed via a combination of one of the word lines and one of the digit lines.

[0003] As integration levels increase, tight packing of capacitors becomes increasingly important. There is a need to develop architectures that enable tight packing of capacitors of DRAM arrays and to develop methods for manufacturing such architectures. SUMMARY

[0004] In one aspect, the present application provides an integrated assembly comprising: active regions each having a digit line contact region between a pair of capacitor contact regions, the capacitor contact regions arranged in a pattern such that six adjacent capacitor contact regions form a substantially rectangular configuration; conductive plugs coupled with the capacitor contact regions; conductive redistribution material coupled with the conductive plugs and passing through the conductive plugs to the capacitor contact regions; the conductive redistribution material extending upwardly and laterally outwardly from the conductive plugs; upper surfaces of the conductive redistribution material arranged in a pattern such that seven adjacent upper surfaces form a unit of a substantially hexagonal close packed configuration; digit lines over the digit line contact regions; insulating regions between the digit lines and the conductive plugs; the insulating regions comprising one or both of voids and low-k dielectric material, wherein the voids and / or low-k dielectric material contact upper surfaces of the capacitor contact regions; and capacitors coupled with the upper surfaces of the conductive redistribution material.

[0005] In another aspect, the application further provides an integrated assembly comprising: semiconductor material pillars each having a digit line contact region between a pair of capacitor contact regions; the capacitor contact regions arranged in an array, wherein the array has alternating first and second rows; conductive plugs coupled with the capacitor contact regions; conductive redistribution material coupled with the conductive plugs and through the conductive plugs to the capacitor contact regions; the conductive redistribution material having a first configuration along the first rows, wherein the first configuration extends laterally outward from the capacitor contact regions of the first rows in a first direction generally along the first rows; the conductive redistribution material having a second configuration along the second rows, wherein the second configuration extends laterally outward from the capacitor contact regions of the second rows in a second direction generally along the second rows; the second direction being generally opposite the first direction; the conductive redistribution material having an upper surface; digit lines over the digit line contact regions; insulative regions between the digit lines and the conductive plugs; the insulative regions comprising one or both of voids and low-k dielectric material, wherein the voids and / or low-k dielectric material contact the upper surface of the capacitor contact regions; and capacitors coupled with the upper surface of the conductive redistribution material.

[0006] In yet another aspect, the application further provides a method of forming an integrated assembly comprising: forming a construction having semiconductor material pillars each having a digit line contact region between a pair of capacitor contact regions; the capacitor contact regions arranged in an array, wherein the array has alternating first and second rows; the digit line contact regions spaced apart from the capacitor contact regions along a first cross-section, the first cross-section along the first rows, and along a second cross-section, the second cross-section along the second rows; digit lines directly over the digit line contact regions along the first and second cross-sections; conductive plugs directly over the capacitor contact regions along the first and second cross-sections; sacrificial material between the conductive plugs and the digit lines; removing the sacrificial material to form void regions; forming insulative blocks extending across the conductive plugs; forming first openings extending to the conductive plugs along the first cross-section, and forming second openings extending to the conductive plugs along the second cross-section; the first and second openings having first and second shapes, respectively, wherein the second shape is generally a mirror image of the first shape; forming conductive redistribution material within the first and second shapes of the first and second openings; and forming capacitors coupled with the conductive redistribution material. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 Illustrative top-down view of a region of an example memory array.

[0008] Figure 2 Illustrative top-down view of an example memory array modified with respect to Figure 1 Illustrative top-down view of an example memory array modified with respect to

[0009] Figure 3for Figure 2 Another illustrative top-down view of the modified memory array.

[0010] Figure 3A for Figure 3 A magnified top-down view of the area marked "A".

[0011] Figure 4 For along Figure 3 A diagrammatic cross-sectional side view of line 4-4.

[0012] Figure 5 and 6 For along Figure 2 and 3 A schematic cross-sectional side view in the direction marked "5" and "6".

[0013] Figure 7 and 8 To follow the same path at the instance processing phase of the instance method. Figure 5 and 6 A schematic cross-sectional side view of the same cross section.

[0014] Figure 9 and 10 In order to be in Figure 7 and 8 The instance processing phase following the instance processing phase is along with... Figure 7 and 8 A schematic cross-sectional side view of the same cross section.

[0015] Figure 11 and 12 In order to be in Figure 9 and 10 The instance processing phase following the instance processing phase is along with... Figure 7 and 8 A schematic cross-sectional side view of the same cross section.

[0016] Figure 13 and 14 In order to be in Figure 11 and 12 The instance processing phase following the instance processing phase is along with... Figure 7 and 8 A schematic cross-sectional side view of the same cross section.

[0017] Figure 15 and 16 In order to be in Figure 13 and 14 The instance processing phase following the instance processing phase is along with... Figure 7 and 8 A schematic cross-sectional side view of the same cross section.

[0018] Figure 17 and 18 is an illustrative cross-sectional side view along the same cross-section as Figure 15 and 16 at an example processing stage after the example processing stages of Figure 7 and 8 .

[0019] Figure 19 and 20 is an illustrative cross-sectional side view along the same cross-section as Figure 17 and 18 at an example processing stage after the example processing stages of Figure 7 and 8 .

[0020] Figure 21 and 22 is an illustrative cross-sectional side view along the same cross-section as Figure 19 and 20 at an example processing stage after the example processing stages of Figure 7 and 8 .

[0021] Figure 23 and 24 is an illustrative cross-sectional side view along the same cross-section as Figure 13 and 14 at an example processing stage after the example processing stages of Figure 13 and 14 .

[0022] Figure 25 and 26 is an illustrative cross-sectional side view along the same cross-section as Figure 23 and 24 at an example processing stage after the example processing stages of Figure 23 and 24 .

[0023] Figure 27 and 28 is an illustrative cross-sectional side view along the same cross-section as Figure 25 and 26 at an example processing stage after the example processing stages of Figure 23 and 24 .

[0024] Figure 29 and 30 is an illustrative cross-sectional side view along the same cross-section as Figure 27 and 28 at an example processing stage after the example processing stages of Figure 23 and 24diagrammatic cross-sectional side view along the same cross-section as

[0025] Figure 31 and 32 is an example processing stage after the example processing stages of Figure 29 and 30 diagrammatic cross-sectional side view along the same cross-section as Figure 23 and 24 is an example processing stage after the example processing stages of

[0026] Figure 33 and 34 is an example processing stage after the example processing stages of Figure 23 and 24 diagrammatic cross-sectional side view along the same cross-section as Figure 23 and 24 is an example processing stage after the example processing stages of

[0027] Figure 35 and 36 is an example processing stage after the example processing stages of Figure 33 and 34 diagrammatic cross-sectional side view along the same cross-section as Figure 33 and 34 is an example processing stage after the example processing stages of

[0028] Figure 37 and 38 is an example processing stage after the example processing stages of Figure 31 and 32 diagrammatic cross-sectional side view along the same cross-section as Figure 31 and 32 is an example processing stage after the example processing stages of DETAILED DESCRIPTION

[0029] Some embodiments include methods of forming electrically conductive redistribution structures that convert a rectangular pattern of interconnect regions (e.g., container contact regions of a DRAM array) into a hexagonal pattern (e.g., a pattern of substantially close-packed hexagons). Some embodiments include integrated assemblies (e.g., DRAM assemblies) having a pattern of interconnect regions that are substantially close-packed hexagons. Voids and / or low-k dielectric material can be proximate to the interconnect regions. Example embodiments are described with reference to the drawings provided herein.

[0030] Referring to Figure 1 , a region of an integrated assembly 10 is shown in a diagrammatic top-down view. The assembly includes a plurality of active regions 12 (only some of which are labeled) that are spaced apart from one another by insulating material 14. The active regions 12 are hatched to assist the reader in distinguishing them from the intervening insulating material 14.

[0031] The active regions 12 include a semiconductor material 16. The semiconductor material 16 can include any suitable composition; and in some embodiments can include, consist essentially of, or consist of one or more of: silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc.; where the term III / V semiconductor material refers to a semiconductor material that includes an element selected from Groups III and V of the periodic table (where Groups III and V are the old nomenclature, and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material can include silicon. Such silicon can be in any suitable crystalline form (e.g., single-crystalline, poly-crystalline, amorphous, etc.), and in some embodiments can include, consist essentially of, or consist of single-crystalline silicon in which one or more suitable dopants are provided.

[0032] Each of the active regions 12 is shown as including a pair of capacitor contact regions 18 and 20 (represented with a square structure), and including a digit line contact region 22 between the capacitor contact regions. The digit line contact region 22 is represented by a ring structure.

[0033] The capacitor contact regions 18 and 20 can be referred to as first and second capacitor contact regions, respectively.

[0034] The capacitor contact regions 18, 20 can be viewed as being distributed in an array 24. Digit lines 26 extend along columns of the array, and word lines 28 extend along rows of the array.

[0035] The capacitor contact regions 18, 20 are arranged in a pattern such that six adjacent capacitor contact regions form a generally rectangular configuration 30, where one of such rectangular configurations 30 is labeled and identified in Figure 1 The term "generally rectangular" means rectangular within reasonable tolerances of manufacture and measurement. In Figure 1 The six capacitor contact regions utilized in the rectangular configuration 30 are labeled as regions 31.

[0036] A difficulty encountered during fabrication of integrated memory is the need to form a storage element (e.g., a capacitor) that is electrically coupled with each of the capacitor contact regions 18, 20. The rectangular pattern 30 can limit the packing density of the storage elements. Thus, it can be desirable to provide a redistribution material on the capacitor contact regions 18, 20 to alter the pattern available for contact with the storage elements.

[0037] The term "storage element" refers to a device having at least two detectable states; and in some embodiments can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc. For purposes of explaining example embodiments, a "storage element" can be referred to as a capacitor, and can be represented as a capacitor. However, it should be understood that in other embodiments, such a capacitor can be replaced with any suitable storage element.

[0038] Figure 2 The assembly 10 is shown after the positions of the contacts have been shifted to capacitors (storage elements) with a redistribution material 32. The upper surface of the redistribution material 32 is indicated with a diamond-shaped structure.

[0039] For simplicity of the drawing, the word lines 28 are not shown in Figure 2 .

[0040] The capacitor contact regions 18, 20 are shown in Figure 2 dashed (phantom) view to indicate that other material (e.g., a redistribution material) has been formed over the capacitor contact regions. The redistribution material 32 is coupled with the capacitor contact regions 18, 20 and extends upwardly and laterally outwardly from such capacitor contact regions. The array 24 of capacitor contact regions 18, 22 can be considered to include first and second rows 34, 36 that alternate. The redistribution material 32 along the first row 34 has a first configuration such that the upper surface of the redistribution material 32 is shifted in a first direction 38 relative to the capacitor contact regions 18, 20; and the redistribution material 32 along the second row 36 has a second configuration such that the upper surface of the redistribution material 32 is shifted in a second direction 40 relative to the capacitor contact regions 18, 20. In the illustrated embodiment, the first direction 38 is a rightward direction, and the second direction 40 is a leftward direction. The second direction 40 can be considered to be substantially opposite the first direction 38, where the term "substantially opposite" means opposite within reasonable tolerances of manufacturing and measurement.

[0041] The upper surface of the redistribution material 32 is arranged in a pattern such that seven adjacent upper surfaces of the conductive redistribution material 32 form a unit of a substantially hexagonal close-packed configuration 42, with one of such units being labeled and identified in Figure 2 . The term "substantially hexagonal close-packed" means hexagonal close-packed within reasonable tolerances of manufacturing and measurement. The seven adjacent upper surfaces of the conductive redistribution material utilized in the configuration 42 are labeled as surfaces 43. The hexagonal close-packing can enable capacitors to be closely arranged across the underlying active region 12. In some embodiments, the hexagonal close-packing can maximize the packing density that can be achieved with some capacitor configurations (e.g., a cylindrical configuration).

[0042] Figure 3 The configuration 42 is shown in a top view in Figure 2component 10 without the capacitor contact regions (18, 20) and without the shift directions (38, 40) to simplify the drawing. Capacitors 44 are shown electrically coupled with the upper surface of redistribution material 32. The capacitors are arranged in the close-packed hexagonal configuration described above with reference to Figure 2 unit 42.

[0043] Figure 3A An enlarged view of region "A" of Figure 3 is shown to assist the reader in observing various features of Figure 3 . Figure 3A Capacitors 44 of each include a pair of electrodes (nodes 46 and 48), with electrode 46 coupled to redistribution material 32 and electrode 48 coupled with a reference voltage source 50. The reference voltage source is represented by a triangle. The reference voltage source can be at any suitable reference voltage, including, for example, ground, VCC / 2, etc. Capacitor dielectric material 53 is between electrodes 46 and 48. Capacitors 44 can have any suitable configuration. The capacitors are shown arranged in the close-packed hexagonal configuration 42 described above with reference to Figure 3 .

[0044] Figure 4 A section along line 4-4 of Figure 3 is shown, with one of active regions 12 shown. Active region 12 includes pillars 52 of semiconductor material 16, with such pillars extending upwardly from a block 54 of semiconductor material. Pillars 52 can be referred to as semiconductor pillars, or as semiconductor material pillars.

[0045] Pillars 52 have two trenches 56 and 58 extending therein. Trenches 56 and 58 can be referred to as a first trench and a second trench, respectively. Digit line contact region 22 is within a section of pillar 52 between trenches 56 and 58. First capacitor contact region 18 and second capacitor contact region 20 are along sections of semiconductor pillar 52 outside of trenches 56 and 58. Regions 18, 20, and 22 can correspond to conductive doped source / drain regions 60 within an upper portion of semiconductor pillar 52. Channel region 62 can be within semiconductor material 16 along lower surfaces of trenches 56 and 58.

[0046] Capacitor contact regions 18 and 20 are coupled with capacitors 44, and digit line contact region 22 is coupled with digit line 26. To simplify the drawing, redistribution material 32 is not shown in Figure 4 .

[0047] Word lines 28a and 28b are located within trenches 56 and 58, respectively. Word line 28a may be referred to as a first word line, and word line 28b may be referred to as a second word line. Word lines 28a and 28b comprise conductive word line material 64. Word line material 64 may comprise one or more of any suitable conductive composition, such as various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, word lines 28a and 28b may comprise a metal.

[0048] The word line material 64 is spaced apart from the semiconductor material 16 of the pillar 52 by an insulating material (gate dielectric material) 66. Such insulating material may include any suitable composition; and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0049] The first word line 28a links the first capacitor contact 18 to the digital line contact 22 in a gated manner, and the second word line 28b links the second capacitor contact 20 to the digital line contact 22 in a gated manner. The term "gated coupling" refers to the controlled coupling / decoupling of the source / drain regions (e.g., 20 and 22) that can be induced by the electrical activation / deactivation of the word line 28.

[0050] Figure 5 and 6 Briefly showing along Figure 2 and 3 The cross-sections of directions “5” and “6” are shown, and an example configuration of the redistributed material 32 is displayed. Figure 5 and 6 Show the above references Figure 4 The upper region of the semiconductor material pillar 52 is described, and more specifically, capacitor contact regions 18 / 20 and digital line contact regions 22 are shown. Regions 18 / 20 are spaced apart from region 22 by an intervening region comprising an insulating material 14 (in... Figure 5 and 6 (marked as 14a). Figure 5 and 6 Pillar 52 will include the above references Figure 4 The trenches 58 and channel sections 62 are described, but for simplicity, such sections of the support are not shown. Figure 5 and 6 middle.

[0051] Number line 26 relative to Figure 5 and 6The cross-section of the digit line 26 extends in and out of the page. The digit line 26 includes a conductive digit line material 68. The digit line material 68 can include any suitable electrically conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the digit line 26 can include a metal.

[0052] Some of the digit lines 26 extend along Figure 5 and 6 The cross-section of the digit line 26 extends in and out of the page. The digit line 26 includes a conductive digit line material 68. The digit line material 68 can include any suitable electrically conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the digit line 26 can include a metal.

[0053] Some of the digit lines 26 extend along Figure 5 and 6 The cross-section of the digit line 26 extends in and out of the page. The digit line 26 includes a conductive digit line material 68. The digit line material 68 can include any suitable electrically conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the digit line 26 can include a metal.

[0054] In some embodiments, it can be considered to arrange the digit line contact regions 22 and the capacitor contact regions 18 / 20 into the array 24 described above with reference to Figure 2 and 3 Each of the digit line contact regions 22 can be considered to be between a pair of the capacitor contact regions 18 / 20, as shown in Figure 4 The conductive redistribution material 32 is electrically coupled to the capacitor contact regions by a conductive interconnect material 76. The interconnect material 76 can include the same electrically conductive materials described above with reference to the interconnect material 70. The interconnect materials 70 and 76 can be referred to as first and second interconnect materials to distinguish them from one another. The interconnect materials 70 and 76 can include the same composition as one another, or can include different compositions from one another. In some embodiments, the interconnect materials 70 and 76 can each include, consist essentially of, or consist of a conductively-doped semiconductor material (e.g., conductively-doped silicon).

[0055] The interconnect material 76 can be considered to be a conductive plug 77. The conductive plug 77 has segments 79 (only some segments are labeled) that are directly above the underlying capacitor contact regions 18 / 20.

[0056] Figure 5 are cross-sections along one of the first rows 34 of Figure 2 and 3 are cross-sections along one of the second rows 36 of Figure 6 Figure 2 and 3 The conductive redistribution material 32 is configured as first structures 78 along cross-sections of Figure 5 and as second structures 80 along cross-sections of Figure 6 The first structures 78 are offset from the underlying capacitor contact regions 18 / 20 along a first direction indicated by arrow 38, and the second structures 80 are offset from the underlying capacitor contact regions 18 / 20 along a second direction indicated by arrow 40. For example, Figure 5 One of the structures 78 of Figure 6 is identified with label 80a and is shown as being electrically coupled with the underlying capacitor contact region labeled 18 / 20b through a conductive plug 77b. The structure 80a extends upwardly and laterally outwardly from the underlying capacitor contact region 18 / 20b and the conductive plug 77b, and is laterally offset from the underlying capacitor contact region 18 / 20b and the conductive plug 77b along the second direction 40.

[0057] In some embodiments, the first direction 38 can be considered to be generally along the first rows 34 of Figure 5 and the second direction 40 can be considered to be generally along the second rows 36 of Figure 6 The term "generally along" means "coextensive with" within reasonable tolerances of manufacture and measurement. The second direction 40 is generally opposite the first direction 38, where the term "generally opposite" means opposite within reasonable tolerances of manufacture and measurement.

[0058] Figure 5 The conductive redistribution material 32 of 6 has an upper surface 33, and the capacitor 44 is electrically coupled with such an upper surface.

[0059] In the illustrated embodiment, the structures 78 and 80 of the conductive redistribution material 32 are first structures 78 along cross-sections of Figure 5 ​and 6 The structures 78 can be referred to as first boot-shaped structures, and the structures 80 can be referred to as second boot-shaped structures. Each of the first boot-shaped structures 78 has a toe region 82 that extends into the associated conductive plug 77, and similarly each of the second boot-shaped structures 80 has a toe region 84 that extends into the associated conductive plug 77. Also, each of the first boot-shaped structures 78 has a heel region 86 that is directly above a portion of the digit line 26, and each of the second boot-shaped structures 80 has a heel region 88 that is directly above a portion of the digit line 26. In some embodiments, the heel regions of the structures 78 and 80 can be considered to be above the digit line 26, and to partially overlap (i.e., to partially laterally overlap) the digit line.

[0060] The illustrated boot-shaped structures 78 and 80 each include a first material 90 and a second material 92, where such first and second materials 90 and 92 together are the redistribution material 32. The materials 90 and 92 can include any suitable electrically conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, the material 90 is a composition that includes one or more metals. For example, the material 90 can include, consist essentially of, or consist of one or both of tungsten and titanium. In some embodiments, the material 92 includes a metal silicide. For example, the material 92 can include, consist essentially of, or consist of one or more of CoSi, WSi, and TiSi; where the chemical formula indicates the primary constituent rather than a specific stoichiometry. In some embodiments, the material 92 can be referred to as including, consisting essentially of, or consisting of one or more of cobalt silicide, tungsten silicide, and titanium silicide.

[0061] The first boot-shaped structures 78 are substantially mirror images of the second boot-shaped structures 80, where the term "substantially mirror images" means that the mirror images are within reasonable manufacturing and measurement tolerances.

[0062] The insulating material 14b (e.g., silicon nitride, silicon dioxide, etc.) laterally between the structures 78, and along Figure 5 the digit line 26, and along Figure 6The cross-section is transversely located between structures 80. In some embodiments, insulating material 14b may be considered as an insulating block 15 above digital line 26 and conductive plug 77. Structures 78 and 80 may be considered as extending downward through insulating block 15 and into conductive plug 77. In some embodiments, insulating material 14b may be the same as insulating material 14a (e.g., both may comprise silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide). In other embodiments, insulating material 14b may be different from insulating material 14a. For example, in some embodiments, insulating material 14b may comprise silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride, while insulating material 14a comprises silicon dioxide.

[0063] In the illustrated embodiment, insulating regions 200 (only some are labeled) are adjacent to conductive plugs 77 and spaced apart from digital lines 26. Insulating regions 200 are shown as comprising two portions 206 and 208. Portion 206 may be referred to as an insulating structure, beam, track, etc., and includes insulating material 202. Material 202 may include any suitable composition, such as silicon nitride. Portion 208 may include one or both of a void and a low-k dielectric material (wherein the term "low-k" means a dielectric constant less than that of silicon dioxide, and more precisely less than about 3.7). Portion 208 is shown as having region 204 therein. If portion 208 is a void, then region 204 may be an air-filled void (e.g., a void filled with one or more of air, nitrogen, argon, etc.), and if the portion includes a low-k dielectric material, then region 204 may be filled with one or more of porous silicon dioxide, carbon-doped silicon dioxide, boron-doped silicon dioxide, etc.

[0064] although Figure 5 and 6 The example embodiment illustrates an insulating region 200 comprising two separate portions 206 and 208. In other example embodiments, the insulating region may include more than two separate portions or only a single homogeneous configuration. See below for reference. Figure 31 and 32 The description includes an example embodiment where the insulating region 200 includes a single homogeneous configuration.

[0065] In the illustrated embodiment, some of the portions 208, including voids and / or low-k dielectric material, directly contact the upper surface of the capacitor contact areas 18 / 20.

[0066] Figures 2 to 6 The configuration can be formed using any suitable method. (See reference) Figures 7 to 22 Describe the instance method.

[0067] refer to Figure 7 and 8 Component 10 is shown along rows 34 and 36 respectively. Figure 7 and8 The region of component 10 can be considered as being formed with semiconductor material pillars 52 (similar to...) Figure 4 The support 52 is constructed as follows. Support 52 includes a digital line contact area 22 and capacitor contact areas 18 / 20. Areas 22 and 18 / 20 can be configured similarly to... Figure 2 and 3 Within the array 24. This type of array has alternating first row 34 and second row 36. Capacitor contact areas 18 / 20 are spaced apart from digital line contact areas 22 along this row by insulating material 14a.

[0068] Figure 7 and 8 The structure contains 26 digital lines, some of which are along... Figure 7 and 8 The cross-section is directly above the digital line contact area 22.

[0069] Figure 7 and 8 The construction also includes an insulating material 214 above the digital line 26, and a conductive plug material 76 extending above the insulating material 214 and contacting the capacitor contact areas 18 / 20. The insulating material 214 may include any suitable composition, and in some embodiments may include silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride. The insulating material 214 may be... Figure 5 and 6 The same composition as insulating material 14b.

[0070] Materials 202 and 210 are laterally located between materials 76 and 214. Material 202 may include silicon nitride, as referenced above. Figure 5 and 6 As discussed above. Material 210 is a sacrificial material and may include any suitable composition. In some embodiments, material 210 may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. In such embodiments, a protective material (passivating material) may be disposed between oxide 210 and the conductive material 68 of digital line 26 to prevent unwanted oxidation of the digital line. In some embodiments, sacrificial material 210 may include silicon, metal, etc., be substantially composed of silicon, metal, etc., or be composed of silicon, metal, etc.

[0071] See Figure 8 and 9 The planarized surface 201 is formed extending across materials 214, 76, 202, and 210. The planarized surface can be formed by any suitable process including, for example, chemical mechanical polishing (CMP).

[0072] The formation of the planarization surface 201 patterns the conductive material 76 into the conductive plug 77. The conductive plug 77 has a pattern corresponding to the direction along the surface.Figure 9 and 10 a lateral dimension of a cross-section of the dimension D. The dimension D can be any suitable dimension, and in some embodiments, can be in a range from about 10 nanometers (nm) to about 300 nm. The conductive plug 77 can be considered to have an upper surface 81 of a cross-section along Figure 9 and 10 a first dimension of the cross-section of the dimension D.

[0073] In some embodiments, Figure 9 and 10 a cross-section of the cross-section of the first and second cross-sections of the assembly 10; wherein Figure 9 the first cross-section of the cross-section is along one of the first rows 34, and Figure 10 the second cross-section of the cross-section is along one of the second rows 36.

[0074] Referring to Figure 11 and 12 the materials 214, 202, and 210 are recessed relative to the conductive plug 77 to form a cavity 212 adjacent to an upper region of the conductive plug. The sacrificial material 210 is exposed along a bottom surface of the cavity 212.

[0075] Figure 11 and 12 the cavity 212 of the cross-section of the cross-section can have any suitable lateral width W along Figure 11 and 12 the cross-section of the cross-section. In some embodiments, such lateral width can be in a range from about 15 nm to about 30 nm.

[0076] Figure 11 and 12 the assembly 10 of the cross-section of the cross-section can be considered to have a configuration of the sacrificial material 210 between the digit line 26 and the conductive plug 77.

[0077] Referring to Figure 13 and 14 the sacrificial material 210 is removed ( Figure 11 and 12 ) to form a void region (void) 204. In embodiments in which the sacrificial material 210 comprises silicon dioxide, such removal can utilize an etchant comprising hydrofluoric acid.

[0078] Figure 13 and 14 the void region 204 of the cross-section of the cross-section can have any suitable lateral width W1, and in some embodiments, such lateral width can be in a range from about 3 nm to about 10 nm.

[0079] Referring to Figure 15 and 16 an insulating block 218 is formed over the conductive plug 77 and the void. The insulating block 218 seals the void.

[0080] The insulating block 218 comprises an insulating material 216. The insulating material 216 can comprise any suitable composition, and in some embodiments can comprise, consist essentially of, or consist of silicon nitride. The insulating material 216 can be the same composition as the insulating material 14b of Figure 5 and 6 .

[0081] With reference to Figure 17 and 18 , the openings 95 and 97 are formed to extend through the block 218 and into the conductive plug 77; wherein the openings 95 and 97 are respectively along cross-sections of Figure 17 and 18 . In some embodiments, the opening 95 can be referred to as a first opening, and the opening 97 can be referred to as a second opening.

[0082] The openings 95 and 97 can be formed by any suitable process. For example, a patterned mask (not shown) can be utilized to define the locations of the openings, and then a multi-step etching process can be utilized to form the openings. The multi-step etching process can utilize, for example, one or more anisotropic etches to penetrate the block 218 and partially penetrate into the plug 77, followed by an isotropic etch to laterally extend into the plug 77.

[0083] The first and second openings 95 and 97 can be considered to have first and second shapes, respectively, at processing stages of Figure 17 and 18 . The second shape of the opening 97 is generally a mirror image of the first shape of the opening 95. In the illustrated embodiment, the first and second shapes of the openings 95 and 97 are boot shapes, with the toe of the boot extending into the conductive plug 77.

[0084] With reference to Figure 19 and 20 , a metal silicide 92 is formed along the exposed upper surface of the conductive material 76 of the plug 77. In some embodiments, the conductive material 76 can comprise conductively-doped silicon, and the metal silicide 92 can be formed by one or more suitable reactions of one or more metals with the silicon of the material 76. Alternatively or additionally, the metal silicide 92 can be formed using, for example, one or more of atomic layer deposition, chemical vapor deposition, and physical vapor deposition. The metal silicide 92 can comprise any suitable composition; and in some embodiments can comprise, consist essentially of, or consist of one or more of cobalt silicide, tungsten silicide, and titanium silicide.

[0085] With reference to Figure 21 and 22Conductive material 90 is formed within openings 95 and 97 to fill such openings. In some embodiments, conductive material 90 may comprise one or both of titanium and tungsten, be substantially composed of one or both of titanium and tungsten, or be composed of one or both of titanium and tungsten.

[0086] In the illustrated embodiment, the planarized surface 101 extends across the conductive material 90 within the openings 95 and 97 and across the upper surface of the insulating material 216. The planarized surface 101 can be formed using any suitable process, including, for example, CMP.

[0087] Materials 90 and 92 together form redistributed material 32. Therefore, utilization can be considered. Figures 15 to 22 The processing stage forms redistributed material 32 within openings 95 and 97.

[0088] In subsequent processes, a capacitor may be formed above surface 101 and coupled to redistributed material 32 to form the above reference. Figure 5 and 6 The integrated components described. Capacitors can be generally arranged as follows: Figure 3A The close-packed hexagonal configuration 42 shown is an example.

[0089] The redistribution configuration described above (i.e., the configuration including redistribution material 32) can be used to shift the capacitor contact area in any suitable direction by any suitable amount. Although the embodiments presented herein utilize a redistribution structure to shift the capacitor contact area in opposite directions along rows 34 and 36, and shift the capacitor contact area by approximately equal amounts along each of these opposite directions, in other embodiments, a redistribution structure can be used to shift the capacitor contact area in other directions, or shift it by other amounts. For example, in exemplary embodiments that are alternative to those specifically shown in the figures provided herein, the amount by which the capacitor contact area is shifted along row 34 may be different from the amount shifted along row 36.

[0090] refer to Figures 23 to 32 Describe another instance method.

[0091] Figure 23 and 24 The display can be Figure 13 and 14 Component 10 is processed in the next stage after the previous stage. Material 202 is removed. Figure 13 and 14 This allows the void region 204 to extend laterally. In some embodiments, material 202 may include silicon nitride and may be removed using phosphoric acid etching. Material 202 may be referred to as a second sacrificial material to be used in conjunction with... Figure 11 and 12 The first sacrificial material 210 is distinguished.

[0092] Figure 23 and 24 The void region 204 of Figure 13 , 14 , 23 and 24 is formed by first removing the first sacrificial material (210) of Figure 11 and 12 and then removing the second sacrificial material (202) of Figure 11 and 12 In other embodiments, the sacrificial material 202 can be omitted, such that the material 210 completely fills the space between the conductive plug 77 and the digit line 26 at the processing stage of Figure 11 and 12 and thus the void region 204 of Figure 23 and 24 may be formed by simply removing the material 210.

[0093] In the illustrated embodiment, the insulating material 214 on top of the digit line 26 is laterally thinned by the conditions used to remove the material 202. In some embodiments, both materials 202 and 214 can comprise silicon nitride, and thus material 214 can be thinned by the conditions used to remove material 202. The height of material 214 can be reduced during such etching, even if this reduction is not specifically shown in Figure 23 and 24 .

[0094] With reference to Figure 25 and 26 , a low-k dielectric material 220 is formed over the assembly 10 and within the void region 204. In the illustrated embodiment, the low-k dielectric material completely fills the void region 204. In other regions, the low-k dielectric material can only partially fill the void region.

[0095] The low-k dielectric material can comprise any suitable composition, and in some embodiments can comprise, consist essentially of, or consist of one or more of porous silicon dioxide, SiOC, and SiOB, where the chemical formula indicates the primary constituent rather than a specific stoichiometry. In some embodiments, SiOC and SiOB can correspond to carbon-doped and boron-doped silicon dioxide, respectively.

[0096] With reference to Figure 27 and 28 , the low-k dielectric material 220 is removed from the entire upper surface of the conductive plug 77. The remaining low-k dielectric material is shown as completely filling the void 204. In other embodiments, the material 220 can be removed to an extent such that the remaining material only partially fills the void 204.

[0097] Referring to Figure 29 and 30 , an insulative block 218 of material 216 is formed over the conductive plug 77 and over the low-k dielectric material 220.

[0098] Referring to Figure 31 and 32 , the materials 90 and 92 are formed using processes similar to those described above with reference to Figures 17 to 22 to form the conductive redistribution material 32. Figure 31 and 32 are similar to the configuration of Figure 5 and 6 except that the low-k dielectric material 220 completely fills the intervening region 200 between the digit lines 26 and the conductive plugs 77.

[0099] In the illustrated embodiments of Figure 31 and 32 , the low-k dielectric material 220 extends across the upper surfaces of the digit lines 26 as a result of the lateral thinning of the material 214. The material 220 does not extend under the digit lines. In other embodiments, the material 74 can be laterally thinned along with the material 214 during removal of the sacrificial material 202. For example, Figure 33 and 34 show the integrated assembly 10 at a processing stage that can follow the processing stages of Figure 13 and 14 and is similar to the processing stages of Figure 23 and 24 except that the lower insulative material 74 is laterally thinned along with the material 214 during removal of the material 202. Subsequent processes form the configuration shown in Figure 35 and 36 which is similar to the configuration of Figure 31 and 32 but in which the low-k dielectric material 220 extends under some of the digit lines 26 and over some of the digit lines. In the illustrated embodiments, the material 220 extends over all of the digit lines within the cross-section of Figure 35 and 36 but only under every other digit line along such cross-sections (and, in particular, only under digit lines that are supported by the insulative materials 72 and 74).

[0100] In some embodiments, the intervening region 200 between the digit lines 26 can include both voids and low-k dielectric material. For example, Figure 37 and 38 show that the intervening region 200 between the digit lines 26 can include both voids and low-k dielectric material. For example, Figure 27 and 28a region of the integrated assembly 10 at a processing stage after the processing stage of the first processing stage, and wherein the region 200 includes a lower portion containing the low-k dielectric material 220, and includes an upper region including the void 204. Figure 37 and 38 The assembly of FIG. 2 can be formed by recessing the material 220 below the digit line 68 to leave a void 204 above the recessed material 220, and then sealing the void 204 with the material 216.

[0101] Although Figure 37 and 38 The configuration is shown in which the intervening region 200 includes a void region 204 above the low-k dielectric material, but in other embodiments the void region can be laterally adjacent to the low-k dielectric material, and / or can be below the low-k dielectric material.

[0102] With the advantage of one or both of a void region and a low-k dielectric material within the intervening region 200, this can enable the k value of such regions to be modulated (adjusted) by adjusting the location and thickness of the void region and the low-k dielectric material containing region utilized within such intervening region 200.

[0103] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit that is supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and business machines, and can include multilayer, multichip modules. The electronic systems can be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0104] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed using any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0105] The terms "dielectric" and "insulative" can be used to describe materials having insulative electrical properties. The terms are considered synonymous within the present disclosure. The use of the term "dielectric" in some instances and the term "insulative" (or "electrically insulative") in other instances can provide a linguistic variation within this disclosure to simplify the premise in the claims that follow, and not to indicate any significant chemical or electrical difference.

[0106] The terms "electrically connected" and "electrically coupled" can both be used in the present disclosure. The terms are considered synonymous. Use of one term in some instances and the other in others can provide linguistic variety within this disclosure to simplify the premise base within the appended claims.

[0107] The particular orientations of the various embodiments in the drawings are for purposes of illustration only and the embodiments can, in some applications, be rotated relative to the orientations shown. The description herein and the appended claims relate to any structure that has the described relationship between the various features, regardless of the particular orientation of the structure in the drawings.

[0108] Unless otherwise noted, the cross-sectional views of the accompanying drawings are only exemplary and do not show the material behind the cross-sectional plane in order to simplify the drawings.

[0109] When a structure is referred to as being "on," "adjacent," or "resisting" another structure, the structure can be directly on the other structure or intervening structures can also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent," or "directly resisting" another structure, no intervening structure is present. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0110] A structure (e.g., a layer, material, etc.) can be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying base (e.g., a substrate). A vertically extending structure can extend generally perpendicular relative to an upper surface of the base, or can not extend perpendicular relative to an upper surface of the base.

[0111] Some embodiments include an integrated assembly having active regions each having a digit line contact region between a pair of capacitor contact regions. The capacitor contact regions are arranged in a pattern such that six adjacent capacitor contact regions form a generally rectangular configuration. A conductive plug is coupled with the capacitor contact regions. A conductive redistribution material is coupled with the conductive plug and passes through the conductive plug to the capacitor contact regions. The conductive redistribution material extends upward and laterally outward from the conductive plug. An upper surface of the conductive redistribution material is arranged in a pattern such that seven adjacent upper surfaces form a generally hexagonal close packed configuration of cells. A digit line is over the digit line contact regions. An insulating region is between the digit line and the conductive plug. The insulating region contains one or both of voids and low-k dielectric material, where the voids and / or low-k dielectric material contact upper surfaces of the capacitor contact regions. A capacitor is coupled with the upper surface of the conductive redistribution material.

[0112] Some embodiments include an integrated assembly having semiconductor material pillars each having a digit line contact region between a pair of capacitor contact regions. The capacitor contact regions are arranged in an array, where the array has alternating first and second rows. Conductive plugs are coupled with the capacitor contact regions. A conductive redistribution material is coupled with the conductive plugs and through the conductive plugs to the capacitor contact regions. The conductive redistribution material has a first configuration along the first rows, where the first configuration extends laterally outward from the capacitor contact regions of the first rows in a first direction generally along the first rows. The conductive redistribution material has a second configuration along the second rows, where the second configuration extends laterally outward from the capacitor contact regions of the second rows in a second direction generally along the second rows. The second direction is generally opposite the first direction. The conductive redistribution material has an upper surface. A digit line is over the digit line contact regions. An insulating region is between the digit line and the conductive plugs. The insulating region includes one or both of voids and low-k dielectric material, where the voids and / or low-k dielectric material contact the upper surface of the capacitor contact regions. A capacitor is coupled with the upper surface of the conductive redistribution material.

[0113] Some embodiments include a method of forming an integrated assembly. A semiconductor material pillar is formed to have a digit line contact region between a pair of capacitor contact regions. The capacitor contact regions are arranged in an array, where the array has alternating first and second rows. The digit line contact region is spaced apart from the capacitor contact regions along a first cross-section that is along the first rows and along a second cross-section that is along the second rows. A digit line is over the digit line contact region along the first and second cross-sections. A conductive plug is over the capacitor contact regions along the first and second cross-sections. A sacrificial material is between the conductive plug and the digit line. The sacrificial material is removed to form a void region. An insulating block is formed to extend across the conductive plug. A first opening is formed to extend to the conductive plug along the first cross-section and a second opening is formed to extend to the conductive plug along the second cross-section. The first and second openings have a first shape and a second shape, respectively, where the second shape is generally a mirror image of the first shape. A conductive redistribution material is formed within the first and second shapes of the first and second openings. A capacitor is formed to be coupled with the conductive redistribution material.

[0114] In compliance with the statute, the subject matter disclosed herein has been described in language specific to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means disclosed herein comprise example embodiments. Rather, the scope of the claims should be construed as broadly as the language permits and specified equivalents are to be given the full scope of equivalents throughout the nation.

Claims

1. An integrated assembly comprising: active regions each having a digit line contact region between a pair of capacitor contact regions, the capacitor contact regions arranged in a pattern such that six adjacent capacitor contact regions form a generally rectangular configuration; conductive plugs coupled with the capacitor contact regions; conductive redistribution material coupled with the conductive plugs and through the conductive plugs to the capacitor contact regions; the conductive redistribution material extending upwardly and laterally outwardly from the conductive plugs; an upper surface of the conductive redistribution material arranged in a pattern such that seven adjacent upper surfaces form a generally hexagonal close packed configuration; digit lines over the digit line contact regions; insulation regions between the digit lines and the conductive plugs; the insulation regions comprising one or both of voids and low-k dielectric material, wherein the voids and / or low-k dielectric material contact upper surfaces of the capacitor contact regions; and capacitors coupled with the upper surfaces of the conductive redistribution material.

2. The integrated assembly of claim 1, wherein: the capacitor contact regions are arranged in an array; the array has alternating first and second rows; the conductive redistribution material has a first configuration along the first rows, wherein the first configuration extends laterally outwardly from the capacitor contact regions of the first rows in a first direction generally along the first rows; and the conductive redistribution material has a second configuration along the second rows, wherein the second configuration extends laterally outwardly from the capacitor contact regions of the second rows in a second direction generally along the second rows; the second direction is generally opposite the first direction.

3. The integrated assembly of claim 1, wherein: the active regions are semiconductor material pillars; each of the pillars has two trenches extending therein, wherein the two trenches are a first trench and a second trench; each of the pillars has two of the capacitor contact regions and one of the digit line contact regions, wherein the two capacitor contact regions are a first capacitor contact region and a second capacitor contact region; a first word line is within the first trench and gates the first capacitor contact region to the digit line contact region; and a second word line is within the second trench and gates the second capacitor contact region to the capacitor contact region.

4. The integrated assembly of claim 1, wherein the conductive plugs comprise conductively doped semiconductor material.

5. The integrated assembly of claim 1, wherein the conductive plugs comprise conductively doped silicon.

6. The integrated assembly of claim 1, wherein the insulation regions comprise the voids.

7. The integrated assembly of claim 1, wherein the insulation regions comprise the low-k dielectric material.

8. The integrated assembly of claim 1, wherein the insulation regions comprise both the voids and the low-k dielectric material.

9. The integrated assembly of claim 1, wherein the conductive redistribution material comprises metal on metal silicide.

10. The integrated assembly of claim 9, wherein the metal consists essentially of one or both of tungsten and titanium; and wherein the metal silicide comprises one or more of cobalt silicide, tungsten silicide, and titanium silicide.

11. The integrated assembly of claim 1, wherein the insulative regions extend above the digit lines.

12. The integrated assembly of claim 1, wherein the insulative regions extend below at least some of the digit lines.

13. The integrated assembly of claim 1, wherein the insulative regions include a low-k dielectric material that extends above all of the digit lines and extends below some of the digit lines.

14. An integrated assembly comprising: semiconductor material pillars each having a digit line contact region between a pair of capacitor contact regions; the capacitor contact regions arranged in an array, with the array having alternating first and second rows; conductive plugs coupled with the capacitor contact regions; conductive redistribution material coupled with the conductive plugs and through the conductive plugs to the capacitor contact regions; the conductive redistribution material having a first configuration along the first rows, with the first configuration extending laterally outward from the capacitor contact regions of the first rows in a first direction generally along the first rows; the conductive redistribution material having a second configuration along the second rows, with the second configuration extending laterally outward from the capacitor contact regions of the second rows in a second direction generally along the second rows; the second direction being generally opposite the first direction; the conductive redistribution material having an upper surface, with the upper surface of the conductive redistribution material arranged in a pattern such that seven adjacent upper surfaces form a unit of a generally hexagonal close packed configuration; digit lines above the digit line contact regions; insulative regions between the digit lines and the conductive plugs; the insulative regions including one or both of voids and a low-k dielectric material, with the voids and / or low-k dielectric material contacting upper surfaces of the capacitor contact regions; and capacitors coupled with the upper surface of the conductive redistribution material.

15. The integrated assembly of claim 14, the insulative regions including the voids.

16. The integrated assembly of claim 14, wherein the insulative regions include the low-k dielectric material.

17. The integrated assembly of claim 14, wherein the insulative regions include the voids and the low-k dielectric material.

18. The integrated assembly of claim 14, wherein the conductive redistribution material is above the digit lines and partially laterally overlaps the digit lines.

19. The integrated assembly of claim 14, wherein: the digit line contact regions are spaced apart from the capacitor contact regions within a cross-section, the cross-section being along a longitudinal section of the first rows; the digit line contact regions are directly above the digit lines within the cross-section; insulative blocks are above the conductive plugs and the digit lines; and the conductive redistribution material extends down through the insulative blocks and into the conductive plugs within the cross-section. ​ 20. The integrated assembly of claim 19, wherein the electrically conductive plugs comprise an electrically conductive doped semiconductor material.

21. The integrated assembly of claim 19, wherein the electrically conductive plugs comprise electrically conductive doped silicon.

22. The integrated assembly of claim 19, wherein the electrically conductive redistribution material is configured as a boot-shaped structure within the cross-section, wherein each of the boot-shaped structures has a toe region extending into one of the electrically conductive plugs and has a heel region directly above one of the digit lines.

23. The integrated assembly of claim 22, wherein: the electrically conductive redistribution material comprises a composition consisting essentially of one or both of tungsten and titanium; and the toe region of the boot-shaped structure comprises a metal silicide.

24. The integrated assembly of claim 23, wherein the metal silicide comprises one or more of CoSi, WSi, and TiSi, wherein the chemical formula indicates a primary component rather than a specific stoichiometry.

25. The integrated assembly of claim 22, wherein: the cross-section is a first cross-section and the boot-shaped structure is a first boot-shaped structure; the digit line contact region is spaced apart from the capacitor contact region within a second cross-section, the second cross-section being along a longitudinal section of the second row; and the electrically conductive redistribution material is configured as a second boot-shaped structure within the second cross-section, wherein the second boot-shaped structure is substantially a mirror image of the first boot-shaped structure.

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