Three-dimensional memory and methods of manufacturing the same

Abstract

The application provides a method for manufacturing a three-dimensional memory and the three-dimensional memory. The method comprises: forming a stack structure on a substrate; forming a channel structure and a gate line gap extending into the substrate through the stack structure, and forming a gate layer in the stack structure through the gate line gap, the channel structure comprising a functional layer and a channel layer; forming a deposition layer on the inner wall of the gate line gap and arranging a conductive filler in the gate line gap; removing part of the substrate, part of the deposition layer and part of the functional layer to expose the conductive filler and the channel layer; and forming a conductive layer on the side of the substrate away from the stack structure and in contact with the exposed conductive filler and channel layer.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to a three-dimensional memory and a method for manufacturing the same. Background Technology

[0002] In conventional 3D NAND flash memory fabrication processes, forming the gate slot structure for partitioning the memory typically involves creating gate slots and depositing oxides and conductive materials to fill them. To facilitate subsequent fabrication processes, existing techniques often partially etch the high-dielectric-constant dielectric layer at the bottom of the gate slots before oxide deposition and conductive material filling, using the remaining high-dielectric-constant dielectric layer at the bottom of the gate slots as an etch stop layer for subsequent substrate removal. The structure of 3D NAND flash memory fabricated using this technique is characterized by a floating conductive material filling layer within the gate slot structure; that is, an intermediate dielectric exists between the conductive material filling layer and the source layer.

[0003] Because the intermediate dielectric layer between the conductive filler layer and the source layer in the gate gap electrically isolates the conductive filler from the source layer, an inductive coupling effect occurs between the selected memory block and the surrounding unselected memory blocks when an operating voltage (e.g., read / write voltage or erase operation) is applied to the selected memory block. This causes charge to accumulate around the portion of the channel structure of the unselected memory blocks located in the source layer, affecting the voltage state of the unselected memory blocks and consequently impacting the electrical performance of the 3D memory. As the number of memory blocks in a 3D memory increases, this adverse effect caused by inductive coupling becomes increasingly severe.

[0004] Therefore, there is a need for a method for manufacturing three-dimensional memory and a three-dimensional memory that can effectively eliminate the inductive coupling effect between memory blocks.

[0005] It should be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not part of what a person skilled in the art knew or understood prior to the relevant valid application date of the subject matter disclosed herein. Summary of the Invention

[0006] In order to solve or partially solve at least one of the above-mentioned problems existing in the prior art, or to solve other problems existing in the prior art, this application provides a method for manufacturing a three-dimensional memory.

[0007] This application provides a method for fabricating a three-dimensional memory, characterized in that the method includes: forming a stacked structure on a substrate; forming a channel structure and a gate wire gap that penetrate the stacked structure and extend into the substrate, and forming a gate layer within the stacked structure via the gate wire gap, the channel structure including a functional layer and a channel layer; forming a deposited layer on the inner wall of the gate wire gap and disposing a conductive filler in the gate wire gap; removing a portion of the substrate, and removing a portion of the deposited layer and a portion of the functional layer to expose the conductive filler and the channel layer on the side of the substrate away from the stacked structure; and forming a conductive layer on the remaining substrate away from the stacked structure that contacts the exposed conductive filler and the channel layer.

[0008] In one embodiment of this application, the method further includes: forming a dielectric layer on the inner wall of the gate line slot before forming the gate layer; and removing the portion of the dielectric layer located at the bottom of the gate line slot before forming the deposited layer.

[0009] In one embodiment of this application, forming a deposition layer on the inner wall of the gate wire slot includes: forming a first deposition layer on the inner wall of the gate wire slot; removing the portion of the first deposition layer located at the bottom of the gate wire slot to expose the substrate; and forming a second deposition layer on the inner wall of the gate wire slot.

[0010] In one embodiment of this application, removing a portion of the substrate includes: removing a portion of the substrate to expose the bottom end of the second deposited layer and a portion of the functional layer.

[0011] In one embodiment of this application, removing a portion of the deposited layer further includes removing the portion of the second deposited layer located at the bottom of the gate wire gap to expose the conductive filler in the gate wire gap.

[0012] In one embodiment of this application, removing a portion of the functional layer includes removing the exposed functional layer while removing the second deposition layer to expose the channel layer.

[0013] In one embodiment of this application, forming a first deposition layer on the inner wall of the grid line slot includes: sequentially forming a first sub-deposition layer and a second sub-deposition layer on the inner wall of the grid line slot.

[0014] In one embodiment of this application, the conductive filler includes polycrystalline silicon.

[0015] In one embodiment of this application, the conductive layer is a polycrystalline silicon layer.

[0016] This application also provides a three-dimensional memory, characterized in that it includes: a substrate; and a stacked structure disposed on one side of the substrate;

[0017] A conductive layer is disposed on the side of a substrate away from the stacked structure; a channel structure extends through the stacked structure, the channel structure including a channel layer and a functional layer surrounding the channel layer; a gate line slot structure extends through the stacked structure, the gate line slot structure including a conductive filler and a deposited layer surrounding the conductive filler; and wherein the conductive layer is in contact with the conductive filler and the channel layer.

[0018] In one embodiment of this application, the conductive filler includes polycrystalline silicon.

[0019] In one embodiment of this application, the conductive layer is a polycrystalline silicon layer.

[0020] In one embodiment of this application, the deposition layer includes a first deposition layer and a second deposition layer.

[0021] In one embodiment of this application, the first deposition layer includes a first sub-deposition layer and a second sub-deposition layer.

[0022] In one embodiment of this application, the first deposition layer and the second deposition layer comprise oxide layers.

[0023] Compared with the prior art, the advantages of the method for preparing a three-dimensional memory provided by some embodiments of this application include at least the following:

[0024] The charge generated around the selected non-operated memory block due to the inductive coupling effect with the selected memory block can be discharged to the outside of the three-dimensional memory. This can effectively reduce the inductive coupling effect between memory blocks, thereby eliminating the influence of the selected memory block on the state of the surrounding memory blocks and thus ensuring the electrical performance of the three-dimensional memory. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of this application;

[0027] Figures 2 to 11 This is a cross-sectional schematic diagram of the structure obtained by the fabrication method of the three-dimensional memory according to the embodiments of this application; and

[0028] Figure 12 This is a cross-sectional schematic diagram of the structure of a three-dimensional memory according to an embodiment of this application. Detailed Implementation

[0029] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, the following discussion is not devised without departing from the teachings of this application. Conversely, the same applies.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, as used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] Relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device beyond those depicted in the figures. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “below” the other element will be oriented “above” the other element. Thus, depending on the specific orientation of the figure, the exemplary term “below” can encompass both “below” and “above” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “above” and “below” orientations.

[0033] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of this application. (Reference) Figure 1 The method 1000 provided in this application includes:

[0037] Step S110: A multilayer structure is formed on the substrate;

[0038] Step S120: Form a channel structure and gate line gap that penetrate the stacked structure and extend into the substrate, and form a gate layer in the stacked structure through the gate line gap. The channel structure includes a functional layer and a channel layer.

[0039] Step S130: A deposition layer is formed on the inner wall of the grid line slot and a conductive filler is disposed in the grid line slot;

[0040] Step S140: Remove part of the substrate, part of the deposited layer, and part of the functional layer to expose the conductive filler and the channel layer;

[0041] Step S150: A conductive layer is formed on the side of the remaining substrate away from the stacked structure, which is in contact with the exposed conductive filler and channel layer.

[0042] The specific processes of each step in the above-described fabrication method 1000 will be described in detail below. For ease of understanding, the structure of a 3D NAND memory is used as an example in the following description; however, this application is not limited thereto. Those skilled in the art will understand that this application can also be applied to other three-dimensional memories with similar structures.

[0043] Figures 2 to 11 This is a cross-sectional schematic diagram of the structure obtained by the three-dimensional memory fabrication method 1000 according to an embodiment of this application. It should be understood that some of the steps in this process may be performed simultaneously or in a manner different from [the steps described herein]. Figure 1The execution order is shown below. (Followed by...) Figures 2 to 11 The steps S110 to S150 described above are described in further detail.

[0044] Step S110: Form a stacked structure on the substrate.

[0045] In step S110, as Figure 2 As shown, substrate 110 can be a composite substrate. Specifically, a first oxide layer 112, a first polysilicon layer 113, a second oxide layer 114, and a second polysilicon layer 115 can be sequentially formed on substrate 111 using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form substrate 110. It is understood that the above structure is merely exemplary, and the substrate of the present invention is not limited thereto; the substrate can be realized by depositing other different layers on the substrate.

[0046] Optionally, the substrate 111 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. The materials of the first oxide layer 112 and the second oxide layer 114 may be silicon oxide, and the materials of the first polycrystalline silicon layer 113 and the second polycrystalline silicon layer 115 may be polycrystalline silicon, but are not limited thereto.

[0047] After forming the substrate 110, a stacked structure 120 can be formed on one side of the substrate 110. The stacked structure 120 includes a plurality of overlapping gate dielectric layers 121 and gate sacrificial layers 122. The formation method of the stacked structure 120 may include thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. In the stacked structure 120, the thicknesses of the plurality of gate dielectric layers 121 may be the same or different, and the thicknesses of the plurality of gate sacrificial layers 122 may be the same or different, and can be set according to specific process requirements. In addition, in the manufacturing process of the stacked structure 120, different numbers of stacked layers correspond to different stacking heights. For example, the number of stacked layers in the stacked structure 120 may be 8 layers, 32 layers, 64 layers, 128 layers, etc., and this application does not impose specific limitations on this. The gate dielectric layer 121 and the gate sacrificial layer 122 may each include a first dielectric material and a second dielectric material different from the first dielectric material. According to one exemplary embodiment, the gate dielectric layer 121 may be made of silicon dioxide, which may also be doped with impurities such as phosphorus, boron, fluorine, and carbon, but is not limited thereto. According to one exemplary embodiment, the gate sacrificial layer 122 may be made of silicon nitride, but is not limited thereto.

[0048] The fabrication method of a single stacked structure 120 has been described above. In fact, with the increasing demand for storage capacity in three-dimensional memory, the size of the memory stack is gradually increasing. To overcome the limitations of traditional processes, dual-stack or multi-stack techniques can be used. This involves sequentially stacking N (N≥2) sub-stacked structures along the thickness direction of the stacked structure to form a stacked structure. Each sub-stacked structure may include multiple alternately stacked insulating layers and gate sacrificial layers. The number of layers in each sub-stacked structure can be the same or different. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on either a multi-stacked structure or a single-stacked structure.

[0049] In some embodiments, the edges of the stacked structure 120 may form a stepped structure. This stepped structure can be formed by performing multiple trim-etch cycles on the plurality of gate dielectric layers 121 and the plurality of gate sacrificial layers 122 of the stacked structure 120. After the above process, the region on the substrate 110 corresponding to the stepped structure formed by the stacked structure 120 may be referred to as the stepped region, which may be an electrical connection region for providing word lines (gate layers).

[0050] Step S120: Form a channel structure and gate line gap that penetrate the stacked structure and extend into the substrate, and via the gate... The wire gap forms the gate layer within the stacked structure, and the channel structure includes a functional layer and a channel layer.

[0051] In step S120, as Figure 3 As shown, a channel hole 310 is formed in the stacked structure 120, extending through the stacked structure 120 and into the substrate 110 along the thickness direction of the stacked structure 120. The channel hole 310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing. The channel hole 310 may have a cylindrical or columnar shape that extends through the stacked structure 120 and into the substrate 110.

[0052] The channel structure 300 includes a channel hole 310 filled with a semiconductor layer and a composite dielectric layer. A functional layer 320 and a channel layer 330 can be formed on the inner wall of the channel hole 310 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Specifically, the functional layer 320 may include a barrier layer (not shown) formed on the inner wall of the channel hole 310 to prevent charge outflow, a charge trapping layer (not shown) on the surface of the barrier layer to store charge during operation of the three-dimensional memory, and a tunneling layer (not shown) on the surface of the charge trapping layer. The charge trapping layer may include one or more layers, which may include one or more materials. Materials used for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. In embodiments of this application, the functional layer 320 includes an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may have a structure different from the ONO configuration. For example, functional layer 320 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. Channel layer 330 may be formed on the surface of functional layer 320 by a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Channel layer 330 is capable of transporting desired charges (electrons or holes). According to an exemplary embodiment of this application, channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. Similar to channel via 310, functional layer 320 and channel layer 330 also extend through stack structure 120 and into substrate 110.

[0053] like Figure 4 As shown, gate line slots 410, spaced from the channel structure 300, can also be formed in the stacked structure 120. The gate line slots 410 penetrate the stacked structure 120 along its thickness direction and extend into the substrate 110. The gate line slots 410 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes. According to an exemplary embodiment, the gate line slots 410 can be formed using, for example, anisotropic etching (e.g., dry etching such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.), and the etching time can be controlled so that the etching stops in the substrate 110 after penetrating the stacked structure 120.

[0054] The gate gaps 410 can be used as pathways to provide etchant and chemical precursors. A process such as wet etching can be used to remove all of the gate sacrificial layer 122 in the stacked structure 120 to form a sacrificial gap. Specifically, isotropic etching can be used to remove the gate sacrificial layer 122 in the stacked structure 120, where isotropic etching can employ selective wet etching or vapor phase etching. When using wet etching, an etching solution is used as the etchant, and the memory structure is immersed in the etching solution. When using vapor phase etching, an etching gas is used as the etchant, and the memory structure is exposed to the etching gas. During etching, the etchant fills the gate gaps 410 and gradually etches the gate sacrificial layer 122 into the stacked structure 120. To ensure that the gate dielectric layer 121 is not removed while the gate sacrificial layer 122 is removed in this step, the materials used to fabricate the gate sacrificial layer 122 and the gate dielectric layer 121 should have a high etch selectivity. Due to the selectivity of the etchant, the etching removes the gate sacrificial layer 122 in the stacked structure 120 while retaining the gate dielectric layer 121. A dielectric layer 130 is formed on the inner wall of the gate line gap 410 and the inner wall of the sacrificial gap via the gate line gap 410. The dielectric layer 130 may include, but is not limited to, a high-dielectric-constant material, alumina (Al2O3). The aluminum source for forming the alumina (Al2O3) may be trimethylaluminum (TMA), aluminum chloride (AlCl3), etc., and the oxygen source may be water (H2O), ozone (O3), etc. A gate layer 140 is formed in the sacrificial gap where the dielectric layer 130 is deposited. Specifically, the gate layer 140 can be formed in the sacrificial gap using thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. The gate layer 140 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. The gate layer 140 can extend laterally (perpendicular to the thickness direction of the stacked structure 120) as a word line. To facilitate subsequent fabrication processes, after the gate layer 140 is formed, the portion of the dielectric layer 130 located at the bottom of the gate line gap 410 is etched to expose the substrate 110.

[0055] Step S130: A deposition layer is formed on the inner wall of the grid line slot and a conductive filler is placed in the grid line slot.

[0056] In step S130, a gate line slot structure 400 can be formed by filling the gate line slots 410. For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the gate line slots 410 with a deposited layer.

[0057] In this step, a first deposition layer 411 can be formed on the inner wall of the grid slot 410. The first deposition layer 411 includes a first sub-deposition layer 421 and a second sub-deposition layer 422 formed sequentially, such as... Figure 5As shown. The first sub-deposited layer 421 can be formed at a lower temperature (e.g., about 50°C) by a process such as atomic layer deposition (ALD) to prevent oxidation of the gate layer 140. A second sub-deposited layer 422 is formed on the first sub-deposited layer 421. The second sub-deposited layer 422 can be formed at a higher temperature (e.g., about 550°C). The first sub-deposited layer 421 and the second sub-deposited layer 422 may include, but are not limited to, silicon oxide (SiO2). Subsequently, the gate gap 410 can be sidewall etched to shape and planarize the portion of the second sub-deposited layer 422 located on the sidewall of the gate gap 410 and remove the portion of the first deposited layer 411 located at the bottom of the gate gap 410 to expose the substrate 110, as shown. Figure 6 As shown. A second deposition layer 412 continues to be formed on the inner wall of the grid slot 410, as... Figure 7 As shown. The second deposition layer 412 can be formed at a higher temperature (e.g., about 550°C), and the thickness of the second deposition layer 412 can be controlled by controlling the deposition time of the second deposition layer 412. The material of the second deposition layer 412 can be the same as the material of the first sub-deposition layer 421 and the second sub-deposition layer 422, and may include, but is not limited to, silicon oxide (SiO2). According to an embodiment of this application, when the material of the second deposition layer 412 is the same as that of the oxide layer in the oxide-nitride-oxide (ONO) structure of the functional layer 320, the thickness of the portion of the second deposition layer 412 located at the bottom of the gate gap 410 can be substantially equal to the sum of the thicknesses of the oxide layers in the oxide-nitride-oxide (ONO) structure of the functional layer 320. According to the embodiments of this application, when the materials of the oxide layer in the oxide-nitride-oxide (ONO) structure of the second deposition layer 412 and the functional layer 320 are different, the thickness of the second deposition layer 412 and the thickness of the oxide layer in the oxide-nitride-oxide (ONO) structure of the functional layer 320 can be set according to the different etching rates of the etchant to be used in the subsequent etching process for different materials.

[0058] After forming the second deposition layer 412, a conductive filler 430 can be selected to fill the gate line gaps 410. For example, polysilicon can be selected to fill the gate line gaps 410, but it is not limited to this. According to an exemplary embodiment of this application, the amount of conductive filler 430 can be adjusted according to the stress required by the wafer, while controlling the thickness of the deposition layer on the inner wall of the gate line gaps 410 to prevent excessive thinning, thereby preventing leakage current between the word line and gate line gaps, and thus ensuring the yield and reliability of the memory. After forming the conductive filler 430, an etch-back operation can be performed to planarize the filled conductive filler 430, such as... Figure 8 As shown. Other methods can also be used for planarization, such as chemical mechanical polishing (CMP).

[0059] Step S140: Remove a portion of the substrate, and remove a portion of the deposited layer and a portion of the functional layer, to remove the substrate. The side away from the stacked structure exposes the conductive filler and the channel layer.

[0060] In step S140, the substrate 111 of the substrate 110 can be removed using processes such as CMP or dry / wet etching. Further, the first oxide layer 112 can be removed using, for example, a wet etching process, and the first polysilicon layer 113 can serve as an etching stop layer for the wet etching process to remove the first oxide layer 112.

[0061] Furthermore, the first polysilicon layer 113 of the substrate 110 can be removed using, for example, a wet etching process, and the etching can be stopped at the second oxide layer 114, the second deposited layer 412, and the functional layer 320 of the channel structure 300 by selecting a predetermined etchant, such as... Figure 9 As shown. Further, for example, a wet etching process can be used to remove the second oxide layer 114 of the substrate 110, and by selecting a predetermined etchant, the etching can be stopped at the second polysilicon layer 115 and the conductive filler 430 exposed in the channel layer 330 and gate gap structure of the channel structure 300, thereby exposing a portion of the channel layer 330 of the channel structure 300 and a portion of the conductive filler 430 in the gate gap 410, such as... Figure 10 As shown. According to the embodiments of this application, when the materials of the oxide layers 321 and 323 in the ONO structure of the functional layer 320 of the second deposition layer 412 and the channel structure 300 are the same, since the thickness of the portion of the second deposition layer 412 located at the bottom of the gate line gap 410 can be substantially equal to the sum of the thicknesses of the oxide layers in the oxide-nitride-oxide (ONO) structure of the functional layer 320, the etching process of the portion of the second deposition layer 412 located at the bottom of the gate line gap 410 and the etching process of the oxide-nitride-oxide (ONO) structure of the functional layer 320 can be stopped simultaneously. According to the embodiments of this application, when the materials of the oxide layers 321 and 323 in the ONO structure of the second deposition layer 412 and the functional layer 320 of the channel structure 300 are different, since the thickness of the second deposition layer 412 and the thickness of the oxide layer in the oxide-nitride-oxide (ONO) structure of the functional layer 320 are set according to the different etching rates of the etchant used in this step for different materials, the etching process of the portion of the second deposition layer 412 located at the bottom of the gate line gap 410 and the etching process of the oxide-nitride-oxide (ONO) structure of the functional layer 320 can be stopped simultaneously.

[0062] The semiconductor structure processed in step S140 does not have the substrate 111, first oxide layer 112, first polysilicon layer 113, and second oxide layer 114 described above in the substrate 110, but still retains the second polysilicon layer 115. The second polysilicon layer 115 can also serve as a spacer layer between the stacked structure 120 and the conductive layer formed in subsequent processes. Furthermore, by controlling the thickness of the second polysilicon layer 115, the distance between the gate layer 140 (word line) and the conductive layer in the stacked structure 120 can be effectively controlled.

[0063] Step S150: Form the exposed conductive fill and trench on the side of the remaining substrate away from the stacked structure. The conductive layer that contacts the channel layer.

[0064] In step S150, a conductive layer 170 may be formed on the side of the second polysilicon layer 115 away from the stacked structure 120 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the conductive layer 170 may include, for example, P-type or N-type doped polysilicon, but is not limited thereto. The conductive layer 170 may cover the exposed channel layer 330 of the channel structure 300 after the process in step S140 and the exposed conductive filler 430 in the gate gap structure 400, such as... Figure 11 As shown, but not limited to.

[0065] Therefore, after this step, the conductive layer 170 can directly contact the exposed portion of the channel layer 330 and the conductive filler 430 after step S140, thereby achieving electrical connection between the channel structure 300, the conductive filler 430 and the conductive layer 170.

[0066] In the three-dimensional memory obtained by the method of preparing a three-dimensional memory according to the embodiments of this application, the first memory block 11 is selected as the memory block to be operated, and the second memory block 12 is selected as the memory block to be not operated. After the conductive filler 430 in the gate gap 410 is grounded through the conductive layer 170, the charge accumulated around the second memory block 12 due to the inductive coupling effect with the first memory block 11 will be conducted to the outside of the memory through the conductive layer 170 and the conductive filler 430 in the gate gap structure 400. This can effectively reduce the inductive coupling effect between the first memory block 11 and the second memory block 12, thereby reducing the influence of the inductive coupling effect on the state of the second memory block 12 and ensuring the electrical performance of the three-dimensional memory.

[0067] This application also provides a three-dimensional memory 100. The three-dimensional memory 100 can be obtained by any of the fabrication methods described in the above embodiments, but is not limited thereto. Figure 12 This is a schematic cross-sectional view of the structure of a three-dimensional memory 100 according to an embodiment of this application. Figure 12As shown, the three-dimensional memory 100 may include: a substrate 115, a stacked structure 120, a channel structure 300, a gate line gap structure 400, and a conductive layer 170.

[0068] The substrate 115 may be made of polycrystalline silicon, but is not limited to this. A stacked structure 120 is located on one side of the substrate 115 and includes multiple overlapping gate dielectric layers 121 and gate layers 140. According to an exemplary embodiment, the gate dielectric layer 121 may be made of silicon dioxide, which may also be doped with impurities such as phosphorus, boron, fluorine, and carbon, but is not limited to this. According to an exemplary embodiment, the gate layer 140 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides, but is not limited to this. In the stacked structure 120, the thicknesses of the multiple gate dielectric layers 121 may be the same or different, and the thicknesses of the multiple gate layers 140 may be the same or different, and can be set according to specific process requirements.

[0069] The conductive layer 170 is located on the side of the substrate 115 away from the stacked structure 120. According to an exemplary embodiment of this application, the conductive layer 170 covers at least a portion of the substrate 115, a portion of the channel layer 330 away from the stacked structure 120, and a portion of the conductive filler 430 in the gate gap 410 away from the stacked structure 120. The material of the conductive layer 170 may include, for example, P-type or N-type doped polysilicon, but is not limited thereto. The conductive layer 170 serves to provide support for device structures, such as the stacked structure 120, located above it, and also enables electrical connections between the device structures in contact with it, such as the channel layer 330 and the conductive filler 430.

[0070] The channel structure 300 extends through the stacked structure 120 and into the conductive layer 170. The channel structure 300 includes a channel layer 330 and a functional layer 320 surrounding the channel layer 330. The diameter of the channel structure 300 gradually increases along the stacking direction of the stacked structure 120, and this diameter is the maximum distance of the channel structure 300 in the extension direction of the substrate 115 (polycrystalline silicon layer). The channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon, but is not limited thereto. The functional layer 320 may have an oxide-nitride-oxide (ONO) structure surrounding the channel layer 330, but is not limited thereto.

[0071] The gate line slot structure 400 penetrates the stacked structure 120 and extends to the conductive layer 170. The gate line slot structure 400 includes a conductive filler 430 and a deposited layer surrounding the conductive filler 430. The conductive filler 430 may be made of polysilicon, but is not limited thereto. The deposited layer may include a first deposited layer 411 and a second deposited layer 412, wherein the first deposited layer 411 may include a first sub-deposited layer 421 and a second sub-deposited layer 422. The first sub-deposited layer 421 may be formed at a lower temperature (e.g., about 50°C) by a process such as atomic layer deposition (ALD) to prevent oxidation of the gate layer 140. The second sub-deposited layer 422 may be formed on the first sub-deposited layer 421 at a higher temperature (e.g., about 550°C). The second deposited layer 412 may be formed on the first sub-deposited layer 412 at a higher temperature (e.g., about 550°C). The first sub-deposited layer 421, the second sub-deposited layer 422, and the second deposited layer 412 may be made of the same oxide, and their thicknesses may be set to different values ​​according to different practical needs.

[0072] In the three-dimensional memory 100 provided according to the embodiments of this application, the first memory block 11 is selected as the memory block to be operated, and the second memory block 12 is selected as the memory block to be not operated. After the conductive filler 430 in the gate gap 410 is grounded through the conductive layer 170, the charge accumulated around the second memory block 12 due to the inductive coupling effect with the first memory block 11 will be conducted to the outside of the memory through the conductive layer 170 and the conductive filler 430 in the gate gap structure 400. This can effectively reduce the inductive coupling effect between the first memory block 11 and the second memory block 12, thereby reducing the impact of the inductive coupling effect on the state of the second memory block 12 and ensuring the electrical performance of the three-dimensional memory.

[0073] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0074] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A multilayer structure is formed on the substrate; A channel structure and gate line slot are formed through the stacked structure and extend into the substrate, and a gate layer is formed within the stacked structure via the gate line slot. The channel structure includes a functional layer and a channel layer, and the dimensions of the channel structure in the extension direction of the substrate gradually increase along the stacking direction of the stacked structure. A deposition layer is formed on the inner wall of the grid line slot, and a conductive filler is disposed in the grid line slot; A portion of the substrate is removed, along with a portion of the deposited layer and a portion of the functional layer, to expose the conductive filler and the channel layer on the side of the substrate away from the stacked structure. as well as A conductive layer is formed on the side of the remaining substrate away from the stacked structure, which is in direct contact with the exposed conductive filler and channel layer.

2. The method according to claim 1, characterized in that, The conductive layer is in direct contact with the remaining portion of the functional layer, the bottom wall of the channel layer, and part of the sidewall.

3. The method according to claim 1, characterized in that, The conductive layer surrounds the bottom wall and part of the sidewall of the channel layer.

4. The method according to claim 1, characterized in that, The method further includes: Before forming the gate layer, a dielectric layer is formed on the inner wall of the gate line slot; and Before the deposition layer is formed, the portion of the dielectric layer located at the bottom of the grid line slot is removed.

5. The method according to claim 1, characterized in that, Forming the deposition layer on the inner wall of the grid slot includes: A first deposition layer is formed on the inner wall of the grid line slot; Remove the portion of the first deposited layer located at the bottom of the gate wire gap to expose the substrate; and A second deposition layer is formed on the inner wall of the grid line slot.

6. The method according to claim 5, characterized in that, Removing a portion of the substrate includes: A portion of the substrate is removed to expose the bottom end of the second deposited layer and the portion of the functional layer.

7. The method according to claim 6, characterized in that, Removing a portion of the deposited layer further includes removing the portion of the second deposited layer located at the bottom of the gate wire gap to expose the conductive filler in the gate wire gap.

8. The method according to claim 7, characterized in that, Removing part of the functional layer includes removing the exposed functional layer while removing the second deposited layer to expose the channel layer.

9. The method according to claim 5, characterized in that, Forming the first deposition layer on the inner wall of the grid wire slot includes: A first sub-deposition layer and a second sub-deposition layer are sequentially formed on the inner wall of the grid line slot, wherein the temperature at which the first sub-deposition layer is formed is lower than the temperature used to form the second sub-deposition layer.

10. The method according to claim 1, characterized in that, The conductive filler includes polycrystalline silicon.

11. The method according to claim 1, characterized in that, The conductive layer is a polycrystalline silicon layer.

12. A three-dimensional memory, characterized in that, include: Polycrystalline silicon layer; A stacked structure is disposed on one side of the polycrystalline silicon layer; A conductive layer is disposed on the side of the polysilicon layer away from the stacked structure; A channel structure extends through the stacked structure, the channel structure comprising a channel layer and a functional layer surrounding the channel layer, the diameter of the channel structure gradually increasing along the stacking direction of the stacked structure; A gate line slot structure extends through the stacked structure, the gate line slot structure comprising a conductive filler, a deposited layer surrounding the sidewalls of the conductive filler, and a dielectric layer located between the deposited layer and the stacked structure; as well as The conductive layer is in direct contact with the conductive filler and the channel layer, and the conductive layer is in direct contact with a portion of the sidewall of the dielectric layer.

13. The three-dimensional memory according to claim 12, characterized in that, The conductive layer is in direct contact with a portion of the functional layer, the bottom wall of the channel layer, and a portion of the sidewall.

14. The three-dimensional memory according to claim 12, characterized in that, The conductive layer surrounds the bottom wall and part of the sidewall of the channel layer.

15. The three-dimensional memory according to claim 12, characterized in that, The conductive filler includes polycrystalline silicon.

16. The three-dimensional memory according to claim 12, characterized in that, The deposition layer includes a first deposition layer and a second deposition layer.

17. The three-dimensional memory according to claim 16, characterized in that, The first deposition layer includes a first sub-deposition layer and a second sub-deposition layer.

18. The three-dimensional memory according to claim 16, characterized in that, The first and second deposition layers comprise oxide layers.

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