Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof, the semiconductor device comprising a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source and a drain. The semiconductor structure comprises a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers the top surface and the side wall of the first metal oxide layer. The second metal oxide layer has a step structure at the side wall of the first metal oxide layer. The carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer. The thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer. The difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 micrometers.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device including a metal oxide layer and a manufacturing method thereof. Background Art

[0002] At present, common thin film transistors usually use amorphous silicon semiconductors as channels, wherein amorphous silicon semiconductors are widely used in various thin film transistors due to their simple process and low cost.

[0003] With the advancement of display technology, the resolution of display panels has been increasing year by year. In order to shrink the thin film transistors in the pixel circuit, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material. Summary of the invention

[0004] The invention provides a semiconductor device, the semiconductor structure of which has the advantage of high carrier mobility and can reduce the hot carrier effect caused by the electric field on the gate.

[0005] The invention provides a method for manufacturing a semiconductor device, which has the advantages of high process yield and low cost.

[0006] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source and a drain. The semiconductor structure is located on the substrate and includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer. The second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer. The carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer. The thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer. The first gate dielectric layer is located on the semiconductor structure. The first gate is located on the first gate dielectric layer and overlaps the first metal oxide layer. The difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 microns. The source and the drain are electrically connected to the second metal oxide layer.

[0007] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first metal oxide layer on a substrate; forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, wherein the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; forming a first gate dielectric layer on the second metal oxide layer; forming a first gate on the first gate dielectric layer, and the first gate overlaps the first metal oxide layer, wherein the difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 micrometers; forming a source region, a drain region, and a channel region located between the source region and the drain region in the second metal oxide layer, wherein the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer; forming a source and a drain electrically connected to the second metal oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a top view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 1B yes Figure 1A A schematic cross-sectional view of line AA'.

[0010] Figures 2A to 2G yes Figure 1A and Figure 1B A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0011] Figure 3A is a top view of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 3B yes Figure 3A A schematic cross-sectional view of line AA'.

[0013] FIG. 4A to FIG. 4G yes Figure 3A and Figure 3B A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0014] Figure 5A is a top view of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 5B yes Figure 5A A schematic cross-sectional view of line AA' and line BB'.

[0016] 6A to 6H yes Figure 5A and Figure 5B A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0017] Description of reference numerals:

[0018] 10A, 10B, 10C: Semiconductor devices

[0019] 100: Substrate

[0020] 102: Buffer layer

[0021] 110: Second gate dielectric layer

[0022] 120: First gate dielectric layer

[0023] 130: Interlayer dielectric layer

[0024] 210: Second gate

[0025] 220: Semiconductor Structure

[0026] 220A: First metal oxide layer

[0027] 220A': first metal oxide material layer

[0028] 220B: Second metal oxide layer

[0029] 220B': second metal oxide material layer

[0030] 222: Source region

[0031] 224: Channel Area

[0032] 226: Drain region

[0033] 232: Source

[0034] 234: Drain

[0035] 240: First gate

[0036] 240s: Edge

[0037] 310: Signal line

[0038] 320: Transfer electrode

[0039] A-A',B-B': line

[0040] d: horizontal distance

[0041] ND: Normal Direction

[0042] P: Doping process

[0043] s: side wall

[0044] t: top surface

[0045] st: ladder structure

[0046] T1, T2: thickness

[0047] TH1: First contact hole

[0048] TH2: Second contact hole

[0049] TH3: The third contact hole

[0050] TH4: fourth contact hole

[0051] TH5: fifth contact hole

[0052] TH6: Sixth contact hole

[0053] W1, W2, W3: Width DETAILED DESCRIPTION

[0054] Figure 1A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 1B yes Figure 1A A schematic cross-sectional view of line AA'.

[0055] Please refer to Figure 1A and Figure 1B The semiconductor device 10A includes a substrate 100 , a semiconductor structure 220 , a first gate dielectric layer 120 , a first gate 240 , a source 232 , and a drain 234 . In some embodiments, the semiconductor device 10A further includes a buffer layer 102 and an interlayer dielectric layer 130 .

[0056] The material of the substrate 100 can be glass, quartz, organic polymer or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems.

[0057] The buffer layer 102 is formed on the surface of the substrate 100. The material of the buffer layer 102 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or other insulating materials. In some embodiments, the buffer layer 102 is a single-layer structure or a multi-layer structure.

[0058] The semiconductor structure 220 is located on the substrate 100. In the present embodiment, the semiconductor structure 220 is formed on the buffer layer 102. The semiconductor structure 220 includes a first metal oxide layer 220A and a second metal oxide layer 220B.

[0059] The first metal oxide layer 220A is formed on the buffer layer 102. In some embodiments, the first metal oxide layer 220A includes at least one of indium, tungsten, gallium, zinc, and tin. For example, the first metal oxide layer 220A is indium tungsten zinc oxide (InWZnO, IWZO) or indium gallium zinc oxide (InGaZnO, IGZO).

[0060] The second metal oxide layer 220B covers the top surface t and the sidewall s of the first metal oxide layer 220A. The second metal oxide layer 220B is conformally formed on the first metal oxide layer 220A, and the second metal oxide layer 220B has a step structure st at the sidewall s of the first metal oxide layer 220A. In some embodiments, the second metal oxide layer 220B includes at least one of indium, gallium, and zinc. For example, the second metal oxide layer 220B is indium gallium zinc oxide (InGaZnO, IGZO).

[0061] In the present embodiment, the second metal oxide layer 220B includes a source region 222, a drain region 226, and a channel region 224 located between the source region 222 and the drain region 226. The channel region 224 overlaps the first metal oxide layer 220A in the normal direction ND of the top surface of the substrate 100, and the channel region 224 covers the top surface t of the first metal oxide layer 220A. The source region 222 and the drain region 226 cover the sidewall s of the first metal oxide layer 220A. In some embodiments, the step structure st is located in the source region 222 and / or the drain region 226.

[0062] The source region 222 and the drain region 226 are, for example, hydrogen-doped regions. The resistivity of the source region 222 and the drain region 226 is less than the resistivity of the channel region 224. In some embodiments, the oxygen concentration of the source region 222 and the drain region 226 is less than the oxygen concentration of the channel region 224, and the hydrogen concentration of the source region 222 and the drain region 226 is greater than the hydrogen concentration of the channel region 224.

[0063] The carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. For example, the carrier mobility of the first metal oxide layer 220A is 25 cm 2 / Vs to 35cm 2 / Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 8cm 2 / Vs to 10cm 2 / Vs. In some embodiments, by adjusting the oxygen concentration and / or indium concentration in the first metal oxide layer 220A and the second metal oxide layer 220B, the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. In some embodiments, the oxygen concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is greater than the oxygen concentration of the first metal oxide layer 220A, and the oxygen vacancy concentration of the channel region 224 of the second metal oxide layer 220B is less than the oxygen vacancy concentration of the first metal oxide layer 220A. In some embodiments, the indium concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is less than the indium concentration of the first metal oxide layer 220A.

[0064] The thickness T2 of the second metal oxide layer 220B is greater than or equal to the thickness T1 of the first metal oxide layer 220A. In some embodiments, the thickness T2 of the second metal oxide layer 220B is 15 nm to 25 nm, and the thickness T1 of the first metal oxide layer 220A is 5 nm to 15 nm.

[0065] The first gate dielectric layer 120 is located on the semiconductor structure 220. The first gate dielectric layer 120 includes an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stack of at least two of the above materials), an organic material, other suitable materials, or a combination thereof.

[0066] The first gate 240 is located on the first gate dielectric layer 120 and overlaps the channel region 224 of the first metal oxide layer 220A and the second metal oxide layer 220B in the normal direction ND of the top surface of the substrate 100. The material of the first gate 240 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides, or a combination of the above or other conductive materials. In the present embodiment, the first gate 240 is a stacked layer of titanium, aluminum and titanium. When the first gate 240 contains aluminum, the first gate 240 can act as a hydrogen barrier layer, thereby reducing the probability of hydrogen atoms diffusing into the channel region 224.

[0067] The difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers. In a preferred embodiment, the edge 240s of the first gate 240 overlaps with the sidewall s of the first metal oxide layer 220A in the normal direction ND of the top surface of the substrate 100. Based on the foregoing, the probability of the first metal oxide layer 220A being damaged by etching solution or ultraviolet light in subsequent processes can be reduced.

[0068] The horizontal distance d between the edge 240s of the first gate 240 and the step structure st of the second metal oxide layer 220B is less than 0.5 micrometers, and the step structure st of the semiconductor structure 220 is substantially adjacent to the edge of the first gate 240. When the semiconductor device 10A is operated, a strong electric field is likely to appear at the edge 240s of the first gate 240. By disposing the step structure st with a variable thickness of the semiconductor structure 220 at a position adjacent to the edge 240s of the first gate 240, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10A.

[0069] The interlayer dielectric layer 130 is located on the first gate dielectric layer 120 and the first gate electrode 240. Two contact holes penetrate the interlayer dielectric layer 130 and the first gate dielectric layer 120 and extend to the source region 222 and the drain region 226 of the second metal oxide layer 220B.

[0070] The interlayer dielectric layer 130 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or a stacked layer of at least two of the above materials), an organic material or other suitable materials, or a combination thereof. In some embodiments, the interlayer dielectric layer 130 includes hydrogen elements. In some embodiments, during the manufacturing process of the semiconductor device 10A, the hydrogen elements in the interlayer dielectric layer 130 are diffused into the source region 222 and the drain region 226 of the second metal oxide layer 220B by a heat treatment process, but the present invention is not limited thereto. In other embodiments, the hydrogen elements are diffused into the source region 222 and the drain region 226 by a hydrogen plasma process or other doping processes.

[0071] The source 232 and the drain 234 are located on the interlayer dielectric layer 130 and filled into the first contact hole TH1 and the second contact hole TH2 penetrating the interlayer dielectric layer 130 and the first gate dielectric layer 120 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B, respectively.

[0072] The signal line 310 is located on the interlayer dielectric layer 130 and is filled into the third contact hole TH3 penetrating the interlayer dielectric layer 130 to be electrically connected to the first gate 240 .

[0073] In some embodiments, the signal line 310, the source 232 and the drain 234 are made of, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials. In this embodiment, the signal line 310, the source 232 and the drain 234 are stacked layers of titanium, aluminum and titanium.

[0074] In the present embodiment, the semiconductor device 10A is a top-gate thin film transistor, which has the advantage of fast response and is suitable for use as a switching element.

[0075] Figures 2A to 2G yes Figure 1A and Figure 1B A schematic cross-sectional view of a method for manufacturing a semiconductor device 10A.

[0076] Please refer to FIG. 2A to FIG. 2B , forming a first metal oxide layer 220A on the substrate 100. First, a blanket first metal oxide material layer 220A' is formed on the substrate 100 and the buffer layer 102, and then, a patterned photoresist (not shown) is formed on the first metal oxide material layer 220A' by a photolithography process; then, a wet or dry etching process is performed on the first metal oxide material layer 220A' using the patterned photoresist as a mask to form the first metal oxide layer 220A; finally, the patterned photoresist is removed.

[0077] Please refer to Figure 2C to Figure 2D , forming the second metal oxide layer 220B on the first metal oxide layer 220A. First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the buffer layer 102 and the first metal oxide layer 220A, then, a patterned photoresist (not shown) is formed on the second metal oxide material layer 220B' by a photolithography process; then, a wet or dry etching process is performed on the second metal oxide material layer 220B' using the patterned photoresist as a mask to form the second metal oxide layer 220B; finally, the patterned photoresist is removed.

[0078] The second metal oxide layer 220B covers the top surface t and the sidewall s of the first metal oxide layer 220A, and the second metal oxide layer 220B has a step structure st at the sidewall s of the first metal oxide layer 220A.

[0079] Please refer to Figure 2E , forming a first gate dielectric layer 120 on the second metal oxide layer 220B. Forming a first gate electrode 240 on the first gate dielectric layer 120. The first gate electrode 240 overlaps the first metal oxide layer 220A.

[0080] Using the first gate 240 as a mask, a doping process P is performed on the second metal oxide layer 220B to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

[0081] Please refer to Figure 2F, an interlayer dielectric layer 130 is formed on the first gate electrode 240 and the first gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate electrode 240 .

[0082] Please refer to Figure 2G , forming a first contact hole TH1 and a second contact hole TH2 penetrating the interlayer dielectric layer 130 and the first gate dielectric layer 120. In some embodiments, a third contact hole ( Figure 2G Omitted for illustration).

[0083] Finally, please return Figure 1A and Figure 1B , forming a source 232, a drain 234, and a signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The signal line 310 is filled into the third contact hole TH3 to electrically connect the first gate 240.

[0084] Based on the above, the semiconductor structure 220 of the semiconductor device 10A includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10A. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10A.

[0085] Figure 3A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 3B yes Figure 3A It must be noted that, Figure 3A and Figure 3B The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0086] Figure 3A and Figure 3B The semiconductor device 10B and Figure 1A The main difference between the semiconductor device 10A and the semiconductor device 10B is that the semiconductor device 10B further includes a second gate dielectric layer 110 and a second gate 210 .

[0087] The second gate 210 is located on the substrate 100. In some embodiments, a buffer layer ( Figure 3A The second gate 210 may be made of, for example, metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or combinations thereof or other conductive materials.

[0088] The second gate dielectric layer 110 is located on the second gate electrode 210. The second gate dielectric layer 110 is located between the semiconductor structure 220 and the substrate 100. The second gate electrode 210 is located between the second gate dielectric layer 110 and the substrate 100. The second gate electrode 210 overlaps the semiconductor structure 220, and the width W3 of the second gate electrode 210 is greater than the width W2 of the first metal oxide layer 210. In some embodiments, the first gate electrode 240 fills the fourth contact hole TH4 penetrating the first gate dielectric layer 120 and the second gate dielectric layer 110, and is electrically connected to the second gate electrode 210.

[0089] In the present embodiment, the semiconductor structure 220 is formed on the second gate dielectric layer 110. The semiconductor structure 220 includes a first metal oxide layer 220A and a second metal oxide layer 220B.

[0090] The carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. For example, the carrier mobility of the first metal oxide layer 220A is 65 cm 2 / Vs to 75cm 2 / Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 16cm 2 / Vs to 23cm 2 / Vs. In some embodiments, by adjusting the oxygen concentration and / or indium concentration in the first metal oxide layer 220A and the second metal oxide layer 220B, the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. In some embodiments, the oxygen concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is greater than the oxygen concentration of the first metal oxide layer 220A, and the oxygen vacancy concentration of the channel region 224 of the second metal oxide layer 220B is less than the oxygen vacancy concentration of the first metal oxide layer 220A. In some embodiments, the indium concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is less than the indium concentration of the first metal oxide layer 220A.

[0091] The thickness T2 of the second metal oxide layer 220B is greater than or equal to the thickness T1 of the first metal oxide layer 220A. In some embodiments, the thickness T2 of the second metal oxide layer 220B is 15 nm to 25 nm, and the thickness T1 of the first metal oxide layer 220A is 5 nm to 15 nm.

[0092] The first gate 240 is located on the first gate dielectric layer 120 and overlaps the first metal oxide layer 220A, the channel region 224 of the second metal oxide layer 220B and the second gate 210 in the normal direction ND of the top surface of the substrate 100. The semiconductor structure 220 is located between the first gate 240 and the second gate 210.

[0093] The difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers. In a preferred embodiment, the edge 240s of the first gate 240 overlaps with the sidewall s of the first metal oxide layer 220A in the normal direction ND of the top surface of the substrate 100. Based on the foregoing, the probability of the first metal oxide layer 220A being damaged by etching solution or ultraviolet light in subsequent processes can be reduced.

[0094] The horizontal distance d between the edge 240s of the first gate 240 and the step structure st of the second metal oxide layer 220B is less than 0.5 micrometers, and the step structure st of the semiconductor structure 220 is substantially adjacent to the edge 240s of the first gate 240. When the semiconductor device 10B is operated, a strong electric field is likely to appear at the edge 240s of the first gate 240. By disposing the step structure st with a variable thickness of the semiconductor structure 220 at a position adjacent to the edge of the first gate 240, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

[0095] In the present embodiment, the semiconductor device 10B includes a dual-gate thin film transistor, which has an advantage of a large drain current and is suitable as a driving element.

[0096] FIG. 4A to FIG. 4G yes Figure 3A and Figure 3B A schematic cross-sectional view of a method for manufacturing a semiconductor device 10B.

[0097] Please refer to Figure 4A , forming a second gate electrode 210 on the substrate 100 , forming a second gate dielectric layer 110 on the second gate electrode 210 , and forming a blanket first metal oxide material layer 220A′ on the substrate 100 and the second gate dielectric layer 110 .

[0098] Please refer to Figure 4B, patterning the first metal oxide material layer 220A′ to form a first metal oxide layer 220A on the second gate dielectric layer 110 .

[0099] Please refer to FIG. 4C to FIG. 4D First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the second gate dielectric layer 110 and the first metal oxide layer 220A, and then the second metal oxide material layer 220B' is patterned to form the second metal oxide layer 220B.

[0100] refer to Figure 4E , forming the first gate dielectric layer 120 on the second metal oxide layer 220B. Forming the first gate 240 on the first gate dielectric layer 120. The first gate 240 overlaps the first metal oxide layer 220A. In some embodiments, before forming the first gate 240, a fourth contact hole ( Figure 4E (Not shown) The first gate 240 is electrically connected to the second gate 210 through a fourth contact hole.

[0101] Using the first gate 240 as a mask, a doping process P is performed on the second metal oxide layer 220B to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

[0102] Please refer to Figure 4F , an interlayer dielectric layer 130 is formed on the first gate electrode 240 and the first gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate electrode 240 .

[0103] Please refer to Figure 4G , forming a first contact hole TH1 and a second contact hole TH2 penetrating the interlayer dielectric layer 130 and the first gate dielectric layer 120. In some embodiments, a third contact hole ( Figure 4G Omitted for illustration).

[0104] Finally, please return Figure 3A and Figure 3B , forming a source 232, a drain 234, and a signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The signal line 310 is filled into the third contact hole TH3 to electrically connect the first gate 240.

[0105] Based on the above, the semiconductor structure 220 of the semiconductor device 10B includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10B. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

[0106] Figure 5A is a top view of a semiconductor device according to an embodiment of the present invention. Figure 5B yes Figure 5A It should be noted that: Figure 3A and Figure 3B The implementation examples are used Figure 1A and Figure 1B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0107] Figure 5A and Figure 5B The semiconductor device 10C and Figure 3A The main difference between the semiconductor device 10B and the semiconductor device 10C is that the source 232 of the semiconductor device 10C is electrically connected to the second gate 210 .

[0108] Please refer to Figure 5A and Figure 5B , the semiconductor device 10C further includes a transfer electrode 320. The transfer electrode 320 is filled into the fifth contact hole TH5 penetrating the second gate dielectric layer 110 and the first gate dielectric layer 120 and electrically connected to the second gate 210, and the source 232 is filled into the sixth contact hole TH6 penetrating the interlayer gate dielectric layer 130 and electrically connected to the transfer electrode 320. In this embodiment, the first gate 240 and the second gate 210 are not directly connected.

[0109] In this embodiment, the source 232 of the semiconductor device 10C is electrically connected to the second gate 210 , so that it has the advantage of small parasitic capacitance and is suitable for being used as a driving element.

[0110] In some embodiments, the carrier mobility of the first metal oxide layer 220A is 30 cm 2 / Vs to 40cm 2 / Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 3cm 2 / Vs to 6cm 2 / Vs.

[0111] 6A to 6H yes Figure 5A and Figure 5B A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0112] Please refer to Fig. 6A , forming a second gate electrode 210 on the substrate 100 , forming a second gate dielectric layer 110 on the second gate electrode 210 , and forming a blanket first metal oxide material layer 220A′ on the substrate 100 and the second gate dielectric layer 110 .

[0113] Please refer to Figure 6B , patterning the first metal oxide material layer 220A′ to form a first metal oxide layer 220A on the second gate dielectric layer 110 .

[0114] Please refer to FIG. 6C to FIG. 6D First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the second gate dielectric layer 110 and the first metal oxide layer 220A, and then the second metal oxide material layer 220B' is patterned to form the second metal oxide layer 220B.

[0115] Please refer to Fig. 6E , forming a first gate dielectric layer 120 on the second metal oxide layer 220B. Forming a fifth contact hole TH5 penetrating the second gate dielectric layer 110 and the first gate dielectric layer 120. The fifth contact hole TH5 exposes the second gate 210.

[0116] Please refer to Fig. 6F , forming a first gate 240 and a transfer electrode 320 on the first gate dielectric layer 120. The first gate 240 and the transfer electrode 320 belong to the same patterned conductive layer. The first gate 240 overlaps the first metal oxide layer 220A. The transfer electrode 320 is filled in the fifth contact hole TH5 to be electrically connected to the second gate 210. The transfer electrode 320 is formed on the second gate 210.

[0117] Using the first gate 240 as a mask, a doping process P is performed on the second metal oxide layer 220B to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

[0118] Please refer to Figure 6G, an interlayer dielectric layer 130 is formed on the first gate electrode 240 , the first gate dielectric layer 120 and the transfer electrode 320 . The interlayer dielectric layer 130 covers the first gate electrode 240 and the transfer electrode 320 .

[0119] Please refer to Figure 6H , forming a first contact hole TH1 and a second contact hole TH2 penetrating the interlayer dielectric layer 130 and the first gate dielectric layer 120. In some embodiments, a sixth contact hole TH6 of the interlayer gate dielectric layer 130 is also formed simultaneously. In some embodiments, a third contact hole ( Figure 6H Omitted for illustration).

[0120] Finally, please return Figure 5A and Figure 5B , forming a source 232, a drain 234, and a signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The source 232 is filled into the sixth contact hole TH6 to electrically connect the transfer electrode 320, and the source 232 is electrically connected to the second gate 210 through the transfer electrode 320. The signal line 310 is filled into the third contact hole TH3 to electrically connect the first gate 240.

[0121] Based on the above, the semiconductor structure 220 of the semiconductor device 10C includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10C. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

Claims

1. A semiconductor device comprising: a substrate; A semiconductor structure is located on the substrate and includes: a first metal oxide layer; as well as a second metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, the carrier mobility of the first metal oxide layer is greater than the carrier mobility of a channel region of the second metal oxide layer, and the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; a first gate dielectric layer located on the semiconductor structure; a first gate electrode, located on the first gate dielectric layer and overlapping the first metal oxide layer, wherein the difference between the width of the first gate electrode and the width of the first metal oxide layer is less than 0.5 micrometers; and a source electrode and a drain electrode, electrically connected to the second metal oxide layer, The horizontal distance between the side wall of the first gate and the step difference of the step structure of the second metal oxide layer is less than 0.5 micrometer. 2 . The semiconductor device as claimed in claim 1 , wherein an oxygen concentration of the channel region of the second metal oxide layer is greater than an oxygen concentration of the first metal oxide layer. 3 . The semiconductor device as claimed in claim 1 , wherein an indium concentration in the channel region of the second metal oxide layer is less than an indium concentration in the first metal oxide layer. 4 . The semiconductor device as claimed in claim 1 , wherein the second metal oxide layer has a thickness of 15 nm to 25 nm, and the first metal oxide layer has a thickness of 5 nm to 15 nm.

5. The semiconductor device according to claim 1, further comprising: a second gate dielectric layer located between the semiconductor structure and the substrate; as well as A second gate is located between the second gate dielectric layer and the substrate and overlaps the semiconductor structure, wherein the width of the second gate is greater than the width of the first metal oxide layer. The semiconductor device as claimed in claim 5 , wherein the source is electrically connected to the second gate. 7 . The semiconductor device as claimed in claim 1 , wherein a sidewall of the first gate overlaps a sidewall of the first metal oxide layer in a normal direction to a top surface of the substrate.

8. The semiconductor device of claim 1 , wherein the second metal oxide layer comprises a source region, a drain region, and the channel region between the source region and the drain region, wherein the resistivity of the source region and the drain region is less than the resistivity of the channel region, and the channel region overlaps the first metal oxide layer. 9 . The semiconductor device as claimed in claim 8 , wherein the stepped structure is located in the source region and / or the drain region. 10 . The semiconductor device as claimed in claim 1 , wherein a material of the second metal oxide layer is indium gallium zinc oxide, and a material of the first metal oxide layer is indium gallium zinc oxide or indium tungsten zinc oxide.

11. A method for manufacturing a semiconductor device, comprising: forming a first metal oxide layer on a substrate; forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, wherein the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; forming a first gate dielectric layer on the second metal oxide layer; Forming a first gate on the first gate dielectric layer, wherein the first gate overlaps the first metal oxide layer, wherein the difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 micrometers; forming a source region, a drain region, and a channel region between the source region and the drain region in the second metal oxide layer, wherein the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer; as well as forming a source and a drain, wherein the source and the drain are electrically connected to the second metal oxide layer, The horizontal distance between the side wall of the first gate and the step difference of the step structure of the second metal oxide layer is less than 0.5 micrometer.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a second gate on the substrate; forming a second gate dielectric layer on the second gate; as well as The first metal oxide layer is formed on the second gate dielectric layer.

13. The method for manufacturing a semiconductor device according to claim 12, further comprising: forming a transfer electrode on the second gate; forming an interlayer dielectric layer on the transfer electrode and the first gate; as well as The source and the drain are formed on the interlayer dielectric layer, wherein the source is electrically connected to the second gate through the transfer electrode. 14 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein a width of the second gate is greater than a width of the first metal oxide layer. 15 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein a doping process is performed on the second metal oxide layer using the first gate as a mask to form the source region, the drain region and the channel region in the second metal oxide layer. 16 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein a material of the second metal oxide layer comprises indium gallium zinc oxide, and a material of the first metal oxide layer comprises indium gallium zinc oxide or indium tungsten zinc oxide. 17 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein a thickness of the second metal oxide layer is 15 nm to 25 nm, and a thickness of the first metal oxide layer is 5 nm to 15 nm. 18 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein a sidewall of the first gate is aligned with a sidewall of the first metal oxide layer.

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