A zero-current detection circuit and a buck-type DC-DC converter

Abstract

The application provides a zero-current detection circuit and a Buck type DC-DC converter. The zero-current detection circuit comprises a bias current source, a plurality of PMOS tubes, a plurality of inverters and resistors. The zero-current detection circuit is applied to the Buck type DC-DC converter. The Buck type DC-DC converter is connected through the cooperation between components, dynamically adjusts the working state of the zero-current detection circuit, solves the power consumption problem in the prior art, and makes the zero-current detection circuit detect the inductor current in advance, turns off the freewheeling tube in advance, and solves the existing current backflow problem.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a zero current detection circuit and a Buck-type DC-DC converter. Background Technology

[0002] With the rapid development of technologies such as the Internet of Things (IoT) and 5G, the requirements for low-power systems are constantly increasing. Consequently, low-power power management chips have received widespread attention, especially regarding power consumption under light load, ultra-light load, and no-load conditions. Buck-type DC-DC converters, commonly used in power management chips, generally employ synchronous rectification technology. However, this technology also has some problems. The most significant is that if the system load is light, the inductor current in the freewheeling stage is prone to reverse current flow, causing power loss under light load and affecting the overall conversion efficiency of the system under light load. Excessive reverse current can also damage the chip. Therefore, to avoid these negative effects, when applying synchronous rectification technology, a zero-current detection module is often added inside the system to sample whether the inductor current is reversed in real time. By taking timely measures to turn off the freewheeling diode, the problem of reverse current flow can be solved.

[0003] Existing zero-current detection circuits typically employ multi-stage operational amplifier structures. Furthermore, during normal operation of the DC-DC converter, the circuit's operating state is not dynamically adjusted according to the system's operating phase. The zero-current detection circuit remains operational throughout the entire system cycle, consuming a significant amount of quiescent current and greatly increasing the DC-DC converter's static power consumption. Additionally, existing zero-current detection circuits often compare the sampled signal to zero potential. However, due to line delays and logic delays within the Buck-type DC-DC converter, the freewheeling diode may not be turned off in time, resulting in some reverse current flowing into the system. Therefore, this application addresses these issues by implementing improvements that dynamically adjust the operating state of the zero-current detection circuit during normal operation, resolving the power consumption problem in existing technologies. Simultaneously, the zero-current detection circuit detects the inductor current in advance and turns off the freewheeling diode earlier, thus resolving the current reverse current problem. Summary of the Invention

[0004] This application provides a zero-current sensing circuit and a Buck-type DC-DC converter, which can be used to solve the technical problems of low static power consumption of zero-current sensing circuit and reduced power consumption of DC-DC converter under light load or no-load conditions.

[0005] In a first aspect, this application provides a zero-current detection circuit, the circuit comprising: a bias current source I BIASThe first NMOS transistor M n1 The first PMOS transistor M p1 First inverter INV1, second NMOS transistor M n2 The third NMOS transistor M n3 The fourth NMOS transistor M n4 The fifth NMOS transistor M n5 The sixth NMOS transistor M n6 The second PMOS transistor M p2 The third PMOS transistor M p3 The fourth PMOS transistor M p4 The fifth PMOS transistor M p5 Second inverter INV2, seventh NMOS transistor M n7 First resistor R1, second resistor R2, eighth NMOS transistor M n8 The sixth PMOS transistor M p6 The seventh PMOS transistor M p7 The eighth PMOS transistor M p8 Ninth PMOS transistor M p9 The tenth NMOS transistor M n10 11th NMOS transistor M n11 The tenth PMOS transistor M p10 11th PMOS transistor M p11 The twelfth NMOS transistor M n12 1. NAND gate NAND1; 2. Inverter INV3;

[0006] Bias current source I BIAS One end is connected to the input power signal V IN The other end is connected to the first NMOS transistor M. n1 Drain terminal and first PMOS transistor M p1 Source end, first NMOS transistor M n1 The gate terminal is connected to the input terminal of the first inverter INV1 and the input signal LS, and the first PMOS transistor M p1 The gate terminal is connected to the output terminal of the first inverter INV1, and the first NMOS transistor M n1 Source terminal and first PMOS transistor M p1 The drain terminal is connected to the second NMOS transistor M. n2 Drain and gate terminals, second NMOS transistor M n2 The source is connected to the third NMOS transistor M. n3 Drain and gate terminals, third NMOS transistor M n3 The source is connected to ground, and the fourth NMOS transistor M n4 The gate terminal is connected to the second NMOS transistor M. n2 Gate terminal, fourth NMOS transistor M n4 The source is connected to the fifth NMOS transistor M. n5Drain terminal, fifth NMOS transistor M n5 The gate terminal is connected to the third NMOS transistor M. n3 Gate terminal, fifth NMOS transistor M n5 Source terminal connected to ground; sixth NMOS transistor M n6 The source is connected to the fourth NMOS transistor M. n4 Drain terminal, sixth NMOS transistor M n6 The gate terminal is connected to the input signal LS and the input terminal of the second inverter INV2, and the sixth NMOS transistor M n6 The drain terminal is connected to the third PMOS transistor M. p3 Drain and gate terminals, third PMOS transistor M p3 The source terminal is connected to the second PMOS transistor M. p2 Drain and gate terminals, second PMOS transistor M p2 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The gate terminal is connected to the second PMOS transistor M. p2 Gate terminal, fourth PMOS transistor M p4 The drain terminal is connected to the fifth PMOS transistor M. p5 Source terminal, fifth PMOS transistor M p5 The gate terminal is connected to the third PMOS transistor M. p3 Gate terminal, fifth PMOS transistor M p5 The drain terminal is connected to the seventh NMOS transistor M. n7 Drain and gate terminals; one end of the first resistor R1 is connected to the seventh NMOS transistor M. n7 The source is connected to the source, and the other end is connected to ground; one end of the second resistor R2 is connected to the switching node signal SW, and the other end is connected to the eighth NMOS transistor M. n8 Source terminal; Eighth NMOS transistor M n8 The gate terminal is connected to the seventh NMOS transistor M. n7 Gate terminal and ninth NMOS transistor M n9 Drain terminal, eighth NMOS transistor M n8 The drain terminal is connected to the seventh PMOS transistor M. p7 Drain and the tenth NMOS transistor M n10 Drain terminal and eleventh NMOS transistor M n11 Gate terminal; Ninth NMOS transistor M n9 The gate terminal is connected to the output terminal of the second inverter INV2, and the ninth NMOS transistor M... n9 Source grounded; seventh PMOS transistor M p7 The gate terminal is connected to the fifth PMOS transistor M. p5 Gate terminal, seventh PMOS transistor M p7 The source terminal is connected to the sixth PMOS transistor M. p6 Drain terminal, sixth PMOS transistor Mp6 The gate terminal is connected to the fourth PMOS transistor M. p4 Gate terminal, sixth PMOS transistor M p6 The source terminal is connected to the input power signal V. IN The eighth PMOS transistor M p8 The gate terminal is connected to the sixth PMOS transistor M. p6 Gate terminal, eighth PMOS transistor M p8 The drain terminal is connected to the ninth PMOS transistor M. p9 Source terminal, ninth PMOS transistor M p9 The gate terminal is connected to the seventh PMOS transistor M. p7 Gate terminal, ninth PMOS transistor M p9 The drain terminal is connected to the eleventh NMOS transistor M. n11 Drain terminal, tenth PMOS transistor M p10 Drain terminal, eleventh PMOS transistor M p11 Gate terminal and twelfth NMOS transistor M n12 Gate terminal, eleventh NMOS transistor M n11 Source terminal connected to ground; tenth PMOS transistor M p10 The source terminal is connected to the input power signal V. IN The tenth PMOS transistor M p10 The gate terminal is connected to the input signal LS and one input terminal of the first NAND gate NAND1, and the eleventh PMOS transistor M p11 The source terminal is connected to the input power signal V. IN 11th PMOS transistor M p11 The drain terminal is connected to the twelfth NMOS transistor M. n12 The drain terminal is connected to the other input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter is connected to the output signal V. ZCD .

[0007] Secondly, this application provides a Buck-type DC-DC converter, which includes a zero-current detection circuit.

[0008] Optionally, the converter includes: an input power signal V IN upper power transistor M P Lower power transistor M N Switch node signal SW, inductance L, equivalent series resistance R esr Output capacitor C out First feedback resistor R fb1 Second feedback resistor R fb2 Feedback voltage V FB Load resistance R load Logic processing, Zero Current Detection Circuit (ZCD), Drive module, Power transistor (M)P Gate control signal HS, lower power transistor M N Gate control signal LS;

[0009] upper power transistor M P The source terminal is connected to the input power signal V. IN upper power transistor M P Drain terminal connected to power transistor M N The drain terminal and one end of the inductor L, the lower power transistor M N Source terminal connected to ground; equivalent series resistance R esr One end is connected to the other end of the inductor L, with an equivalent series resistance R. esr The other end is connected to the output capacitor C. out One end, output capacitor C out The other end is connected to ground; the first feedback resistor R fb1 One end is connected to the other end of the inductor L, and the first feedback resistor R fb1 The other end is connected to the second feedback resistor R. fb2 One end, and the feedback voltage V FB The data is sent to the logic processing unit, and the second feedback resistor R... fb2 The other end is grounded; load resistance R load One end is connected to the other end of the inductor L, and the load resistor is R. load The other end is connected to ground; the logic output is sent to the driver module, and the output signals of the driver module are respectively connected to the upper power transistor M. P The gate and lower power transistor M N The gate terminal is then fed back to the zero current detection circuit ZCD.

[0010] Optionally, when the input signal LS is high and the circuit is operating normally, the switch node signal SW is compared with a preset threshold. When the switch node signal SW exceeds the preset threshold, the output signal V... ZCD The circuit flips to a high level; when the input signal LS is low, the entire circuit is turned off.

[0011] Optionally, the zero-current detection circuit (ZCD) detects the switching node signal SW, processes it, generates a corresponding output signal, and sends it to the logic processing module (Logic) for further processing. The signal is then transmitted to the power transistor M via the drive module (Drive). P Gate control signal HS and lower power transistor M N Gate control signal LS, and simultaneously power transistor M N The gate control signal LS controls the normal operation and shutdown of the zero current detection circuit ZCD.

[0012] The zero-current detection circuit provided in this application not only enables the system to flip in advance to turn off the lower power transistor in advance, but also, because the circuit operates intermittently during normal system operation, it only operates when needed and remains off during other times. Especially when the system load is light or very light, its duty cycle is long, meaning the system operating frequency is very low, and the power consumption generated by the circuit itself is very low. Attached Figure Description

[0013] Figure 1 A circuit schematic diagram of the zero current detection circuit provided in the embodiments of this application;

[0014] Figure 2 The zero-current detection circuit provided in this application is configured to operate in a Buck converter.

[0015] Figure 3 (a) in the figure is the working waveform of the converter system provided in the embodiment of this application under light load without zero current detection circuit;

[0016] Figure 3 (b) is the waveform diagram of the converter system provided in the embodiment of this application under light load with zero current detection circuit;

[0017] Figure 4 The simulation waveform diagram related to the circuit of the converter operating in DCM mode provided in the embodiments of this application;

[0018] Figure 5 The simulation waveform diagram related to the circuit of the converter operating in CCM mode provided in the embodiments of this application;

[0019] Figure 6 The static current simulation results of the zero-current detection circuit provided in the embodiments of this application when it is working normally in the system. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] The embodiments of this application will now be described in conjunction with the accompanying drawings.

[0022] This application provides a zero-current detection circuit, including: a bias current source I BIAS The first NMOS transistor M n1 The first PMOS transistor M p1 First inverter INV1, second NMOS transistor M n2 The third NMOS transistor M n3 The fourth NMOS transistor M n4The fifth NMOS transistor M n5 The sixth NMOS transistor M n6 The second PMOS transistor M p2 The third PMOS transistor M p3 The fourth PMOS transistor M p4 The fifth PMOS transistor M p5 Second inverter INV2, seventh NMOS transistor M n7 First resistor R1, second resistor R2, eighth NMOS transistor M n8 The sixth PMOS transistor M p6 The seventh PMOS transistor M p7 The eighth PMOS transistor M p8 Ninth PMOS transistor M p9 The tenth NMOS transistor M n10 11th NMOS transistor M n11 The tenth PMOS transistor M p10 11th PMOS transistor M p11 The twelfth NMOS transistor M n12 1. NAND gate NAND1; 2. Inverter INV3;

[0023] Bias current source I BIAS One end is connected to the input power signal V IN The other end is connected to the first NMOS transistor M. n1 Drain terminal and first PMOS transistor M p1 Source end, first NMOS transistor M n1 The gate terminal is connected to the input terminal of the first inverter INV1 and the input signal LS, and the first PMOS transistor M p1 The gate terminal is connected to the output terminal of the first inverter INV1, and the first NMOS transistor M n1 Source terminal and first PMOS transistor M p1 The drain terminal is connected to the second NMOS transistor M. n2 Drain and gate terminals, second NMOS transistor M n2 The source is connected to the third NMOS transistor M. n3 Drain and gate terminals, third NMOS transistor M n3 The source is connected to ground, and the fourth NMOS transistor M n4 The gate terminal is connected to the second NMOS transistor M. n2 Gate terminal, fourth NMOS transistor M n4 The source is connected to the fifth NMOS transistor M. n5 Drain terminal, fifth NMOS transistor M n5 The gate terminal is connected to the third NMOS transistor M. n3 Gate terminal, fifth NMOS transistor M n5 Source terminal connected to ground; sixth NMOS transistor M n6 The source is connected to the fourth NMOS transistor M.n4 Drain terminal, sixth NMOS transistor M n6 The gate terminal is connected to the input signal LS and the input terminal of the second inverter INV2, and the sixth NMOS transistor M n6 The drain terminal is connected to the third PMOS transistor M. p3 Drain and gate terminals, third PMOS transistor M p3 The source terminal is connected to the second PMOS transistor M. p2 Drain and gate terminals, second PMOS transistor M p2 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The gate terminal is connected to the second PMOS transistor M. p2 Gate terminal, fourth PMOS transistor M p4 The drain terminal is connected to the fifth PMOS transistor M. p5 Source terminal, fifth PMOS transistor M p5 The gate terminal is connected to the third PMOS transistor M. p3 Gate terminal, fifth PMOS transistor M p5 The drain terminal is connected to the seventh NMOS transistor M. n7 Drain and gate terminals; one end of the first resistor R1 is connected to the seventh NMOS transistor M. n7 The source is connected to the source, and the other end is connected to ground; one end of the second resistor R2 is connected to the switching node signal SW, and the other end is connected to the eighth NMOS transistor M. n8 Source terminal; Eighth NMOS transistor M n8 The gate terminal is connected to the seventh NMOS transistor M. n7 Gate terminal and ninth NMOS transistor M n9 Drain terminal, eighth NMOS transistor M n8 The drain terminal is connected to the seventh PMOS transistor M. p7 Drain and the tenth NMOS transistor M n10 Drain terminal and eleventh NMOS transistor M n11 Gate terminal; Ninth NMOS transistor M n9 The gate terminal is connected to the output terminal of the second inverter INV2, and the ninth NMOS transistor M... n9 Source grounded; seventh PMOS transistor M p7 The gate terminal is connected to the fifth PMOS transistor M. p5 Gate terminal, seventh PMOS transistor M p7 The source terminal is connected to the sixth PMOS transistor M. p6 Drain terminal, sixth PMOS transistor M p6 The gate terminal is connected to the fourth PMOS transistor M. p4 Gate terminal, sixth PMOS transistor M p6 The source terminal is connected to the input power signal V. IN The eighth PMOS transistor M p8The gate terminal is connected to the sixth PMOS transistor M. p6 Gate terminal, eighth PMOS transistor M p8 The drain terminal is connected to the ninth PMOS transistor M. p9 Source terminal, ninth PMOS transistor M p9 The gate terminal is connected to the seventh PMOS transistor M. p7 Gate terminal, ninth PMOS transistor M p9 The drain terminal is connected to the eleventh NMOS transistor M. n11 Drain terminal, tenth PMOS transistor M p10 Drain terminal, eleventh PMOS transistor M p11 Gate terminal and twelfth NMOS transistor M n12 Gate terminal, eleventh NMOS transistor M n11 Source terminal connected to ground; tenth PMOS transistor M p10 The source terminal is connected to the input power signal V. IN The tenth PMOS transistor M p10 The gate terminal is connected to the input signal LS and one input terminal of the first NAND gate NAND1, and the eleventh PMOS transistor M p11 The source terminal is connected to the input power signal V. IN 11th PMOS transistor M p11 The drain terminal is connected to the twelfth NMOS transistor M. n12 The drain terminal is connected to the other input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter is connected to the output signal V. ZCD .

[0024] like Figure 1 As shown, the zero-current detection circuit consists of a bias circuit, an input stage, an output stage, and gate circuits. The bias circuit is constructed using an NMOS cascode current mirror, with a bias current I... BIAS The current is transmitted through the transmission gate and mirrored by the current mirror, thus providing the current required for the normal operation of the entire circuit. The transmission gate is controlled by the signal LS. The bias current I is only applied when the LS signal is high. BIAS Only when current is supplied can transmission occur; otherwise, without current to the circuit, the circuit cannot function properly.

[0025] The input stage is the core of the circuit. Instead of a traditional voltage comparator, it uses a current comparator to directly sample and compare the inductor current. Since the zero-current sensing circuit's function is to detect whether there is reverse current in the Buck converter's inductor, it allows the converter to operate in DCM mode under light load, avoiding excessive power consumption and thus improving system efficiency. Therefore, compared to a voltage comparator, the current comparator can directly sample the current at the switching node and compare the current directly, which can improve the comparison speed to some extent. (By M...)p4 ~M p7 M n7 M n8 Together with resistors R1 and R2, it forms a structure, where M n7 and M n8 The input transistor of the current comparator has a smaller width-to-length ratio, increasing its on-resistance and thus its voltage withstand capability. The two input terminals of the current comparator are not directly connected to their respective potentials; instead, they are connected to resistors R1 and R2 respectively, and then fed into the source terminals of the input transistor. This not only increases the voltage withstand capability of the comparator input transistor to a certain extent, but also, by setting the resistance values ​​of resistors R1 and R2, allows the zero-current detection circuit to have an advance capability during operation. This ensures that the lower power transistor of the converter is turned off before the inductor current drops to zero. This can, to some extent, reduce the problem of untimely turn-off of the lower power transistor caused by internal logic and drive delays in the converter system, thus preventing inductor current backflow. The currents in the two branches of the current comparator are obtained by mirroring the PMOS common-source cascode current mirror.

[0026] (1);

[0027] (2);

[0028] Where I1 and I2 are the current values ​​on the two branches of the current comparator input, respectively, and a and b are the current amplification factors. BIAS The bias current is provided for the bias circuit. The output stage consists of a common-source circuit, an inverter, and a NAND gate. When the comparator in the input stage outputs the corresponding comparison signal, it is shaped by the output stage to output a corresponding pulse signal, which controls the turn-off of the lower power transistor in the converter.

[0029] In the circuit, signal LS is the enable control signal for the normal operation and shutdown of the entire circuit, obtained from the gate control signal of the lower power transistor inside the Buck converter system. SW is the input signal terminal of this zero-current detection circuit, connected to the switching node SW of the Buck converter, sampling the inductor current change signal, and comparing it to determine whether the inductor current has crossed zero. IN This provides the power supply voltage for the circuit to operate, i.e., the input voltage of the Buck converter, V. ZCD This is the pulse signal output by the circuit.

[0030] The basic principle of the zero-current detection circuit is as follows: when the LS signal is high, the transmission gate transmits the bias current I. BIASThe internal comparator of the circuit performs the comparison. Theoretically, the Buck converter activates the zero-current detection circuit to turn off the freewheeling diode when the inductor current just drops to zero. However, in practical applications, considering the system's conversion efficiency under light load conditions, it is necessary to ensure that the zero-current detection circuit activates and turns off the freewheeling diode before the inductor current drops to zero. Therefore, a lead time needs to be set in the circuit. So, when SW is lower than the set lead time, the circuit outputs signal V. ZCD The output is low; when SW is higher than the set lead time, M... n11 The drain potential of the transistor is pulled low. After processing by the inverter and NAND gate circuit, the circuit outputs signal V. ZCD The output is high. When the LS signal is high, the entire circuit is turned off, and the circuit output signal V... ZCD It is pulled low.

[0031] When this zero-current sensing circuit is working normally in the Buck converter system, all its internal MOSFETs operate in the subthreshold region, i.e., the gate-source voltage V of the MOSFETs is V. GS Less than or equal to its threshold voltage V TH At this point, the MOSFET forms a weak inversion layer, and the gate-source voltage V of the MOSFET in this operating region... GS With leakage current I D The relationship is exponential, that is:

[0032] (3);

[0033] Where I D0 V is the characteristic current, W is the width of the MOSFET, L is the length of the MOSFET, η is the non-ideality factor, which is generally greater than 1. T The thermal voltage and characteristic current I are given. D0 This is related to the manufacturing process. Therefore, compared to a MOSFET operating in the saturation region, the current flowing through it is very small. That is, the subthreshold current of a MOSFET operating in the subthreshold region is very low. Moreover, the MOSFET can still be well controlled by the gate voltage, which is beneficial for low power consumption and low voltage applications.

[0034] According to the MOSFET current expression, the voltage V at point A in the circuit is... A The following relationship must be satisfied:

[0035] (4);

[0036] (5);

[0037] Where R1 and R2 are the resistance values ​​of the two resistors connected in series at the input of the current comparator, and I1 and I2 represent M respectively. n7 and M n8The current in the branch containing the tube is obtained by mirroring the current through a current mirror. Here, it is assumed that I2 = nI1, where n is the current amplification factor, and M is designed to... n7 and M n8 The width-to-length ratio of the pipes is consistent, that is:

[0038] (6);

[0039] Then, based on equations (4) and (5), the threshold voltage V at the early flip point of the zero-current detection circuit output can be calculated. SW for:

[0040] (7);

[0041] According to equation (7), the threshold point V for the zero-current detection circuit to flip can be seen. SW The threshold point at which the zero-current detection circuit flips prematurely in the system is determined by setting the resistance difference between R1 and R2, and the branch current I1 is related to the resistance values ​​of R1 and R2. Before the inductor current drops to zero, the circuit outputs a signal V. ZCD To advance the flip-to-high level, the freewheeling diode is turned off. The larger the difference between R1 and R2, the earlier the flip-to-high level occurs. An appropriate threshold needs to be set based on the actual application. If the current comparator's two branches have the same current (i.e., n is 1), then the advance flip-to-high point V... SW The expression is:

[0042] (8);

[0043] This circuit not only enables early shutdown of the lower power transistor in the converter system to prevent inductor current backflow, but also has very low quiescent power consumption, effectively reducing the overall quiescent power consumption of the Buck converter. M... n6 M n9 M n10 M p10 To enable the control section, LS is the control signal. This circuit uses the drive signal at the gate of the lower power transistor of the converter to control its normal operation and shutdown. The zero-current detection circuit only turns on and operates normally when the lower power transistor drive signal jumps to a high level, i.e., during the conduction period of the lower power transistor. It detects whether the inductor current of the converter drops below zero and flips the output signal at the set advance amount. Then, through system logic operation, it turns off the lower power transistor and generates a new lower power transistor gate drive signal to turn off the zero-current detection circuit. It consumes almost no quiescent current, and the quiescent current is extremely low, which helps to reduce the quiescent power consumption of the entire Buck converter and improve the conversion efficiency of the system.

[0044] This application also provides a Buck-type DC-DC converter, which includes a zero-current detection circuit.

[0045] Optionally, the converter includes: an input power signal V IN upper power transistor M P Lower power transistor M N Switch node signal SW, inductance L, equivalent series resistance R esr Output capacitor C out First feedback resistor R fb1 Second feedback resistor R fb2 Feedback voltage V FB Load resistance R load Logic processing, Zero Current Detection Circuit (ZCD), Drive module, Power transistor (M) P Gate control signal HS, lower power transistor M N Gate control signal LS;

[0046] upper power transistor M P The source terminal is connected to the input power signal V. IN upper power transistor M P Drain terminal connected to power transistor M N The drain terminal and one end of the inductor L, the lower power transistor M N Source terminal connected to ground; equivalent series resistance R esr One end is connected to the other end of the inductor L, with an equivalent series resistance R. esr The other end is connected to the output capacitor C. out One end, output capacitor C out The other end is connected to ground; the first feedback resistor R fb1 One end is connected to the other end of the inductor L, and the first feedback resistor R fb1 The other end is connected to the second feedback resistor R. fb2 One end, and the feedback voltage V FB The data is sent to the logic processing unit, and the second feedback resistor R... fb2 The other end is grounded; load resistance R load One end is connected to the other end of the inductor L, and the load resistor is R. load The other end is connected to ground; the logic output is sent to the driver module, and the output signals of the driver module are respectively connected to the upper power transistor M. P The gate and lower power transistor M N The gate terminal is then fed back to the zero current detection circuit ZCD.

[0047] Optionally, when the input signal LS is high and the circuit is operating normally, the switch node signal SW is compared with a preset threshold. When the switch node signal SW exceeds the preset threshold, the output signal V... ZCD The circuit flips to a high level; when the input signal LS is low, the entire circuit is turned off.

[0048] Optionally, the zero-current detection circuit (ZCD) detects the switching node signal SW, processes it, generates a corresponding output signal, and sends it to the logic processing module (Logic) for further processing. The signal is then transmitted to the power transistor M via the drive module (Drive). P Gate control signal HS and lower power transistor M N Gate control signal LS, and simultaneously power transistor M N The gate control signal LS controls the normal operation and shutdown of the zero current detection circuit ZCD.

[0049] like Figure 2 As shown, its basic operation is as follows: When the Buck converter performs a series of logic operations to turn on its lower power transistor, the LS signal jumps to a high level, and the zero-current detection circuit starts to operate normally. At this time, the converter is in the freewheeling phase, and the inductor current shows a decreasing trend. The signal SW at the converter switching node is sent to the zero-current detection circuit and compared with zero. When the signal at this point is less than zero, that is, when the inductor current is greater than zero, the circuit output signal is low. When the inductor current continues to decrease to almost zero, the circuit output signal flips to a high level at the set early flip point. After the internal logic operation of the Buck converter, the gate control signal of the lower power transistor flips, thereby turning off the lower power transistor in advance, that is, the LS signal flips to a low level. At the same time, the LS signal controls the zero-current detection circuit to turn off, and the circuit no longer operates until the next lower power transistor turn-on time period arrives. Then the zero-current detection circuit turns on again and operates normally, and this cycle continues.

[0050] Appendix Figure 3 The figure shows the operating waveforms of the Buck converter system under light load with and without a zero-current detection circuit, where I L SW represents the system inductor current waveform, SW represents the signal waveform at the switching node, and LS represents the gate drive signal of the power transistor in the system.

[0051] When the system is under light load and there is no zero-current detection circuit inside the system, as shown in the attached... Figure 3 As shown in (a), when the LS signal is high, i.e., the lower power transistor is on, the inductor current continues to decrease. Since the load on the system is very light at this time, even after the inductor current reaches zero, the lower power transistor is still not turned off. Therefore, the energy stored in the output capacitor will be released into the inductor and the load, resulting in a reverse current flow in the inductor, also known as inductor current reverse flow. This phenomenon significantly affects the power consumption and efficiency of the system under light load. Therefore, a zero-current detection circuit is often added to the Buck converter system to ensure that the lower power transistor is turned off promptly when the inductor current drops to zero under light load, preventing inductor current reverse flow and thus effectively improving efficiency under light load to a certain extent. Figure 3As shown in (b), when the inductor current drops to zero, the lower power transistor is turned off in time, i.e., LS jumps to a low level, and the inductor current will remain in a zero current state for a period of time.

[0052] Appendix Figure 4 The figure shows the simulation waveform of the Buck converter operating in DCM mode, where V CMP V is the output waveform of the internal loop comparator of the system. TON V is the output signal of the module that generates the on-time within the system. ZCD This is the output waveform of the zero-current detection circuit in this design. HS and LS are the gate drive signals of the upper and lower power transistors of the converter, respectively, and SW is the signal waveform at the switching node. L The diagram shows the inductor current waveform of the converter. Due to the zero-current sensing module's function under light load, the inductor current transformation is not continuous but discontinuous, i.e., discontinuous conduction mode (DCM). The zero-current sensing circuit is set with an early switching point V in the system. SW With a voltage of approximately -9.626mV, the lower power transistor of the system can be turned off before the inductor current reaches zero, thus avoiding the problem of inductor current backflow.

[0053] Appendix Figure 5 The figure shows the simulation waveform of the Buck converter operating in CCM mode. In this mode, the output signal of the zero current detection circuit in this design always remains at a low level, which does not affect the normal operation of the system.

[0054] The zero-current detection circuit provided in this application not only enables early switching of the power transistor in the system, thus turning it off early, but also operates intermittently during normal system operation, only working when needed and remaining off during other times. This is particularly beneficial when the system load is light or very light, as its duty cycle is long (i.e., the system operating frequency is very low) and the power consumption of the circuit itself is extremely low. (See attached diagram.) Figure 6 The figure shows the quiescent current of all modules in the Buck converter system and the total quiescent current waveform of the converter system. Q_ALL , where I ZCD The quiescent current consumed by the zero-current detection circuit in this design is only 159.418 pA, which is extremely low, significantly reducing the overall power consumption of the circuit. The minimal quiescent current consumption effectively reduces the system's static power consumption, thereby significantly lowering the overall system power consumption.

[0055] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A zero-current detection circuit, characterized in that, The circuit includes: a bias current source I BIAS The first NMOS transistor M n1 The first PMOS transistor M p1 First inverter INV1, second NMOS transistor M n2 The third NMOS transistor M n3 The fourth NMOS transistor M n4 The fifth NMOS transistor M n5 The sixth NMOS transistor M n6 The second PMOS transistor M p2 The third PMOS transistor M p3 The fourth PMOS transistor M p4 The fifth PMOS transistor M p5 Second inverter INV2, seventh NMOS transistor M n7 First resistor R1, second resistor R2, eighth NMOS transistor M n8 The sixth PMOS transistor M p6 The seventh PMOS transistor M p7 The eighth PMOS transistor M p8 Ninth PMOS transistor M p9 The tenth NMOS transistor M n10 11th NMOS transistor M n11 The tenth PMOS transistor M p10 11th PMOS transistor M p11 The twelfth NMOS transistor M n12 1. NAND gate NAND1; 2. Inverter INV3; Bias current source I BIAS One end is connected to the input power signal V IN The other end is connected to the first NMOS transistor M. n1 Drain terminal and first PMOS transistor M p1 Source end, first NMOS transistor M n1 The gate terminal is connected to the input terminal of the first inverter INV1 and the input signal LS, and the first PMOS transistor M p1 The gate terminal is connected to the output terminal of the first inverter INV1, and the first NMOS transistor M n1 Source terminal and first PMOS transistor M p1 The drain terminal is connected to the second NMOS transistor M. n2 Drain and gate terminals, second NMOS transistor M n2 The source is connected to the third NMOS transistor M. n3 Drain and gate terminals, third NMOS transistor M n3 The source is connected to ground, and the fourth NMOS transistor M n4 The gate terminal is connected to the second NMOS transistor M. n2 Gate terminal, fourth NMOS transistor M n4 The source is connected to the fifth NMOS transistor M. n5 Drain terminal, fifth NMOS transistor M n5 The gate terminal is connected to the third NMOS transistor M. n3 Gate terminal, fifth NMOS transistor M n5 Source terminal connected to ground; sixth NMOS transistor M n6 The source is connected to the fourth NMOS transistor M. n4 Drain terminal, sixth NMOS transistor M n6 The gate terminal is connected to the input signal LS and the input terminal of the second inverter INV2, and the sixth NMOS transistor M n6 The drain terminal is connected to the third PMOS transistor M. p3 Drain and gate terminals, third PMOS transistor M p3 The source terminal is connected to the second PMOS transistor M. p2 Drain and gate terminals, second PMOS transistor M p2 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The source terminal is connected to the input power signal V. IN The fourth PMOS transistor M p4 The gate terminal is connected to the second PMOS transistor M. p2 Gate terminal, fourth PMOS transistor M p4 The drain terminal is connected to the fifth PMOS transistor M. p5 Source terminal, fifth PMOS transistor M p5 The gate terminal is connected to the third PMOS transistor M. p3 Gate terminal, fifth PMOS transistor M p5 The drain terminal is connected to the seventh NMOS transistor M. n7 Drain and gate terminals; one end of the first resistor R1 is connected to the seventh NMOS transistor M. n7 The source is connected to the source, and the other end is connected to ground; one end of the second resistor R2 is connected to the switching node signal SW, and the other end is connected to the eighth NMOS transistor M. n8 Source terminal; Eighth NMOS transistor M n8 The gate terminal is connected to the seventh NMOS transistor M. n7 Gate terminal and ninth NMOS transistor M n9 Drain terminal, eighth NMOS transistor M n8 The drain terminal is connected to the seventh PMOS transistor M. p7 Drain and the tenth NMOS transistor M n10 Drain terminal and eleventh NMOS transistor M n11 Gate terminal; Ninth NMOS transistor M n9 The gate terminal is connected to the output terminal of the second inverter INV2, and the ninth NMOS transistor M... n9 Source grounded; seventh PMOS transistor M p7 The gate terminal is connected to the fifth PMOS transistor M. p5 Gate terminal, seventh PMOS transistor M p7 The source terminal is connected to the sixth PMOS transistor M. p6 Drain terminal, sixth PMOS transistor M p6 The gate terminal is connected to the fourth PMOS transistor M. p4 Gate terminal, sixth PMOS transistor M p6 The source terminal is connected to the input power signal V. IN The eighth PMOS transistor M p8 The gate terminal is connected to the sixth PMOS transistor M. p6 Gate terminal, eighth PMOS transistor M p8 The drain terminal is connected to the ninth PMOS transistor M. p9 Source terminal, ninth PMOS transistor M p9 The gate terminal is connected to the seventh PMOS transistor M. p7 Gate terminal, ninth PMOS transistor M p9 The drain terminal is connected to the eleventh NMOS transistor M. n11 Drain terminal, tenth PMOS transistor M p10 Drain terminal, eleventh PMOS transistor M p11 Gate terminal and twelfth NMOS transistor M n12 Gate terminal, eleventh NMOS transistor M n11 Source terminal connected to ground; tenth PMOS transistor M p10 The source terminal is connected to the input power signal V. IN The tenth PMOS transistor M p10 The gate terminal is connected to the input signal LS and one input terminal of the first NAND gate NAND1, and the eleventh PMOS transistor M p11 The source terminal is connected to the input power signal V. IN 11th PMOS transistor M p11 The drain terminal is connected to the twelfth NMOS transistor M. n12 The drain terminal is connected to the other input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter is connected to the output signal V. ZCD .

2. A Buck-type DC-DC converter, characterized in that, The DC-DC converter includes the zero-current detection circuit as described in claim 1.

3. The Buck-type DC-DC converter according to claim 2, characterized in that, The converter includes: an input power signal V IN upper power transistor M P Lower power transistor M N Switch node signal SW, inductance L, equivalent series resistance R esr Output capacitor C out First feedback resistor R fb1 Second feedback resistor R fb2 Feedback voltage V FB Load resistance R load Logic processing, Zero Current Detection Circuit (ZCD), Drive module, Power transistor (M) P Gate control signal HS, lower power transistor M N Gate control signal LS; upper power transistor M P The source terminal is connected to the input power signal V. IN upper power transistor M P Drain terminal connected to power transistor M N The drain terminal and one end of the inductor L, the lower power transistor M N Source terminal connected to ground; equivalent series resistance R esr One end is connected to the other end of the inductor L, with an equivalent series resistance R. esr The other end is connected to the output capacitor C. out One end, output capacitor C out The other end is connected to ground; the first feedback resistor R fb1 One end is connected to the other end of the inductor L, and the first feedback resistor R fb1 The other end is connected to the second feedback resistor R. fb2 One end, and the feedback voltage V FB The data is sent to the logic processing unit, and the second feedback resistor R... fb2 The other end is grounded; load resistance R load One end is connected to the other end of the inductor L, and the load resistor is R. load The other end is connected to ground; the logic output is sent to the driver module, and the output signals of the driver module are respectively connected to the upper power transistor M. P The gate and lower power transistor M N The gate terminal is then fed back to the zero current detection circuit ZCD.

4. The Buck-type DC-DC converter according to claim 2, characterized in that, When the input signal LS is high, the circuit operates normally. The switching node signal SW is compared with the preset threshold. When the switching node signal SW exceeds the preset threshold, the output signal V is triggered. ZCD The circuit flips to a high level; when the input signal LS is low, the entire circuit is turned off.

5. The Buck-type DC-DC converter according to claim 2, characterized in that, The zero-current detection circuit (ZCD) detects the switching node signal SW, processes it, and generates a corresponding output signal, which is then sent to the logic processing module (Logic) for further processing. Finally, the driver module (Drive) generates the signal for the power transistor M. P Gate control signal HS and lower power transistor M N Gate control signal LS, and simultaneously power transistor M N The gate control signal LS controls the normal operation and shutdown of the zero current detection circuit ZCD.

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