Functional Test Method for SPI NAND Flash Chip and SPI Test Platform

Abstract

The present application relates to a functional test method and an SPI test platform applied to an SPI NAND FLASH chip, and relates to the technical field of chip testing. The method is applied to the SPI test platform, and the SPI test platform at least includes a first MCU, a second MCU, a command receiving buffer, and a result sending buffer. The second MCU supports the QSPI protocol. The method includes: the first MCU receives a functional test command of the SPI NAND FLASH chip sent by the test host; the first MCU stores the functional test command in the command receiving buffer; when the second MCU detects that there is a functional test command in the command receiving buffer, the second MCU sends the functional test command to the SPI controller; the second MCU receives the functional test result fed back by the SPI controller and stores the functional test result in the result sending buffer; when the first MCU detects that there is a functional test result in the result sending buffer, the first MCU feeds back the functional test result to the test host. By adopting the present application, the SPI test time can be shortened and the test efficiency of the SPI NAND FLASH chip can be improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and particularly to a functional testing method and an SPI testing platform applied to SPI NAND FLASH chips. Background Art

[0002] An SPI NAND FLASH chip is a storage device that uses NAND memory particles internally and has an SPI protocol interface externally. The SPI NAND FLASH chip can include a FLASH storage core and an SPI controller. Externally, information can be exchanged with the SPI controller based on the SPI protocol, and the SPI controller can perform operations such as writing, reading, and erasing relevant data in the FLASH storage core.

[0003] After the manufacturer produces an SPI NAND FLASH chip, it is necessary to test the storage function of the SPI NAND FLASH chip. During the testing process, technicians can use a test host to send various predetermined functional test commands to the SPI NAND FLASH chip. Thus, the SPI controller in the SPI NAND FLASH chip can process the functional test commands, obtain corresponding functional test results, and feedback the functional test results to the test host. In this way, the test host can detect and evaluate the functional parameters of the SPI NAND FLASH chip according to the functional test results.

[0004] In the process of implementing this application, the inventors found that the above technology has at least the following problems:

[0005] When using a test host to perform functional testing on an SPI NAND FLASH chip, after the test host sends a functional test command, it needs to wait for the SPI control to feedback the functional test result of this functional test command before sending the next functional test command to the SPI controller. Therefore, the entire testing process takes a lot of time, and the testing efficiency of the SPI NAND FLASH chip is relatively low. Summary of the Invention

[0006] In order to shorten the time required for the entire SPI testing process and improve the testing efficiency of SPI NAND FLASH chips, embodiments of this application provide a functional testing method and an SPI testing platform applied to SPI NAND FLASH chips. The technical solutions are as follows:

[0007] In a first aspect, an embodiment of the present application provides a functional test method for an SPI NAND FLASH chip. The method is applied to an SPI test platform, which at least includes a first MCU, a second MCU, a command receiving buffer, and a result sending buffer. The second MCU supports the QSPI protocol. The method includes:

[0008] The first MCU receives a functional test command for the SPI NAND FLASH chip sent by the test host;

[0009] The first MCU stores the functional test command in the command receiving buffer;

[0010] When the second MCU detects that there is a functional test command stored in the command receiving buffer, it sends the functional test command to the SPI controller;

[0011] The second MCU receives the functional test result fed back by the SPI controller and stores the functional test result in the result sending buffer;

[0012] When the first MCU detects that there is a functional test result stored in the result sending buffer, it feeds back the functional test result to the test host.

[0013] Based on the above technical solution, the dual-core MCU is used for functional testing. The sending of functional test commands and the feedback of functional test results are independent of each other and do not interfere with each other. There is no need to wait for the functional test result before sending the functional test command, thus shortening the time required for the entire test process and improving the test efficiency of the SPI NAND FLASH chip.

[0014] Optionally, the first MCU receiving the functional test command for the SPI NAND FLASH chip sent by the test host includes:

[0015] The first MCU receives a test command sequence sent by the test host based on the TCP / IP protocol. The test command sequence includes at least one functional test command for the SPI NAND FLASH chip.

[0016] Based on the above technical solution, the first MCU and the test host transmit the test command sequence through the TCP / IP protocol, which can achieve fast, efficient, and orderly transmission of functional test commands.

[0017] Optionally, when the first MCU detects that there is a functional test result stored in the result sending buffer, feeding back the functional test result to the test host includes:

[0018] When the first MCU detects that there is a functional test result in the result sending buffer, it determines the number of test commands corresponding to the functional test result;

[0019] When the number of test commands is equal to the total number of functional test commands in the sent test command sequence, the first MCU feeds back all the functional test results in the result sending buffer to the test host and clears the result sending buffer.

[0020] Based on the above technical solution, taking the total number of functional test commands as the standard to perform the clearing operation on the result sending buffer can ensure that each functional test command corresponds to a functional test result, and can enable the result sending buffer to be cleared in time.

[0021] Optionally, the functional test result carries identification information of the SPI NAND FLASH chip;

[0022] When the first MCU detects that there is a functional test result in the result sending buffer, feeding back the functional test result to the test host includes:

[0023] When the first MCU detects that there is a functional test result in the result sending buffer, it determines the number of functional test results corresponding to the identification information of each SPI NAND FLASH chip;

[0024] When the number of functional test results is equal to the total number of functional test commands in the sent test command sequence, the first MCU feeds back the functional test results corresponding to the identification information in the result sending buffer to the test host.

[0025] Based on the above technical solution, taking the identification information of the SPI NAND FLASH chip as the basis, when the number of functional test results of a certain chip reaches the standard, feeding back the functional test results to the test host can, on the one hand, ensure that the functional test results of each SPI NAND FLASH chip are fed back in time and completely, and on the other hand, can avoid the confusion of the functional test results of multiple SPI NAND FLASH chips.

[0026] Optionally, the method further includes:

[0027] The second MCU counts the average result feedback duration of each functional test command;

[0028] When the actual result feedback duration of the target functional test command of the target SPI NAND FLASH chip is greater than the corresponding average result feedback duration and the difference is greater than the preset threshold, the second MCU resends the target functional test command to the target SPI NAND FLASH chip;

[0029] After receiving the new function test result of the target function test command, the second MCU associatively stores all the function test results of the target function test command in the result sending buffer, so that the first MCU can simultaneously feedback all the function test results of the target function test command to the test host.

[0030] Based on the above technical solution, the result feedback duration is used to determine whether there is an abnormality in the function test, and the function detection is repeatedly executed and all the function test results are fed back, so that the test host can more easily detect the actual situation of the function test abnormality.

[0031] Optionally, the first MCU stores the function test command in the command receiving buffer, including:

[0032] After the first MCU converts the function test command into the SPI protocol format, the function test command is stored in the command receiving buffer;

[0033] The feedback of the function test result to the test host includes:

[0034] After the first MCU converts the function test command into the TCP / IP protocol format, the function test result is fed back to the test host.

[0035] Based on the above technical solution, the first MCU is used to perform format conversion operations between the TCP / IP protocol and the SPI protocol, which can not only ensure fast data interaction with the test host, but also ensure the normal flow of SPI data inside the SPI test platform.

[0036] Optionally, when the second MCU detects that there is a function test command stored in the command receiving buffer, after sending the function test command to the SPI controller, it further includes:

[0037] The second MCU counts the data length in the command receiving buffer and the total amount of data of the function test command that has been sent;

[0038] When the total amount of data is equal to the data length, the second MCU sends a cache clearing instruction to the command receiving buffer.

[0039] Based on the above technical solution, the command receiving buffer is cleared by comparing the data length in the command receiving buffer with the sending amount of the function test command, so that the command receiving buffer can be cleared in a timely and efficient manner, and at the same time, the probability that the function test command is accidentally cleared before being sent can be reduced.

[0040] Second aspect, an embodiment of the present application provides an SPI test platform, which at least includes a first MCU, a second MCU, a command receiving buffer, and a result sending buffer. The second MCU supports the QSPI protocol, where:

[0041] The first MCU is configured to receive a functional test command of an SPI NAND FLASH chip sent by a test host and store the functional test command in the command receiving buffer;

[0042] The second MCU is configured to send the functional test command to an SPI controller when it detects that there is a functional test command in the command receiving buffer;

[0043] The second MCU is further configured to receive a functional test result fed back by the SPI controller and store the functional test result in the result sending buffer;

[0044] The first MCU is further configured to feed back the functional test result to the test host when it detects that there is a functional test result in the result sending buffer.

[0045] Third aspect, an embodiment of the present application provides a control chip, which includes a processor and a memory. At least one instruction, at least one program, a code set, or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the processing of the first MCU or the second MCU in the method.

[0046] Fourth aspect, an embodiment of the present application provides a computer-readable storage medium. At least one instruction, at least one program, a code set, or an instruction set is stored in the storage medium, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the processing of the first MCU or the second MCU in the method.

[0047] In summary, the present application has the following beneficial effects:

[0048] Using the functional test method for SPI NAND FLASH chips disclosed in this application, the first MCU receives the functional test command for the SPI NAND FLASH chip sent by the test host; the first MCU stores the functional test command in the command reception buffer; when the second MCU detects that there is a functional test command stored in the command reception buffer, it sends the functional test command to the SPI controller; the second MCU receives the functional test result fed back by the SPI controller and stores the functional test result in the result transmission buffer; when the first MCU detects that there is a functional test result stored in the result transmission buffer, it feeds back the functional test result to the test host. In this way, the dual-core MCU is used for functional testing, and the sending of the functional test command and the feedback of the functional test result are independent of each other and do not interfere with each other. There is no need to wait for the functional test result before sending the functional test command, thus shortening the time required for the entire test process and improving the test efficiency of the SPI NAND FLASH chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 FIG. is a schematic structural diagram of an SPI test platform in an embodiment of this application;

[0050] Figure 2 FIG. is a flowchart of a functional test method for an SPI NAND FLASH chip in an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] In order to make the objectives, technical solutions and advantages of this application clearer and more understandable, the following further describes this application in detail with reference to the accompanying Figure 1 - Figure 2 drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0052] An embodiment of this application provides a functional test method for an SPI NAND FLASH chip, and this method can be applied to, for example Figure 1The shown SPI test platform can be used to perform functional tests on SPI NAND FLASH chips to detect whether the functional logic of the SPI NAND FLASH chips operates normally. Among them, the SPI test platform can include at least two MCUs: the first MCU and the second MCU, and two buffers: a command receiving buffer and a result sending buffer. The first MCU can be used to establish a communication connection with the test host and perform data interaction based on the communication connection. The second MCU can be used to perform data interaction with the SPI controller of the SPI NAND FLASH chip. Both the first MCU and the second MCU can perform data read and write operations on the command receiving buffer and the result sending buffer. The second MCU can support the QSPI protocol, that is, it can perform relatively high-speed data interaction with the SPI controller based on the QSPI protocol.

[0053] The following will combine specific implementation manners to Figure 2 make a detailed description of the shown processing flow, and the content can be as follows:

[0054] Step 201, the first MCU receives the functional test command of the SPI NAND FLASH chip sent by the test host.

[0055] In implementation, when technicians need to perform a functional test on the SPI NAND FLASH chip, they can configure the SPI NAND FLASH chip to be tested in the SPI test platform and operate the test host to start the test process of the SPI NAND FLASH chip. Subsequently, the test host can respond to the operation of the technicians, generate a functional test command for the SPI NAND FLASH chip, and then send the functional test command through the communication connection already established with the first MCU. Therefore, the first MCU can receive the functional test command of the SPI NAND FLASH chip sent by the test host.

[0056] Optionally, the first MCU and the test host can use the TCP / IP protocol for large-volume and fast data transmission. Correspondingly, the processing of step 201 can be as follows: The first MCU receives the test command sequence sent by the test host based on the TCP / IP protocol, and the test command sequence includes at least one functional test command for the SPI NAND FLASH chip.

[0057] In implementation, the first MCU can support the TCP / IP protocol and can establish a communication connection with the test host based on the TCP / IP protocol. In this way, after the test host generates function test commands for the SPI NAND FLASH chip, it can combine the function test commands into a test command sequence and send the test command sequence to the first MCU based on the TCP / IP protocol. Therefore, the first MCU can receive a test command sequence containing at least one function test command for the SPI NAND FLASH chip.

[0058] Step 202: The first MCU stores the function test command in the command reception buffer.

[0059] In implementation, after receiving the function test command, the first MCU can store the function test command in the command reception buffer in sequence. It can be understood that after the test host generates multiple function test commands, it can mark the function test commands according to the generation order, and the first MCU can store the multiple received function test commands according to the marked order, or can directly store the function test commands in sequence according to the reception order.

[0060] Optionally, the SPI test platform can use the SPI protocol to complete the internal data transfer. Correspondingly, the processing of step 202 can be as follows: After converting the function test command into the SPI protocol format, the first MCU stores the function test command in the command reception buffer.

[0061] In implementation, after receiving the test command sequence based on the TCP / IP protocol, the first MCU can read the function test commands in the test command sequence one by one, then use the SPI protocol to perform format conversion on each function test command, and then store the function test commands in the SPI protocol format in the command reception buffer.

[0062] Step 203: When the second MCU detects that there is a function test command stored in the command reception buffer, it sends the function test command to the SPI controller.

[0063] In implementation, after the test starts, the second MCU can monitor the data storage status in the command reception buffer in real time. When it detects that there is a newly stored function test command in the command reception buffer, the second MCU can read the newly stored function test command and send the function test command to the SPI controller of the SPI NAND FLASH chip. It is worth mentioning that the SPI test platform can be used for the function test of multiple SPI NAND FLASH chips at the same time, that is, the second MCU can send each function test command to the SPI controllers of multiple SPI NAND FLASH chips at the same time.

[0064] Optionally, the second MCU can clear the command reception buffer according to the total amount of data. Correspondingly, after step 203, the following processing may exist: The second MCU counts the data length in the command reception buffer and the total amount of data of the sent function test commands; when the total amount of data is equal to the data length, the second MCU sends a buffer clearing instruction to the command reception buffer.

[0065] In implementation, before the second MCU reads the function test command from the command reception buffer, it can first obtain the data length in the command reception buffer. At the same time, when the second MCU sends the function test command to the SPI controller, it can also record the total amount of data of the sent function test commands in real time. Furthermore, the second MCU can continuously compare the relationship between the above data length and the total amount of data. When the total amount of data is equal to the data length, it can be determined that all function test commands in the command reception buffer have been sent. Therefore, the second MCU can send a buffer clearing instruction to the command reception buffer. It is worth mentioning that when the first MCU receives the test command sequence, it can first determine whether there is already a function test command stored in the command reception buffer. If it is already stored, it can wait until the command reception buffer is cleared before storing. If it is not stored, it can write all function test commands included in the test command sequence into the command reception buffer.

[0066] Step 204, the second MCU receives the function test result fed back by the SPI controller and stores the function test result in the result sending buffer.

[0067] In implementation, the SPI controller can receive and execute the function test command sent by the second MCU to generate the corresponding function test result. After that, the SPI controller can feed back the function test result to the second MCU. After receiving the function test result fed back by the SPI controller, the second MCU can store the function test result in the result sending buffer. Further, when storing the function test result, the second MCU can store the function test results corresponding to the function test commands in sequence in the result sending buffer according to the sending order of the function test commands.

[0068] Step 205, when the first MCU detects that there is a function test result stored in the result sending buffer, it feeds back the function test result to the test host.

[0069] In implementation, while storing the function test command in the command reception buffer, the first MCU can monitor the data storage status in the result sending buffer in real time. When it detects that there is a newly stored function test result in the result sending buffer, the second MCU can read the newly stored function test result and feed back the function test result to the test host, so that the test host can determine the function indicators of the SPI NAND FLASH chip according to the function test result.

[0070] Optionally, based on the mechanism of sending the test command sequence described above, the first MCU can feedback the function test results corresponding to the same test command sequence at one time. Correspondingly, the processing of step 205 can be as follows: when the first MCU detects that there are function test results stored in the result sending buffer, it judges the number of test commands corresponding to the function test results; when the number of test commands is equal to the total number of function test commands in the sent test command sequence, the first MCU feedbacks all the function test results in the result sending buffer to the test host and clears the result sending buffer.

[0071] In implementation, when receiving the test command sequence sent by the test host, the first MCU can record the total number of function test commands in the test command sequence. In this way, when detecting that there are function test results stored in the result sending buffer, the first MCU can first judge the number of test commands corresponding to the function test results. When the number of test commands is equal to the total number of the above function test commands, the first MCU can feedback all the function test results in the result sending buffer to the test host and at the same time clear the result sending buffer.

[0072] It is worth mentioning that if the test host sends multiple test command sequences to the first MCU successively during a test, the first MCU can store the first test command sequence in the command receiving buffer. The second MCU can delete the read function test commands in real time when reading the function test commands from the command receiving buffer. After the first MCU detects that the command receiving buffer is emptied, it can continue to store the next test command sequence.

[0073] Optionally, when testing multiple SPI NAND FLASH chips simultaneously, the function test results of the multiple SPI NAND FLASH chips can be jointly stored in the result sending buffer. Correspondingly, the processing of step 205 can be changed as follows: when the first MCU detects that there are function test results stored in the result sending buffer, it judges the number of function test results corresponding to the identification information of each SPI NAND FLASH chip; when the number of function test results is equal to the total number of function test commands in the sent test command sequence, the first MCU feedbacks the function test results corresponding to the identification information in the result sending buffer to the test host.

[0074] In implementation, after generating the functional test result, the SPI controller can add the identification information of the SPI NAND FLASH chip to the functional test result. This identification information can be used to uniquely identify the SPI NAND FLASH chip to which the SPI controller belongs, and can be the chip number, chip model, etc. Based on this, when the first MCU detects that there is a functional test result in the result sending buffer, it can first judge the number of functional test results corresponding to the identification information of each SPI NAND FLASH chip. When the number of functional test results of a certain SPI NAND FLASH chip is equal to the total number of functional test commands in the corresponding test command sequence, the first MCU can then feedback the functional test result corresponding to the identification information of this SPI NAND FLASH chip in the result sending buffer to the test host.

[0075] Optionally, the SPI test platform can repeatedly execute the functional test process that has an exception, and the corresponding processing can be as follows: The second MCU counts the average result feedback duration of each functional test command; when the actual result feedback duration of the target functional test command of the target SPI NAND FLASH chip is greater than the corresponding average result feedback duration, and the difference is greater than the preset threshold, the second MCU resends the target functional test command to the target SPI NAND FLASH chip; after receiving the new functional test result of the target functional test command, the second MCU associates and stores all the functional test results of the target functional test command in the result sending buffer, so that the first MCU can feedback all the functional test results of the target functional test command to the test host at the same time.

[0076] In implementation, when using the SPI test platform to perform functional tests on multiple SPI NAND FLASH chips, the second MCU can count the average result feedback duration of each functional test command, that is, it can start timing from when the functional test command is sent to each SPI controller and end timing after receiving the functional test command feedback from the SPI controller, to obtain the result feedback duration of each SPI controller for the functional test command, and then can obtain the average result feedback duration based on all the result feedback durations of the same functional test command. Therefore, for SPI NAND FLASH chips of the same model, each functional test command can correspond to an average result feedback duration.

[0077] Based on the above processing, taking the target function test command as an example, when it is detected that the actual duration of the result feedback of the target SPI NAND FLASH chip for the target function test command is greater than the average duration of the result feedback of the target function test command, and the difference is greater than the preset threshold, the second MCU can resend the target function test command to the SPI controller of the target SPI NAND FLASH chip. After receiving the new function test result of the target function test command feedback by the target SPI NAND FLASH chip, the second MCU can store the new function test result in the result sending buffer and establish an association relationship with the original function test result of the target function test command feedback by the target SPI NAND FLASH chip. Furthermore, when the first MCU sends the function test result to the test host, it can send both the original function test result and the new function test result of the target function test command feedback by the target SPI NAND FLASH chip.

[0078] It is worth mentioning that if the result feedback duration of the new function test result still differs greatly from the average result feedback duration, the second MCU can resend the target function test command and continue to associate and store the corresponding function test result in the result sending buffer until the result feedback duration is close to the average result feedback duration, or the number of times the target function test command is sent reaches the specified value.

[0079] Optionally, based on the setting that the foregoing function test command is in the SPI protocol format, the feedback processing of the function test result can be as follows: After converting the function test command into the TCP / IP protocol format, the first MCU feeds back the function test result to the test host.

[0080] In implementation, the data format conversion function can be configured only on the first MCU to achieve the format conversion between the TCP / IP protocol and the SPI protocol. After obtaining the function test result from the result sending buffer, the first MCU can first convert the function test result into the TCP / IP protocol format, and then can feed back the function test result to the test host through the TCP / IP protocol. It can be understood that the SPI test platform uses the TCP / IP protocol to interact with the test host and uses the SPI protocol for data flow internally. On the one hand, it can achieve the rapid transmission of a large amount of data such as test command sequences based on the TCP / IP protocol, and on the other hand, it can ensure the normal progress of the internal function test of the SPI NAND FLASH chip.

[0081] Using the functional test method for SPI NAND FLASH chips disclosed in this application, the first MCU receives the functional test commands for the SPI NAND FLASH chip sent by the test host; the first MCU stores the functional test commands in the command reception buffer; when the second MCU detects that there are functional test commands stored in the command reception buffer, it sends the functional test commands to the SPI controller; the second MCU receives the functional test results fed back by the SPI controller and stores the functional test results in the result transmission buffer; when the first MCU detects that there are functional test results stored in the result transmission buffer, it feeds back the functional test results to the test host. In this way, by using a dual-core MCU for functional testing, the sending of functional test commands and the feedback of functional test results are independent of each other and do not interfere with each other. There is no need to wait for the functional test results before sending the functional test commands, thereby shortening the time required for the entire test process and improving the test efficiency of the SPI NAND FLASH chip.

[0082] Based on the same technical concept, an embodiment of this application further provides an SPI test platform, which at least includes a first MCU, a second MCU, a command reception buffer, and a result transmission buffer. The second MCU supports the QSPI protocol, where:

[0083] The first MCU is used to receive the functional test commands for the SPI NAND FLASH chip sent by the test host and store the functional test commands in the command reception buffer;

[0084] The second MCU is used to send the functional test commands to the SPI controller when it detects that there are functional test commands stored in the command reception buffer;

[0085] The second MCU is further used to receive the functional test results fed back by the SPI controller and store the functional test results in the result transmission buffer;

[0086] The first MCU is further used to feed back the functional test results to the test host when it detects that there are functional test results stored in the result transmission buffer.

[0087] Optionally, the first MCU is specifically used for:

[0088] Receiving a test command sequence sent by the test host based on the TCP / IP protocol, where the test command sequence includes at least one functional test command for the SPI NAND FLASH chip.

[0089] Optionally, the first MCU is specifically used for:

[0090] When it is detected that the result sending cache stores function test results, determine the number of test commands corresponding to the function test results;

[0091] When the number of test commands is equal to the total number of function test commands in the sent test command sequence, feedback all function test results in the result sending cache to the test host, and clear the result sending cache.

[0092] Optionally, the function test results carry identification information of the SPI NAND FLASH chip;

[0093] Optionally, the first MCU is specifically used for:

[0094] When it is detected that the result sending cache stores function test results, determine the number of function test results corresponding to the identification information of each SPI NAND FLASH chip;

[0095] When the number of function test results is equal to the total number of function test commands in the sent test command sequence, feedback the function test results corresponding to the identification information in the result sending cache to the test host.

[0096] Optionally, the second MCU is further used for:

[0097] Statistically calculate the average result feedback duration of each function test command;

[0098] When the actual result feedback duration of the target function test command of the target SPI NAND FLASH chip is greater than the corresponding average result feedback duration, and the difference is greater than the preset threshold, resend the target function test command to the target SPI NAND FLASH chip;

[0099] After receiving the new function test result of the target function test command, associatively store all function test results of the target function test command in the result sending cache, so that the first MCU simultaneously feedbacks all function test results of the target function test command to the test host.

[0100] Optionally, the first MCU is specifically used for:

[0101] After converting the function test command into the SPI protocol format, store the function test command in the command receiving cache;

[0102] After converting the function test command into the TCP / IP protocol format, feedback the function test result to the test host.

[0103] Optionally, the second MCU is further used for:

[0104] Statistically calculate the data length in the command reception buffer and the total amount of data of the function test commands that have been sent;

[0105] When the total amount of data is equal to the data length, send a cache clearing instruction to the command reception buffer.

[0106] The embodiment of the present application also provides a control chip, which includes a processor and a memory. At least one instruction, at least one program, a code set or an instruction set is stored in the memory. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the function test method applied to the SPI NAND FLASH chip as described in steps 201 - 205.

[0107] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk or an optical disc, etc.

[0108] The above are all the preferred embodiments of the present application. The protection scope of the present application is not limited accordingly. Any feature disclosed in this specification (including the abstract and the drawings), unless specifically described, can be replaced by other equivalent or similar-purpose alternative features. That is, unless specifically described, each feature is only an example in a series of equivalent or similar features.

Claims

1. A functional test method applied to an SPI NAND FLASH chip, characterized in that The method is applied to an SPI test platform, which at least includes a first MCU, a second MCU, an SPI controller located in an SPI NAND FLASH chip, a command receiving buffer, and a result sending buffer. The second MCU supports the QSPI protocol. The method includes: The first MCU receives a functional test command of an SPI NAND FLASH chip sent by a test host; The first MCU stores the functional test command in the command receiving buffer; When the second MCU detects that there is a functional test command in the command receiving buffer, it sends the functional test command to the SPI controller; The second MCU receives the functional test result fed back by the SPI controller and stores the functional test result in the result sending buffer; When the first MCU detects that there is a functional test result in the result sending buffer, it feeds back the functional test result to the test host.

2. The method according to claim 1, wherein The first MCU receives a functional test command of an SPI NAND FLASH chip sent by a test host, including: The first MCU receives a test command sequence sent by a test host based on the TCP / IP protocol, and the test command sequence includes at least one functional test command for the SPI NAND FLASH chip.

3. The method according to claim 2, wherein When the first MCU detects that there is a functional test result in the result sending buffer, it feeds back the functional test result to the test host, including: When the first MCU detects that there is a functional test result in the result sending buffer, it judges the number of test commands corresponding to the functional test result; When the number of test commands is equal to the total number of functional test commands in the sent test command sequence, the first MCU feeds back all the functional test results in the result sending buffer to the test host and clears the result sending buffer.

4. The method according to claim 2, characterized in that, The functional test result carries identification information of the SPI NAND FLASH chip; When the first MCU detects that there is a functional test result in the result sending buffer, it feeds back the functional test result to the test host, including: When the first MCU detects that there is a functional test result in the result sending buffer, it judges the number of functional test results corresponding to the identification information of each SPI NAND FLASH chip; When the number of functional test results is equal to the total number of functional test commands in the sent test command sequence, the first MCU feeds back the functional test results corresponding to the identification information in the result sending buffer to the test host.

5. The method according to claim 4, wherein The method further includes: The second MCU counts the average result feedback duration of each functional test command; When the actual result feedback duration of the target functional test command of the target SPI NAND FLASH chip is greater than the corresponding average result feedback duration and the difference is greater than a preset threshold, the second MCU resends the target functional test command to the target SPI NAND FLASH chip; After receiving the new function test results of the target function test command, the second MCU associates and stores all the function test results of the target function test command in the result sending buffer, so that the first MCU can feedback all the function test results of the target function test command to the test host at the same time.

6. The method according to claim 2, wherein The first MCU stores the function test command in the command receiving buffer, including: After the first MCU converts the function test command into the SPI protocol format, it stores the function test command in the command receiving buffer; The feedback of the function test results to the test host includes: After the first MCU converts the function test command into the TCP / IP protocol format, it feedbacks the function test results to the test host.

7. The method according to claim 1, characterized in that, When the second MCU detects that there is a function test command in the command receiving buffer, after sending the function test command to the SPI controller, it further includes: The second MCU counts the data length in the command receiving buffer and the total amount of data of the sent function test commands; When the total amount of data is equal to the data length, the second MCU sends a cache clearing instruction to the command receiving buffer.

8. An SPI test platform, characterized in that, The SPI test platform at least includes a first MCU, a second MCU, an SPI controller located in the SPI NAND FLASH chip, a command receiving buffer, and a result sending buffer. The second MCU supports the QSPI protocol, where: The first MCU is used to receive the function test command for the SPI NAND FLASH chip sent by the test host and store the function test command in the command receiving buffer; The second MCU is used to send the function test command to the SPI controller when it detects that there is a function test command in the command receiving buffer; The second MCU is also used to receive the function test results feedback by the SPI controller and store the function test results in the result sending buffer; The first MCU is also used to feedback the function test results to the test host when it detects that there are function test results in the result sending buffer.

9. A control chip, characterized in that, The control chip includes a processor and a memory. At least one instruction, at least one program, a code set, or an instruction set is stored in the memory. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the processing of the first MCU or the second MCU in the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, At least one instruction, at least one program, a code set, or an instruction set is stored in the storage medium. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the processing of the first MCU or the second MCU in the method according to any one of claims 1-7.

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