Array substrate, manufacturing method thereof, and display panel

Abstract

The present application provides an array substrate, a manufacturing method of the array substrate, and a display panel. The array substrate includes: a substrate, including a display area and a non-display area; a first thin-film transistor disposed in the display area on the substrate, the first thin-film transistor having a first active layer; a second thin-film transistor disposed in the non-display area on the substrate, the second thin-film transistor having a second active layer, and the mobility of the first active layer being less than that of the second active layer; a third thin-film transistor disposed in the display area on the substrate, the third thin-film transistor and the first thin-film transistor being spaced apart on the substrate, the third thin-film transistor having a third active layer, and the mobility of the first active layer being less than that of the third active layer. The circuit in the array substrate of the present application has relatively high stability while meeting performance requirements, and is conducive to the realization of high resolution and narrow borders.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular, to an array substrate, a manufacturing method of the array substrate, and a display panel. Background Art

[0002] Organic light emitting diode (OLED) has a series of advantages such as wide viewing angle, wide color gamut, high contrast ratio, low power consumption, and foldable / flexible, etc., and is highly competitive and promising in the new generation display technology. Among them, the active matrix organic light emitting diode (AMOLED) technology is one of the key development directions of the current display technology.

[0003] Compared with amorphous silicon, as an amorphous oxide semiconductor thin film in a thin film transistor (TFT), the carrier mobility of metal oxide is 20 - 30 times that of amorphous silicon, which can greatly improve the charge and discharge rate of the TFT to the pixel electrode, improve the response speed of the pixel, achieve a faster refresh rate, and at the same time, the faster response also greatly improves the row scanning rate of the pixel, making it possible to produce large-size ultra-high resolution panels. Therefore, the thin film transistor of metal oxide is more competitive in the field of active matrix organic light emitting diode (AMOLED). However, the higher the mobility of the metal oxide thin film transistor, the worse its stability often is.

[0004] In addition, compared with low-temperature polycrystalline silicon, metal oxide still has certain deficiencies. Especially at present, the mobility of metal oxide is relatively low. Therefore, to achieve the required current, a relatively large transistor size is often needed, which occupies a large space and is not conducive to realizing a narrow border for panel design. Summary of the Invention

[0005] The present application provides an array substrate, a manufacturing method of the array substrate, and a display panel to solve the problem that it is difficult for an array substrate to balance stability and a narrow border.

[0006] On the one hand, the present application provides an array substrate, including:

[0007] A substrate, including a display area and a non-display area;

[0008] A first thin film transistor, disposed in the display area on the substrate, the first thin film transistor having a first active layer;

[0009] A second thin film transistor, disposed in the non-display area on the substrate, the second thin film transistor having a second active layer, and the mobility of the first active layer is less than the mobility of the second active layer;

[0010] A third thin-film transistor is disposed in a display area on the substrate. The third thin-film transistor and the first thin-film transistor are spaced apart on the substrate. The third thin-film transistor has a third active layer, and the mobility of the first active layer is less than that of the third active layer.

[0011] In a possible implementation manner of the present application, the second active layer and the third active layer are disposed on the same layer;

[0012] The first active layer includes a first metal oxide film, the second active layer includes a second metal oxide film, the third active layer includes a third metal oxide film, and the materials of the second metal oxide film and the third metal oxide are the same.

[0013] In a possible implementation manner of the present application, the carrier mobility range of the first metal oxide film is 5 cm2 / (V·s) - 20 cm2 / (V·s), and the carrier mobility range of the second metal oxide film is 20 cm2 / (V·s) - 100 cm2 / (V·s).

[0014] In a possible implementation manner of the present application, the first active layer is a single-layer structure;

[0015] The second active layer is a double-layer structure. The second active layer further includes the first metal oxide film, and the second metal oxide film is disposed on the first metal oxide film; and / or,

[0016] The third active layer is a double-layer structure. The third active layer further includes the first metal oxide film, and the third metal oxide film is disposed on the first metal oxide film.

[0017] In a possible implementation manner of the present application, the first metal oxide film includes an indium-containing metal oxide, and the total atomic percentage content of indium in the indium-containing metal oxide ranges from 10% to 50%;

[0018] The second metal oxide film includes an indium-containing metal oxide, and the total atomic percentage content of indium in the indium-containing metal oxide ranges from 50% to 80%.

[0019] In a possible implementation manner of the present application, the first metal oxide film, the second metal oxide film, or the third metal oxide includes at least one of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.

[0020] On the other hand, the present application further provides a method for manufacturing an array substrate, including:

[0021] A substrate is provided, and the substrate includes a display area and a non-display area;

[0022] A second active layer of a second thin film transistor is formed in the non-display area on the substrate, and a third active layer of a third thin film transistor is formed in the display area on the substrate;

[0023] A first active layer of a first thin film transistor is formed in the display area on the substrate. The third thin film transistor and the first thin film transistor are arranged at intervals on the substrate, and the mobility of the first active layer is less than the mobilities of the third active layer and the second active layer.

[0024] In a possible implementation manner of the present application, the materials of the second active layer and the third active layer have a greater tolerance to an acidic etching solution than the first active layer.

[0025] In a possible implementation manner of the present application, after the step of forming a second active layer of a second thin film transistor in the non-display area on the substrate and forming a third active layer of a third thin film transistor in the display area on the substrate, the method further includes:

[0026] Annealing the second active layer and the third active layer.

[0027] On the other hand, the present application further provides a display panel including the array substrate.

[0028] An array substrate, a manufacturing method of the array substrate, and a display panel provided by the present application, by arranging a first thin film transistor having a first active layer and a third thin film transistor having a third active layer in the display area of the substrate of the array substrate and arranging a second thin film transistor having a second active layer in the non-display area, and by setting the mobility of the first active layer to be less than the mobilities of the second active layer and the third active layer, the performance requirements of circuit designs in different regions can be met. For circuit designs with higher stability requirements in the display area, the first thin film transistor is used as a switching device, and thus the circuit in the display area has relatively high stability while meeting the performance requirements; for circuit designs with higher mobility requirements in the non-display area, the second thin film transistor is used as a switching device, and thus the switching device in the non-display area has relatively high mobility, so that the size of the corresponding switching device can be reduced, which is beneficial to the realization of a narrow border while ensuring high performance of the circuit in the non-display area. For circuits with higher resolution designs in the display area, the third thin film transistor is used as a switching device, and thus the switching device in the display area has relatively high mobility, so that the size of the corresponding switching device can be reduced, which is beneficial to improving the high resolution of the display panel. Description of the Drawings

[0029] Combined with the accompanying drawings, through a detailed description of the specific embodiments of the present application, the technical solutions and other beneficial effects of the present application will become obvious.

[0030] Figure 1 It is a schematic structural diagram of an array substrate provided by an embodiment of the present application.

[0031] Figure 2 It is a schematic structural diagram of an array substrate provided by another embodiment of the present application.

[0032] Figure 3 It is a schematic flow diagram of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0033] Figure 4 It is a schematic flow diagram of a method for manufacturing an array substrate provided by another embodiment of the present application. Specific Embodiments

[0034] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0035] In the description of the present application, it should be understood that the features of the terms "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically defined. It should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, they may be directly connected or indirectly connected through an intermediate medium, and may be the internal connection or interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0036] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0037] Embodiments of the present application provide an array substrate, a manufacturing method of the array substrate, and a display panel, which will be introduced in detail below.

[0038] Please refer to Figure 1 - Figure 2 , embodiments of the present application provide an array substrate, which includes a substrate 10, a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.

[0039] The substrate 10 includes a display area 101 and a non-display area 102. The display area 101 is an area for displaying images, and the non-display area 102 is an area for arranging pixel driving circuits. For example, the pixel driving circuit can be a gate driving circuit (Gate on Array, GOA), etc. Specifically, in the embodiments of the present application, the non-display area 102 can be the border area of the array substrate, and the border area can be located on at least one side of the display area 101. Exemplarily, the border area can be located on opposite sides of the display area 101, or the border area can enclose the display area 101 on all four sides, etc.

[0040] Among them, the first thin film transistor T1 is disposed in the display area 101 on the substrate 10, and the first thin film transistor T1 has a first active layer 110. Since the width of the thin film transistor does not need to be reduced in the display area 101, therefore, the active layer of the first thin film transistor T1 in the display area 101, that is, the first active layer 110, can still use a semiconductor material with a lower mobility, so as to ensure that the first active layer 110 can have better stability.

[0041] The third thin film transistor T3 is disposed in the display area 101 on the substrate 10. The third thin film transistor T3 and the first thin film transistor T1 are spaced apart on the substrate 10. The third thin film transistor T3 has a third active layer 310, and the mobility of the first active layer 110 is less than the mobility of the third active layer 310.

[0042] The second thin-film transistor T2 is disposed in the non-display area 102 on the substrate 10. The second thin-film transistor T2 has a second active layer 210. Among them, the carrier mobility of the first active layer 110 is less than that of the second active layer 210. In the embodiment of the present application, by using a semiconductor material with high mobility for the second active layer 210, after the mobility of the second thin-film transistor T2 in the non-display area 102 is improved, the channel width of the second thin-film transistor T2 can be reduced, so that the border of the array substrate can be made narrower, which is beneficial to the realization of a narrow border of the array substrate. Exemplarily, when the channel length of the second thin-film transistor T2 remains unchanged, assuming that the channel length of the second thin-film transistor T2 is L = 6.5um, after the mobility of the second active layer 210 is improved, the channel width W = 2000um of the second thin-film transistor T2 can be reduced to the channel width W = 1000um.

[0043] In the embodiment of the present application, the first thin-film transistor T1 can be a driving thin-film transistor in the pixel driving circuit for driving the display area 101 to emit light in the display area 101. The third thin-film transistor T3 can be a switching thin-film transistor in the pixel driving circuit. The second thin-film transistor T2 can be a thin-film transistor in the GOA circuit in the non-display area 102.

[0044] In the embodiment of the present application, the first thin-film transistor T1 further includes a light-shielding layer 120. Among them, the light-shielding layer 120 is made of an opaque metal material. The light-shielding layer 120 is disposed between the substrate 10 and the first active layer 110, and is used to block the first active layer 110 of the first thin-film transistor T1, which helps to eliminate the interference of external ambient light on the first active layer 110, so as to achieve a good display effect. Among them, the light-shielding layer 120 can adopt a single-layer metal structure, such as metals or metal alloys such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Ti, etc., or a metal stack structure, such as a Cu / Mo or Cu / MoTi metal stack. Among them, in addition to playing a role in light shielding, the light-shielding layer 120 can also act as a wiring, increasing the wiring design space of the circuit design.

[0045] Exemplarily, when the channel length of the third thin-film transistor T3 remains unchanged, assuming that the channel length of the third thin-film transistor T3 is L = 6.5um, after the mobility of the third active layer 310 is improved, the channel width W = 20um of the third thin-film transistor T3 can be reduced to the channel width W = 10um.

[0046] It should be noted that in the array substrate of this embodiment, thin-film transistors such as the third thin-film transistor T3, the first thin-film transistor T1, and the second thin-film transistor T2 can be top-gate thin-film transistors or bottom-gate thin-film transistors, and no specific limitation is made here.

[0047] In the array substrate according to the embodiment of the present application, a first thin-film transistor T1 having a first active layer 110, a third thin-film transistor T3 having a third active layer 310 are disposed in the display area 101 of the substrate 10, and a second thin-film transistor T2 having a second active layer 210 is disposed in the non-display area 102. By setting the mobility of the first active layer 110 to be less than the mobilities of the second active layer 210 and the third active layer 310, the performance requirements of circuit designs in different regions can be met. For the circuit design with relatively high stability requirements in the display area 101, the first thin-film transistor T1 is used as the switching device. Further, the circuit in the display area 101 has relatively high stability while meeting the performance requirements. For the circuit design with relatively high mobility requirements in the non-display area 102, the second thin-film transistor T2 is used as the switching device. Further, the switching device in the non-display area 102 has relatively high mobility, so that the size of the corresponding switching device can be reduced, which is beneficial to the realization of a narrow border while ensuring high performance of the circuit in the non-display area 102. In the circuit design with relatively high resolution in the display area 101, the third thin-film transistor T3 is used as the switching device. Further, the switching device in the display area 101 has relatively high mobility, so that the size of the corresponding switching device can be reduced, which is beneficial to improving the high resolution of the display panel.

[0048] In some embodiments, the second active layer 210 of the second thin-film transistor T2 and the third active layer 310 of the third thin-film transistor T3 are disposed in the same layer. Specifically, the first active layer 110 includes a first metal oxide thin film, the second active layer 210 includes a second metal oxide thin film, and the third active layer 310 includes a third metal oxide thin film. Among them, the materials of the second metal oxide thin film and the third metal oxide thin film are the same. In the embodiment of the present application, the materials of the first metal oxide thin film and the second metal oxide thin film or the third metal oxide thin film are all different. By making the materials of the metal oxide thin films of the second active layer 210 and the third active layer 310 the same, while the first active layer 110 uses a different type of metal oxide thin film material from the second active layer 210 or the third active layer 310, the mobility of the first active layer 110 can be designed to be different from the mobilities of the second active layer 210 and the third active layer 310, so that different circuit designs can be selected according to the performance requirements of circuit designs in different regions.

[0049] It should be noted that the so-called same-layer setting in the embodiment of the present application means that two or more structures are formed through the same deposition process and patterned through the same patterning process, and their materials can be the same. Exemplarily, the materials of the precursors for forming the structures of the second active layer 210 and the third active layer 310 disposed in the same layer are the same, and the finally formed materials can also be the same.

[0050] In some embodiments, the carrier mobility of the first metal oxide film ranges from 5 cm 2 / (V·s) to 20 cm 2 / (V·s), and the carrier mobility of the second metal oxide film ranges from 20 cm 2 / (V·s) to 100 cm 2 / (V·s). Among them, the second active layer 210 and the third active layer 310 can adopt the second metal oxide film with the same carrier mobility, or can adopt the second metal oxide film with different carrier mobilities. Exemplarily, the carrier mobility of the second active layer 210 and the carrier mobility of the second active layer 210 can both be 25 cm 2 / (V·s), or the carrier mobility of the second active layer 210 can be 25 cm 2 / (V·s), and the carrier mobility of the third active layer 310 can be 30 cm 2 / (V·s), etc. This embodiment does not make any restrictions on this.

[0051] In some embodiments, as Figure 2 shown, the first active layer 110 is a single-layer structure, the second active layer 210 and / or the third active layer 310 are double-layer structures, and the second active layer 210 and / or the third active layer 310 further include a first metal oxide film. Specifically, when the second active layer 210 is a double-layer structure, the second metal oxide film is disposed on the first metal oxide film; when the third active layer 310 is a double-layer structure, the third metal oxide film is disposed on the first metal oxide film. Exemplarily, in the embodiments of the present application, it can be that only the first active layer 110 adopts a single-layer structure, and both the second active layer 210 and the third active layer 310 adopt double-layer structures, or it can be that both the first active layer 110 and the second active layer 210 adopt single-layer structures, and only the third active layer 310 adopts a double-layer structure, or it can be that both the first active layer 110 and the third active layer 310 adopt single-layer structures, and only the second active layer 210 adopts a double-layer structure.

[0052] In the embodiments of the present application, in order to ensure the stability of the material of the first active layer 110, therefore, in the preparation process, the first active layer 110 is formed after the second active layer 210 or the third active layer 310. Therefore, when subsequently preparing the first active layer 110, in the regions corresponding to the second active layer 210 and the third active layer 310, the first metal oxide film material can be used to form a double-layer active layer structure on the basis of the second metal oxide film for the second active layer 210 and the third active layer 310, so that both the second active layer 210 and the third active layer 310 form a double-stack layer structure of the first metal oxide film and the second metal oxide film.

[0053] In some embodiments, the first metal oxide film includes an indium-containing metal oxide, and the total atomic percentage content of indium in the indium-containing metal oxide ranges from 10% to 50%. Since the first thin film transistor T1 corresponding to the first metal oxide film requires relatively high stability, an indium-containing metal oxide with a relatively low total atomic percentage content of indium is selected, so that the first thin film transistor T1 is not easily damaged during operation, which is conducive to ensuring that the first thin film transistor T1 made of the metal oxide can work properly, that is, it is conducive to improving the operating stability of the first thin film transistor T1.

[0054] The second metal oxide film includes an indium-containing metal oxide, and the total atomic percentage content of indium in the indium-containing metal oxide ranges from 50% to 80%. Since the second thin film transistor T2 corresponding to the second metal oxide film requires relatively high mobility, an indium-containing metal oxide with a relatively high total atomic percentage content of indium is selected. After the mobility of the thin film transistor in the GOA region of the non-display area 102 corresponding to the second thin film transistor T2 is improved, the width of the thin film transistor in the GOA region can be reduced, so that the border of the substrate 10 can be made narrower, realizing a narrow border of the display substrate.

[0055] In some embodiments, the first metal oxide film, the second metal oxide film, or the third metal oxide film includes at least one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (ITZO), and indium gallium zinc tin oxide (IGTZO). Exemplarily, the material types among the first metal oxide film, the second metal oxide film, and the third metal oxide film can be the same or different. For example, both the first metal oxide film and the second metal oxide film can adopt indium gallium zinc oxide, and indium gallium zinc oxide has good stability, or the first metal oxide film can adopt indium zinc tin oxide while the second metal oxide film can adopt indium gallium zinc tin oxide. It should be noted that the material types mentioned in the embodiments of the present application refer to the same elemental composition, but the proportion of each elemental component in the first metal oxide film and the second metal oxide film or the first metal oxide film and the third metal oxide film is different. Exemplarily, when both the first metal oxide film and the second metal oxide film adopt indium gallium zinc oxide, the proportion of indium atoms in the indium gallium zinc oxide in the first metal oxide film and the second metal oxide film is different.

[0056] The thickness of the second metal oxide film can be 100 - 1000 angstroms, so as to not only improve the mobility of the second thin film transistor T2 in the GOA region, but also ensure the stability of the performance of the thin film transistor in the GOA region.

[0057] Please refer toFigure 3 In order to better implement the array substrate of the present application, an embodiment of the present application further provides a method for manufacturing an array substrate, including the following steps S100 - S300:

[0058] S100. Provide a substrate 10, where the substrate 10 includes a display area 101 and a non - display area 102.

[0059] Among them, the substrate 10 can be a flexible substrate 10 or a rigid substrate 10. The flexible substrate 10 can be polyimide, and the rigid substrate 10 can be a glass substrate or a quartz substrate, etc. The material of the substrate 10 is not specifically limited herein.

[0060] S200. Form a second active layer 210 of the second thin - film transistor T2 in the non - display area 102 on the substrate 10 and form a third active layer 310 of the third thin - film transistor T3 in the display area 101 on the substrate 10.

[0061] The second active layer 210 is formed by patterning a second metal - oxide thin film, and the third active layer 310 is formed by patterning a third metal - oxide thin film. In the embodiment of the present application, the second active layer 210 and the third active layer 310 are formed of the same material in the same lithography process. Specifically, the materials of the second metal - oxide thin film and the third oxide thin film are the same, which can be IGZO, IZTO, IGZTO, etc., and the thickness can be 100 - 1000 angstroms.

[0062] The deposition of the materials of the second metal - oxide thin film and the third metal - oxide thin film can be carried out using existing deposition power and pressure, but the content of In atoms in the second metal - oxide and the third metal - oxide needs to be controlled to be between 50% - 80%, so as to ensure that the second thin - film transistor T2 and the third thin - film transistor T3 have a higher mobility.

[0063] S300. Form a first active layer 110 of the first thin - film transistor T1 in the display area 101 on the substrate 10. The third thin - film transistor T3 and the first thin - film transistor T1 are arranged at intervals on the substrate 10, and the mobility of the first active layer 110 is less than the mobilities of the third active layer 310 and the second active layer 210.

[0064] When forming the first active layer 110, first, a deposition process is adopted to form a first metal oxide thin film over the entire surface on which the second active layer 210 and the third active layer 310 are formed. Then, a wet etching process is used to pattern the first metal oxide thin film material on the second active layer 210 and the third active layer 310, thereby forming the patterned first active layer 110. Among them, in the process of patterning the first metal oxide thin film material, the first metal oxide thin film material corresponding to the upper parts of the second active layer 210 and the third active layer 310 can be retained or removed. It can be understood that when the first metal oxide thin film material corresponding to the upper parts of the second active layer 210 and the third active layer 310 is retained, the second active layer 210 and the third active layer 310 form a double-layer active layer structure, and when the first metal oxide thin film material corresponding to the upper parts of the second active layer 210 and the third active layer 310 is removed, the second active layer 210 and the third active layer 310 form a single-layer active layer structure.

[0065] Among them, the material of the first active layer 110 can be a first metal oxide thin film, such as IGZO, IZTO, IGZTO, etc., and the thickness can be 100 - 1000 angstroms. The first active layer 110 is formed by patterning the first metal oxide thin film. The deposition of the first metal oxide thin film material can be carried out using existing deposition power and pressure, but the content of In atoms in the first metal oxide needs to be controlled between 10% - 50% so as not to cause the mobility of the first thin film transistor T1 to increase too little, and at the same time, it also has good stability.

[0066] In the steps of preparing the first active layer 110, the second active layer 210, and the third active layer 310, since the second active layer 210 and the third active layer 310 need to use semiconductor materials with better stability, making the first active layer 110 first and then making the second active layer 210 can ensure that the material of the second active layer 210 does not need to be interfered by the active layer manufacturing process again, thereby avoiding the damage to the temperature resistance of the material of the second active layer 210 caused by gas atmosphere or particle residue, etc.

[0067] The manufacturing method of the array substrate according to the embodiments of the present application fabricates the first thin-film transistor T1 with the first active layer 210, the third thin-film transistor T3 with the third active layer 310 in the display area 101 of the substrate 10, and the second thin-film transistor T2 with the second active layer 210 in the non-display area 102. By setting the mobility of the first active layer 110 to be less than that of the second active layer 210 and the third active layer 310, the performance requirements of circuit designs in different regions can be met. For the circuit design in the display area 101 with higher stability requirements, the first thin-film transistor T1 is used as the switching device. Thus, the circuit in the display area 101 has relatively high stability while meeting the performance requirements. For the circuit design in the non-display area 102 with higher mobility requirements, the second thin-film transistor T2 is used as the switching device. Thus, the switching device in the non-display area 102 has relatively high mobility, which can reduce the size of the corresponding switching device, ensuring high performance of the circuit in the non-display area 102 and facilitating the realization of a narrow border. In the circuit design with higher resolution in the display area 101, the third thin-film transistor T3 is used as the switching device. Thus, the switching device in the display area 101 has relatively high mobility, which can reduce the size of the corresponding switching device, facilitating the improvement of the high resolution of the display panel.

[0068] In some embodiments, the materials of the second active layer 210 and the third active layer 310 have a greater tolerance to the acidic etching solution than the first active layer 110.

[0069] Among them, the etching process of the active layer is a wet etching process. The etching solution used in the wet etching process can be an oxalic acid-based etching solution or a mixed solution of sulfuric acid, acetic acid, and phosphoric acid. Among them, the acidity of the etching solution for etching the first active layer 110 is greater than that of the etching solution for etching the second active layer 210 and the third active layer 310.

[0070] In the embodiments of the present application, since the active layer is fabricated by depositing a metal oxide thin film layer over the entire surface and then performing patterning, and the formation steps of the second active layer 210 and the third active layer 310 are prior to those of the first active layer 110. When forming the first active layer 110, first, a deposition process is employed to form the first metal oxide thin film over the entire surface on the second active layer 210 and the third active layer 310, and then the first metal oxide thin film material on the second active layer 210 and the third active layer 310 is etched away through a wet etching process, thereby forming the patterned first active layer 110. During this process, in terms of the material selection of the second metal oxide thin film and the third metal oxide thin film, by setting the acid etching solution tolerance of the materials of the second active layer 210 and the third active layer 310 to be greater than that of the first active layer 110, when etching the first active layer 110 with an acid etching solution, the second active layer 210 and the third active layer 310 can be prevented from being corroded and damaged by the etching process, which is conducive to ensuring the normal operation of the second thin film transistor T2 and the third thin film transistor T3, and is conducive to improving the manufacturing yield of the array substrate of the present application.

[0071] In some embodiments, in step S200, the second active layer 210 of the second thin film transistor T2 is formed in the non-display area 102 on the substrate 10, and the third active layer 310 of the third thin film transistor T3 is formed in the display area 101 on the substrate 10. After that, step S201 is further included:

[0072] S201. Anneal the second active layer 210 and the third active layer 310.

[0073] Among them, since the formation steps of the second active layer 210 and the third active layer 310 are prior to those of the first active layer 110, during the preparation process of the first active layer 110, by annealing the second active layer 210 and the third active layer 310, the second metal oxide thin film in the second active layer 210 and the third metal oxide thin film in the third active layer 310 are formed into stable semiconductor materials, which can prevent the second active layer 210 and the third active layer 310 from being corroded and damaged by the etching process, which is conducive to ensuring the normal operation of the second thin film transistor T2 and the third thin film transistor T3, and is conducive to improving the manufacturing yield of the array substrate of the present application.

[0074] In some embodiments, after S100, providing a substrate 10, the following steps S101 - S102 may further be included:

[0075] S101. Deposit a layer of light-shielding metal and form a light-shielding layer 120 by a patterning process.

[0076] Among them, the light-shielding layer 120 can adopt a single-layer metal structure, such as metals or metal alloys like Cu, Al, Ag, Mo, Cr, Nd, Ni, Ti, etc., or can adopt a metal laminate structure, such as a Cu / Mo or Cu / MoTi metal laminate. Among them, in addition to playing a role in blocking light, the light-shielding layer 120 can also act as a wiring line to increase the wiring design space of the circuit design.

[0077] S102. Form a buffer layer 11.

[0078] The buffer layer 11 can adopt oxides, nitrides or oxynitrides, such as a combination of one or more insulating materials in SiNx, SiOx, SiONx. The buffer layer 11 can prevent ions in the substrate 10 from moving into the thin-film transistor and affecting the performance of the thin-film transistor. The thickness of the buffer layer 11 can be 300 - 10000 angstroms.

[0079] As Figure 4 shown, among them, after step S300 of forming the first active layer 110 of the first thin-film transistor T1 in the display area 101 on the substrate 10, the following steps S401 - S405 can also be included;

[0080] S401. Form a gate insulating layer 12 and a gate layer 13 on the first active layer 110 and the second active layer 210.

[0081] The gate insulating layer 12 (GI) can be a single-layer or multi-layer structure formed of SiOx or SiNx. The thickness of the gate insulating layer 12 can be 1000 - 3000 angstroms.

[0082] The gate layer 13 can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The gate metal layer 7 can be a single-layer structure or a multi-layer structure, such as multi-layer structures like Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. The thickness of the gate layer 13 can be 2000 - 10000 angstroms.

[0083] S402. Perform a patterning process on the gate insulating layer 12 and the gate layer 13.

[0084] Adopt a single yellow light process. First, etch the pattern of the gate layer 13, and then use the pattern of the gate layer 13 for self-alignment to etch the gate insulating layer 12. The gate insulating layer 12 only exists below the film layer with the pattern of the gate layer 13, and the gate insulating layer 12 in other places is etched away. Then, perform a full-surface plasma treatment on the gate layer 13 and the gate insulating layer 12. As a result, for the semiconductor metal oxide not protected by the gate insulating layer 12 and the gate layer 13 above, its resistance is significantly reduced after treatment, forming an N+ conductor layer. The semiconductor oxide below the gate insulating layer 12 is not treated and retains its semiconductor properties as the channel of the thin film transistor (TFT).

[0085] S403. Form an interlayer insulating layer 14 on the gate layer 13.

[0086] The interlayer insulating layer 14 can be a metal such as Mo, Al, Cu, Ti or its metal alloy, and the thickness of the source-drain layer 15 can be 2000 - 10000 angstroms.

[0087] S404. Form a source-drain layer 15 on the interlayer insulating layer 14.

[0088] The source-drain layer 15 can be a metal such as Mo, Al, Cu, Ti or its metal alloy, and the thickness of the source-drain layer 15 can be 2000 - 8000 angstroms.

[0089] S405. Form a passivation layer 16 on the source-drain layer 15, and define a contact hole 106 in the source-drain layer 15 of the passivation layer 16 corresponding to the third thin film transistor T3.

[0090] It should be noted that in the manufacturing method of the array substrate in this embodiment, the thin film transistor types such as the third thin film transistor T3, the first thin film transistor T1, and the second thin film transistor T2 can be top-gate thin film transistors or bottom-gate thin film transistors. Correspondingly, the positions of the gate layer and the active layer can be adjusted and interchanged according to the specific type of the thin film transistor, and no specific limitation is made here.

[0091] To better implement the array substrate of the present application, an embodiment of the present application further provides a display panel, and the display panel includes the array substrate described above. Since this display panel has the above array substrate, it has all the same beneficial effects, which will not be elaborated in this embodiment. Among them, the embodiment of the present application does not specifically limit the application of the display panel. The display panel can be a display panel applied to any product or component with a display function, such as a handheld device (smartphone, tablet computer, etc.), a wearable device (smart bracelet, wireless earphone, smart watch, smart glasses, etc.), a vehicle-mounted device (navigator, auxiliary reverse system, driving recorder, vehicle-mounted refrigerator, etc.), a virtual reality device, an augmented reality device, a terminal device, etc.

[0092] Specifically, the above display panel can be an organic light emitting diodes (OLED) display panel, a quantum dot light emitting diodes (QLED) display panel, a liquid crystal display (LCD) panel, a MiniLED display panel, etc.

[0093] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. When specifically implemented, the above-mentioned respective units or structures can be implemented as independent entities, or can be arbitrarily combined and implemented as the same or several entities. The specific implementation of the above-mentioned respective units or structures can refer to the method embodiments described above, which will not be elaborated herein.

[0094] The above has introduced in detail an array substrate, a manufacturing method of the array substrate, and a display panel provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the embodiments of the present application. The description of the above embodiments is only used to help understand the technical solutions and their core ideas of the embodiments of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing respective embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the respective embodiments of the present application.

Claims

1. An array substrate, characterized in that, Comprising: A substrate, including a display area and a non-display area; A first thin-film transistor, disposed in the display area on the substrate, the first thin-film transistor having a first active layer; A second thin-film transistor, disposed in the non-display area on the substrate, the second thin-film transistor having a second active layer, the mobility of the first active layer being less than the mobility of the second active layer; And A third thin-film transistor, disposed in the display area on the substrate, the third thin-film transistor and the first thin-film transistor being spaced apart on the substrate, the third thin-film transistor having a third active layer, the mobility of the first active layer being less than the mobility of the third active layer; Wherein, the second active layer and the third active layer are disposed on the same layer; The first active layer is a single-layer structure, and the first active layer includes a first metal oxide film; The second active layer is a double-layer structure, the second active layer includes the first metal oxide film and a second metal oxide film, the first metal oxide film being disposed on the second metal oxide film; The third active layer is a double-layer structure, the third active layer includes the first metal oxide film and a third metal oxide film, the first metal oxide film being disposed on the third metal oxide film; The materials of the second metal oxide film and the third metal oxide are the same.

2. The array substrate according to claim 1, wherein The carrier mobility range of the first metal oxide film is 5 cm 2 / (V·s) - 20 cm 2 / (V·s), and the carrier mobility range of the second metal oxide film is 20 cm 2 / (V·s) - 100 cm 2 / (V·s).

3. The array substrate according to claim 1, characterized in that, The first metal oxide film includes an indium-containing metal oxide, and the total atomic percentage content of indium in the indium metal oxide ranges from 10% to 50%; The second metal oxide film and the third metal oxide include an indium-containing metal oxide, and the total atomic percentage content of indium in the indium metal oxide ranges from 50% to 80%.

4. The array substrate according to claim 3, wherein The first metal oxide film, the second metal oxide film or the third metal oxide includes at least one of indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.

5. A manufacturing method of an array substrate, characterized in that, Comprising: Providing a substrate, the substrate including a display area and a non-display area; Forming a first metal oxide film of the second active layer of the second thin-film transistor in the non-display area on the substrate and forming a first metal oxide film of the third active layer of the third thin-film transistor in the display area on the substrate; Forming a first metal oxide film of the first active layer of the first thin-film transistor, a second metal oxide film of the second active layer, and a third metal oxide film of the third active layer in the display area on the substrate, the materials of the second metal oxide film and the third metal oxide being the same; In the second active layer, the first metal oxide film is located on the second metal oxide film, and in the third active layer, the first metal oxide film is located on the third metal oxide film; the third thin-film transistor and the first thin-film transistor are spaced apart on the substrate, and the mobility of the first active layer is less than the mobilities of the third active layer and the second active layer.

6. The manufacturing method of the array substrate according to claim 5, wherein The acid etching solution tolerance of the materials of the second active layer and the third active layer is greater than that of the first active layer.

7. The manufacturing method of the array substrate according to claim 6, wherein, After the step of forming the second active layer of the second thin film transistor in the non-display area on the substrate and the third active layer of the third thin film transistor in the display area on the substrate, the method further includes: Annealing the second active layer and the third active layer.

8. A display panel, characterized in that, An array substrate including any one of claims 1-4.

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