Control circuit and optimization method of four-switch buck-boost converter

Abstract

The application discloses a control circuit and an optimization method of a four-switch buck-boost converter. The control circuit is used for realizing single-mode soft switching control of the converter and mainly comprises a voltage-controlled current source control circuit, an S4ZVS detection circuit, a voltage loop, a cycle control circuit and a driving signal generation circuit. The method realizes the maximization of the duration of the direct power transmission stage of the converter at different working voltages and loads by optimizing the conversion coefficient of the voltage-controlled current source control circuit, optimizes the conversion efficiency, ensures the soft switching of the converter at light loads by designing the minimum values of the durations of the input energy storage stage and the direct power transmission stage, simultaneously realizes the control of the reduction of the load and the adaptive reduction of the switching frequency, thereby reducing the switching loss at light loads and further optimizing the conversion efficiency of the converter.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of boost-buck converter control, and particularly relates to a control circuit and an optimization method of a four-switch boost-buck converter. BACKGROUND

[0002] The four-switch boost-buck converter is widely used in various power supplies, and has two main control strategies. One is a multi-mode control strategy, that is, according to the relationship between the input and output voltages, the converter is controlled to work in a boost mode (V in , o , a buck mode (V in , V o ) and a boost-buck mode (V in , V o is close), which needs to introduce a hysteresis to avoid frequent switching in different working modes, causing oscillation, and the multi-mode operation also increases the design difficulty of the control loop, and it is difficult to balance the dynamic performance of all working modes. At the same time, the converter works in hard switching, which limits the switching frequency and makes it difficult to improve the power density of the system.

[0003] The second is a single-mode soft-switching control strategy, that is, the control period is divided into an input energy storage stage, a direct power transmission stage, a freewheeling stage and a current clamping stage, and the duration of each stage is adjusted to realize the regulation of the output voltage, which can overcome the above technical problems. However, the control circuit using the above control method has the following problems: 1. When the input and output voltages are greatly different, the turn-off time of the first switch tube may be earlier than that of the fourth switch tube, which makes the converter enter the current clamping stage at the peak value of the energy transmission inductor current, increasing the loss of the converter. 2. When the load is light, the switching frequency is high, the switching loss is high, and the switch tube may not be able to realize ZVS turn-on due to the too short duration of the input energy storage stage and the direct power transmission stage, further increasing the loss and reducing the efficiency of the converter. 3. Under the same working voltage and load, the duration of the input energy storage stage and the direct power transmission stage has multiple combinations, and there is optimization space to improve the conversion efficiency of the converter. SUMMARY

[0004] Objective of this invention: The objective of this invention is to propose a control circuit for a four-switch buck-boost converter. By optimizing the conversion coefficient of the voltage-controlled current source control circuit with the goal of maximizing the duration of the direct power transfer phase, the conversion efficiency of the entire converter is improved. Through optimization of the control logic of the entire control process, the duration of the input energy storage phase and the direct power transfer phase is limited to a minimum, ensuring that the ZVS turn-on condition is met even when the switches are turned on under light load, thus reducing switching losses. Furthermore, it prevents the first switch from turning off before the fourth switch, which would cause a large current to enter the current clamping phase, further reducing converter losses.

[0005] Another objective of this invention is to provide an optimization method for the above-mentioned control circuit.

[0006] Technical Solution: The control circuit of the four-switch buck-boost converter of the present invention adopts a single-mode soft-switching control strategy to control the first, second, and fourth switches of the four-switch buck-boost converter. The single-mode soft-switching control strategy includes a sequentially cyclical input energy storage stage T1, a direct power transfer stage T2, a freewheeling stage T3, and a current clamping stage T4, including: a voltage-controlled current source control circuit, used to control the input voltage V of the buck-boost converter according to the input voltage V. in and output voltage V o Generate voltage-controlled current signal I for controlling the on / off state of the first and second switching transistors. t1 and I t2 Voltage-controlled current signal I t1 and I t2 The S4ZVS detection circuit is used to determine the end time t1 of the input energy storage stage T1 and the end time t2 of the DC power transfer stage T2, respectively; the S4ZVS detection circuit is used to detect the voltage v at the midpoint of the switching bridge arm composed of the third and fourth switching transistors. B This generates a voltage signal v that characterizes whether the ZVS turn-on condition of the fourth switch S4 has been met. ZVS Voltage loop, used to adjust based on input voltage V o With reference voltage V ref The difference output error control signal v er1 Periodic control circuit, used to control the input voltage V in Output voltage V o and error control signal v er1 Generates a voltage-controlled current signal I for adjusting the switching cycle size of the converter. Ts and error control signal v er2 The drive signal generation circuit is used to generate a signal based on the voltage-controlled current signal I. t1 I t2 and I Ts and error control signal v er2 and voltage signal vZVS , generating drive control signals v GS1 , v GS2 , and v GS3 for controlling the first, second, and fourth switching tubes; wherein the conversion coefficient of the voltage-controlled current source control circuit satisfies: the ratio T2 / T1 of the durations of the input energy storage phase T1 and the direct power transmission phase T2 is maximum under different loads.

[0007] Further, the voltage-controlled current source control circuit comprises a sampling network and a voltage-controlled current source circuit composed of operational amplifiers OP11 and OP12, diodes D 11 to D 14 , and voltage-to-current conversion circuits VCCS1 to VCCS4, the sampling network obtains sampling voltages V in1 and V in2 of an input voltage V in according to sampling coefficients k ins1 and k ins2 , and obtains a sampling voltage V o2 of an output voltage V o according to a sampling coefficient k os1 , the non-inverting input terminal of the operational amplifier OP11 and the inverting input terminal of the operational amplifier OP12 are connected to the sampling voltage V ins1 , the inverting input terminal of the operational amplifier OP11 and the non-inverting input terminal of the operational amplifier OP12 are connected to the sampling voltage V os1 , the output terminal of the operational amplifier OP11 is connected to the input terminal of the voltage-to-current conversion circuit VCCS2, the output terminal of the operational amplifier OP12 is connected to the input terminal of the voltage-to-current conversion circuit VCCS3, the input terminal of the voltage-to-current conversion circuit VCCS1 is connected to the sampling voltage V ins1 , the output terminal of the voltage-to-current conversion circuit VCCS1 outputs a voltage-controlled current signal I t1 , the output terminal of the voltage-to-current conversion circuit VCCS2 is connected to the negative electrode of diode D 11 and the positive electrode of diode D 12 , the positive electrode of diode D 11 is grounded, the output terminal of the voltage-to-current conversion circuit VCCS3 is connected to the negative electrode of diode D 13 and the positive electrode of diode D 14 , the positive electrode of diode D 13 is grounded, the input terminal of the voltage-to-current conversion circuit VCCS4 is connected to the sampling voltage V ins2 , the negative electrode of diode D 12 is connected to the negative electrode of diode D 14 and the output terminal of the voltage-to-current conversion circuit VCCS4, and the current-combined output terminal outputs a voltage-controlled current signal I t2 .

[0008] Further, the drive signal generating circuit comprises: a t1 timer for controlling the duration of the input energy storage phase T1 of the boost-buck converter according to the voltage-controlled current signal I t1 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I t2 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I Ts a period timer for controlling the duration of the switching period of the whole converter according to the voltage-controlled current signal I ZVS a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I t1 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I t2 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I GS1 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I GS2 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I GS4 a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I ZVS a t2 timer for controlling the duration of the direct power transfer phase T2 of the boost-buck converter according to the voltage-controlled current signal I

[0009] Further, the period control circuit limits the minimum value of the input energy storage phase T1 and the direct power transfer phase T2 according to the input voltage V in and the output voltage V o to ensure that the first, second and fourth switches can realize ZVS turn-on.

[0010] Further, the conversion coefficients of the voltage-controlled current source control circuit comprise k t1 affecting the length of the input energy storage phase T1, k t2_boost affecting the length of the direct power transfer phase T2, k t2_buck affecting the length of the direct power transfer phase T2, and k t2-min affecting the minimum value of the length of the direct power transfer phase T2.

[0011] Further, the optimization of the conversion coefficients k t1 , k t2_boost and k t2_buck must satisfy the following constraint relationships:

[0012] I Lf_t1 >|I N |

[0013] (T1+T2) max <T s

[0014] k t2_boost >0

[0015] kt2_buck >0

[0016] Where T s I is the switching period of the converter. Lf_t1 For power transfer inductor L f The instantaneous value of I at the end of the input energy storage phase T1. N This is the ZVS turn-on condition for the second switch S2.

[0017] Furthermore, the durations of the input energy storage phase T1 and the direct power transfer phase T2 under the control of the voltage-controlled current source control circuit satisfy the following equation:

[0018]

[0019]

[0020] Among them, C t1 and C t2 The capacitance values ​​are the timing capacitors for timers t1 and t2, respectively.

[0021] Furthermore, the t2 logic limiting circuit includes an OR gate and an AND gate. The two inputs of the OR gate are electrically connected to the outputs of the comparators of the t1 and t2 timers, respectively. The inputs of the AND gate are electrically connected to the outputs of the OR gate, the t1 timer, and the t2 timer, respectively. The output of the AND gate is connected to the v... GS1 &v GS2 This generates an electrical connection in the circuit.

[0022] The optimization method of the control circuit of the four-switch buck-boost circuit described in this invention aims to maximize the ratio T2 / T1 of the duration of the input energy storage stage T1 and the direct power transmission stage T2 under different loads, and optimizes the conversion coefficient of the voltage-controlled current source control circuit.

[0023] Furthermore, by optimizing the control logic, it is ensured that in each switching cycle, the first switch S1 is always turned off later than the fourth switch S4, or is turned off simultaneously with the fourth switch S4.

[0024] Furthermore, based on the input voltage V of the converter in and output voltage V o Limit the minimum values ​​of the input energy storage stage T1 and the direct power transfer stage T2 to ensure that the ZVS turn-on conditions are always met when the first, second and fourth switches are turned on.

[0025] Furthermore, the conversion coefficients of the voltage-controlled current source control circuit include k, which affects the length of the input energy storage stage T1. t1 k, which affects the length of the direct power transfer stage T2t2_boost and k t2_buck , and k t2-min .

[0026] Further, the optimization of the conversion coefficient k t1 , k t2_boost , and k t2_buck needs to satisfy the following constraint relationship:

[0027] I Lf _ t1 > |I N |

[0028] (T1+T2) max <T s

[0029] k t2_boost > 0

[0030] k t2_buck > 0

[0031] where T s is the switching period of the converter, I Lf_t1 is the instantaneous value of the power transmission inductance L f at the end of the input energy storage stage T1, I N is the ZVS turn-on condition of the second switch S2.

[0032] Further, the optimization of the conversion coefficient k t2-min needs to satisfy the following constraint relationship:

[0033] T1+T2+T3≤T s_min

[0034] k t2_min > 0

[0035] where T s_min is the minimum value of the switching period of the converter.

[0036] Further, the value range of k t2_min / k t1 is 0.05 to 0.25.

[0037] Further, the value range of k t2_buck / k t1 is 0.2 to 1.0, and the value range of k t2_boost / k t1 is 0.4 to 1.0.

[0038] Advantages: Compared with the prior art, the present application has the following advantages:

[0039] 1. By optimizing the conversion coefficient of the voltage-controlled current source control circuit, the duration of the maximum direct power transmission stage can be maintained under different loads, and the conversion efficiency of the converter is improved.

[0040] 2. The control logic of the period control circuit is optimized, and the minimum duration of the input energy storage stage and the direct power transmission stage is limited according to the input voltage and output voltage of the converter, so as to avoid losing the ZVS opening condition under light load and reduce the switching loss.

[0041] 3. Under light load, the switching frequency is adaptively reduced with the decrease of the load, which can further reduce the switching loss.

[0042] 4. The logic limiting circuit is provided to prevent the first switch tube from being turned off before the fourth switch tube, so that the current of the energy transmission inductor enters the current clamping stage with a large value, and the converter loss is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 It is a control system block diagram of the four-switch buck-boost converter.

[0044] Figure 2 It is a waveform diagram of the single-mode soft switching control strategy.

[0045] Figure 3 It is a principle block diagram of the control circuit of the embodiment of the application.

[0046] Figure 4 It is a principle diagram of the voltage-controlled current source control circuit of the embodiment of the application.

[0047] Figure 5 It is a principle diagram of the first to fourth voltage-current conversion circuit specific embodiment of the embodiment of the application.

[0048] Figure 6 It is a principle diagram and waveform diagram of the S4 ZVS detection circuit of the embodiment of the application.

[0049] Figure 7 It is a principle diagram of the period control circuit of the embodiment of the application.

[0050] Figure 8 It is a principle diagram of the drive signal generation circuit of the embodiment of the application.

[0051] Figure 9 It is an inductor current waveform diagram under the control of the existing drive signal generation circuit.

[0052] Figure 10 It is an inductor current waveform diagram under the control of the drive signal generation circuit of the embodiment of the application.

[0053] Figure 11Control logic diagram of t2 logic limiting circuit of embodiment of the present application.

[0054] Figure 12 And Figure 13 Experimental waveform diagram under control of drive signal generating circuit of embodiment of the present application.

[0055] Figure 14 Four working regions of converter under control of control circuit of embodiment of the present application.

[0056] Figure 15 Typical waveform diagram of working region I of converter controlled by embodiment of the present application.

[0057] Figure 16 Typical waveform diagram of working region II of converter controlled by embodiment of the present application.

[0058] Figure 17 Typical waveform diagram of working region III of converter controlled by embodiment of the present application.

[0059] Figure 18 Typical waveform diagram of working region IV of converter controlled by embodiment of the present application.

[0060] Figure 19 Experimental waveform diagram of four working regions of converter under control of control circuit of embodiment of the present application.

[0061] Figure 20 Comparison diagram of conversion efficiency of control method of embodiment of the present application and conventional method under light load.

[0062] Figure 21 Comparison diagram of conversion efficiency of control method of embodiment of the present application and conventional method under heavy load. DETAILED DESCRIPTION

[0063] The technical solutions of the present application are further described below in combination with the drawings.

[0064] Referring to Figure 1 , the control circuit of the four-switch boost-buck converter of the embodiment of the present application is used to execute the single-mode soft-switching control strategy as shown in Figure 2 . One control period of the single-mode soft-switching control strategy includes four stages in sequence: input energy storage stage T1: the first switch S1 and the fourth switch S4 are turned on, the input voltage V in stores energy for the energy transmission inductor L f , the current i f of the inductor L Lf increases linearly with the slope of V in / L f ; direct power transmission stage T2: the first switch S1 and the third switch S3 are turned on, the input voltage Vin inductor L f continuously delivers energy to the output, when in the step-down mode (V in >V o ), i Lf will rise, when in the step-up mode (V in <V o ), i Lf will drop, when in the balance mode (V in =V o ), i Lf remains unchanged, and the change slope of i Lf is (V in -V o ) / L f ; freewheeling stage T3: the second switch S2 and the third switch S3 are turned on, and the inductor L f alone delivers energy to the output, i Lf linearly drops, and the drop slope is -V o / L f ; current clamping stage T4: the second switch S2 and the fourth switch S4 are turned on, and the capacitor C o maintains the load power supply requirement, and i Lf remains unchanged.

[0065] With reference to Figure 1 and Figure 3 , the control circuit of the four-switch buck-boost converter of the embodiment of the present application is mainly used for controlling the first, second and fourth switches, thereby realizing power conversion control of the converter. The third switch S3 adopts synchronous rectification control, and the control circuit of S3 has been disclosed in patents such as CN114337261A, and the specific structure will not be repeated here.

[0066] With reference to Figure 3 , the control circuit of the four-switch buck-boost converter of the embodiment of the present application includes a voltage-controlled current source control circuit, an S4 ZVS detection circuit, a voltage loop, a period control circuit and a drive signal generation circuit. The difference between the sampled output voltage V o (k o1 is a sampling coefficient and is greater than zero) and the reference voltage V ref is output as an error control signal v er1 by an error amplifier. The voltage-controlled current source control circuit generates voltage-controlled current signals I in and I o according to the input voltage V t1 and the output voltage V t2 ., respectively, for determining the ending time t1 of the input energy storage stage T1 and the ending time t2 of the direct power transfer stage T2, and by optimizing the conversion coefficient of the voltage-controlled current source control circuit, the ratio of T2 / T1 is maximized, so as to ensure that the duration T2 of the direct power transfer stage is as long as possible under different working voltages and load conditions, and thus the converter is optimized. The periodic control circuit generates a voltage-controlled current signal I in and an error control signal v o based on the input voltage V er1 , the output voltage V Ts , and the error control signal v er2 output by the voltage loop, and controls the size of the switching period of the converter, and realizes the control of load reduction and adaptive reduction of switching frequency, so as to reduce switching loss and optimize efficiency under light load. The S4 ZVS detection circuit generates a voltage signal v B indicating whether S4 realizes ZVS turn-on by detecting the midpoint voltage v zvs of the S3 / S4 composed switching bridge arm. The drive signal generation circuit generates drive control signals v t1 , v t2 , and v Ts for driving the first switch S1, the second switch S2, and the fourth switch S4, respectively, based on the voltage-controlled current signals I er2 , I zvs , and I GS1 , and the error control signal v GS2 and the voltage signal v GS4 .

[0067] Referring to Figure 4 , the voltage-controlled current source control circuit of the embodiment includes a sampling network and a voltage-controlled current source circuit. The sampling network includes three sampling coefficients. The sampling network acquires input voltage V in1 to obtain V in2 and V in according to sampling coefficients k ins1 and k ins2 , and acquires output voltage V o2 to obtain V o according to sampling coefficient k os1 , where k in1 =k o2 in the embodiment. The voltage-controlled current source circuit is composed of voltage-to-current conversion circuits VCCS1 to VCCS4, operational amplifiers OP11 and OP12, and diodes D 11 to D 14 . The non-inverting input terminal of the operational amplifier OP11 and the inverting input terminal of the operational amplifier OP12 are connected to the sampling voltage V ins1 , and the inverting input terminal of the operational amplifier OP11 and the non-inverting input terminal of the operational amplifier OP12 are connected to the sampling voltage Vos1 The output terminal of the operational amplifier OP11 is connected to the input terminal of the voltage-to-current conversion circuit VCCS2, and the output terminal of the operational amplifier OP12 is connected to the input terminal of the voltage-to-current conversion circuit VCCS3. The input terminal of the voltage-to-current conversion circuit VCCS1 is connected to the sampling voltage V ins1 The output terminal of the voltage-to-current conversion circuit VCCS1 outputs a voltage-controlled current signal I t1 The output terminal of the voltage-to-current conversion circuit VCCS2 is connected to the negative electrode of the diode D 11 and the positive electrode of the diode D 12 , the positive electrode of the diode D 11 is grounded, and the output terminal of the voltage-to-current conversion circuit VCCS3 is connected to the negative electrode of the diode D 13 and the positive electrode of the diode D 14 , the positive electrode of the diode D 13 is grounded, and the input terminal of the voltage-to-current conversion circuit VCCS4 is connected to the sampling voltage V ins2 The negative electrode of the diode D 12 is connected to the negative electrode of the diode D 14 and the output terminal of the voltage-to-current conversion circuit VCCS4, realizing the convergence and output of the voltage-controlled current signal I t2 The output voltages of the operational amplifiers OP11 and OP12 are V o_OP11 = V inS1 -V oS1 and V o_OP12 = V oS1 -V inS1 , respectively, so that

[0068] I CS2 = k VC2 (V ins1 -V os1 ) = k VC2 k in1 (V in -V o ) = k t2_buck (V in -V o ) (1)

[0069] I CS3 = k VC3 (V os1 -V ins1 ) = k VC3 k in1 (V o -V in ) = k t2_boost (V o -V in ) (2)

[0070] In the formulae, I CS2and I CS3 VCCS2 and VCCS3, respectively, k VC2 and k VC3 the conversion coefficients of VCCS2 and VCCS3, respectively, when V in ≥ V o , the voltage-controlled current signal I CS2 ≥ 0, I CS3 < 0, diodes D 12 and D 13 are on, D 11 and D 14 are off, and there is I t2 = I CS2 + I CS4 ; when V in < V o , the voltage-controlled current signal I CS2 < 0, I CS3 > 0, diodes D 11 and D 14 are on, D 12 and D 13 are off, and there is I t2 = I CS3 + I CS4 , where I CS4 is the voltage-controlled current signal output by VCCS4, and there is

[0071] I CS4 = k VC4 V ins2 = k VC4 k in2 V in = k t2_min V in (3)

[0072] where k VC4 is the conversion coefficient of VCCS4. The voltage-controlled current signal I t2 is equal to

[0073]

[0074] The voltage-controlled current signal I t1 is equal to the voltage-controlled current signal output by VCCS1, and there is

[0075] I t1 = k VC1 V ins1 = k VC1 k in1 V in = k t1 V in (5)

[0076] where kVC1 Let k be the conversion coefficient of VCCS1. According to equations (4) and (5), the conversion coefficient k is determined by optimizing the voltage-controlled current source control circuit. t1 k t2_buck k t2_boost and k t2_min It can optimize the voltage-controlled current signal I. t1 and I t2 The combination, with Figure 3 The drive signal generation circuit in this embodiment of the invention, in conjunction with the design goal of making T2 as long as possible, can achieve the improvement of change efficiency.

[0077] The specific implementation circuits of VCCS1 to VCCS4 are as follows: Figure 5 As shown, V SET I is the input voltage of VCCS. CS The voltage-controlled current signal output by the VCCS is... That is, the conversion coefficient k of VCCS VC =1 / R set Those skilled in the art can design according to actual needs to form Figure 5 (a) or Figure 5 (b) and other forms.

[0078] S4ZVS detection circuit and waveform are as follows: Figure 6 As shown, during the conduction period of the third switch S3, v B =V o diode D 21 When cut off, the voltage at the inverting input of comparator CP21 is equal to the voltage across resistor R. 21 and R 22 For V CC The voltage drop is higher than the threshold voltage V. th1 At this time, v zvs Low level. The third switch S3 is at i Lf After decreasing to zero, it is turned off, and then the junction capacitance of the fourth switch S4 discharges, v B Reduced to zero, diode D 21 When the circuit is turned on, the voltage at the inverting input of comparator CP21 is zero, which is lower than the threshold voltage V. th1 v zvs A high level indicates that the fourth switch S4 meets the ZVS turn-on condition.

[0079] Periodic control circuit, such as Figure 7 As shown, including T 1_min Control circuit and I Ts Control circuit. Where T 1_min The control circuit mainly consists of v er_min Circuit, operational amplifiers OP31-OP32, diode D 31 ~D32 components, v er_min circuit output v er_min to the non-inverting input of operational amplifier OP31, the output of OP31 is connected to the anode of diode D 31 The non-inverting input of operational amplifier OP32 is connected to the error control signal v er1 output by the voltage loop, and the output is connected to the anode of diode D 32 The inverting input of operational amplifier OP31 and OP32 and the cathode of diode D 31 and D 32 are connected to output the error control signal v er2 I Ts The control circuit mainly consists of operational amplifiers OP33, OP34 and voltage-to-current conversion circuit VCCS5. The inverting input of operational amplifier OP33 is inputted with v er1 , the non-inverting input is inputted with v er_min , and the output is connected to the inverting input of OP34. The non-inverting input of operational amplifier OP34 is connected to a constant voltage V Ts1 through a sampling circuit with a sampling coefficient of k CC , and the output of OP34 is connected to the input of voltage-to-current conversion circuit VCCS5, and the output of VCCS5 outputs I Ts which controls the length of the switching period of the converter.v er_min The circuit generates the minimum error signal value v in according to the input voltages V o and V er_min , which is used to limit the minimum value of T1 and T2, ensure the realization of soft switching under light load, further reduce switching loss and improve efficiency.

[0080] T1 and T2 are proportional to the error control signal v er2 , and inversely proportional to the voltage-controlled current signals I t1 and I t2 (which will be described in detail below), therefore, the minimum value of T1 and T2 will be proportional to v er_min , and inversely proportional to I t1 and I t2 . As can be seen from equations (4) and (5), with the change of input and output voltages, I t1 and I t2 will change, so that T1 and T2 will also change, therefore, the limit of soft switching realization condition on v er_min is different at different input and output voltages. If v er_minis a fixed value, which needs to be designed according to the worst case of the full input and output voltage range, resulting in the minimum value of T1 and T2 being much larger than the minimum time required to achieve soft switching at some operating points. In order to meet the demand of output voltage control, the switching frequency needs to be reduced very low when the load is empty. This will increase the difficulty of output ripple suppression and is not conducive to suppressing audio noise. To solve this problem, in the embodiment, v er_min is related to the input and output voltages er_min The operation process of the circuit is as follows:

[0081]

[0082] where C1 is a constant greater than zero, k min is a coefficient greater than zero, V in_min is the minimum value of the input voltage of the converter. According to equation (6), v er_min is also different at different input and output voltages, and under the premise of meeting the soft switching implementation, the problem of too low running frequency due to too long minimum conduction time, leading to difficulty in suppressing ripple and audio noise, can be avoided.

[0083] v er_min The circuit can be realized by a digital circuit, or an analog operation circuit using operational amplifiers to build addition and subtraction and maximum value taking.

[0084] Operational amplifiers OP31-OP32 and diodes D 31 -D 32 form a maximum value taking circuit, and have

[0085]

[0086] That is, T 1_min The control circuit outputs v er2 is the larger one of v er1 and v er_min .

[0087] I Ts The control circuit is used to output a voltage-controlled current signal I Ts that controls the switching period length of the entire converter, and the larger I Ts , the higher the switching frequency f s_max of the converter. The operational amplifier OP33 is used to implement the following operation:

[0088]

[0089] where V o_OP33 is the output voltage of the operational amplifier OP33, k Ts2 and k Ts3 are coefficients, and k Ts2≥k Ts3 >0. Operational amplifier OP34 is used to perform the following operations:

[0090]

[0091] In the formula V o_OP34 k is the output voltage of the operational amplifier OP34. Ts1 The coefficient is greater than zero. The voltage-to-current conversion circuit VCCS5 converts the input voltage signal V... o_OP34 Converted to voltage-controlled current I Ts Output the following:

[0092]

[0093] In the formula k VC5 The conversion factor for VCCS5.

[0094] Drive signal generation circuit such as Figure 8 As shown, it includes timer t1, timer t2, t2 logic limit circuit, periodic timer, and v. GS1 &v GS2 Generation circuit and v GS4 Generation circuit. The timer t1 is based on the voltage-controlled current signal I. t1 and error control signal v er2 The control input energy storage stage T1 ends at time t1; the timer t2 and the logic limit circuit t2 are based on the voltage-controlled current signal I. t2 and error control signal v er2 Controls the end time t2 of the direct power transfer phase T2; the periodic timer is based on the voltage-controlled current signal I. Ts Control the switching cycle of the converter; v GS1 &v GS2 The generating circuit outputs drive control signals v to control the switching transistors S1 and S2 based on the switching period and time t2. GS1 and v GS2 ;v GS4 The generation circuit generates the voltage signal v based on the switching period, time t1, and the output voltage signal v from the S4 ZVS detection circuit. zvs The output control signal v of the fourth switch S4 is used to drive the switch. GS4 The converter is based on v GS1 v GS2 and v GS4 The duration of the four working stages T1 to T4 is adjusted to achieve power conversion and output voltage regulation control.

[0095] The t1 timer includes a comparator CP41 and a timing capacitor C. t1 Switching transistor Q 41 And RS flip-flop RS41. Timing capacitor Ct1 One end is grounded, and the other end is connected to the voltage-controlled current signal I. t1 Switch Q 41 Connected in parallel to timing capacitor C t1 At both ends, the Q output signal of RS41 controls Q. 41 The switching on and off. The non-inverting input of CP41 is connected to C. t1 Connection signal I t1 One end, the inverting input terminal is connected to the error control signal v er2 The output terminal is connected to the S terminal of RS41, and the R terminal of RS41 is connected to the output terminal of the AND gate AND42 in the periodic timer. Q 41 When turned off, the timing capacitor C t1 Charging, when the timing capacitor C t1 The voltage rises to v er2 When CP41 outputs a high level, the Q output of RS41 also outputs a high level, and the switching transistor Q... 41 On, timing capacitor C t1 After discharging to zero, CP41 outputs a low level, and the Q output of RS41 remains high until the AND gate AND42 in the periodic timer outputs a high level, and RS41 outputs a low level. The construction and principle of timer t2 are basically the same as those of timer t1, as detailed below. Figure 8 As shown, the difference lies in the timing capacitor C. t2 By voltage-controlled current signal I t2 Charge.

[0096] The periodic timer includes an AND gate AND42, a comparator CP43, and a timing capacitor C. Ts and switching transistor Q 43 The inputs of AND gate AND42 are connected to the output of CP43 and the voltage signal V, respectively. zvs Furthermore, AND gate AND42 serves as the reset signal for RS flip-flops RS41 and RS42 in timers t1 and t2, and also controls the switching transistor Q. 43 On / off state. When Q 43 When C is turned off Ts By voltage-controlled current signal I Ts Charging, when C Ts The voltage value reaches V th2 When CP43 outputs a high level, if switch S4 meets the ZVS turn-on condition, it indicates that one switching cycle of the converter has ended. Then, AND42 outputs a high level, resetting timers t1 and t2, and simultaneously controlling Q. 43 On, C Ts Discharge to achieve periodic reset.

[0097] When the voltage control current I t1 t2 ​When, t2 timer circuit in timing capacitor C t2 The voltage will be in the t1 timer circuit in timing capacitor C t1 Rises to v er2 , So that the comparator CP42 output high CP41 first, RS trigger RS42 output high RS41 first, in order to avoid the emergence of the first switch S1 S4 shut-off phenomenon, the embodiment increases the t2 logic limiting circuit, otherwise as Figure 9 The transformer will be in the inductor current i Lf At the peak into the current clamping phase, because the inductor current i Lf Only through the switch S2 and S4, and the current remains constant, will introduce a large conduction loss, reduce the efficiency of the converter.

[0098] Reference Figure 8 , The t2 logic limiting circuit of the embodiment is composed of OR gate OR41 and AND gate AND41, wherein the two input terminals of OR gate OR41 are connected with the output terminals of comparators CP41 and CP42 respectively, the three input terminals of AND gate AND41 are connected with the output terminal of OR gate OR41, the Q terminals of RS triggers RS41 and RS42 respectively, and the output terminal of AND gate AND41 is connected with the R terminal of RS trigger RS43. The key point working waveform of the t2 logic limiting circuit is shown in Figure 11 , Wherein v o_CP41 and v o_CP42 are the output voltages of comparators CP41 and CP42 respectively, v Q_RS41 and v Q_RS42 are the Q terminal voltages of RS triggers RS41 and RS42 respectively, and v R_RS43 is the R terminal voltage of RS43, which is also the output voltage of AND gate AND41. Combined with Figure 11 , When I t1 <I t2 , At this time, the comparator CP42 outputs high before CP41, and the RS trigger RS42 also outputs high before RS41, the t2 logic limiting circuit output (i.e. v R_RS43 ) is consistent with the output terminal voltage signal v o_CP41 of the comparator CP41, so that the RS triggers RS43 and RS44 are reset at the same time and output low, that is, the driving control signals v GS1 and v GS4 are low at the same time, and the switch S1 will not shut off before S4, but will shut off at the same time. At this time, the typical waveform of the inductor current i Lf of the transformer is shown in Figure 10 . When I t1 >I t2 , the comparator CP42 outputs high later than CP41, at this time, the t2 logic limiting circuit output (i.e. vR_RS43 ) with the comparator CP42 output voltage signal v o_CP42 , so that the switch S1 is turned off later than S4, and the converter works in input energy storage stage, direct power transmission stage, freewheeling stage and current clamping stage in sequence in a switching cycle. GS1 , that is, S1 is always turned off later than S4 or simultaneously with S4, so that the peak current clamping stage is avoided, the current stress and conduction loss are reduced, and the conversion efficiency is improved. GS4

[0099] Referring to Figure 8 , the durations of the input energy storage stage and the direct power transmission stage of the embodiment satisfy the following formula:

[0100]

[0101] In the formula, C t1 and C t2 are the capacitances of the timing capacitors of the t1 timer and the t2 timer respectively, and equal-capacitance capacitors are generally used for convenience of calculation. Figure 12 and Figure 13 are experimental waveform diagrams of the drive control signals of the first, second and fourth switches under the control of the control circuit with the t2 logic limiting circuit in the embodiment, and are basically consistent with the requirements of Figure 10 , so that S1 is avoided from being turned off earlier than S4.

[0102] Referring to Figure 7 , the cycle control circuit of the embodiment limits the minimum value of the error control signal v er2 to limit the minimum values of T1 and T2, so as to ensure the soft switching implementation of the converter at light load, reduce the switching loss and improve the efficiency. At the same time, the control of adaptive reduction of the switching frequency with the reduction of the load is realized, so as to further reduce the switching loss at light load and optimize the efficiency. As shown in Figure 14 , the converter under the control of the control circuit of the embodiment has four working regions, wherein region I and II are light load frequency reduction working regions, region III is a constant frequency mode working region, and region IV is a heavy load frequency reduction mode working region, and the typical working waveforms of the four working regions are shown in Figures 15 to 18 .

[0103] Next, the working principles of the converter in the four working regions are briefly described in combination with Figure 7 and Figures 15 to 18 .

[0104] According to the formulas (6), (7) and (10), when k Ts3 v er1 >k Ts2 ​v er_min v er2 v er1 , and the voltage-controlled current signal I Ts for period control is VC5 k Ts1 V CC , a constant, and has

[0105]

[0106] where T s_min is the minimum switching period of the converter, C Ts is the timing capacitor of the period timer circuit, V th2 is the threshold voltage, and is greater than zero. At this time, the converter operates in Region III or Region IV, when T1+T2+T3≤T s_min , at which time the rising time of the voltage signal v ZVS is prior to the rising time of the output of the comparator CP43, the converter operates in Region III, the switching frequency is fixed, and as the load increases, the error control signal v er2 = v er1 increases, T1 and T2 increase to achieve output voltage control, and the typical operating waveform is shown in Figure 17 ; as the load continues to increase, and when T1+T2+T3>T s_min , the rising of the voltage signal v ZVS needs to wait for the end of the freewheeling stage, i.e., the turn-off of the switch S3, which will be later than the time when the output of the comparator CP43 rises, at which time v er2 = v er1 , but the switching period of the converter is determined by the rising time of the voltage signal v ZVS , which increases with the increase of the error control signal, and the typical operating waveform is shown in Figure 18 .

[0107] As the load decreases, the error control signal v er1 decreases, and when k Ts3 v er1 ≤ k Ts2 v er_min , the converter will operate in the light load frequency reduction operating region. When v er1 > v er_min and k Ts2 v er_min ≥ k Ts3 v er1 , it can be known from equation (7) and equation (10) that v er2 = v er1 and I Ts = k VC5 [k Ts1 V CC -(kTs2 v er_min -k Ts3 v er1 At this time, as the load decreases, the error control signal v er1 Decrease, v er2 Decrease, I Ts This decreases, thus reducing T1 / T2, and the switching frequency f of the converter. s Decrease, switching period T s The converter operates in Region II with a variable length, and its typical operating waveform is as follows: Figure 16 As shown.

[0108] As the load continues to decrease, the error control signal v er1 It also continues to decrease, until it decreases to v er1 <v er_min And k Ts2 v er_min ≥k Ts3 v er1 At that time, it can be seen from equations (7) and (10) that v er2 =v er_min And I Ts =k VC5 [k Ts1 V CC -(k Ts2 v er_min -k Ts3 v er1 At this time, as the load decreases, although the error control signal v er1 Decrease, but v er2 Remain unchanged, for v er_min At this time, only I Ts Decrease, T1 / T2 remains unchanged, only f s Decrease, T s The converter operates in region I with a variable length, and its typical operating waveform is as follows: Figure 15 As shown.

[0109] The experimental waveforms of the converter under the control of the control circuit in this embodiment of the invention in four operating regions are as follows: Figure 19 As shown, respectively with Figures 15 to 18 The requirements are consistent, and the converter can automatically operate in regions I to IV according to the load size. Under light load, the switching frequency is reduced as the load decreases, and soft switching is ensured by limiting the duration of T1 and T2, which can reduce switching losses and optimize efficiency.

[0110] It is understood that the specific implementation of each circuit in the above embodiments can be built using analog circuits or implemented using digital circuits according to the required control logic programming.

[0111] Based on the converter's operating principle, in the direct power transfer stage, energy is transferred directly from the input to the output via an inductor. Therefore, under the same voltage and load conditions, the longer this stage lasts, the higher the converter's efficiency. From the formulas for T1 and T1+T2 above, it can be seen that the conversion coefficient k can be controlled by designing a voltage-controlled current source circuit. t1 k t2_buck k t2_boost and k t2_min Change k t2_buck k t2_boost and k t2_min Relative to k t1 The ratio of T2 to T1 is used to change the ratio of T2 to T1 for different input and output voltages, thereby optimizing the duration of T2 and improving efficiency. In practice, this can be achieved through optimization... Figure 4 The sampling coefficients k of the medium sampling network in1 (k vo2 =k in1 ) and k in2 And the conversion coefficient k of the voltage-to-current conversion circuit VCCS1~VCCS VC1 ~k VC4 This optimizes the duration of T2.

[0112] It is understandable that the conversion coefficient k of the voltage-controlled current source control circuit is adjusted. t2_min k t2_buck k t2_boost and k t1 This requires satisfying the constraints of a single-mode soft-switching control strategy. The design must be 0 < k. t2_min <k t1 That is, 0 <k t2_min / k t1 Substituting equations (4) and (5) into equation (11) respectively, we get:

[0113]

[0114]

[0115] From equations (13) and (14), it can be seen that when V in =V o When T2 / T1 is maximized, that is, T2 is relatively longest, and k t2_min / k t1 The smaller the value, the longer the time (T2), and the higher the conversion efficiency the converter can achieve.

[0116] To ensure V in =V o There is also a region III to prevent a logical error from jumping directly from region II to region IV when the load increases. That is, the following condition must be met:

[0117]

[0118] Where T s_min The minimum switching period of the converter can be obtained from the above formula:

[0119]

[0120] k can be obtained from equation (16) t2_min / k t1 The minimum value of k in practice t2_min / k t1 The value typically ranges from 0.05 to 0.25.

[0121] Simultaneously, from equations (15) and (16), we can see that k t2_buck / k t1 and k t2_buck / k t1 The smaller the value of T2, the longer the T2 time, which is more conducive to reducing the stress on the effective value of the current and improving efficiency. As T2 increases, the T1 time decreases, thus affecting I. Lf_t1 (t1 time i) Lf If the instantaneous value of k is too small, S2 will lose the ZVS activation condition, therefore k t2_buck / k t1 and k t2_buck / k t1 During the design process, the size should be minimized as much as possible while ensuring soft switching. The design constraints are as follows:

[0122]

[0123] At the same time, it is necessary to ensure that the inductor current i at the end of the direct power transfer phase is constant. Lf instantaneous value I Lf_t2 >0, meaning T1+T2 is less than the switching period:

[0124] (T1+T2) max <T s (18)

[0125] In practice, k t2_buck / k t1 The value of k typically ranges from 0.2 to 1.0. t2_buck / k t1 The value range is typically from 0.4 to 1.0.

[0126] To further verify the effectiveness of the control circuit and optimization method described in this invention, Figure 20 and Figure 21 Experimental efficiency comparison curves for specific embodiments are provided. Figure 20It can be seen that the period control circuit ensures the soft switching implementation of light load by limiting the minimum values of T1 and T2, reduces the switching loss at light load by adaptively reducing the switching frequency as the load decreases, and optimizes the conversion efficiency. Figure 21 It can be seen that the conversion efficiency of the converter is further improved by optimizing the conversion factor of the voltage-controlled current source control circuit and then realizing the T2 / T1 optimization mode to optimize the duration T2 of the direct power transmission stage under different operating voltages and load conditions.

Claims

1. A control circuit of a four-switch boost-buck converter, employing a single-mode soft-switching control strategy for controlling first, second, third and fourth switches of the four-switch boost-buck converter, the single-mode soft-switching control strategy comprising an input energy storage phase T1, a direct power transfer phase T2, a freewheeling phase T3 and a current clamping phase T4 in a sequential cycle, characterized in that, Comprise: The voltage-controlled current source control circuit is used to control the current based on the input voltage V of the buck-boost converter. in and output voltage V o Generate voltage-controlled current signal I for controlling the on / off state of the first and second switching transistors. t1 and I t2 Voltage-controlled current signal I t1 and I t2 These are used to determine the end time t1 of the input energy storage stage T1 and the end time t2 of the DC power transmission stage T2, respectively. S4 ZVS detection circuit for detecting the voltage v at the midpoint of the switch bridge arm consisting of the third and fourth switch B , generating a voltage signal v characterizing whether the ZVS turn-on condition for the fourth switch S4 is fulfilled ZVS ; a voltage loop for outputting an error control signal v o in accordance with a difference between the reference voltage V ref and the output voltage V er1 ; a period control circuit for generating a voltage-controlled current signal I in and an error control signal v o in response to an input voltage V er1 , an output voltage V Ts , and a duty cycle signal D er2 for regulating the size of the switching period of the converter. The drive signal generation circuit is used to generate a signal based on the voltage-controlled current signal I. t1 I t2 and I Ts and error control signal v er2 and voltage signal v ZVS This generates drive control signals v to control the first, second, and fourth switching transistors. GS1 v GS2 and v GS4 ; The conversion coefficient of the voltage-controlled current source control circuit satisfies: the ratio T2 / T1 of the durations of the input energy storage stage T1 and the direct power transmission stage T2 is maximum under different loads.

2. The control circuit of a four-switch boost-buck converter according to claim 1, characterized in that, The voltage-controlled current source control circuit includes a sampling network and operational amplifiers OP11 and OP12, and diode D. 11 To D 14 The voltage-to-current conversion circuits VCCS1 to VCCS4 form a voltage-controlled current source circuit, and the sampling network is based on the sampling coefficient k. in1 and k in2 Obtain the input voltage V in Sampling voltage V ins1 and V ins2 And according to the sampling coefficient k o2 Obtain the output voltage V o Sampling voltage V os1 The non-inverting input of operational amplifier OP11 and the inverting input of OP12 are connected to the sampling voltage V. ins1 The inverting input of operational amplifier OP11 and the non-inverting input of OP12 are connected to the sampling voltage V. os1 The output of operational amplifier OP11 is connected to the input of voltage-to-current converter circuit VCCS2, the output of operational amplifier OP12 is connected to the input of voltage-to-current converter circuit VCCS3, and the input of voltage-to-current converter circuit VCCS1 is connected to the sampling voltage V. ins1 The voltage-to-current conversion circuit VCCS1 outputs a voltage-controlled current signal I. t1 The output terminal of the voltage-to-current conversion circuit VCCS2 is connected to diode D. 11 negative electrode and D 12 The positive terminal of diode D 11 The positive terminal is grounded, and the output terminal of the voltage-to-current converter circuit VCCS3 is connected to diode D. 13 negative electrode and D 14 The positive terminal of diode D 13 The positive terminal is grounded, and the input terminal of the voltage-to-current conversion circuit VCCS4 is connected to the sampling voltage V. ins2 diode D 12 The negative terminal of the diode D is connected. 14 The negative terminal and the output terminal of the voltage-to-current conversion circuit VCCS4 are used to output the voltage-controlled current signal I. t2 .

3. The control circuit of a four-switch boost-buck converter according to claim 1, characterized in that, The driving signal generation circuit comprises: a t1 timer for determining the duration of the input energy storage phase T1 of the boost-buck converter in dependence on the voltage-controlled current signal I t1 controlling the duration of the input energy storage phase T1 of the boost-buck converter; a t2 timer for determining the duration of the direct power transfer phase T2 of the buck-boost converter in dependence on the voltage-controlled current signal I t2 controlling the duration of the direct power transfer phase T2 of the buck-boost converter; a periodic timer for controlling the duration of the switching period of the entire converter in dependence on the voltage signal v Ts and the voltage signal v ZVS controlling the duration of the switching period of the entire converter; a t2 logic limiting circuit for optimizing control logic, ensuring that the first switch S1 is turned off later than the fourth switch S4 when the voltage-controlled current signal I t1 t2 voltage-controlled current signal I​ v GS1 &v GS2 a generating circuit for generating a drive control signal for controlling the first and second switch tubes according to the t1 timer, the t2 timer and the t2 logic limiting circuit; v GS4 a circuit for generating a voltage signal v ZVS generating a drive control signal for controlling the fourth switch S4.

4. The control circuit of a four-switch boost-buck converter according to claim 1, characterized in that, The period control circuit limits the minimum value of the input energy storage phase T1 and the direct power transmission phase T2, to ensure that the first, second and fourth switch tubes are turned on with ZVS turn-on. in and the output voltage V o The period control circuit limits the minimum value of the input energy storage phase T1 and the direct power transmission phase T2, to ensure that the first, second and fourth switch tubes are turned on with ZVS turn-on.

5. The control circuit of a four-switch boost-buck converter according to claim 1, characterized in that, The periodic control circuit includes T 1_min Control circuit and I TS Control circuit, the T 1_min The control circuit includes V er_min The circuit and the maximum value circuit, wherein V er_min The circuit is used to determine the input voltage V of the converter. in and output voltage V o Output minimum error signal v er_min The maximum value circuit is used to select the error control signal v. er1 and minimum error signal v er_min The larger value in is used as the error control signal v er2 I TS The control circuit is used to control the error signal v er1 and minimum error signal v er_min Generate voltage control circuit signal I Ts The voltage-controlled current signal I under the control of the periodic control circuit Ts and error control signal v er2 Satisfy the following formula: wherein k VC5 is a conversion coefficient of a voltage-current conversion coefficient VCCS5 in the period control circuit, k Ts1 , k Ts2 , and k Ts3 are preset coefficients, and satisfy k Ts2 ≥ k Ts1 > 0 and k Ts1 > 0, Vcc is a constant voltage value, and the value of the minimum error signal v er_min satisfies the following equation: where C1 is a constant greater than zero, k min is a coefficient greater than zero, V in_min is the minimum value of the transformer input voltage.

6. The control circuit of a four-switch boost-buck converter according to claim 3, wherein, The durations of the input energy storage stage T1 and the direct power transmission stage T2 controlled by the voltage-controlled current source control circuit satisfy the following formula: where C t1 and C t2 are the capacitances of the timing capacitors of the t1 timer and t2 timer, respectively.

7. The control circuit of a four-switch boost-buck converter according to claim 3, wherein, The t2 logic limiting circuit comprises an OR gate and an AND gate, two input ends of the OR gate are electrically connected with the output ends of the comparators of the t1 timer and the t2 timer respectively, an input end of the AND gate is electrically connected with the output end of the OR gate, output ends of the t1 timer and the t2 timer respectively, and an output end of the AND gate is electrically connected with the v GS1 &v GS2 The generating circuit is electrically connected.

8. An optimization method of a control circuit of a four-switch converter according to any one of claims 1 to 7, characterized in that, The conversion coefficient of the voltage-controlled current source control circuit is optimized to keep the ratio T2 / T1 of the durations of the input energy storage stage T1 and the direct power transmission stage T2 maximum under different loads.

9. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 8, wherein, The control logic is also optimized to ensure that the first switch S1 is always turned off later than the fourth switch S4 or simultaneously with the fourth switch S4 in each switching cycle.

10. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 8, wherein, According to the input voltage V in and the output voltage V o of the converter The minimum value of the input energy storage phase T1 and the direct power transmission phase T2 is limited to ensure that the first, second and fourth switch tubes always meet the ZVS turn-on condition when they are turned on.

11. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 8, wherein, The conversion factor of the control circuit of the voltage-controlled current source comprises k t1 , which influences the length of the input energy storage phase T1 t2_boost , which influences the length of the direct power transfer phase T2 t2_buck , and k t2-min , which influences the minimum value of the length of the direct power transfer phase T2.

12. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 11, wherein, The conversion coefficient k t1 , k t2_boost and k t2_buck The optimization of k must satisfy the following constraint relationship: I Lf_t1 |I N | (T1+T2) max <T s k t2_boost ＞0 k t2_buck ＞0 where T s is the switching period of the transformer, I Lf_t1 is the power transfer inductance L f is the instantaneous value at the end of the input energy storage phase T1, I N is the ZVS turn-on condition for the second switch S2.

13. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 11, wherein, The conversion coefficient k t2-min The optimization of k must satisfy the following constraint: T1+T2+T3≤T s_min k t2_min ＞0 where T s_min is the minimum value of the switching period of the converter.

14. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 11, wherein, k t2_min / k t1 the value range of a is 0.05 to 0.

25.

15. The method of optimizing a control circuit for a four-switch boost-buck converter of claim 11, wherein, k t2_buck / k t1 k t2_boost / k t1 k

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