Caching logical to physical mapping information in a memory subsystem

Abstract

A request is received that specifies a logical address associated with a host initiated operation for a first portion of a memory device. A logical to physical (L2P) table is accessed. The L2P table includes mappings between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and it is determined that the entry points to an entry in a read cache table. A block address of a block from among a plurality of blocks of a read cache is calculated based on an entry number of the entry in the read cache table. A physical address corresponding to the logical address specified by the request is identified by accessing the block of the read cache. A host initiated operation is performed at a physical location in the first portion of the memory device that corresponds to the physical address.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to logical-to-physical (L2P) mapping information of cache memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory components may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can use a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of various embodiments thereof.

[0004] Figure 1 This is a block diagram illustrating an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2A and 2B This is a block diagram illustrating an instance architecture for a memory subsystem according to some embodiments of the present disclosure.

[0006] Figure 3 This is a block diagram illustrating an instance cache algorithm implemented by a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 4-6 This is a flowchart illustrating an example method for using a logic-to-physical (L2P) table stored in a dedicated portion of a NAND memory device, according to some embodiments of the present disclosure.

[0008] Figure 7 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0009] This disclosure relates to caching techniques for logical-to-physical (L2P) mapping information in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of both. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may use a memory subsystem that includes one or more components such as a memory device for storing data. The host system can provide data that will be stored in the memory subsystem and can request data that will be retrieved from the memory subsystem.

[0010] Data operations can be performed by the memory subsystem. Data operations can be initiated by the host system. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on the memory devices located in the memory subsystem and to read data from the memory devices located in the memory subsystem.

[0011] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. Some memory devices, such as NAND memory devices, contain arrays of memory cells (e.g., flash cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as the threshold voltage of the transistor. More specifically, the range of the transistor's threshold voltage can be divided into multiple regions, where each region corresponds to a charge level decoded into a data value. The memory cells in these devices can be grouped into pages that can refer to logical units of the memory device used to store data. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), can store multiple bits per cell. Memory devices may contain one or more arrays of SLC, MLC, TLC, QLC, or any combination thereof.

[0012] Within the context of the memory subsystem, a physical address identifies the physical location of data within a memory device. A logical address is a virtual address used by the host system as a reference to access data units corresponding to physical locations within the memory device. Data units can correspond to blocks, pages, or subpages. The memory subsystem maintains a logic-to-physical (L2P) table (also called a "data map") to handle access requests received from the host system. The L2P table contains the mapping between physical and logical addresses. Traditionally, the L2P table is stored in the dynamic random access memory (DRAM) component of the memory subsystem.

[0013] The density of NAND cells within memory devices is increasing at a relatively high rate, which increases the number of physical memory locations in the device. As the number of physical memory locations increases, the size of the L2P table increases, requiring larger DRAM sizes to store these larger L2P tables. However, while NAND cell density is steadily increasing, DRAM density remains relatively stable to some extent. This is because, in addition to increasing the complexity of the DRAM-to-memory subsystem controller interface, a larger number of DRAM components can also make hardware layout infeasible.

[0014] Common methods to address the increasing size of L2P tables involve increasing the mapped indirect size unit (e.g., from 4KB to 8-16KB) to reduce the DRAM requirements for storing the L2P table. However, this method often results in increased write amplification. Another common method involves using paging to segment the L2P table from flash memory to DRAM. However, this method causes excessively high refresh rates due to updates to the L2P table. This method also increases the amount of flash memory utilized by Flash Translation Layer (FTL) metadata, which can lead to compromised performance and durability compared to other methods.

[0015] This disclosure addresses the problem of large L2P table size in the memory subsystem by using a NAND memory device to store the L2P table and by using a read cache to quickly process L2P lookup requests from the L2P table stored on the NAND memory device. A portion of the NAND memory device is dedicated to storing primary L2P data, while the remainder is used to store user data. For example, the L2P table may be stored in the SLC portion of the memory device, while user data is stored in the QLC portion. In addition to a primary flash translation layer using a conventional indirection unit size (e.g., 4KB), the memory subsystem further includes a secondary fine-grained FTL with a reduced indirection unit size (e.g., 256 bytes instead of 4KB), which works in conjunction with the primary FTL to handle host-initiated operations. During a lookup, the secondary FTL uses a secondary L2P table (e.g., stored in DRAM) to identify a physical location with a dedicated portion that stores the relevant portion of the primary L2P table. The secondary FTL accesses the relevant portion of the primary L2P table from a dedicated section (e.g., the SLC section) to identify the physical address corresponding to the logical address targeted by the host command. The primary FTL then performs the host-initiated operation at the identified physical address.

[0016] As mentioned above, the memory subsystem includes a read cache (e.g., in DRAM) for a primary L2P table for location-constrained workloads. The read cache is managed across multiple blocks, each storing a portion of the primary L2P table. The size of each block corresponds to the size of the indirect unit used by the secondary FTL. In the event of a cache miss, the secondary FTL accesses the physical location within a dedicated section storing the portion of the primary L2P table and caches the read portion of the primary L2P table in the read cache. In the event of a cache hit, the secondary FTL can quickly identify the physical address corresponding to the logical address targeted by the host command by accessing the relevant portion from the block of the read cache. Using the read cache in the manner described herein reduces the cache miss rate.

[0017] Storing primary L2P data in NAND memory devices instead of DRAM is advantageous because it allows for a reduction in DRAM footprint. This approach also scales to address the problem of increasingly large L2P tables as NAND density continues to increase. Furthermore, storing primary L2P data in NAND memory uses less FTL metadata budget and significantly reduces post-boot setup time compared to conventional methods.

[0018] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0021] The computing system 100 may include multiple host systems coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example host system 120 is shown coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and software stack executed by a processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110 to, for example, write data to and read data from memory subsystem 110.

[0023] Host system 120 may be coupled to memory subsystem 110 via a host interface. Examples of host interfaces include, but are not limited to, SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, DIMM interfaces (e.g., DIMM socket interfaces supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further use an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Typically, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional (3D) cross-point memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array for bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0026] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For example, memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks. In addition, word lines within a memory device can be organized into multiple word line groups, each of which contains one or more word lines, but each word line group contains fewer word lines than a block contains.

[0027] Although non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0029] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing operations controlling the memory subsystem 110, including various processes, operations, logical flows, and routines for handling communication between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include ROM for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and ECC, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communication with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translates responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0032] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0033] The memory subsystem 110 also includes a primary flash translation layer (FTL) 113 and a secondary FTL 114. The primary FTL 113 performs lookups and garbage collection. The primary FTL 113 uses a first indirection unit size (e.g., 4KB) for lookups. The secondary FTL 114 provides virtual persistent memory for the primary FTL 113 to store a primary L2P table. The primary L2P table is stored in a first portion of the memory device 130 (e.g., the SLC portion of the memory device 130). The primary L2P table contains a mapping between logical addresses and physical addresses in a second portion of the memory device 130 (e.g., the QLC portion). The secondary FTL 114 uses the primary L2P table to process read and write commands from the primary FTL 113 for the second portion of the memory device 130 (e.g., one or more QLC blocks). The secondary FTL 114 uses a second indirection unit size (e.g., 256 bytes) smaller than the first indirection unit size used by the primary FTL 113.

[0034] When a read or write command for a logical address corresponding to a second portion of memory device 130 is received by primary FTL 113, primary FTL 113 sends a lookup request to secondary FTL 114. In response to the request, secondary FTL 114 accesses a secondary L2P table from a volatile memory component of memory subsystem 110, such as DRAM or holographic random access memory (HRAM). The secondary L2P table contains a mapping between logical addresses and physical addresses within the first portion of memory device 130, where the primary L2P table is stored. Therefore, secondary FTL 114 uses the secondary L2P table to identify physical locations within the first portion of memory device 130 corresponding to portions of the primary L2P table, which contain the mapping between logical addresses and physical addresses within the second portion of memory device 130. Secondary FTL 114 accesses portions of the primary L2P table to identify physical addresses within the second portion of memory device 130 that correspond to the location where data will be read or written based on the command. The secondary FTL 114 provides the physical address as an output to the primary FTL 113, and the primary FTL 113 then performs an operation (e.g., write, read, or erase data) in the second part of the memory device 130 at the physical location corresponding to the physical address identified by the secondary FTL 114 based on the command.

[0035] In some embodiments, the memory subsystem controller 115 includes at least a portion of a primary FTL 113 and a secondary FTL 114. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, at least a portion of the primary FTL 113 and the secondary FTL 114 is part of the host system 120, an application program, or an operating system.

[0036] Figure 2A and 2B This is a block diagram illustrating an example architecture for a memory subsystem 110 according to some embodiments of the present disclosure. Figure 2A and 2B In the example shown, memory device 130 is a NAND memory device containing multiple memory blocks.

[0037] refer to Figure 2AThe memory device 130 includes QLC blocks 200 and SLC blocks 202. Specifically, each QLC block 200 contains QLCs, and each SLC block 202 contains SLCs. Typically, a NAND block contains an array (2D or 3D) of pages (rows) and strings (columns). Each NAND cell contains a transistor, and within each cell, data is stored as the threshold voltage of the transistor. For example, SLCNAND can store one bit per cell. Other types of memory cells, such as MLC, TLC, QLC, and PLC, can store multiple bits per cell. Strings are connected within the NAND block to allow storage and retrieval of data from selected cells. NAND cells in the same column are connected in series to form a bit line. All cells in a bit line are connected to a common ground at one end and to a common sense amplifier at the other end for reading the threshold voltage of one of the cells when decoding data. NAND cells are horizontally connected to word lines (WL) at their control gates to form pages. In MLC, TLC, QLC, and PLC NAND, a page is a group of connected units that share the same word line and are the smallest unit of programming.

[0038] The memory subsystem 110 further includes a host interface 204 (e.g., NVMe) for the host system 120 to send access requests (e.g., write commands, read commands) to the memory device 130 in order to store data on or read data from the memory device 130.

[0039] Back-end channel 206 facilitates communication between the NAND blocks (QLC blocks 200 and SLC blocks 202) and the primary FTL 113 and secondary FTL 114. As mentioned above, secondary FTL 114 provides virtual persistent memory for primary FTL 113 to store primary L2P table 208. Virtual persistent memory is implemented by SLC block 202. That is, primary L2P table 208 is stored in SLC block 202. Primary L2P table 208 contains a mapping between logical addresses and physical addresses in QLC block 200. Secondary FTL 114 uses primary L2P table 208 to process read and write commands from primary FTL 113 for one or more QLC blocks 200. Secondary FTL 114 uses a second indirection unit size (e.g., 256 bytes) smaller than the first indirection unit size used by primary FTL 113.

[0040] When a lookup request specifying a logical address corresponding to QLC block 200 is received from primary FTL 113, secondary FTL 114 accesses secondary L2P table 212 to identify a physical location within SLC block 202, at which the corresponding portion of primary L2P table 208 is stored. Secondary L2P table 212 may be stored in volatile memory component 210 of memory subsystem 110, such as DRAM or holographic random access memory (HRAM). Volatile memory component 210 may form part of memory device 130 together with QLC block 200 and SLC block 202, or volatile memory component 210 may correspond to or form part of another memory device (e.g., memory device 140). Using secondary L2P table 212, secondary FTL 114 identifies the physical address corresponding to the physical location within SLC block 202 and accesses a portion of primary L2P table 208 to identify the physical address in QLC block 200 corresponding to the physical location where data will be read or written based on a command. The secondary FTL 114 provides the physical address in QLC block 200 to the primary FTL 113, which in turn performs host startup operations at the physical location within QLC block 200 corresponding to the identified physical address.

[0041] like Figure 2B As shown, according to some embodiments, the secondary FTL 114 may employ a read cache 214 to assist in performing lookups. The read cache 214 may be implemented in the volatile memory component 210. The read cache table 216 may also be stored in the volatile memory component 210 together with the secondary L2P table 212. The read cache 214 is managed in multiple blocks, and each entry in the cache table 216 corresponds to a block. The size of each block corresponds to the indirection unit size utilized by the secondary L2P table 212. As described above, in this example, the indirection unit size of the secondary L2P table 212 is 256 bytes, and therefore, each entry in the cache table 216 corresponds to a 256-byte block of the read cache 214. Each block of the read cache 214 contains a portion of the primary L2P table 208.

[0042] Each entry in cache table 216 is logically linked to a corresponding block of memory in SLC block 202. That is, the entry number in cache table 216 can be used to calculate the physical address of the corresponding block in SLC block 202. Further details regarding the use of cache table 216 are discussed below.

[0043] Figure 3 This is a block diagram illustrating an instance cache algorithm implemented by memory subsystem 110 according to some embodiments of the present disclosure. More specifically, Figure 3The behavior of the memory subsystem is shown in several scenarios: cache miss at 302, cache hit at 304, and non-cleared cache hit at 306.

[0044] Referring to 302, a cache miss occurs when the entry corresponding to the requested logical address in the host command is not included in the read cache table 216. In the case of a cache miss, the secondary FTL 114 directly uses the secondary L2P table 212 to identify the physical location in the SLC block 202, where a portion of the primary L2P table 208 is stored. A portion of the primary L2P table 208 is cached in the read cache 214, and new entries are created in the read cache table 216. The physical address in the QLC block 200 corresponding to the logical address in the host command can be identified from a portion of the primary L2P table 208.

[0045] If a cache miss occurs while cache cache 214 is full, the secondary FTL 114 randomly selects the new entry corresponding to the cache miss and replaces the entry in the read cache table 216. The read cache table 216 is allocated from start to finish because read cache 214 fills up after power-on. New entries in read cache table 216 are logically linked to the latest cached portion of the primary L2P table 208 because the address corresponding to the latest cached portion in read cache 214 can be directly calculated from the entries in read cache table 216, as will be discussed below.

[0046] Referring to 304, a cache hit occurs when the entry corresponding to the requested logical address in the host command is contained in the read cache table 216. In the case of a cache hit, the secondary L2P table 212 points to the entry in the read cache table 216. The secondary FTL 114 calculates the address of the block corresponding to the read cache 214 based on the entry number of the entry in the read cache table 216 pointed to by the secondary L2P table 212. The block in the read cache 214 contains a portion of the primary L2P table 208 from which the physical location within the QLC block 200 can be identified. In an example, the address of a 256-byte block in the read cache 214 can be calculated as follows: Block address = cacheTableEntry# * chunksize + baseAddress, where “cacheTableEntry#” is the entry number in the read cache table 216, “chunksize” is the unit size of the block in the read cache 214, and “baseAddress” corresponds to the logical address specified by the host command. The secondary FTL 114 accesses and reads blocks from cache 214 to determine the physical address in QLC block 200 corresponding to the logical address specified in the host command.

[0047] Compared to conventional methods, maintaining the read cache 214 in this manner reduces computational resource utilization (e.g., memory and CPU processing power). For example, because the read cache address can be directly calculated from the read cache table 216 entries, it is not necessary to maintain a list of recently used (LRU) or free entries in the read cache table 216, each of which would require additional memory resources. Furthermore, since there is a fixed mapping between the cache table 216 entries and the actual read cache table 214 resources, the need to maintain forward and backward pointers for each entry is eliminated, thereby reducing the amount of memory resources required to store the read cache table 216.

[0048] Referring to 306, in the event of a non-cleared cache hit, the secondary L2P table 212 points to an entry in the non-cleared cache table 308. The entries in the non-cleared cache table 308 contain the physical addresses associated with non-cleared blocks in the read cache 214 within the QLC block 200. These entries are logically linked to entries in buffer 310, where updated data is accumulated for the corresponding portion of the secondary L2P table 212. Once the buffer is full, data from buffer 310 is programmed into the SLC block 202.

[0049] Figure 4-6This is a flowchart illustrating an example method 400 for programming data into a memory device by transmitting an indicator of a target charge level to the memory device according to some embodiments of the present disclosure. Method 400 may be performed by a processing device that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. In some embodiments, the processing means includes... Figure 1 The primary FTL 113 and secondary FTL 114. According to these embodiments, any one or more operations of method 400 may be performed by the primary FTL 113 or the secondary FTL 114. Although the processes are shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Other process flows are also possible.

[0050] At operation 405, the processing device receives a request specifying a logical address associated with a host-initiated data operation (e.g., read, write, or erase) targeting a memory device (e.g., memory device 130). The request may include an access request (e.g., a write command, a read command) received from a host system (e.g., host system 120) or based on said access request. The logical address is specified by the access request from the host system.

[0051] In some embodiments, the memory device is a NAND memory device comprising at least an SLC portion and a QLC portion. That is, the memory device comprises SLC blocks and QLC blocks. In these embodiments, logical addresses may correspond to physical locations within the QLC portion of the memory device.

[0052] The processing device identifies a physical location within a first portion of the memory device corresponding to the logical address contained in the request (operation 410). The physical location corresponds to a physical address determined by the processing device according to the primary L2P table. In an embodiment where the memory device is a NAND memory device, the processing device identifies a physical location within the QLC portion of the memory device corresponding to the physical address determined according to the logical address.

[0053] In some embodiments, the primary FTL of the processing device receives a request associated with a data operation initiated by the host, and the secondary FTL is responsible for identifying a physical address in a first portion of the memory device. According to these embodiments, the primary FTL may generate a lookup request and provide the lookup request to the secondary FTL containing the logical address, and the secondary FTL may provide the physical address to the primary FTL in response to the lookup request. References below Figure 5 Further details regarding the operations performed by the secondary FTL are discussed.

[0054] At operation 415, the processing device performs host-initiated data operations at a physical location within the first portion of the memory device. For example, the processing device may read data from or write data to the physical location.

[0055] like Figure 5 As shown, in some embodiments, method 400 may include operations 505, 510, 515, 520, and 525. According to these embodiments, operations 505, 510, 515, 520, and 525 may be performed as part of operation 410, wherein the processing device identifies the physical location corresponding to the logical address in the request. In some embodiments, operations 505, 510, 515, 520, and 525 are performed via a secondary FTL of the processing device in response to receiving a lookup request generated by a primary FTL based on an access request received from the host system by the primary FTL.

[0056] At operation 505, the processing device accesses a secondary L2P table (e.g., secondary L2P table 212) stored in a volatile memory component (e.g., volatile memory component 210). The secondary L2P table contains mappings between logical addresses and physical addresses within a second portion of the memory device dedicated to storing the primary L2P table (e.g., primary L2P table 208). The primary L2P table contains mappings between logical addresses and physical addresses within a first portion of the memory device targeted by a host-initiated operation (e.g., the portion of the memory device storing user data). The primary L2P table uses a first indirection size (e.g., 4KB), while the secondary L2P table uses a second indirection size smaller than the first indirection size (e.g., 256 bytes).

[0057] In embodiments where the memory device is a NAND memory device having an SLC portion and a QLC portion, the secondary L2P table contains a mapping between logical addresses and physical addresses within the SLC portion of the memory device, and the primary L2P table is stored in the memory device. According to these embodiments, the primary L2P table contains a mapping between logical addresses and physical addresses within the QLC portion of the memory device.

[0058] The processing device identifies the physical location of a portion of the primary L2P table within the second portion of the memory device that corresponds to the logical address in the request (operation 510). That is, the portion of the primary L2P table specifies the physical address within the first portion of the memory device corresponding to the logical address in the request. In some embodiments, the processing device determines the physical location within the second portion of the memory device based on the physical address specified by the secondary L2P table. In some embodiments, the processing device determines the physical location within the second portion of the memory device based on data read from a read cache.

[0059] In the example of the aforementioned operation, the processing device identifies the physical location within the SLC portion of the memory device corresponding to a portion of the primary L2P table, which provides a mapping between logical addresses and physical addresses in the QLC portion of the memory device. In this example, the processing device identifies the physical location within the SLC portion based on the physical address specified by the secondary L2P table.

[0060] At operation 515, the processing device accesses a portion of the primary L2P table from a physical location in the second part of the memory device. At operation 520, the processing device identifies the physical address in the first part of the memory device corresponding to the requested logical address based on the portion of the primary L2P table accessed from the physical location in the second part of the memory device. The accessed portion of the primary L2P table contains a mapping from logical addresses to physical addresses in the first part of the memory device. In the example of the aforementioned operations, the processing device uses a portion of the primary L2P table accessed from the SLC part of the memory device to identify the physical address in the QLC part of the memory device.

[0061] At operation 525, the processing device provides a physical address as output. In this example, the secondary FTL of the processing device provides the physical address as output to the primary FTL to perform a host-initiated operation (write, read, or erase) at a physical location in the memory device (operation 415).

[0062] like Figure 6 As shown, in some embodiments, method 400 may include operations 605, 610, 615, 620, 625, 630, 635, 640, 645, and 650. According to some embodiments, operation 605 may be performed as part of operation 410, wherein the processing device identifier corresponds to the physical address of the requested logical address.

[0063] At operation 605, the processing device accesses a secondary L2P table (e.g., secondary L2P table 212) stored in a volatile memory component (e.g., volatile memory component 210). The secondary L2P table contains mappings between logical addresses and physical addresses within a second portion of the memory device dedicated to storing primary L2P tables (e.g., primary L2P table 208). The primary L2P table contains mappings between logical addresses and physical addresses within a first portion of the memory device targeted by a host-initiated operation (e.g., the portion of the memory device storing user data).

[0064] At operation 610, the processing device determines whether the corresponding entry in the secondary L2P table points to an entry in the read cache table associated with the read cache. The read cache and the read cache table, together with the secondary L2P table, can be maintained in a volatile memory component (e.g., DRAM).

[0065] According to these embodiments, if the processing device determines that an entry in the secondary L2P table does not point to a cache table entry that has been missed, the processing device identifies the physical location of the portion of the primary L2P table within the second part of the memory device corresponding to the logical address in the request (operation 615). That is, the portion of the primary L2P table specifies the physical address within the first part of the memory device corresponding to the logical address in the request. The processing device determines the physical location within the second part of the memory device based on the physical address specified by the secondary L2P table.

[0066] At operation 620, the processing device accesses a portion of the primary L2P table from a physical location in the second part of the memory device, and at operation 625, the processing device caches the accessed portion of the primary L2P table. That is, the processing device adds a portion of the L2P table to a block in the read cache. The portion of the primary L2P table contains a mapping of logical addresses to physical addresses in the first part of the memory device.

[0067] At operation 630, the processing device adds a new entry to the read cache table corresponding to the portion of the L2P table added to the block in the read cache. The read cache table is allocated from start to finish because the cache fills up after power-on. If the read cache table is full, the processing device randomly selects an existing entry in the read cache table and replaces the existing entry with a new entry.

[0068] Returning to operation 610, if the processing unit determines that the entry in the secondary L2P table does indeed point to the read cache table entry, a cache hit occurs, and the processing unit accesses the read cache table entry at operation 640.

[0069] At operation 645, the processing apparatus identifies a read cache block from a plurality of blocks from the read cache based on a cache table entry. The size of each block corresponds to the indirect size used by the secondary L2P table (e.g., 256 bytes). To identify a block, the processing apparatus calculates the block address based on the entry number of the table entry. As an example, the processing apparatus can calculate the block address by multiplying the entry number by the size of each block and adding the product to the logical address specified in the request. As explained above, by directly calculating the block address based on the entry, the processing apparatus eliminates the need to maintain a recently used (LRU) policy or a pool of free entries.

[0070] At operation 650, the processing device accesses the identified cache block. The identified cache block contains a portion of the primary L2P table specifying the physical address mapping (within the first part of the memory device) used to request the specified logical address.

[0071] At operation 635, the processing device identifies the physical address in the first part of the memory device corresponding to the requested logical address based on a portion of the primary L2P table accessed from the physical location in the second part of the memory device (at operation 620) or based on a portion of the primary L2P table accessed from a block of the read cache (at operation 650). In this example, the processing device identifies the physical address in the QLC part of the memory device corresponding to the logical address specified in the request. In the case of a cache miss, the processing device identifies the physical address from the primary L2P table accessed from the SLC part of the memory device. In the case of a cache hit, the processing device identifies the physical address from a block of the read cache implemented in volatile memory (e.g., DRAM or HRAM).

[0072] The specific implementation of the subject matter may include one or more features, individually or in combination, as illustrated by examples below.

[0073] Example 1 is a system comprising: a memory device; and a processing device coupled to the memory device, the processing device being configured to perform operations including: receiving a request specifying a logical address associated with a host-initiated operation for a first portion of the memory device; accessing a logic-to-physical (L2P) table from a volatile memory component, the L2P table including a mapping between logical addresses and physical addresses in a second portion of the memory device; identifying an entry in the L2P table corresponding to the logical address; determining that the entry in the L2P table points to an entry in a read cache table; and calculating a corresponding entry based on the entry number of the entry in the read cache table. The block address of a block from a plurality of blocks in a read cache, the block in the read cache storing information about a physical address within the first portion of the memory device corresponding to the logical address specified in the request; the physical address corresponding to the logical address specified in the request based on the block identifier of the read cache corresponding to the block address, the physical address corresponding to a physical location within the first portion of the memory device; and the execution of the host start operation at the physical location within the first portion of the memory device, the physical location corresponding to the physical address corresponding to the logical address specified in the request.

[0074] Example 2 includes the system according to Example 1, wherein the calculation of the block address is further based on the block size in the read cache and the logical address specified in the request.

[0075] Example 3 includes a system according to any one or more of Examples 1 or 2, wherein the calculation of the block address includes adding the logical address to the result of multiplying the entry number by the block size.

[0076] Example 4 includes a system according to any one or more of Examples 1 to 3, wherein the L2P table is a first L2P table; and the second portion of the memory device stores a second L2P table, the second L2P table including a mapping between logical addresses and physical addresses in the first portion of the memory device.

[0077] Example 5 includes a system according to any one or more of Examples 1 to 4, wherein: the request is a first request; the logical address is a first logical address; the host-initiated operation is a first host-initiated operation; the entry is a first entry; and the operation further includes: receiving a second request specifying a second logical address associated with a second host-initiated operation for the first portion of the memory device; identifying a second entry in the first L2P table corresponding to the second logical address; accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and adding the accessed portion of the second L2P table to the read cache based on determining that the entry in the first L2P table does not point to the read cache table.

[0078] Example 6 includes a system according to any one or more of Examples 1 to 5, wherein the operation further includes adding a new entry corresponding to the accessed portion of the first L2P table added to the read cache table.

[0079] Example 7 includes a system according to any one or more of Examples 1 to 6, wherein adding the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

[0080] Example 8 includes a system according to any one or more of Examples 1 to 7, wherein the operation further includes: identifying a physical location within a second portion of the memory device corresponding to a portion of the second L2P table based on the first L2P table, the portion specifying a second physical address within the first portion of the memory device corresponding to a second logical address; identifying a second physical address within the first portion of the memory device corresponding to a second logical address specified by the second request based on the portion of the second L2P table; and performing a second host start operation at the second physical address within the first portion of the memory device.

[0081] Example 9 includes a system according to any one or more of Examples 1 to 8, wherein: the memory device is a NAND memory device; the first portion includes a plurality of four-level cell (QLC); and the second portion includes a plurality of single-level cell (SLC).

[0082] Example 10 includes a system according to any one or more of Examples 1 to 9, wherein the host-initiated operation includes one of the following: a read operation, a write operation, or an erase operation.

[0083] Example 11 includes a system according to any one or more of Examples 1 to 10, wherein the volatile memory component includes one of the following: dynamic random access memory (DRAM) or holographic random access memory (HRAM).

[0084] Example 12 is a method comprising: receiving, by a processing device, a request specifying a logical address associated with a host-initiated operation for a first portion of a memory device; accessing a logic-to-physical (L2P) table from a volatile memory component, the L2P table including a mapping between logical addresses and physical addresses in a second portion of the memory device; identifying an entry in the L2P table corresponding to the logical address; based on determining that the entry in the L2P table points to an entry in a read cache table, the processing device calculates a block address corresponding to a block among a plurality of blocks from a read cache, the blocks in the read cache storing information specifying a physical address within the first portion of the memory device corresponding to the requested logical address; the processing device, based on a block identifier in the read cache corresponding to the block address, to the physical address corresponding to the requested logical address, the physical address corresponding to a physical location within the first portion of the memory device; and performing the host-initiated operation at the physical location within the first portion of the memory device, the physical location corresponding to the physical address corresponding to the requested logical address.

[0085] Example 13 includes the method according to Example 12, wherein the calculation of the block address is further based on the block size in the read cache and the logical address specified in the request.

[0086] Example 14 includes the method according to any one or more of Examples 12 or 13, wherein the calculation of the block address includes adding the logical address to the result of multiplying the entry number by the block size.

[0087] Example 15 includes the method according to any one or more of Examples 12 to 14, wherein the L2P table is a first L2P table; and the second portion of the memory device stores a second L2P table, the second L2P table including a mapping between logical addresses and physical addresses in the first portion of the memory device.

[0088] Example 16 includes the method according to any one or more of Examples 12 to 15, wherein: the request is a first request; the logical address is a first logical address; the host-initiated operation is a first host-initiated operation; the entry is a first entry; and the operation further includes: receiving a second request specifying a second logical address associated with a second host-initiated operation for the first portion of the memory device; identifying a second entry in the first L2P table corresponding to the second logical address; accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and adding the accessed portion of the second L2P table to the read cache based on determining that the entry in the first L2P table does not point to the read cache table.

[0089] Example 17 includes the method according to any one or more of Examples 12 to 16, wherein the operation further includes adding a new entry corresponding to the accessed portion of the first L2P table added to the read cache table.

[0090] Example 18 includes the method according to any one or more of Examples 12 to 17, wherein adding the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

[0091] Example 19 includes a method according to any one or more of Examples 12 to 18, wherein the operation further includes: identifying a physical location within a second portion of the memory device corresponding to a portion of the second L2P table based on the first L2P table, the portion specifying a second physical address within the first portion of the memory device corresponding to a second logical address; identifying a second physical address within the first portion of the memory device corresponding to a second logical address specified by the second request based on the portion of the second L2P table; and performing a second host start operation at the second physical address within the first portion of the memory device.

[0092] Example 20 is a computer-readable storage medium including instructions that, when executed by a processing device, configure the processing device to perform operations including: receiving a request specifying a logical address associated with a host-initiated operation for a first portion of a memory device; accessing a logic-to-physical (L2P) table from a volatile memory component, the L2P table including a mapping between logical addresses and physical addresses in a second portion of the memory device; determining that an entry in the L2P table corresponding to the logical address points to an entry in a read cache table; and calculating a block address corresponding to a block among a plurality of blocks from a read cache based on the entry number of the entry in the read cache table, wherein the read... The cache stores information about a physical address corresponding to the logical address specified in the request within the first portion of the memory device; accesses the block corresponding to the block address in the read cache from the volatile memory component; identifies the block identifier corresponding to the block address in the read cache with the physical address corresponding to the logical address specified in the request, the physical address corresponding to a physical location in the first portion of the memory device; and performs the host start operation at the physical location in the first portion of the memory device, the physical location corresponding to the physical address specified in the request.

[0093] Figure 7 An example machine in the form of a computer system 700 is shown, within which an executable instruction set is provided to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to execute commands corresponding to the controller). Figure 1 (Operation of primary FTL 113 or secondary FTL 114). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0094] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0095] The example computer system 700 includes a processing device 702 that communicates with each other via a bus 730, a main memory 704 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM) such as SRAM), and a data storage system 718.

[0096] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 702 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0097] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0098] In one embodiment, instruction 726 includes instructions for implementing the corresponding FTL (e.g., Figure 1The machine-readable storage medium 724 contains instructions for the function of the primary FTL 113 or secondary FTL 114. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0099] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0100] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0101] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, each coupled to a computer system bus, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions.

[0102] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0103] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as ROM, RAM, disk storage media, optical storage media, flash memory components, etc.

[0104] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to the present disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system comprising: a memory device; and a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising: receiving a request specifying a logical address associated with a host initiated operation for a first portion of the memory device; and providing a lookup request to the secondary FTL based on the request, the lookup request specifying the logical address; the secondary FTL configured to perform operations comprising: accessing a logical to physical (L2P) table from a volatile memory component, the L2P table comprising mappings between logical addresses and physical addresses in a second portion of the memory device; identifying an entry in the L2P table corresponding to the logical address; determining that the entry in the L2P table points to an entry in a read cache table; calculating a block address corresponding to a block from among a plurality of blocks in a read cache based on a combination of an entry number of the entry in the read cache table, a unit size of blocks in the read cache, and the logical address associated with the host initiated operation for the first portion of the memory device, the block in the read cache storing information specifying a physical address within the first portion of the memory device corresponding to the logical address specified by the request; identifying a physical address corresponding to the logical address specified by the request based on the block of the read cache corresponding to the block address, the physical address corresponding to a physical location in the first portion of the memory device; and providing the physical address to the primary flash translation layer (FTL) in response to the lookup request, the primary FTL further configured to perform the host initiated operation at the physical location within the first portion of the memory device, the physical location corresponding to the physical address corresponding to the logical address specified by the request.

2. The memory system of claim 1, wherein the block size corresponds to an indirection size of the L2P table.

3. The memory system of claim 1, wherein the calculation of the block address comprises: adding the logical address to a result of the entry number multiplied by the block size.

4. The memory system of claim 1, wherein: the L2P table is a first L2P table; and the second portion of the memory device stores a second L2P table, the second L2P table comprising mappings between logical addresses and physical addresses in the first portion of the memory device.

5. The memory system of claim 4, wherein: the request is a first request; the logical address is a first logical address; the host initiated operation is a first host initiated operation; the entry is a first entry; and the operations further comprise: receiving a second request specifying a second logical address associated with a second host initiated operation for the first portion of the memory device; identifying a second entry in the first L2P table corresponding to the second logical address; accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and based on determining that the entry in the first L2P table does not point to the read cache table, adding the accessed portion of the second L2P table to the read cache.

6. The memory system of claim 5, wherein the operations further comprise: adding a new entry corresponding to the accessed portion of the first L2P table added to the read cache to the read cache table.

7. The memory system of claim 6, wherein adding the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

8. The memory system of claim 5, wherein the operations further comprise: based on the first L2P table identifying a physical location within the second portion of the memory device corresponding to the portion of the second L2P table, the portion specifying a second physical address within the first portion of the memory device corresponding to the second logical address; and based on the portion of the second L2P table identifying the second physical address within the first portion of the memory device corresponding to the second logical address specified by the second request; and performing the second host initiated operation at the second physical address within the first portion of the memory device.

9. The memory system of claim 1, wherein: the memory device is a NAND memory device; the first portion comprises a plurality of quad-level cells (QLCs); and the second portion comprises a plurality of single-level cells (SLCs).

10. The memory system of claim 1, wherein the host initiated operation comprises one of: a read operation, a write operation, or an erase operation.

11. The memory system of claim 1, wherein the volatile memory component comprises one of: a dynamic random access memory (DRAM) or a holographic random access memory (HRAM).

12. A method for memory operations, comprising: receiving, by a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host initiated operation for a first portion of a memory device; providing, by the primary flash translation layer (FTL) based on the request, a lookup request to a secondary FTL of the memory sub-system controller, the lookup request specifying the logical address; accessing, by the secondary FTL, from a volatile memory component, a logical-to-physical (L2P) table that includes mappings between logical addresses and physical addresses in a second portion of the memory device; identifying, by the secondary FTL, an entry in the L2P table that corresponds to the logical address; based on determining that the entry in the L2P table points to an entry in a read cache table, calculating, by the secondary FTL, a block address corresponding to a block from among a plurality of blocks in a read cache, based on a combination of an entry number of the entry in the read cache table, a unit size of blocks in the read cache, and the logical address specified in the request, the block in the read cache storing information specifying a physical address in the first portion of the memory device that corresponds to the logical address specified by the request; identifying, by the secondary FTL, based on the block of the read cache corresponding to the block address, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of the memory device; providing, by the secondary FTL, the physical address to the primary flash translation layer (FTL) in response to the lookup request; performing, by the primary FTL, the host-initiated operation at the physical location in the first portion of the memory device, the physical location corresponding to the physical address that corresponds to the logical address specified by the request.

13. The method of claim 12, wherein the block size corresponds to an indirection size of the L2P table.

14. The method of claim 12, wherein the calculating of the block address comprises: adding the logical address to a result of the entry number multiplied by the block size.

15. The method of claim 12, wherein: the L2P table is a first L2P table; and the second portion of the memory device stores a second L2P table that includes mappings between logical addresses and physical addresses in the first portion of the memory device.

16. The method of claim 15, wherein: the request is a first request; the logical address is a first logical address; the host-initiated operation is a first host-initiated operation; the entry is a first entry; and the operation further comprises: receiving a second request specifying a second logical address associated with a second host-initiated operation for the first portion of the memory device; identifying a second entry in the first L2P table that corresponds to the second logical address; accessing, from the second portion of the memory device identified based on the second entry in the first L2P table, a portion of the second L2P table; and based on determining that the entry in the first L2P table does not point to the read cache table, adding the accessed portion of the second L2P table to the read cache. ​ 17. The method of claim 16, wherein the operations further comprise: adding a new entry corresponding to the accessed portion of the first L2P table added to the read cache to the read cache table.

18. The method of claim 17, wherein adding the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry corresponding to the accessed portion of the first L2P table added to the read cache.

19. The method of claim 16, wherein the operations further comprise: identifying, based on the first L2P table, a physical location within the second portion of the memory device corresponding to the portion of the second L2P table, the portion specifying a second physical address within the first portion of the memory device corresponding to the second logical address; and identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device corresponding to the second logical address specified by the second request; and performing the second host-initiated operation at the second physical address within the first portion of the memory device.

20. A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: receiving, by a primary flash translation layer (FTL) of the processing device, a request specifying a logical address associated with a host-initiated operation for a first portion of a memory device; providing, by the primary flash translation layer (FTL) based on the request, a lookup request to a secondary FTL of the processing device, the lookup request specifying the logical address; accessing, by the secondary FTL from a volatile memory component, a logical-to-physical (L2P) table, the L2P table comprising mappings between logical addresses and physical addresses in a second portion of the memory device; determining, by the secondary FTL, that an entry in the L2P table corresponding to the logical address points to an entry in a read cache table; calculating, by the secondary FTL, a block address corresponding to a block from among a plurality of blocks in a read cache, based on a combination of an entry number of the entry in the read cache table, a unit size of a block in the read cache, and the logical address associated with the host-initiated operation for the first portion of the memory device, the block in the read cache storing information specifying a physical address within the first portion of the memory device corresponding to the logical address specified by the request; accessing, by the secondary FTL from the volatile memory component, the block of the read cache corresponding to the block address; identifying, by the secondary FTL, based on the block of the read cache corresponding to the block address, a physical address corresponding to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of the memory device; providing, by the secondary FTL, the physical address to the primary flash translation layer (FTL) in response to the lookup request; and performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device, the physical location corresponding to the physical address corresponding to the logical address specified by the request.

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