Modeling Method for Register Burst Access Based on UVM Storage Model

Abstract

The present invention discloses a modeling method for register burst access based on the UVM storage model, which creates a UVM verification environment for verifying a device under test; models a target register to obtain a register model; creates a storage model for burst access to the target register; creates a register block and adds the register model and the storage model to the register block; calls the reg2bus method of the adapter in the UVM verification environment to convert the burst access type into a single register access type; sets the register display prediction mechanism of the UVM verification environment to update the expected value and the mirror value of the register model; creates a dynamic array in the sequence of the register model and sets the size of the dynamic array; calls the burst_write method and the burst_read method of the storage model to read and write the target register. The present invention solves the verification vulnerability in the prior art that the UVM lacks support for the function of register burst read and write access behavior, and improves the verification efficiency and simulation efficiency of verification personnel.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and particularly relates to a modeling method for register burst access based on a UVM storage model. Background Art

[0002] Normally, the register model (RAL, Register Abstraction Layer) provided by UVM (Universal Verification Methodology) can very conveniently model the registers in the DUT (Device Under Test), and provides a series of register access interface methods to conveniently verify the read and write accesses and their functions of the registers in the DUT. For example, verification developers can easily complete a single read or write access to a certain register by calling the read and write methods of the register. However, each time a register read / write access method is called, only a single read or write access to a certain register is initiated, because the adapter in the register model can only process accesses to one register at a time. However, some common SOC (System on Chip) buses support burst read / write accesses. For example, the typical AHB bus (Advanced High-performance Bus) supports burst access transmission characteristics. That is to say, the register model interface methods provided by UVM do not support burst read / write accesses to registers, but only provide support for burst read / write accesses to storage, which brings trouble to the verification work of verification developers and requires more effort to verify the design of this register burst read / write access function. At the same time, this also means that the register burst read / write access function points will never be covered by testing, leaving verification loopholes, which may lead to the failure of chip tape-out. Moreover, due to the lack of support for burst read / write accesses, the efficiency of read / write accesses and simulation will also be affected. In addition, verification developers need to manually update and maintain the mirror values in the register model instead of using the prediction synchronization mechanism provided in the UVM register model. For a relatively complex chip, there are often thousands of registers, and this manual update and maintenance verification method is very inefficient.

[0003] The prior art has the following defects:

[0004] (1) The existing register model built based on the UVM verification methodology does not support the modeling of the burst read / write access behavior function of registers, resulting in no effective and feasible solution for the time being.

[0005] (2) Since UVM lacks support for the function of burst read and write access behavior of registers, this function point cannot be covered by testing, leaving a verification vulnerability that may lead to the failure of chip tape-out.

[0006] (3) The efficiency of register read and write access and simulation will also be adversely affected.

[0007] (4) Verification developers need to manually update and maintain the mirror values in the register model instead of using the prediction synchronization mechanism provided in the UVM register model. For a relatively complex chip, there are often thousands of registers, and this manual update and maintenance verification method is very inefficient. Summary of the Invention

[0008] According to an embodiment of the present invention, a modeling method for burst access of registers based on a UVM storage model is provided, which is characterized by including the following steps:

[0009] Create a UVM verification environment for verifying the device under test;

[0010] Model the target registers of the device under test to obtain a register model;

[0011] Create a storage model in the UVM verification environment for burst access to the target registers;

[0012] Create a register block in the UVM verification environment and add the register model and the storage model to the register block;

[0013] Call the reg2bus method of the adapter in the UVM verification environment to convert the burst access type generated when calling the storage model into a single register access type;

[0014] Set the register display prediction mechanism in the UVM verification environment to update the expected value and mirror value of the register model;

[0015] Create a dynamic array in the sequence of the register model and set the size of the dynamic array;

[0016] Call the burst_write method and burst_read method of the storage model to read and write the target registers.

[0017] Furthermore, the register model is derived from the uvm_reg register class.

[0018] Furthermore, the depth of the storage model is the length of the target registers supported by the device under test.

[0019] Furthermore, the bit width of the storage model is the same as the bit width of the target registers.

[0020] Further, when adding a register model and a storage model to a register block, the get_offset method provided by the class library of the UVM verification environment is called using the handle of the first target register accessed by a burst to obtain the physical address of the first target register accessed by the burst as the starting address of the storage model.

[0021] Further, the register display prediction mechanism of the UVM verification environment is set to update the expected value and mirror value of the register model, including the following sub-steps:

[0022] In the UVM verification environment, a corresponding address mapping table and adapter are set for the predictor of the UVM verification environment.

[0023] Connect the broadcast port of the register bus transaction data monitored by the register bus monitor in the UVM verification environment to the receiving port of the predictor.

[0024] Further, when calling the burst_write method and burst_read method of the storage model to read and write the target register, the methods for obtaining the expected value of the target register and the mirror value of the target register in the UVM verification environment are called for verification.

[0025] Further, converting the burst access type generated when calling the storage model into a single register access type includes the following sub-steps:

[0026] When calling the burst_write method and burst_read method of the storage model, a request sequence and sequence elements of the storage model data request type are generated.

[0027] Call the reg2bus method of the adapter to convert the sequence elements of the storage model data request type into request sequence elements of the register bus transaction type.

[0028] Convert the burst access type generated when calling the storage model into a single register access type.

[0029] According to the modeling method of register burst access based on the UVM storage model in the embodiments of the present invention, the interface method of the storage model in the UVM verification environment is used to make the embodiments simple and easy to implement. At the same time, the adapter of the register model is used to convert the burst register access into single register read and write access, thereby realizing the burst read and write access of the register, solving the verification vulnerability that the prior art lacks support for the function of burst read and write access behavior of registers in UVM, and improving the verification efficiency and simulation efficiency of verification personnel.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed technology. Description of the Drawings

[0031] Figure 1 It is a schematic diagram of a modeling method for register burst access based on the UVM storage model according to an embodiment of the present invention;

[0032] Figure 2 It is a flowchart of the steps of a modeling method for register burst access based on the UVM storage model according to an embodiment of the present invention;

[0033] Figure 3 It is Figure 2 a flowchart of the sub-steps of step S5 in

[0034] Figure 4 It is Figure 2 a flowchart of the sub-steps of step S6 in Detailed Embodiment

[0035] The register bus of this embodiment includes the following signals:

[0036] bus_valid: When it is 1, the bus data is valid; when it is 0, it is invalid. This valid signal only lasts for one clock. The DUT should sample the data on the bus during the period when it is 1. If it is a write operation, the DUT should sample the data on the bus and write it into its internal register after detecting that the bus data is valid in the next clock. If it is a read operation, the DUT should read the register data to the data bus after detecting that the bus data is valid in the next clock.

[0037] bus_op: Bus read and write operations. When it is 2'b00, it is an operation to write a single register to the bus; when it is 2'b01, it is an operation to read a single register from the bus; 2'b10 is a burst read operation initiated to the bus; 2'b11 is a burst write operation initiated to the bus.

[0038] bus_addr: Represents the address on the address bus, and its bit width is 16 bits.

[0039] bus_wr_data: Represents the 16-bit wide data on the write data bus.

[0040] bus_rd_data: Represents the 16-bit wide data read from the data bus.

[0041] Here, the address bus width is 16 bits, and the data bus width is also 16 bits. The bit width of the burst access read and write register burst_reg exemplified here is also 16 bits, that is, the same as the bus width. The bus addresses assigned to the burst access read and write registers burst_reg0~7 for us are 16'h20~16'h27.

[0042] If a burst access is to be performed on the above burst_reg, only a read / write access to the register burst_reg0 needs to be initiated, and at this time, the bus_vaild signal needs to be at a high effective level. Specifically, it is divided into the following two processes: burst write and burst read access:

[0043] (1) When a burst write access operation is initiated, while the bus_vaild signal is high, the data on the write data bus bus_wr_data is sequentially written into the registers burst_reg0~7. The specific number of registers written depends on the length of the burst access.

[0044] (2) When a burst read access operation is initiated, it is detected that the bus_valid signal is high, and then the values of the registers burst_reg0~7 are sequentially transferred to the read data bus bus_rd_data. The specific number of registers transferred to the read data bus also depends on the length of the burst access.

[0045] The following will describe in detail the preferred embodiments of the present invention in conjunction with the accompanying drawings, and further elaborate on the present invention.

[0046] First, in conjunction with Figures 1 - 4 Describe a modeling method for register burst access based on the UVM storage model according to an embodiment of the present invention, which is used for chip verification and has a wide range of application scenarios.

[0047] As Figures 1 - 4 shown, the modeling method for register burst access based on the UVM storage model according to an embodiment of the present invention includes the following steps:

[0048] In S1, as Figures 1 - 2 shown, create a UVM verification environment for verifying the device under test.

[0049] In S2, as Figures 1 - 2 shown, model the target register of the device under test to obtain a register model.

[0050] Furthermore, the register model is derived from the uvm_reg register class.

[0051] In S3, as Figures 1 - 2 shown, create a storage model in the UVM verification environment for burst access to the target register.

[0052] Furthermore, the depth of the storage model is the length of the target register supported by the device under test.

[0053] Furthermore, the bit width of the storage model is the same as the bit width of the target register.

[0054] In S4, as Figures 1 - 2As shown, a register block is created in the UVM verification environment, and the register model for the burst access target register and the memory model for burst register access are added to the register block.

[0055] Furthermore, when adding the register model and the memory model to the register block, the get_offset method provided by the class library of the UVM verification environment is called using the handle of the first target register accessed by burst to obtain the physical address of the first target register accessed by burst as the starting address of the memory model. That is, it is equivalent to accessing the target register accessed by burst as the target storage unit modeled in the memory model. In this way, the burst_write method and burst_read method provided by the UVM verification environment can be used to perform burst access to the register.

[0056] In S5, as Figures 1 - 2 shown, the reg2bus method of the adapter in the UVM verification environment is called to convert the burst access type generated when calling the memory model into a single register access type, so that the register display prediction mechanism can work properly.

[0057] Furthermore, converting the burst access type generated when calling the memory model into a single register access type includes the following sub-steps:

[0058] In S51, as Figure 3 shown, request sequences and sequence elements of the memory model data request type are generated when calling the burst_write method and burst_read method of the memory model;

[0059] In S52, as Figure 3 shown, the reg2bus method of the adapter is called to convert the sequence elements of the memory model data request type into request sequence elements of the register bus transaction type;

[0060] In S53, as Figure 3 shown, the burst access type generated when calling the memory model is converted into a single register access type.

[0061] In S6, as Figures 1 - 2 shown, the register display prediction mechanism of the UVM verification environment is set to update the expected value and mirror value of the register model.

[0062] Furthermore, setting the register display prediction mechanism of the UVM verification environment to update the expected value and mirror value of the register model includes the following sub-steps;

[0063] In S61, as Figure 1 、 4As shown, in the UVM verification environment, set the corresponding address mapping table and adapter for the predictor.

[0064] In S62, as Figure 1 、 4 shown, connect the register bus transaction data broadcast port monitored by the register bus monitor in the UVM verification environment to the receiving port of the predictor, so that the register model can automatically update and synchronize the expected value and the mirrored value.

[0065] In S7, as Figures 1 - 2 shown, create a dynamic array in the sequence of the register model and set the size of the dynamic array, that is, the length of the burst access.

[0066] In S8, as Figures 1 - 2 shown, call the burst_write method and burst_read method of the storage model to read and write the target register.

[0067] Furthermore, when calling the burst_write method and burst_read method of the storage model to read and write the target register, call the relevant acquisition methods of the expected value and the mirrored value of the target register for verification, so as to verify whether this embodiment is simple and feasible.

[0068] As Figure 1 shown, the process and principle of the burst read access to the register are as follows:

[0069] (1) Set the length of the target register for the burst read access and the dynamic array of the burst read access data.

[0070] (2) Call the storage burst read access method provided by the storage model in the UVM verification environment to perform a read access to the target register.

[0071] (3) The storage model generates a request sequence and generates sequence elements of the storage model data request type.

[0072] (4) Call the reg2bus method of the adapter to convert the sequence elements of the above storage model data request type into request sequence elements of the register bus transaction type. Here, it is necessary to automatically convert the burst read access type generated by calling the storage model into a single register read access type.

[0073] (5) These individual register bus transaction type request sequence elements are transmitted to the register bus sequencer, and then by the sequencer to the register bus driver. Then the register bus driver drives these individual register bus transaction type request sequence elements onto the register bus and sequentially returns the value of the target register read, and places the returned value back into the transaction request data.

[0074] (6) The register bus monitor monitors the transaction request data driven onto the register bus as described above and broadcasts it one by one to the predictor.

[0075] (7) The predictor updates and synchronizes the mirror value and the actual value of the burst read access register according to the received register bus transaction request data.

[0076] (8) Call the bus2reg method of the adapter to pass the value read in the bus transaction request data to the transaction type in the register model, which is equivalent to returning it to the register model. At this time, the values of the burst access registers can be seen sequentially on the register read bus.

[0077] As Figure 1 shown, the process and principle of the burst write access register are as follows:

[0078] (1) Set the length of the target register for burst write access and the dynamic array of burst write access data.

[0079] (2) Call the storage burst write access method of the storage model provided by the UVM verification environment to perform a write access to the target burst access register.

[0080] (3) The storage model generates a request sequence and generates sequence elements of the storage model data request type.

[0081] (4) Call the reg2bus method of the adapter to convert the sequence elements of the storage model data request type into request sequence elements of the register bus transaction type. Here, it is necessary to automatically convert the burst write access type generated by calling the storage model into individual register write access types.

[0082] (5) These individual register bus transaction type request sequence elements are transmitted to the register bus sequencer, and then by the sequencer to the register bus driver. Then the register bus driver drives them onto the register bus according to the previously set dynamic array of burst write access and the length information of the burst write access register.

[0083] (6) The register bus monitor monitors the transaction request data driven onto the register bus as described above, and then broadcasts it to the predictor one by one.

[0084] (7) The predictor updates and synchronizes the mirror value and the actual value of the target register for the burst write access according to the received register bus transaction request data.

[0085] (8) At this time, the data in the previously set burst write access array can be seen to be written into the target register accessed by burst on the register write bus in sequence, and the success of the write can also be verified by initiating a read access again.

[0086] In the prior art, the UVM verification environment does not provide an interface method for burst read and write access to the target register, but provides an interface method for burst read and write access to the memory. We can utilize this feature to solve the modeling problem of register burst read and write access. This embodiment utilizes the existing interface method of the memory model in the UVM verification environment, making the method proposed in this embodiment more simple and feasible; and uses the adapter of the register model to convert the burst register access into the read and write access of a single register, so as to realize the burst read and write access of the register. In this way, the method proposed in this embodiment can be seamlessly connected with the display prediction mechanism provided by the UVM verification environment for the register model, so that the prediction update of the mirror value and the expected value of the target register for burst access can be conveniently realized.

[0087] As described above, with reference to Figures 1 - 4 The modeling method of register burst access based on the UVM memory model according to the embodiment of the present invention is described. Utilizing the interface method of the memory model in the UVM verification environment makes this embodiment simple and feasible. At the same time, the adapter of the register model is used to convert the burst register access into the read and write access of a single register, so as to realize the burst read and write access of the register, solve the verification vulnerability that the prior art lacks support for the function of register burst read and write access behavior in UVM, and improve the verification efficiency and simulation efficiency of the verification personnel.

[0088] It should be noted that in this specification, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0089] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be construed as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A modeling method for register burst access based on the UVM storage model, characterized in that The steps are as follows: Create a UVM verification environment for verifying the device under test; Model the target register of the device under test to obtain a register model; Create a storage model in the UVM verification environment for burst access to the target register; Create a register block in the UVM verification environment and add the register model and the storage model to the register block; Call the reg2bus method of the adapter of the UVM verification environment to convert the burst access type generated when calling the storage model into a single register access type; Set the register display prediction mechanism of the UVM verification environment to update the expected value and mirror value of the register model; Create a dynamic array in the sequence of the register model and set the size of the dynamic array; Call the burst_write method and burst_read method of the storage model to read and write the target register; Convert the burst access type generated when calling the storage model into a single register access type, including the following sub-steps: Generate a request sequence and sequence elements of the storage model data request type when calling the burst_write method and burst_read method of the storage model; Call the reg2bus method of the adapter to convert the sequence elements of the storage model data request type into a request sequence element of the register bus transaction type; Convert the burst access type generated when calling the storage model into a single register access type.

2. The modeling method for register burst access based on the UVM storage model according to claim 1, wherein The register model is derived from the uvm_reg register class.

3. The modeling method for register burst access based on the UVM storage model according to claim 1, characterized in that The depth of the storage model is the length of the target register supported by the device under test.

4. The modeling method for register burst access based on the UVM storage model according to claim 1, wherein The bit width of the storage model is the same as the bit width of the target register.

5. The modeling method for register burst access based on the UVM storage model according to claim 1, characterized in that When adding the register model and the storage model to the register block, use the handle of the first target register accessed by burst to call the get_offset method provided by the class library of the UVM verification environment to obtain the physical address of the first target register accessed by burst as the starting address of the storage model.

6. The modeling method for register burst access based on the UVM storage model according to claim 1, wherein Set the register display prediction mechanism of the UVM verification environment to update the expected value and mirror value of the register model, including the following sub-steps; In the UVM verification environment, set the corresponding address mapping table and the adapter for the predictor of the UVM verification environment; Connect the register bus transaction data broadcast port monitored by the register bus monitor of the UVM verification environment to the receiving port of the predictor.

7. The modeling method for register burst access based on the UVM storage model according to claim 1, wherein When calling the burst_write method and burst_read method of the storage model to read and write the target register, call the methods for obtaining the expected value and mirror value of the target register in the UVM verification environment for verification.

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