Parallel test apparatus and method for multi-stack memory packages

Abstract

The application discloses a parallel testing device and method for a multi-stack memory package. The parallel testing device comprises a testing machine and a first number of AND gate operators. The testing machine comprises a first number of comparators. The outputs of the first number of AND gate operators are connected to the first inputs of the first number of comparators one by one. The first inputs of each AND gate operator are connected to pins with the same preset identification of each single memory at the same time, and the preset identifications of the pins connected to the first inputs of each AND gate operator are different from each other. The second inputs of the AND gate operators are used for inputting a preset reference voltage. The second inputs of the comparators are used for inputting a preset expected voltage. The parallel testing device for the multi-stack memory package can simultaneously perform parallel testing on a plurality of single memories in the multi-stack memory package, thereby greatly reducing the testing time, improving the testing efficiency, and reducing the testing time cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a parallel testing apparatus and method for multi-stacked memory packages. Background Technology

[0002] The integration density of DRAM (Dynamic Random Access Memory) is increasing, and multi-layer memory packages that integrate multiple monolithic memory chips vertically or horizontally are becoming more and more common. A package containing only one memory chip is called a monolithic package, while a package that stacks or arranges multiple monolithic memory chips in multiple layers or multiple rows in parallel is called a multi-memory stacked package.

[0003] Multi-memory stacked packages (MMCs) consist of multiple stacked single-chip memories. The reduced measurement sensitivity of the output pins in MMCs leads to measurement uncertainty. This is because the outputs of multiple stacked single-chip memories are simultaneously accumulated to determine the result. In other words, if the output pins of N single-chip memories all output high-speed or low-speed data, the combined pin result will naturally output high-speed or low-speed data, and the measurement will proceed without issue. However, if, out of the N single-chip memories that should be connected to high-speed or low-speed data, n (n≤N) single-chip memories output data opposite to low-speed or high-speed, the output value may be "n / N" or no result. In such cases, the test equipment may produce inaccurate test results due to unstable sensing.

[0004] In existing technologies, testing a multi-memory stack package requires testing each individual memory chip sequentially, resulting in a total of N tests for the N individual memory chips in the entire multi-memory stack package. This testing time is more than N times that required to test a single memory chip package, significantly increasing testing time costs and placing a heavy burden on production. Summary of the Invention

[0005] The purpose of this disclosure is to provide a parallel testing apparatus and method for multi-stacked memory packages. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0006] According to one aspect of the present disclosure, a parallel testing apparatus for a multi-stacked memory package is provided, wherein the multi-stacked memory package includes a plurality of identical single-chip memories, each single-chip memory includes a first number of pins with different preset identifiers, the parallel testing apparatus includes a test machine and a first number of AND gate operators, the test machine includes a first number of comparators, and the output terminals of the first number of AND gate operators are connected one-to-one with the first input terminals of the first number of comparators.

[0007] Each of the AND gate arithmetic units has its first input terminal connected to a pin of each of the single-chip memory with the same preset identifier, and the preset identifiers of the pins connected to the first input terminals of each of the AND gate arithmetic units are different from each other.

[0008] The second input terminal of the AND gate is used to input a preset reference voltage; the second input terminal of the comparator is used to input a preset desired voltage.

[0009] According to another aspect of the present disclosure, a parallel testing method for multi-stacked memory packages is provided, implemented using the parallel testing apparatus described above. The parallel testing method includes:

[0010] Start one of the single-chip memory in the multi-stacked memory package, which will cause the other preset single-chip memory to perform the startup action at the same time;

[0011] Each AND gate arithmetic unit performs an operation on the electrical signal received at its first input terminal and the preset reference voltage received at its second input terminal, and outputs the operation result.

[0012] Each comparator compares the received calculation result with a preset expected voltage to obtain a test result.

[0013] One aspect of the technical solution provided by the embodiments of this disclosure may include the following beneficial effects:

[0014] The parallel testing apparatus for multi-stacked memory packages provided in this disclosure can simultaneously perform parallel testing on multiple single-chip memory within the multi-stacked memory package, thereby greatly reducing testing time, improving testing efficiency, and reducing testing time costs.

[0015] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram showing the connection between a parallel test apparatus for a multi-stacked memory package and the multi-stacked memory package in one embodiment of this application is shown.

[0018] Figure 2 This invention provides a comparison diagram of the output signal waveforms under different states of a multi-stacked memory package in another embodiment of this application.

[0019] Figure 3 A schematic diagram of the structure of a parallel testing apparatus according to another embodiment of this application is shown;

[0020] Figure 4 A schematic diagram of the structure of a parallel testing apparatus according to another embodiment of this application is shown;

[0021] Figure 5 A flowchart illustrating a parallel testing method for a multi-stacked memory package according to an embodiment of this application is shown;

[0022] Figure 6 It shows Figure 5 The flowchart of step S30 in the method shown;

[0023] Figure 7 It shows Figure 5 The diagram illustrates the principle of comparing the calculation result with the preset expected voltage in step S30 of the method shown. Detailed Implementation

[0024] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0025] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0026] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0027] like Figure 1 As shown, one embodiment of this application provides a parallel testing apparatus for a multi-stacked memory package. The multi-stacked memory package 1 includes several identical single-chip memories, each of which can be represented as M(1), M(2), ..., M(N-1), M(N), where N is a positive integer representing the number of single-chip memories included in the multi-stacked memory package 1. A total of N single-chip memories are vertically stacked or horizontally arranged to form a multi-stacked memory package 1. Each single-chip memory includes a first number of pins 2 with different preset identifiers. For example, the preset identifiers can be numbers, assigning different numbers to each pin 2 of each single-chip memory. These numbers are only for distinguishing each pin 2, not for limiting each pin 2.

[0028] The parallel testing device includes a test unit 5 and a first number of AND gates 4. The test unit 5 includes a first number of comparators 6, and the outputs of the first number of AND gates 4 are connected one-to-one with the first inputs of the first number of comparators 6. The first input 10 of each AND gate 4 is used to simultaneously connect to pins 2 of each single-chip memory with the same preset identifier, so that each pin 2 is connected to one of the AND gates 4, and the preset identifiers of the pins 2 connected to the first input 10 of each AND gate 4 are different from each other. The second input of the AND gate 4 is used to input a preset reference voltage. The second input of the comparator 6 is used to input a preset desired voltage. This parallel testing device can be used to perform parallel testing on several single-chip memories in at least one multi-stacked memory package 1. Assuming that the number of multi-stacked memory packages 1 tested simultaneously using this parallel test device is p, the number of single-chip memory included in the multi-stacked memory package 1 is N, and the number of pins 2 of each single-chip memory is k, then the number of AND gates 4 included in the parallel test device is at least p*N*k, and the number of comparators 6 included in the test machine 5 is also at least p*N*k, where p, N, and k are all positive integers.

[0029] In some embodiments, pins with the same preset identifier in each individual memory chip of the multi-memory stack package 1 can be pins used to perform the same function, and the pins with the same preset identifier in each individual memory chip are connected to the first input terminal 10 of the same AND gate arithmetic unit 4. Other pins with the same preset identifier are respectively connected to the first input terminal 10 of their respective corresponding AND gate arithmetic unit 4.

[0030] like Figure 2 As shown, the N signals within solid box 800 are the N output signals appearing in the multi-memory stacked package 1. These N signals originate from the output segments of the N single-chip memories output from the multi-memory stacked package, and all signals are output normally. Therefore, if output signal 420 is undistorted, it is directly output through the conductive contact point 8 of the chip under test fixture 7 and reaches the test machine 5. The test machine 5 can stably sense the signal and determine whether it is valid or invalid. However, if, like in solid boxes 810, 820, and 830, some or most of the N signals are distorted, then the signal reaching the test machine 5 will be distorted like signals 510, 610, and 710, easily leading to unclear determination of validity or invalidity. Signal 700 is lower than the voltage reference value, and the sum of signals 710 is more distorted. To improve signal distortion, multiple AND gates 4 are used, which can reduce signal distortion and achieve accurate testing.

[0031] In some implementations, specialized DUT (Device Under Test) jigs are used to more efficiently test the proper functioning or failure of multi-memory stacked packages using a test machine. For example... Figure 3 As shown, in some embodiments, the parallel testing apparatus further includes at least one chip under test fixture 7, each fixture 7 being used to accommodate and fix a multi-stacked memory package 1. The chip under test fixture 7 is provided with a first number of conductive contacts 8, each conductive contact 8 being connected to the first input terminal 10 of an AND gate arithmetic unit 4. Each conductive contact 8 is also used to simultaneously connect pins 2 of each single-chip memory with the same preset identifier. Each conductive contact 8 can be connected to the first input terminal 10 of the AND gate arithmetic unit 4 via a wire. For example, pins numbered A006 of each single-chip memory are all connected to the same conductive contact 8, and pins with different preset identifiers are connected to different conductive contacts 8. Therefore, from the perspective of the conductive contacts 8 on the chip under test fixture 7, N single-chip memories are connected to the same pin. That is, activating one single-chip memory will cause all N single-chip memories to simultaneously perform the activation action. Activating one single-chip memory in this way can activate all single-chip memories in the multi-stacked memory package 1, thereby reducing the test time to 1 / N of the traditional test time.

[0032] Each conductive contact 8 is connected to the first input terminal 10 of an AND gate arithmetic unit 4. In some embodiments, all signals emitted by the N single-chip memories of the multi-memory stack package 1—whether high-speed or low-speed signals—are output as high-speed data if all signals are the same, and as low-speed data if not all signals are the same among the N single-chip memories.

[0033] In some implementations, the same signal is simultaneously applied to all the individual memory chips in the multi-memory stacked package 1, as if testing a single memory chip. In this case, the signal-applying fixture is composed of the internal circuitry of the multi-memory stacked package consisting of N individual memory chips, allowing the signal to be simultaneously transmitted to each of the internal memory chips. That is, from the perspective of the chip under test fixture, all signals from the N memory chips are merged into one signal. Therefore, after reading the signal, the specific output pin used in the determination process must also be treated the same as the other pins, merging the N signals from the corresponding specific output pins of the N memory chips into one, forming the corresponding circuitry of the chip under test fixture for measurement. Similarly, the signals from all output pins are merged in the same way, and the chip under test fixture is connected to the corresponding pin.

[0034] In some implementations, for ease of connection, pins of each individual memory chip with the same preset identifier converge to a single conductive contact point. Each conductive contact point contacts a conductive contact point 8 when the chip under test fixture 7 clamps and fixes the multi-stacked memory package 1, thereby achieving electrical connection between the conductive contact point and its corresponding conductive contact point 8. Each conductive contact point can be fixedly positioned on a fixed location on the outer surface of the multi-stacked memory package 1 to facilitate contact with its corresponding conductive contact point 8. The conductive contact point 8 can be, for example, a metal sphere. Additionally, the conductive contact point can be used to adjust appropriate DRAM instructions to meet testing requirements.

[0035] In some embodiments, the chip under test fixture includes a cuboid structure comprising a first number of conductive contact points 8, at least three side plates, and at least one movable cover plate. The cuboid structure is used to accommodate multiple stacked memory packages and to clamp and secure the multiple stacked memory packages by closing the movable cover plate. For example... Figure 3As shown, the chip under test fixture 7 includes three side plates 400 and two movable cover plates 430. The three side plates 400 are connected in sequence, and the two movable cover plates 430 are respectively connected to one of the side plates 400. In some embodiments, the chip under test fixture 7 can be a cuboid box with a movable cover plate. This cuboid box can accommodate and place multiple stacked memory packages and clamp and fix the multiple stacked memory packages by closing the movable cover plate. Each conductive contact point 8 is provided on the inner surface of the movable cover plate of the chip under test fixture. Each conductive contact point 8 is correspondingly provided with each conductive bonding point provided on the outer surface of the multiple memory stacked package 1. After the movable cover plate is closed, each conductive contact point 8 contacts a conductive bonding point, thereby realizing the electrical connection between the conductive bonding point and the corresponding conductive contact point 8.

[0036] In some implementations, in order to test the multi-memory stack package 1, a device consisting of a small circuit board connecting various address pins and control pins and a socket supporting the multi-memory stack package can be used to stably connect signals to the circuit board or wires of the corresponding pins of the multi-memory stack package 1.

[0037] In some implementations, such as Figure 3 As shown, the parallel testing device also includes an interface board 9. The chip under test (DUT) fixture 7 and each AND gate unit 4 are mounted on the interface board 9, with the AND gate units 4 in close contact with the DUT fixture 7. The AND gate units 4 are designed to effectively prevent signal distortion output from the multi-memory stacked package 1. Placing the AND gate units 4 in close contact with the DUT fixture 7 minimizes signal distortion and improves test accuracy. The test machine 5 can also be mounted on the interface board 9, allowing for a fixed connection between the multi-memory stacked package 1 and the test machine 5. The interface board 9 is physically detachable.

[0038] In some embodiments, each microcontroller is equipped with a switch for turning the corresponding microcontroller on or off. During actual operation, the switch of any one microcontroller can be turned on or off, allowing only that microcontroller to operate independently. Turning off a microcontroller's switch prevents it from being tested; turning it on allows it to be tested. In some embodiments, the microcontroller can also be selected for testing by disconnecting its pins from the corresponding conductive contact point 8.

[0039] In some implementations, such as Figure 4As shown, the test machine 5 also includes a first number of data writing terminals 630, and the parallel test device also includes a first number of selection switches 631 and a first number of connection terminals 632. Each data writing terminal 630 is connected to a connection terminal 632, and each selection switch 631 can select to connect to a corresponding conductive contact point 8. The data writing terminals 630 are used to write data. When it is necessary to write data to the monolithic memory of the multi-memory stack package 1, the selection switch 631 is connected to the connection terminal 632, and then the data is written by the data writing terminal 630. The data transmission line is data writing terminal 630 → connection terminal 632 → selection switch 631 → conductive contact point 8 → monolithic memory. When testing is required, the selection switch 631 is connected to the first input terminal 10 of the AND gate arithmetic unit 4.

[0040] The parallel testing apparatus for multi-stacked memory packages provided in this disclosure can simultaneously perform parallel testing on multiple single-chip memory within the multi-stacked memory package, thereby greatly reducing testing time, improving testing efficiency, and reducing testing time costs.

[0041] Another embodiment of this application provides a parallel testing method for multi-stacked memory packages, implemented using the parallel testing apparatus of any of the above embodiments, such as... Figure 5 As shown, this parallel testing method includes:

[0042] S10. Start one of the single-chip memory in the multi-stacked memory package, which will drive the other preset single-chip memory to perform the startup action at the same time.

[0043] S20. Each AND gate arithmetic unit 4 performs a calculation on the electrical signal received at its first input terminal 10 and the preset reference voltage received at its second input terminal, and outputs the calculation result.

[0044] S30. Each comparator compares the received calculation result with the preset expected voltage to obtain the test result.

[0045] Specifically, such as Figure 6 As shown, step S30 includes:

[0046] S301. Each comparator compares the received calculation result with the preset expected voltage.

[0047] S302. If the preset desired voltage is a first voltage value, then when the voltage received from the output of the corresponding AND gate arithmetic unit 4 at the first input terminal of comparator 6 is greater than the first voltage value, it is determined to be valid; otherwise, it is determined to be invalid.

[0048] S303. If the preset desired voltage is the second voltage value, then when the voltage received from the output of the corresponding AND gate arithmetic unit 4 at the first input terminal of the comparator 6 is lower than the second voltage value, it is determined to be valid; otherwise, it is determined to be invalid. The first voltage value is greater than the second voltage value.

[0049] Vref (Voltage Reference) represents the reference voltage at the second input terminal of AND gate 4, which can be set according to the multi-stack memory package configuration. Comparator 6 is used to determine the expected value of the output. The preset expected voltage is the pre-set output reference value, including a high voltage Voh (i.e., the first voltage value) and a low voltage Vol (i.e., the second voltage value). Voh is an abbreviation for Output Voltage High, and Vol is an abbreviation for Output Voltage Low. The preset expected voltage is input to the second input terminal 11 of comparator 6. When the preset expected voltage is a high voltage Voh, the voltage received at the first input terminal of comparator 6 from the output terminal of the corresponding AND gate 4 is considered valid (PASS) only if it is greater than the preset expected voltage Voh value, otherwise it is considered invalid (FAIL). When the preset expected voltage is a low voltage Vol, the voltage received at the first input terminal of comparator 6 from the output terminal of the corresponding AND gate 4 is considered valid only if it is lower than the Vol value, otherwise it is considered invalid (FAIL). The voltage 900 received at the first input of comparator 6 from the output of the corresponding AND gate arithmetic unit 4 is determined to be valid or invalid (FAIL) at the strobe point 910. Figure 7 As shown, 903 represents the failure value region of voltage 900, 904 represents the effective value region of voltage 900 higher than Voh, and 905 represents the effective value region of voltage 900 lower than Vol.

[0050] The parallel testing method for multi-memory stacked packages does not sequentially test each individual memory chip within the package. Instead, it uses a tester to simultaneously test all individual memory chips in parallel and read the test data, thereby improving test accuracy. In some embodiments, the tester 5 also includes a display device that simultaneously displays whether the expected value of each tested individual memory chip has passed the test, distinguishing the output values.

[0051] In some implementations, to reduce signal distortion during a single test of a multi-memory stacked package, multiple repeated tests can be performed, allowing for separate testing of individual memory chips of 1 / 2, 1 / 4, or 1 / 8 of the multi-memory stacked package 1. Other pre-defined individual memory chips are configured by pre-activating their respective switches. Specifically, the individual memory chips to be tested are selected by turning certain switches on or off. Turning off a switch prevents testing of that chip, while turning it on allows testing. This allows for separate testing of the individual memory chips of 1 / 2, 1 / 4, or 1 / 8 of the multi-memory stacked package 1. In some implementations, the individual memory chips participating in the test can also be selected by disconnecting the connection between the chip chip's pins and the corresponding conductive contact point 8.

[0052] The parallel testing method for multi-stacked memory packages provided in this application can simultaneously perform parallel testing on multiple single-chip memory within the multi-stacked memory package, thereby greatly reducing testing time, improving testing efficiency, and reducing testing time costs.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A parallel test apparatus for multi-stacked memory packages, wherein, The multi-stacked memory package includes several identical single-chip memory, each of the single-chip memory includes a first number of pins with different preset identifiers, characterized in that, The parallel testing device includes a test machine and a first number of AND gate operators. The test machine includes a first number of comparators, and the output terminals of the first number of AND gate operators are connected one-to-one with the first input terminals of the first number of comparators. Each of the AND gate arithmetic units has its first input terminal connected to a pin of each of the single-chip memory with the same preset identifier, and the preset identifiers of the pins connected to the first input terminals of each of the AND gate arithmetic units are different from each other. The second input terminal of the AND gate is used to input a preset reference voltage; the second input terminal of the comparator is used to input a preset desired voltage; the comparator is used to compare the operation result from the AND gate with the preset desired voltage to obtain the test result.

2. The parallel testing apparatus according to claim 1, characterized in that, The parallel testing apparatus further includes at least one chip under test fixture, which is used to accommodate and fix the multi-stack memory package; the chip under test fixture includes a first number of conductive contacts, each of the conductive contacts being connected to a first input terminal of one of the AND gate arithmetic units, and each of the conductive contacts being used to simultaneously connect to pins with the same preset identifier of each of the single memory chips.

3. The parallel testing apparatus according to claim 2, characterized in that, The pins of each individual memory chip with the same preset identifier are converged to the same conductive contact point. When the chip under test is clamped and fixed in place by the multi-stack memory package, the conductive contact point comes into contact with one of the conductive contact points to achieve electrical connection.

4. The parallel testing apparatus according to claim 2, characterized in that, The chip under test fixture includes a cuboid structure consisting of at least three side plates and at least one movable cover plate. The cuboid structure is used to accommodate the multi-stacked memory package and clamps and fixes the multi-stacked memory package by closing the movable cover plate.

5. The parallel testing apparatus according to claim 2, characterized in that, The parallel testing device also includes an interface board, on which the chip under test fixture and each of the AND gate operators are disposed, and the AND gate operators are in close contact with the chip under test fixture.

6. The parallel testing apparatus according to claim 2, characterized in that, The test machine further includes a first number of data writing terminals for writing data, and the parallel test device further includes a first number of selection switches and a first number of connection terminals. Each data writing terminal is connected to one of the connection terminals, and each selection switch can select to connect to a corresponding conductive contact point.

7. The parallel testing apparatus according to claim 1, characterized in that, Each of the aforementioned single-chip memory is provided with a switch for turning the single-chip memory on or off.

8. A parallel testing method for multi-stacked memory packages, characterized in that, Implemented by any one of the parallel testing devices described in claims 1-7, the parallel testing method includes: Start one of the single-chip memory in the multi-stacked memory package, which will cause the other preset single-chip memory to perform the startup action at the same time; Each AND gate arithmetic unit performs an operation on the electrical signal received at its first input terminal and the preset reference voltage received at its second input terminal, and outputs the operation result. Each comparator compares the received calculation result with a preset expected voltage to obtain a test result.

9. The parallel testing method according to claim 8, characterized in that, Each comparator compares the received calculation result with a preset expected voltage to obtain a test result, including: Each comparator compares the received calculation result with the preset expected voltage; If the preset expected voltage is a high voltage, then when the voltage received at the first input terminal of the comparator from the output terminal of the corresponding AND gate is greater than the high voltage, it is determined to be valid; otherwise, it is determined to be invalid. If the preset expected voltage is a low voltage, then the voltage received by the first input terminal of the comparator from the output terminal of the corresponding AND gate arithmetic unit is lower than the low voltage, and is determined to be valid; otherwise, it is determined to be invalid.

10. The parallel testing method according to claim 8, characterized in that, Each of the aforementioned single-chip memory is provided with a switch for turning the single-chip memory on or off; the other preset single-chip memories are set by pre-turning on their respective switches.

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