On-chip transformer and method of making the same

Abstract

The application discloses an on-chip transformer and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, the surface of the substrate is provided with an isolation layer; preparing a primary coil assembly on the isolation layer, the primary coil assembly comprises a primary coil and a first lead coil which are electrically contacted, and a first dielectric layer which is located between the primary coil and the first lead coil; preparing a secondary coil assembly on the primary coil assembly, the secondary coil assembly comprises a secondary coil and a second lead coil which are electrically contacted, and a third dielectric layer which is located between the secondary coil and the second lead coil. According to the scheme, the coil and the dielectric layer which are alternately stacked in sequence can be formed on the same substrate through a deposition process, four layers of coils and three layers of dielectric layers can constitute the same on-chip transformer, the frequency and the efficiency can be improved, the area can be greatly reduced, and the structure is simple and small in size.

Description

Technical Field

[0001] This invention relates to the field of DC-DC converter technology, and in particular to an on-chip transformer and its manufacturing method. Background Technology

[0002] With the development of electronic products, the demand for portable mobile devices is constantly increasing, and competition among manufacturers is becoming increasingly fierce, prompting a reduction in the size and weight of electronic systems. Among these electronic devices, the power supply section, due to the presence of magnetic components such as inductors and transformers, has become a major factor affecting the size and weight of electronic devices. In existing technologies, transformers are large and complex in structure, which is inconvenient for use. Summary of the Invention

[0003] In view of this, the present invention provides an on-chip transformer and its manufacturing method, which is not only simple in structure and small in size, but also improves frequency and efficiency.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A method for manufacturing an on-chip transformer, the method comprising:

[0006] A substrate is provided, the surface of which has an isolation layer;

[0007] A primary coil assembly is fabricated on the isolation layer. The primary coil assembly includes: a primary coil and a first lead coil that are electrically connected, and a first dielectric layer located between the primary coil and the first lead coil. The primary coil is located between the substrate and the first lead coil. The outer end of the primary coil is connected to a first lead end, and the inner end of the first lead coil is connected to a second lead end.

[0008] A secondary coil assembly is fabricated on the primary coil assembly, and a second dielectric layer is provided between the secondary coil assembly and the primary coil assembly. The secondary coil assembly includes: a secondary coil and a second lead coil that are electrically in contact, and a third dielectric layer located between the secondary coil and the second lead coil. The secondary coil is located between the second lead coil and the first lead coil. The outer end of the secondary coil is connected to a third lead end, and the inner end of the second lead coil is connected to a fourth lead end.

[0009] Preferably, in the above manufacturing method, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the isolation layer are all SiN layers.

[0010] Preferably, in the above-described fabrication method, the thickness of the SiN layer is 20nm-150nm.

[0011] Preferably, in the above manufacturing method, the method for forming the first dielectric layer includes:

[0012] An unpatterned first dielectric layer is formed, covering the isolation layer and the primary coil;

[0013] The first dielectric layer is graphically represented, and a first cutout pattern is formed on the first dielectric layer to expose a portion of the primary coil;

[0014] The first lead coil is in electrical contact with the primary coil through the first hollow pattern; the first dielectric layer covers the path of the second lead end through the primary coil to isolate the second lead end from the primary coil.

[0015] Preferably, in the above manufacturing method, the method for forming the third dielectric layer includes:

[0016] The unpatterned third dielectric layer is formed, covering the second dielectric layer and the secondary coil;

[0017] The third dielectric layer is graphically represented, and a second cutout pattern is formed on the third dielectric layer to expose a portion of the secondary coil;

[0018] The second lead coil is electrically connected to the secondary coil through the second hollow pattern; the third dielectric layer covers the path of the fourth lead end through the secondary coil to isolate the fourth lead end from the secondary coil.

[0019] Preferably, in the above manufacturing method, each coil is a metal spiral wire; the metal spiral wire is formed by electron beam evaporation process;

[0020] Each lead end is located on the same metal layer as the coil it is connected to.

[0021] Preferably, in the above-described fabrication method, in the same metal spiral, in the direction parallel to the substrate, the maximum diameter is 100μm-600μm, the linewidth is 10μm-68μm, the line spacing is 5μm-80μm, and in the direction perpendicular to the substrate, the thickness of the metal spiral is 200nm-500nm.

[0022] Preferably, in the above manufacturing method, the turns ratio of the primary coil to the secondary coil is n:n, where n is a positive integer greater than 1.

[0023] Preferably, in the above manufacturing method, the metal spiral has a smooth curve at its side edge;

[0024] Alternatively, the metal spiral may comprise multiple metal segments, with a 120° angle between adjacent metal segments.

[0025] The present invention also provides an on-chip transformer prepared by any of the above-described methods, the on-chip transformer comprising:

[0026] Substrate, the surface of which has an isolation layer;

[0027] A primary coil assembly disposed on the isolation layer includes: a primary coil and a first lead coil in electrical contact, and a first dielectric layer located between the primary coil and the first lead coil; the primary coil is located between the substrate and the first lead coil; wherein, the outer end of the primary coil is connected to a first lead end; and the inner end of the first lead coil is connected to a second lead end.

[0028] A secondary coil assembly is provided between the primary coil assembly and the primary coil assembly, the secondary coil assembly having a second dielectric layer between them; the secondary coil assembly includes: a secondary coil and a second lead coil in electrical contact, and a third dielectric layer located between the secondary coil and the second lead coil; the secondary coil is located between the second lead coil and the first lead coil; wherein, the outer end of the secondary coil is connected to a third lead terminal; and the inner end of the second lead coil is connected to a fourth lead terminal.

[0029] As can be seen from the above description, the on-chip transformer and its manufacturing method provided by the present invention can form coils and dielectric layers that are stacked alternately on the same substrate through a deposition process. The same on-chip transformer can be constructed by four layers of coils and three layers of dielectric layers. This can not only improve the frequency and efficiency, but also significantly reduce the area. Compared with the traditional transformer with iron core and winding structure, it has a simple structure and small size. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0032] Figures 1-22 A process flow diagram of a method for manufacturing an on-chip transformer provided in an embodiment of the present invention;

[0033] Figure 23 This is an equivalent circuit diagram of an on-chip transformer provided in an embodiment of the present invention;

[0034] Figures 24-26 The simulation curve of the transformer provided in the embodiment of the present invention. Detailed Implementation

[0035] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] With the development of electronic products, the demand for portable mobile devices is constantly growing, and competition among manufacturers is becoming increasingly fierce, prompting a reduction in the size and weight of electronic systems. Among these electronic devices, the power supply section, due to the presence of magnetic components such as inductors and transformers, has become a major factor affecting the size and weight of electronic devices. The advent of on-chip transformers has greatly reduced the area and weight of transformers, leading to their widespread application.

[0037] Under this development trend, power devices, as key components that directly affect the performance of power systems, must possess the following characteristics: lower on-resistance, lower capacitance, no reverse recovery charge, smaller size, and lower cost.

[0038] GaN materials, due to their excellent properties such as large bandgap, high saturated electron mobility, low dielectric constant, good thermal conductivity, high temperature resistance, and corrosion resistance, are considered to meet the requirements of new power device development and have rapidly become a research hotspot. GaN-based DC-DC converters, with their higher frequencies, higher output power, and higher efficiency, are increasingly becoming a focus in power supply chips. Combining on-chip transformers with GaN technology helps improve the conversion efficiency and operating frequency of power systems. These improvements in operating frequency and efficiency drive the continuous development of electronic products towards miniaturization and low power consumption.

[0039] Therefore, this application provides an on-chip transformer and its manufacturing method, which can form coils and dielectric layers alternately stacked on the same substrate through a deposition process. The same on-chip transformer can be constructed by four layers of coils and three layers of dielectric layers. This can not only improve the frequency and efficiency, but also significantly reduce the area. Compared with the traditional transformer with iron core and winding structure, it has a simple structure and small size.

[0040] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] refer to Figures 1-22 , Figures 1-22 This is a process flow diagram illustrating a method for manufacturing an on-chip transformer according to an embodiment of the present invention. Figures 1-22 As shown, the manufacturing method includes:

[0042] Step S11: As Figure 1 As shown, a substrate 11 is provided, and the surface of the substrate 11 has an isolation layer 12; Figure 1 This is a cross-sectional view perpendicular to substrate 11.

[0043] The isolation layer 12 can prevent the transformer from affecting the substrate 11 and reduce the parasitic effect between the transformer and the substrate 11. The thicker the isolation layer 12, the stronger the isolation capability and the less the parasitic effect. Since the dielectric medium in this process can range from tens of micrometers to hundreds of micrometers, the thickness of the isolation layer 12 can be selected as 300 μm.

[0044] Step S12: As Figures 2-11 As shown, a primary coil assembly 13 is fabricated on the isolation layer 12.

[0045] The primary coil assembly 13 includes: a primary coil 131 and a first lead coil 132 in electrical contact, and a first dielectric layer 133 located between the primary coil 131 and the first lead coil 132; the primary coil 131 is located between the substrate 11 and the first lead coil 132; wherein, the outer end of the primary coil 131 is connected to a first lead terminal A; and the inner end of the first lead coil 132 is connected to a second lead terminal a.

[0046] In this embodiment of the invention, the method for forming the first dielectric layer 133 includes:

[0047] First, such as Figures 2-4 As shown, the primary coil 131 is fabricated on the isolation layer 12. Figure 2 This is a top view of the primary coil 131. Figure 3 yes Figure 2 Cross-sectional view in the MM' direction, Figure 4 yes Figure 2 Front view facing the first lead end A.

[0048] Then, as Figure 5 As shown, an unpatterned first dielectric layer 133 is formed, covering the isolation layer 12 and the primary coil 131; Figure 5 This is a cross-sectional view perpendicular to substrate 11.

[0049] For example Figures 6-8 As shown, the first dielectric layer 133 is graphically represented, and a first cutout pattern 134 is formed on the first dielectric layer 133 to expose a portion of the primary coil 131. Figure 6 This is a top view of the first medium layer 133 after graphical representation. Figure 7 yes Figure 6 Cross-sectional view in the MM' direction, Figure 8 yes Figure 6 A cross-sectional view in the NN' direction. The patterned first dielectric layer 133 can be formed by photolithography and etching processes.

[0050] In this design, the edge of the first cutout pattern 134 can be set to coincide with the edge of the exposed primary coil 131, so that a first lead coil 132 with the same line width as the primary coil 131 can be formed in subsequent processes. In other methods, the line width of the first lead coil 132 can be adjusted by controlling the size of the first cutout pattern 134, so that it is the same as the line width of the primary coil 131 or has a set difference.

[0051] Finally, as Figures 9-11 As shown, the first lead coil 132 is fabricated on the exposed portion of the primary coil 131. The first lead coil 132 is in electrical contact with the primary coil 131 through the first cutout pattern 134. The first dielectric layer 133 covers the path of the second lead end a through the primary coil 131 to isolate the second lead end a from the primary coil 131. Figure 9 This is a top view of the first lead coil 132. Figure 10 yes Figure 9 Cross-sectional view in the MM' direction, Figure 11 yes Figure 9 A cross-sectional view of the middle section in the NN' direction.

[0052] Step S13: As Figures 12-22 As shown, a secondary coil assembly 14 is fabricated on the primary coil assembly 131, and a second dielectric layer 15 is provided between the secondary coil assembly 14 and the primary coil assembly 13. The secondary coil assembly 14 includes: a secondary coil 141 and a second lead coil 142 that are electrically in contact, and a third dielectric layer 143 located between the secondary coil 141 and the second lead coil 142. The secondary coil 141 is located between the second lead coil 142 and the first lead coil 132. The outer end of the secondary coil 141 is connected to a third lead terminal B. The inner end of the second lead coil 142 is connected to a fourth lead terminal b.

[0053] In this embodiment of the invention, the method for forming the third dielectric layer 143 includes:

[0054] First, such as Figure 12 As shown, a second dielectric layer 15 is formed, which covers the first dielectric layer 133 and the first lead coil 132. The second dielectric layer 15 mainly isolates the upper and lower metal layers, allowing only AC signals to pass between them, while DC signals cannot pass through, thereby achieving isolation and realizing the function of a transformer. Figure 12 This is a cross-sectional view perpendicular to substrate 11.

[0055] Then, as Figures 13-15 As shown, a secondary coil 141 is fabricated on the second dielectric layer 15; the secondary coil 141 can be formed by processes such as photolithography, electron beam, etc. The secondary coil 141 is perpendicularly aligned with the primary coil 131 in the lower layer, mainly to increase the transfer of magnetic flux from the primary coil 131 to the secondary coil 141. Figure 13 This is a top view of the secondary coil 141. Figure 14 yes Figure 13 Cross-sectional view in the MM' direction, Figure 15 yes Figure 13 A cross-sectional view of the middle section in the NN' direction.

[0056] For example Figure 16 As shown, the unpatterned third dielectric layer 143 is formed, which covers the second dielectric layer 15 and the secondary coil 141; Figure 16 for Figure 13 Cross-sectional view in the MM' direction.

[0057] For example Figures 17-19 As shown, the third dielectric layer 143 is graphically represented, and a second cutout pattern 144 is formed on the third dielectric layer 143 to expose a portion of the secondary coil 141. Figure 17 This is a top view of the graphical third media layer 143. Figure 18 yes Figure 17 Cross-sectional view in the MM' direction, Figure 19 yes Figure 17 A cross-sectional view of the middle section in the NN' direction.

[0058] It should be noted that, in order to bring out the first lead A and the second lead a, through holes 01 and 02 are respectively provided at the corresponding positions, as follows: Figure 18 As shown. Through hole 01 exposes part of the first lead end A, and through hole 02 exposes part of the second lead end a.

[0059] Finally, as Figures 20-22As shown, the second lead coil 142 is fabricated on the exposed portion of the secondary coil 141. The second lead coil 142 is in electrical contact with the secondary coil 141 through the second cutout pattern 144. The third dielectric layer 143 covers the path of the fourth lead end b through the secondary coil 141 to isolate the fourth lead end b from the secondary coil 141. Figure 22 This is a top view of the second lead coil 142. Figure 21 yes Figure 20 Cross-sectional view in the MM' direction, Figure 22 yes Figure 20 A cross-sectional view of the middle section in the NN' direction.

[0060] Simultaneously with the formation of the second lead coil 142, a first conductor block of the same conductor layer as the second lead coil 142 is formed above the corresponding first lead end A. The first conductor block contacts the first lead end A through a through hole 01. A second conductor block of the same conductor layer as the second lead coil 142 is formed above the corresponding second lead end a. The second conductor block contacts the second lead end a through a through hole 02. A third conductor block of the same conductor layer as the second lead coil 142 is formed above the corresponding third lead end B. The third conductor block contacts the third lead end B through a second cutout pattern 144. The first conductor block, the second conductor block, and the third conductor block are all isolated and insulated from the second lead coil 142.

[0061] In this embodiment of the invention, the first dielectric layer 133, the second dielectric layer 15, the third dielectric layer 143, and the isolation layer 12 are all SiN layers. To enable the on-chip transformer to be used in a DC-DC converter with GaN dielectric layers for parameter setting, the thickness of the SiN layer can be 20nm-150nm, such as 40nm.

[0062] In this embodiment of the invention, each coil is a metal spiral wire; the metal spiral wire can be formed by electron beam evaporation process; each lead end is located in the same metal layer as the connected coil.

[0063] In order to enable the on-chip transformer to be used in a DC-DC converter with a GaN dielectric layer for setting parameters, the maximum diameter of the same metal spiral in the direction parallel to the substrate 11 can be 100μm-600μm, such as 400μm; the linewidth can be 10μm-68μm, such as 30μm or 68μm; the line spacing can be 5μm-80μm, such as 5μm or 40μm; and the thickness of the metal spiral in the direction perpendicular to the substrate 11 can be 200nm-500nm, such as 300nm.

[0064] Furthermore, the metal spiral can have smooth curves on its side edges; or, the metal spiral can include multiple metal segments with a 120° angle between adjacent metal segments.

[0065] In this embodiment of the invention, the turns ratio of the primary coil 131 to the secondary coil 141 can be n:n, where n is a positive integer greater than 1, such as a turns ratio of 3:3.

[0066] It should be noted that the two coils in the primary coil assembly 13 have the same number of turns, and their portions, except for the lead ends, overlap; the two coils in the secondary coil assembly 14 have the same number of turns, and their portions, except for the lead ends, overlap.

[0067] The vertical distance between the upper and lower coils of the transformer coincides, which effectively transfers the magnetic flux generated by the primary coil 131 to the secondary coil 141. Compared to other types of on-chip transformers, this design saves space and has higher efficiency. The primary and secondary coils can transmit signals, including power. This enables the transmission of signals from electrical to magnetic and back to electrical.

[0068] This design employs a circular transformer structure, with the primary coil assembly on the lower layer and the secondary coil assembly on the upper layer. An insulating material separates them, reducing the area required and increasing the efficiency of magnetic flux transfer in the vertical structure. The circular structure, with a 120° angle at the inflection point, is primarily used to balance the resistance, ensuring it is as consistent as possible along the straight line and at the inflection point, thus reducing parasitic effects.

[0069] As can be seen from the above description, in the method for manufacturing an on-chip transformer provided by the technical solution of the present invention, coils and dielectric layers are formed alternately on the same substrate through a deposition process. The same on-chip transformer can be constructed by four layers of coils and three layers of dielectric layers. This not only improves the frequency and efficiency, but also significantly reduces the area. Compared with transformers with traditional iron core and winding structures, the structure is simple and the size is small.

[0070] refer to Figure 23 , Figure 23 This is an equivalent circuit diagram of an on-chip transformer provided in an embodiment of the present invention. Figure 23As shown, the performance parameters of a transformer can be calculated through Z-parameter simulation. The Z-parameter is a physical quantity similar to the S-parameter; it is mainly used to calculate the input and output impedance of a two-port network and can be derived from the S-parameter. Only the parasitic parameters of the primary coil are calculated, as follows (imag represents the imaginary part of the Z-parameter, and real represents the real part). R1 ​​is the parasitic resistance of the primary coil, L1 and L2 are the parasitic inductances of the primary and secondary coils of the transformer, respectively, M12 and M21 represent the mutual inductance of the primary and secondary coils of the transformer, K represents the coupling coefficient of the transformer, and Q represents the quality factor of the transformer.

[0071] The parasitic resistance of the transformer is: R1 = real(Z11)

[0072] The inductance of the transformer is: , ;

[0073] The mutual inductance of the transformer is: (f represents the frequency of the input transformer)

[0074] Coupling coefficient:

[0075] Quality Factor: (w represents the angular frequency of the input transformer)

[0076] Through simulation, various parameters of transformers ranging from 10MHz to 100MHz can be obtained, such as... Figures 24-26 As shown, Figures 24-26 The simulation curve of the transformer provided in the embodiment of the present invention.

[0077] The transformer used in this application is an isolated on-chip transformer, which is composed of transformers in a symmetrical manner, so the turns ratio can be 1, and its coupling coefficient can usually be above 0.66, with a maximum of 0.99.

[0078] The quality factor can be as high as 0.9. The quality factor of an inductor is introduced to indicate its energy storage capacity. The higher the quality factor of an inductor, the more energy it can store.

[0079] Calculations based on various parameters show that the transformers involved can be used over a relatively wide range, and the higher the frequency, the lower the parasitic resistance, indicating potentially lower power consumption. However, parasitic inductance and mutual inductance decrease. At lower frequencies, parasitic inductance and mutual inductance are relatively high, indicating that more volume transfer may occur between the primary and secondary coils. For typical isolated DC-DC converters, this frequency is sufficient.

[0080] Based on the above embodiments, another embodiment of the present invention also provides an on-chip transformer prepared by the manufacturing method described in any of the above claims, such as... Figures 20-22 As shown, the on-chip transformer includes:

[0081] Substrate 11, the surface of which has an isolation layer 12;

[0082] A primary coil assembly 13 is disposed on the isolation layer 12. The primary coil assembly 13 includes: a primary coil 131 and a first lead coil 132 that are electrically in contact, and a first dielectric layer 133 located between the primary coil 131 and the first lead coil 132. The primary coil 131 is located between the substrate 11 and the first lead coil 132. The outer end of the primary coil 131 is connected to a first lead terminal A. The inner end of the first lead coil 132 is connected to a second lead terminal a.

[0083] A secondary coil assembly 14 is provided between the primary coil assembly 13, and a second dielectric layer 15 is provided between the secondary coil assembly 14 and the primary coil assembly 13. The secondary coil assembly 14 includes: a secondary coil 141 and a second lead coil 142 that are electrically in contact, and a third dielectric layer 143 located between the secondary coil 141 and the second lead coil 142. The secondary coil 141 is located between the second lead coil 142 and the first lead coil 132. The outer end of the secondary coil 141 is connected to a third lead terminal B. The inner end of the second lead coil 142 is connected to a fourth lead terminal b.

[0084] This application provides an on-chip transformer that can be integrated onto a single chip and applied to isolated DC-DC converters. Utilizing GaN technology, it integrates the transformer with a GaN-based DC-DC converter onto the same chip. Compared to traditional on-chip transformers in DC-DC converters, the GaN-based on-chip transformer not only increases frequency and efficiency but also significantly reduces area, thereby improving the efficiency of the DC-DC converter.

[0085] As can be seen from the above description, in the method for manufacturing an on-chip transformer provided by the technical solution of the present invention, coils and dielectric layers are formed alternately on the same substrate through a deposition process. The same on-chip transformer can be constructed by four layers of coils and three layers of dielectric layers. This not only improves the frequency and efficiency, but also significantly reduces the area. Compared with transformers with traditional iron core and winding structures, the structure is simple and the size is small.

[0086] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. Regarding the on-chip transformer disclosed in the embodiments, since it corresponds to the manufacturing method of the on-chip transformer disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to the manufacturing method section.

[0087] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0088] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of fabricating an on-chip transformer, comprising: The manufacturing method comprises: providing a substrate, the surface of the substrate having an isolation layer; preparing a primary coil assembly on the isolation layer, the primary coil assembly comprising: an electrically contacted primary coil and a first lead coil, and a first dielectric layer between the primary coil and the first lead coil; the primary coil is between the substrate and the first lead coil; wherein the outer end of the primary coil is connected with a first lead end; the inner end of the first lead coil is connected with a second lead end; the first dielectric layer has a first hollow pattern, the edge of the first hollow pattern coincides with the edge of the exposed primary coil; the first lead coil is electrically contacted with the primary coil through the first hollow pattern; the first dielectric layer covers the path of the second lead end through the primary coil to isolate the second lead end from the primary coil; preparing a secondary coil assembly on the primary coil assembly, the secondary coil assembly having a second dielectric layer between the primary coil assembly and the secondary coil assembly; the secondary coil assembly comprising: an electrically contacted secondary coil and a second lead coil, and a third dielectric layer between the secondary coil and the second lead coil; the secondary coil is between the second lead coil and the first lead coil; wherein the outer end of the secondary coil is connected with a third lead end; the inner end of the second lead coil is connected with a fourth lead end; the third dielectric layer has a second hollow pattern, the second lead coil is electrically contacted with the secondary coil through the second hollow pattern; the third dielectric layer covers the path of the fourth lead end through the secondary coil to isolate the fourth lead end from the secondary coil.

2. The production method according to claim 1, characterized by, The first dielectric layer, the second dielectric layer, the third dielectric layer and the isolation layer are all SiN layers.

3. The method of manufacturing according to claim 2, wherein, The thickness of the SiN layer is 20-150 nm.

4. The method of making of claim 1, wherein, The forming method of the first dielectric layer comprises: forming the first dielectric layer without patterning, covering the isolation layer and the primary coil; patterning the first dielectric layer to form a first hollow pattern on the first dielectric layer, exposing part of the primary coil.

5. The method of manufacturing of claim 1, wherein, The forming method of the third dielectric layer comprises: forming the third dielectric layer without patterning, covering the second dielectric layer and the secondary coil; patterning the third dielectric layer to form a second hollow pattern on the third dielectric layer, exposing part of the secondary coil.

6. The method of making of claim 1, wherein, Each coil is a metal spiral line; the metal spiral line is formed by an electron beam evaporation process; Each lead end is in the same metal layer as the connected coil.

7. The method of manufacturing according to claim 6, wherein, In the same metal spiral line, in the direction parallel to the substrate, the maximum diameter is 100-600 μm, the line width is 10-68 μm, and the line spacing is 5-80 μm; in the direction perpendicular to the substrate, the thickness of the metal spiral line is 200-500 nm.

8. The method of manufacturing according to claim 6, wherein, The turns ratio of the primary coil to the secondary coil is n:n, n is a positive integer greater than 1.

9. The method of manufacturing according to claim 6, wherein, The metal spiral line has a smooth curve as a side edge; Or, the metal spiral wire comprises a plurality of metal wire segments, and an included angle between two adjacent metal wire segments is 120°.

10. A transformer-on-chip produced according to the production method of any one of claims 1 to 9, characterized in that The on-chip transformer comprises: a substrate, a surface of the substrate having an isolation layer; a primary coil assembly disposed on the isolation layer, the primary coil assembly comprising: an electrically contacted primary coil and a first lead coil, and a first dielectric layer between the primary coil and the first lead coil; the primary coil is between the substrate and the first lead coil; wherein an outer end of the primary coil is connected with a first lead end; an inner end of the first lead coil is connected with a second lead end; a secondary coil assembly disposed between the primary coil assembly, the secondary coil assembly and the primary coil assembly having a second dielectric layer; the secondary coil assembly comprises: an electrically contacted secondary coil and a second lead coil, and a third dielectric layer between the secondary coil and the second lead coil; the secondary coil is between the second lead coil and the first lead coil; wherein an outer end of the secondary coil is connected with a third lead end; an inner end of the second lead coil is connected with a fourth lead end.

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