Buried contact structure fabrication method and structure

Abstract

The application relates to the technical field of semiconductor integrated circuits, in particular to a buried layer lead-out structure manufacturing method and structure. The method comprises the following steps: forming a first-conductivity-type buried layer in a substrate; forming a first epitaxial layer on the substrate; performing first-conductivity-type impurity injection on the first epitaxial layer through a first mask with a first energy; performing first-conductivity-type impurity injection on the first epitaxial layer through the first mask with a second energy to form a first-conductivity-type impurity injection area; the first energy is higher than the second energy; performing a rapid thermal annealing process; forming a second epitaxial layer on the first epitaxial layer; performing a hot push well process to form a first-conductivity-type well area A part located in the first epitaxial layer and a first-conductivity-type well area B part located in the second epitaxial layer; performing first-conductivity-type impurity injection on the second epitaxial layer to form a first-conductivity-type lead-out area, and the first-conductivity-type lead-out area is connected with the first-conductivity-type well area B part downward.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, in particular to a buried layer lead-out structure manufacturing method and structure. BACKGROUND

[0002] Figure 1 A cross-sectional structure schematic diagram of an N-type buried layer lead-out structure is shown, from Figure 1 It can be seen that the N-type buried layer lead-out structure includes a substrate with an N-type buried layer, and a first epitaxial layer and a second epitaxial layer are sequentially formed on the substrate. Among them, a first N-type well region is formed in the first epitaxial layer, and a second N-type well region is formed in the second epitaxial layer. The second N-type well region, the first N-type well region and the N-type buried layer are sequentially connected from top to bottom.

[0003] In order to make the buried layer lead-out structure applicable to higher voltage devices, it is usually necessary to increase the thickness of the N-type well region, especially the first N-type well region, so it is necessary to thicken the first epitaxial layer so that the first N-type well region formed by ion implantation has the required thickness.

[0004] In the process of forming the first N-type well region by ion implantation, due to the limitation of the set implantation energy, more thermal processes are needed to push the well, so that the N-type particle injection region diffuses to the required thickness. However, too many thermal processes will cause the wafer to warp. SUMMARY

[0005] The present application provides a buried layer lead-out structure manufacturing method and structure, which can solve the problem that too many thermal processes in the related art will cause the wafer to warp.

[0006] In order to solve the technical problems described in the background art, the first aspect of the present application provides a buried layer lead-out structure manufacturing method, which includes sequentially performing the following steps:

[0007] forming a first conductive type buried layer in the substrate;

[0008] forming a first epitaxial layer on the substrate;

[0009] on the first epitaxial layer, first conductive type impurity implantation is performed by a first mask with a first energy;

[0010] on the first epitaxial layer, first conductive type impurity implantation is performed by the first mask with a second energy to form a first conductive type impurity injection region; the first energy is higher than the second energy;

[0011] performing a rapid thermal annealing process to repair the damage to the first epitaxial layer after impurity implantation;

[0012] forming a second epitaxial layer on the first epitaxial layer;

[0013] performing a hot push-out process so that the first conductive type impurity injection region diffuses to the surroundings to form a first conductive type well region A part in the first epitaxial layer and a first conductive type well region B part in the second epitaxial layer;

[0014] performing a first conductive type impurity injection on the second epitaxial layer to form a first conductive type lead-out region, which is in contact with the first conductive type well region B part downward.

[0015] Optionally, after the step of performing a hot push-out process so that the first conductive type impurity injection region diffuses to the surroundings to form a first conductive type well region A part in the first epitaxial layer and a first conductive type well region B part in the second epitaxial layer is completed, before the step of performing a first conductive type impurity injection on the second epitaxial layer to form a first conductive type lead-out region, which is in contact with the first conductive type well region B part downward, the buried layer lead-out structure manufacturing method further comprises:

[0016] forming a shallow trench isolation structure in the second epitaxial layer.

[0017] Optionally, a spacing region is formed between two adjacent shallow trench isolation structures, and the first conductive type lead-out region is formed in the spacing region.

[0018] Optionally, the step of forming a first conductive type buried layer in the substrate comprises the following steps performed in sequence:

[0019] performing a selective first conductive type impurity injection on the substrate at an energy of 20-200KeV and a concentration of 5.0e113-5.0e15cm -2 .

[0020] performing a hot push-out process for 50-500 minutes in a temperature environment of 1000-1150℃ so that the first conductive type impurity completed by the selective injection diffuses in the longitudinal and transverse directions of the substrate to form a first conductive type buried layer.

[0021] Optionally, in the step of performing a first conductive type impurity injection on the first epitaxial layer through the first mask at a second energy to form a first conductive type impurity injection region, the second energy is in the range of 20-200KeV.

[0022] Optionally, the step of performing a rapid thermal annealing process so that the damage to the first epitaxial layer caused by the impurity injection is repaired comprises:

[0023] The rapid thermal annealing process is performed at a temperature of 900-1100℃ for 10-50 seconds to repair the damage to the first epitaxial layer caused by the impurity implantation.

[0024] Optionally, the step of performing the hot push-out well process to diffuse the first-conductivity-type impurity implantation region to form a first-conductivity-type well region A in the first epitaxial layer and a first-conductivity-type well region B in the second epitaxial layer comprises:

[0025] The hot push-out well process is performed at a temperature of 1000-1150℃ for 50-500 minutes to diffuse the first-conductivity-type impurity implantation region to form a first-conductivity-type well region A in the first epitaxial layer and a first-conductivity-type well region B in the second epitaxial layer.

[0026] Optionally, in the step of performing first-conductivity-type impurity implantation on the second epitaxial layer to form a first-conductivity-type lead-out region, the first-conductivity-type lead-out region comprises a first-conductivity-type lead-out well region and a first-conductivity-type lead-out heavily doped region.

[0027] The first-conductivity-type lead-out well region is in contact with the first-conductivity-type well region B, and the first-conductivity-type lead-out heavily doped region extends downward from the upper surface of the second epitaxial layer, and the first-conductivity-type lead-out heavily doped region is located on the first-conductivity-type lead-out well region.

[0028] To solve the technical problems described in the background, the second aspect of the present application provides a buried layer lead-out structure, which is formed by the buried layer lead-out structure manufacturing method described in the first aspect of the present application.

[0029] The technical scheme of the present application has at least the following advantages: the first epitaxial layer is implanted with the first conductive type impurities twice with different energies, and after the impurity implantation, a rapid thermal annealing process is added instead of immediately performing a hot push well process, so that the vacancies in the first epitaxial layer lattice are filled in the annealing process, the damage to the first epitaxial layer after the impurity implantation is repaired, then a second epitaxial growth is performed to form a second epitaxial layer, and then a hot push well process is performed, so that the first conductive type impurity implantation region diffuses to the surrounding, forming a first conductive type well region A part in the first epitaxial layer and a first conductive type well region B part in the second epitaxial layer, thereby on the one hand, a buried layer under a thicker epitaxial layer can be led out without increasing the process difficulty, so as to improve the application voltage range of the process platform; on the other hand, the first conductive type impurities diffused upward in the hot push well process enter the second epitaxial layer, so that even under the premise of thickening the second epitaxial layer, the first conductive type lead-out region formed in the subsequent process can also be fully connected and contacted with the first conductive type well region B part, thereby improving the reliability of high-voltage range devices. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0031] Figure 1 A flowchart of a buried layer lead-out structure manufacturing method provided by an embodiment of the present application is shown;

[0032] Figure 2 A device cross-sectional structure schematic diagram after step S5 is shown;

[0033] Figure 3 A device cross-sectional structure schematic diagram after step S6 is shown;

[0034] Figure 4 A device cross-sectional structure schematic diagram after step S7 is shown;

[0035] Figure 5 A device cross-sectional structure schematic diagram after step S8 is shown;

[0036] Figure 6 A device cross-sectional structure schematic diagram after step S9 is shown. DETAILED DESCRIPTION

[0037] With reference to the drawings, the technical solutions in the present application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0038] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0039] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0041] The conductivity type of the semiconductor region in the present application includes opposite first conductivity type and second conductivity type, that is, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.

[0042] N-type semiconductor and P-type semiconductor are generated according to different impurities doped into the semiconductor. Among them, by doping a certain element in group V of the periodic table, such as arsenic or antimony, etc. Donor impurities, N-type semiconductor can be obtained; by doping an element in group III of the periodic table, such as boron or indium, etc. Acceptor impurities, P-type semiconductor can be obtained.

[0043] The conductivity of the N-type semiconductor and the P-type semiconductor is different.

[0044] Figure 1A flow chart of a method for manufacturing a buried layer lead-out structure is shown. In the following, the first conductivity type is taken as N type and the second conductivity type is taken as P type. The method for manufacturing the buried layer lead-out structure includes the following steps S1 to S9:

[0045] Step S1: Forming an N type buried layer in a substrate.

[0046] The substrate is of P type and the N type buried layer extends downward from the upper surface of the substrate. First, selective N type impurity implantation is performed on the substrate, and then a heat push well process is performed, so that the N type impurities that have completed selective implantation diffuse in the longitudinal and lateral directions of the substrate, thereby forming an N type buried layer.

[0047] The selective N type impurity implantation can be performed on the substrate 101 at an energy of 20-200 KeV and a concentration of 5.0e113-5.0e15 cm -2 , and then a heat push well process is performed in a temperature environment of 1000-1150 °C for 50-500 minutes, so that the N type impurities that have completed selective implantation diffuse in the longitudinal and lateral directions of the substrate 101, thereby forming an N type buried layer 102.

[0048] Step S2: Forming a first epitaxial layer on the substrate.

[0049] The first epitaxial layer 103 is of P type.

[0050] Step S3: On the first epitaxial layer, N type impurity implantation is performed by a first mask at a first energy.

[0051] Step S4: On the first epitaxial layer, N type impurity implantation is performed by the first mask at a second energy to form an N type impurity implantation region; the first energy is higher than the second energy.

[0052] The mask of step S3 and step S4 is the same mask, i.e. step S4 is based on the impurity implantation region formed after step S3, and then low-energy N type impurity implantation is performed on the impurity implantation region. For example, the first energy range for N type impurity implantation at a first energy in step S3 is 1000-4000 K, and the doping concentration is 1e12-5e13 cm -2 . The second energy range for N type impurity implantation at a second energy in step S4 is 20-200 KeV, and the doping concentration is 1.0e12-5.0e12 cm -2 .

[0053] Step S5: Performing a rapid thermal annealing process to repair the damage to the first epitaxial layer caused by impurity implantation.

[0054] Since the first epitaxial layer is subjected to the impurity implantation process twice with different energies in step S3 and step S4, especially the high-energy implanted impurities collide with the atoms in the lattice of the first epitaxial layer, which causes the lattice atoms in the impurity implantation region to be displaced, resulting in a large number of vacancies, disordered atomic arrangement, or even amorphous region.

[0055] Therefore, through the rapid thermal annealing process in step S5, the vacancies in the lattice of the first epitaxial layer can be filled in the annealing process, so as to repair the damage to the first epitaxial layer after the impurity implantation.

[0056] Optionally, the rapid thermal annealing process can be performed at a temperature of 900-1100°C for 10-50 seconds.

[0057] Referring to Figure 2 , a cross-sectional structure diagram of the device after step S5 is shown, from Figure 2 which can be seen that the first epitaxial layer 103 is arranged on the substrate 101, the N-type buried layer 102 extends downward from the upper surface of the substrate 101, and the N-type impurity implantation region 104 is formed in the first epitaxial layer 103 by twice N-type impurity implantation. The N-type impurity implantation region 104 extends downward from the upper surface of the first epitaxial layer 103, but since no push well process is performed, the depth of the N-type impurity implantation region 104 is not sufficient to contact and connect with the N-type buried layer 102.

[0058] Step S6: forming a second epitaxial layer on the first epitaxial layer.

[0059] The second epitaxial layer is of P-type conductivity.

[0060] Referring to Figure 3 , a cross-sectional structure diagram of the device after step S6 is shown, from Figure 3 which can be seen that the second epitaxial layer 105 is formed on the first epitaxial layer 103, and the N-type impurity implantation region 104 in the first epitaxial layer 103 has the same form as shown in Figure 2 .

[0061] Step S7: performing a thermal push well process, so that the first conductivity type impurity implantation region diffuses to the surrounding, forming an N-type well region A part in the first epitaxial layer and an N-type well region B part in the second epitaxial layer.

[0062] Optionally, the thermal push well process can be performed at a temperature of 1000-1150°C for 50-500 minutes, so that the N-type impurity implantation region diffuses to the surrounding.

[0063] Referring to Figure 4 , a cross-sectional structure diagram of the device after step S7 is shown, in combination with Figure 3 and Figure 4It can be seen that after the hot push trap process, Figure 3 The N-type impurity injection region 104 shown diffuses in all directions, i.e. upward, downward, leftward and rightward. Figure 3 In the hot push trap process, the N-type impurity diffusing upward enters the second epitaxial layer 105 to form an N-type well region B part 104-2 located in the second epitaxial layer 105, and the N-type impurity diffusing leftward and rightward forms an N-type well region A part 104-1 located in the first epitaxial layer 103.

[0064] The N-type well region B part 104-2 extends upward from the lower surface of the second epitaxial layer 105. The N-type well region A part 104-1 is connected to the N-type well region B part 104-2 in contact, and the N-type well region A part 104-1 is connected to the N-type buried layer 102 in contact.

[0065] Step S8: forming a shallow trench isolation structure in the second epitaxial layer.

[0066] Referring to Figure 5 , a schematic diagram of a cross-sectional structure of the device after step S8 is shown, from which Figure 5 it can be seen that the shallow trench isolation structure 106 formed in the second epitaxial layer 105 extends downward from the upper surface of the second epitaxial layer 105. A spacing region is formed between two adjacent shallow trench isolation structures 106.

[0067] Step S9: performing N-type impurity injection on the second epitaxial layer to form an N-type lead-out region, which is connected to the N-type well region B part in contact downward.

[0068] Referring to Figure 6 , a schematic diagram of a cross-sectional structure of the device after step S9 is shown, from which Figure 6 it can be seen that the N-type lead-out region is formed in the spacing region shown. Figure 5 The N-type lead-out region can include an N-type lead-out well region 107 and an N-type lead-out heavily doped region 108. The N-type lead-out well region 107 is connected to the N-type well region B part 104-2 in contact downward, and the N-type lead-out heavily doped region 108 extends downward from the upper surface of the second epitaxial layer 105 and is located on the N-type lead-out well region 107.

[0069] In performing the step S9, N-type impurity injection can be performed on the second epitaxial layer first, and then N-type impurity heavily doped injection is performed after thermal activation and annealing repair, and then thermal activation and annealing repair are performed again, so as to form the N-type lead-out well region 107 and the N-type lead-out heavily doped region 108.

[0070] After step S9, a contact hole 109 can be made on the N-type lead-out heavily doped region 108, which is connected to the N-type lead-out heavily doped region 108 in contact.

[0071] The application also provides a buried layer lead-out structure formed by the buried layer lead-out structure manufacturing method. Figure 1 The buried layer lead-out structure manufacturing method is shown in the following. Figure 6 The buried layer lead-out structure formed by the buried layer lead-out structure manufacturing method is shown in the following.

[0072] The embodiment can lead out a buried layer under a thicker epitaxial layer without increasing the difficulty of the process, so as to improve the application voltage range of the process platform. On the other hand, the first conductive type impurities diffused upward in the heat push well process enter the second epitaxial layer, so that even under the premise of thickening the second epitaxial layer, the first conductive type lead-out region formed in the subsequent process can also be fully connected and contacted with the first conductive type well region B, thereby improving the reliability of the high voltage range device.

[0073] Obviously, the above embodiment is only an example for clearly illustrating, but not a limitation to the embodiments. Based on the above description, other different forms of changes or variations can also be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the application.

Claims

1. A method for fabricating a buried layer lead-out structure, characterized in that, The method for fabricating the buried layer lead-out structure includes the following steps in sequence: A buried layer of the first conductivity type is formed in the substrate; A first epitaxial layer is formed on the substrate; On the first epitaxial layer, impurities of a first conductivity type are implanted with a first energy through a first photomask. On the first epitaxial layer, through the first photomask, a first type of conductivity impurity is implanted with the second energy to form a first type of conductivity impurity implantation region; The first energy is higher than the second energy; A rapid thermal annealing process is performed to repair the damage caused to the first epitaxial layer after impurity injection; A second epitaxial layer is formed on the first epitaxial layer; A hot push-well process is performed to diffuse the first conductivity type impurity implantation region to the surrounding area, forming a first conductivity type well region A located in the first epitaxial layer and a first conductivity type well region B located in the second epitaxial layer. A first conductivity type impurity is implanted on the second epitaxial layer to form a first conductivity type lead-out region, and the first conductivity type lead-out region is contacted and connected downward to the first conductivity type well region B.

2. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, After the step of performing the hot-push-well process to diffuse the first conductive type impurity implantation region to form a first conductive type well region A in the first epitaxial layer and a first conductive type well region B in the second epitaxial layer is completed, the method for fabricating the buried layer lead-out structure further includes: A shallow trench isolation structure is formed in the second epitaxial layer.

3. The method for fabricating the buried layer lead-out structure as described in claim 2, characterized in that, An interval region is formed between two adjacent shallow trench isolation structures, and the first conductive type lead-out region is formed in the interval region.

4. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, The step of forming a buried layer of the first conductivity type in the substrate includes the following steps performed in sequence: With energy of 20~200 keV, 5.0e113~5.0e15cm -2 Selective implantation of first conductivity type impurities at a concentration of [specific value] is performed on the substrate; A hot-push trap process is performed at a temperature of 1000~1150℃ for 50~500 minutes, which allows selectively implanted first-conductivity type impurities to diffuse in the longitudinal and lateral directions of the substrate, forming a first-conductivity type buried layer.

5. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, In the first epitaxial layer, through the first photomask, a first conductivity type impurity is implanted with a second energy to form a first conductivity type impurity implantation region; in the step where the first energy is higher than the second energy, the range of the second energy is 20~200keV.

6. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, The step of performing rapid thermal annealing to repair damage to the first epitaxial layer caused by impurity implantation includes: A rapid thermal annealing process of 10 to 50 seconds is performed in a temperature environment of 900 to 1100℃ to repair the damage caused to the first epitaxial layer after impurity injection.

7. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, The step of performing a hot push-well process, causing the first conductivity type impurity implantation region to diffuse outwards to form a first conductivity type well region A located in the first epitaxial layer and a first conductivity type well region B located in the second epitaxial layer, includes: In a temperature environment of 1000~1150℃, a hot push-well process is performed for 50~500 minutes, which causes the first conductivity type impurity implantation region to diffuse to the surrounding area, forming a first conductivity type well region A in the first epitaxial layer and a first conductivity type well region B in the second epitaxial layer.

8. The method for fabricating the buried layer lead-out structure as described in claim 1, characterized in that, In the step of implanting a first conductivity type impurity on the second epitaxial layer to form a first conductivity type lead-out region, and the first conductivity type lead-out region is contacted and connected downward to the B part of the first conductivity type well region, the first conductivity type lead-out region includes: a first conductivity type lead-out well region and a first conductivity type lead-out heavily doped region. The first conductivity type lead-out well region is in contact with the B part of the first conductivity type well region downwards, the first conductivity type lead-out heavily doped region extends downwards from the upper surface of the second epitaxial layer, and the first conductivity type lead-out heavily doped region is located on the first conductivity type lead-out well region.

9. A buried layer lead-out structure, characterized in that, The buried layer lead-out structure is formed by the buried layer lead-out structure manufacturing method as described in any one of claims 1 to 8.

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