Semiconductor element structure with meandering conductive features and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor element structure having a meandering conductive feature and a method of fabricating the same. The semiconductor element structure has a conductive pad disposed in a semiconductor substrate and a first mask layer disposed on the semiconductor substrate. The semiconductor element structure also has a second mask layer disposed on the first mask layer. The first mask layer and the second mask layer comprise different materials. The semiconductor element structure further has a conductive feature that penetrates through the first mask layer and the second mask layer to connect to the conductive pad. In a top view, the conductive feature has a meandering pattern.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 197,770, filed March 10, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device structure and a method of fabricating the same. In particular, a semiconductor device structure having a serpentine conductive feature and a method of fabricating the same. BACKGROUND

[0003] Semiconductor devices are indispensable for many modern applications. As electronic technology advances, semiconductor devices become smaller and smaller while providing better functionality and including larger numbers of integrated circuits. Due to the miniaturization of semiconductor devices, different forms and sizes of semiconductor devices that implement different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed on the integration of semiconductor devices of various forms.

[0004] However, the manufacturing and integration of these semiconductor devices include many complex steps and operations. The integration in these semiconductor devices becomes more complex. The increase in complexity of the manufacturing and integration of these semiconductor devices can cause a number of defects. Accordingly, there is a need to continuously improve the manufacturing process of these semiconductor devices in order to deal with these defects and can enhance their performance.

[0005] The above description of background art is provided merely for purposes of background information and does not constitute an admission that the background art is prior art to the present disclosure, that any of the above described art is relevant to the present disclosure, or that any of the above described art is part of the common general knowledge of those working in the field of the present disclosure. Any discussion of the above state of the art is intended only to enhance the understanding of the background of the present disclosure and is not an admission that the discussed state of the art forms part of the prior art before the filing date of this application. SUMMARY

[0006] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate; and a first mask layer disposed on the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed on the first mask layer. The first mask layer and the second mask layer include different materials. The semiconductor device structure further includes a conductive feature that penetrates the first mask layer and the second mask layer to connect to the conductive pad. In a top view, the conductive feature has a serpentine pattern.

[0007] In one embodiment, the second masking layer includes a diamond-like carbon material having sp3 bonding. In one embodiment, the second masking layer is doped with carbon. In one embodiment, the conductive feature further includes a conductive layer; and a barrier layer separating the conductive layer from the conductive pad, the first masking layer, and the second masking layer.

[0008] In one embodiment, the serpentine pattern of the conductive feature includes a first line segment and a second line segment extending along a first direction in a top view; and a connecting segment extending along a second direction in a top view and physically connecting the first line segment and the second line segment, wherein the connecting segment has a width along the first direction, and a shortest distance between the first line segment and the second line segment is less than twice the width. In one embodiment, the first direction is perpendicular to the second direction, and an edge of the connecting segment is substantially aligned with an edge of the first line segment and an edge of the second line segment in a top view.

[0009] Another embodiment of the disclosure provides a semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate; and a first masking layer disposed on the semiconductor substrate. The semiconductor device structure also includes a second masking layer disposed on the first masking layer; and a conductive feature disposed in the first masking layer and the second masking layer and electrically connected to the conductive pad. The conductive feature has a connecting segment extending along a first direction; and a first line segment and a second line segment extending along a second direction. The first line segment and the second line segment are physically connected by the connecting segment, and an edge of the connecting segment is substantially aligned with an edge of the first line segment and an edge of the second line segment.

[0010] In one embodiment, the first direction is perpendicular to the second direction. In one embodiment, the first direction and the second direction are parallel to an upper surface of the conductive feature. In one embodiment, the connecting segment has a width along the second direction, and a shortest distance between the first line segment and the second line segment is less than twice the width of the connecting segment. In one embodiment, the first masking layer includes silicon nitride or silicon oxynitride, the second masking layer includes a diamond-like carbon material having sp3 bonding, and the second masking layer is doped with carbon.

[0011] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device structure. The method includes forming a conductive pad in a semiconductor substrate; and forming a first mask layer on the semiconductor substrate and covering the conductive pad. The method also includes forming a second mask layer on the first mask layer; and performing an implantation process to introduce a dopant into the second mask layer. The method further includes, after the implantation process is performed, forming an opening structure in the first mask layer and the second mask layer to expose the conductive pad. In a top view, the opening structure has a serpentine pattern. Moreover, the method includes filling the opening structure with a conductive feature.

[0012] In an embodiment, the first mask layer and the second mask layer comprise different materials before the implantation process is performed. In an embodiment, the second mask layer comprises a type of diamond carbon material having sp3 bonding before the implantation process is performed. In an embodiment, the dopant comprises carbon. In an embodiment, filling the opening structure with the conductive feature comprises depositing a barrier layer to line the opening structure and extend over the second mask layer; forming a conductive layer in a remaining portion of the opening structure and over the barrier layer; and performing a planarization process on the barrier layer and the conductive layer until the second mask layer is exposed.

[0013] In an embodiment, the serpentine pattern of the opening structure comprises a first line segment and a second line segment extending parallel to each other; and a connecting segment physically connecting the first line segment and the second line segment, wherein an edge of the connecting segment is substantially aligned with an edge of the first line segment and an edge of the second line segment. In an embodiment, an extension direction of the connecting segment is perpendicular to an extension direction of the first line segment; and wherein the connecting segment has a width along the extension direction of the first line segment, and a shortest distance between the first line segment and the second line segment is less than twice the width of the connecting segment. In an embodiment, the method further includes forming a dielectric anti-reflective coating (DARC) layer on the second mask layer; and forming a patterned mask on the dielectric anti-reflective coating layer, wherein the opening structure is formed by performing an etching process using the patterned mask as a mask, and the patterned mask and the dielectric anti-reflective coating layer are removed before the conductive feature is formed. In an embodiment, the implantation process is performed after the dielectric anti-reflective coating layer is formed.

[0014] Some embodiments of a semiconductor device structure and a method of fabricating the same are provided. In some embodiments, the semiconductor device structure has a first mask layer and a second mask layer disposed on a semiconductor substrate, and a conductive feature that penetrates the first mask layer and the second mask layer to connect to a conductive pad in the semiconductor substrate. In a top view, the conductive feature has a serpentine pattern, and an implantation process is performed to introduce a dopant species (e.g., carbon) into the second mask layer when the semiconductor device structure is formed, thereby reducing stress of the second mask layer. As a result, device performance can be improved.

[0015] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technical features and advantages of the present disclosure. It should be appreciated that the concepts and technologies disclosed herein can be employed in a variety of other specific embodiments and examples that will be apparent to those of ordinary skill in the art upon review of this disclosure. Those of ordinary skill in the art, with the included description of one or more implementations and the following claims, will be able to ascertain equivalent implementations and adaptations without undue experimentation. BRIEF DESCRIPTION OF DRAWINGS

[0016] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference symbols refer to like elements throughout the several views.

[0017] Figure 1 is a top view schematic diagram illustrating a semiconductor device structure of some embodiments of the present disclosure.

[0018] Figure 2 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure of some embodiments of the present disclosure along the cross-sectional line A-A’ of Figure 1

[0019] Figure 3 is a flow diagram illustrating a method of fabricating a semiconductor device structure of some embodiments of the present disclosure.

[0020] Figure 4 is a flow diagram illustrating a method of fabricating a semiconductor device structure of some embodiments of the present disclosure.

[0021] Figure 5 is a top view schematic diagram illustrating an intermediate stage of forming a conductive pad during the formation of a semiconductor device structure of some embodiments of the present disclosure.

[0022] Figure 6 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure of some embodiments of the present disclosure along the cross-sectional line A-A’ of Figure 5

[0023] is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure of some embodiments of the present disclosure along the cross-sectional line A-A’ of​Figure 7 is a top view schematic diagram illustrating an intermediate stage of forming a first mask layer and a second mask layer on a semiconductor substrate during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0024] Figure 8 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure along cross-sectional line A-A' of Figure 7 in accordance with some embodiments of the present disclosure.

[0025] Figure 9 is a cross-sectional view schematic diagram illustrating an intermediate stage of performing an implantation process during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0026] Figure 10 is a top view schematic diagram illustrating an intermediate stage of forming a dielectric anti-reflective coating (DARC) layer and a patterned mask on the second mask layer during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0027] Figure 11 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure along cross-sectional line A-A' of Figure 10 in accordance with some embodiments of the present disclosure.

[0028] Figure 12 is a top view schematic diagram illustrating an intermediate stage of forming an opening structure in the first mask layer and the second mask layer during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0029] Figure 13 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure along cross-sectional line A-A' of Figure 12 in accordance with some embodiments of the present disclosure.

[0030] Figure 14 is a top view schematic diagram illustrating an intermediate stage of removing the DARC layer and the patterned mask during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0031] Figure 15 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure along cross-sectional line A-A' of Figure 14 in accordance with some embodiments of the present disclosure.

[0032] Figure 16 is a top view schematic diagram illustrating an intermediate stage of forming a barrier layer and a conductive layer in the opening structure and on the second mask layer during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0033] Figure 17 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming a semiconductor device structure along cross-sectional line A-A' of Figure 16is a cross-sectional view illustrating an intermediate stage of a semiconductor device structure along the section line A-A' of

[0034] Figure 18 is a top view illustrating an intermediate stage of forming a DARC layer on a second mask layer during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0035] Figure 19 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure along the section line A-A' of Figure 18

[0036] Figure 20 is a cross-sectional view illustrating an intermediate stage of performing an implantation process during formation of a semiconductor device structure in accordance with some embodiments of the present disclosure.

[0037] BRIEF DESCRIPTION OF DRAWINGS

[0038] 10: fabrication method

[0039] 100: semiconductor device structure

[0040] 101: semiconductor substrate

[0041] 103: conductive pad

[0042] 105: first mask layer

[0043] 107: second mask layer

[0044] 107': second mask layer

[0045] 110: implantation process

[0046] 113: dielectric anti-reflective coating layer

[0047] 115: patterned mask

[0048] 120: aperture structure

[0049] 120a: first line segment

[0050] 120b: second line segment

[0051] 120c: connecting segment

[0052] 130: aperture structure

[0053] 130a: first line segment

[0054] 130b: second line segment

[0055] 130c: connecting segment

[0056] 133: barrier layer ​

[0057] 135: electrically conductive layer

[0058] 137: electrically conductive feature

[0059] 137a: first segment

[0060] 137b: second segment

[0061] 137c: connecting segment

[0062] 210: implantation process

[0063] 30: method of manufacture

[0064] d: distance

[0065] E1: edge

[0066] E2: edge

[0067] E3: edge

[0068] S11: step

[0069] S13: step

[0070] S15: step

[0071] S17: step

[0072] S19: step

[0073] S21: step

[0074] S23: step

[0075] S25: step

[0076] S31: step

[0077] S33: step

[0078] S35: step

[0079] S37: step

[0080] S39: step

[0081] S41: step

[0082] S43: step

[0083] S45: step

[0084] w: width

[0085] X: direction

[0086] Y: direction DETAILED DESCRIPTION

[0087] The following describes specific examples of components and configurations in order to simplify the embodiments of the present disclosure. Of course, these embodiments are merely intended to illustrate and are not intended to limit the scope of the present disclosure. For example, in the description, a first component formed on a second component can include an embodiment in which the first and second components are in direct contact, and can also include an embodiment in which an additional component is formed between the first and second components such that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless specifically described in the context, it does not inherently represent a specific relationship between the various embodiments and / or the configurations being discussed.

[0088] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. The spatially relative terms are intended to encompass different orientations of the elements in use or operation, in addition to the orientations depicted in the drawings. The devices can have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein can be interpreted accordingly.

[0089] Figure 1 is a top view schematic diagram illustrating a semiconductor element structure 100 according to some embodiments of the present disclosure. Figure 2 is a cross-sectional view schematic diagram illustrating the semiconductor element structure 100 along the cross-sectional line A-A' according to some embodiments of the present disclosure. Figure 1 is a cross-sectional view schematic diagram illustrating the semiconductor element structure 100 along the cross-sectional line A-A' according to some embodiments of the present disclosure. Figure 1 and Figure 2 The semiconductor element structure 100 includes a conductive pad 103 disposed in a semiconductor substrate 101, a first mask layer 105 disposed on the semiconductor substrate 101, and a second mask layer 107' disposed on the first mask layer 105. The second mask layer 107' is also regarded as a doped second mask layer 107' herein.

[0090] In some embodiments, the semiconductor element structure 100 also includes a conductive feature 137 disposed in the first mask layer 105 and the second mask layer 107'. In some embodiments, the conductive feature 137 penetrates through the first mask layer 105 and the second mask layer 107' to connect to the conductive pad 103. In some embodiments, the conductive feature 137 is physically and electrically connected to the conductive pad 103. Further, the conductive feature 137 has a conductive layer 135 and a barrier layer 133, and the barrier layer 133 separates the conductive layer 135 from the conductive pad 103, the semiconductor substrate 101, the first mask layer 105, and the second mask layer 107'.

[0091] It should be understood that, Figure 1 In the top view, the conductive feature 137 has a meandering (or zigzag) pattern. In some embodiments, the meandering pattern of the conductive feature 137 has a first line segment 137a and a second line segment 137b extending in opposite directions, and a connecting segment 137c extending between the first line segment 137a and the second line segment 137b. For example, the first line segment 137a and the second line segment 137b extend along the X direction, while the connecting segment 137c extends along the Y direction and physically connects the first line segment 137a and the second line segment 137b. In some embodiments, the X direction is perpendicular to the Y direction, and both the X and Y directions are parallel to the upper surface of the conductive feature 137.

[0092] exist Figure 1 The multiple dashed lines representing the boundaries of the first line segment 137a, the connecting segment 137c, and the second line segment 137b are used to clarify this disclosure. There is no obvious interface between the first line segment 137a, the connecting segment 137c, and the second line segment 137b. In some embodiments, the connecting segment 137c has a width w along the X direction, and a shortest distance d between the first line segment 137a and the second line segment 137b is less than twice the width w of the connecting segment 137c. In some embodiments, the shortest distance d is in the Y direction.

[0093] In addition, such as Figure 1 As shown in the top view, according to some embodiments, the edge E1 of the first segment 137a is substantially aligned with the edge E2 of the second segment 137b and the edge E3 of the connecting segment 137c. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0094] Figure 3 This is a flowchart illustrating a method 10 for fabricating a semiconductor device structure (e.g., semiconductor device structure 100) according to some embodiments of the present disclosure, and the fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23 and S25. Figure 4 This is a flowchart illustrating a method 30 for fabricating a semiconductor device structure (e.g., semiconductor device structure 100) according to some embodiments of the present disclosure, and the fabrication method 30 includes steps S31, S33, S35, S37, S39, S41, S43 and S45. Figure 3 Steps S11 to S25 and Figure 4 Steps S31 to S45 are described in detail with reference to the following figures.

[0095] Figure 5is a top view schematic diagram illustrating an intermediate stage of semiconductor element structure 100 during formation of semiconductor element structure 100 in some embodiments of the present disclosure. Figure 6 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming semiconductor element structure 100 along cross-sectional line A-A' in some embodiments of the present disclosure. Figure 5 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming semiconductor element structure 100 along cross-sectional line A-A' in some embodiments of the present disclosure. Figure 5 and Figure 6 are shown, a semiconductor substrate 101 is provided, and a conductive pad 103 is formed in semiconductor substrate 101. The corresponding steps are explained in step Sll in fabrication method 10 as shown in Figure 3

[0096] Semiconductor substrate 101 can be a portion of an integrated circuit (IC) chip that includes various passive and active electronic elements, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, high-voltage transistors, high-frequency transistors, fin-type field effect transistors (FinFETs), other suitable IC elements, or combinations thereof.

[0097] Depending on the IC fabrication stage, semiconductor substrate 101 can include various layers of materials (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, insulating features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, semiconductor substrate 101 has been simplified. It should be understood that additional features can be added to semiconductor substrate 101, and in other embodiments, some features as described below can be replaced, modified, or removed.

[0098] In some embodiments, an upper surface of conductive pad 103 is exposed on an upper surface of semiconductor substrate 101. Conductive pad 103 can include a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), or combinations thereof. Furthermore, the fabrication technique of conductive pad 103 can include etching semiconductor substrate 101 to form an opening, depositing a conductive material in the opening and on the upper surface of semiconductor substrate 101, and performing a planarization process to remove excess portions of the conductive material outside the opening.

[0099] Figure 7 is a top view schematic diagram illustrating an intermediate stage of semiconductor element structure 100 during formation of semiconductor element structure 100 in some embodiments of the present disclosure. Figure 8 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming semiconductor element structure 100 along cross-sectional line A-A' in some embodiments of the present disclosure. Figure 7 ​is a cross-sectional view illustrating an intermediate stage of forming the semiconductor device structure 100 along the cross-sectional line A-A' of Figure 7 and Figure 8 As shown, a first mask layer 105 is formed on the semiconductor substrate 101 and covers the upper surface of the conductive pads 103, and a second mask layer 107 is formed on the first mask layer 105. The corresponding steps are illustrated in steps S13 and S15 of the fabrication method 10 as shown in Figure 3 .

[0100] In some embodiments, the first mask layer 105 comprises a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof, and the fabrication technique of the first mask layer 105 comprises a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin-coating process, or other applicable processes. Further, in some embodiments, the second mask layer 107 comprises a carbon-containing material, such as a diamond-like carbon material having sp3 bonding, and the process of forming the second mask layer 107 is similar to or the same as the process of forming the first mask layer 105. In some embodiments, the first mask layer 105 and the second mask layer 107 comprise different materials.

[0101] Figure 9 is a cross-sectional view illustrating an intermediate stage of performing an implantation process 110 during the formation of the semiconductor device structure 100 in some embodiments of the present disclosure. In some embodiments, the implantation process 110 is performed directly on the second mask layer 107 (please refer to Figure 8 ) to introduce a dopant into the second mask layer 107. The corresponding steps are illustrated in step S17 of the fabrication method 10 as shown in Figure 3 .

[0102] In some embodiments, the dopant implanted into the second mask layer 107 comprises carbon. By implanting the dopant (e.g., carbon) inside the second mask layer 107, the stress of the second mask layer 107 can be reduced, and the device performance of the final structure can be improved. After the implantation process 110 is performed, a (doped) second mask layer 107' is obtained.

[0103] Figure 10 is a top view illustrating an intermediate stage during the formation of the semiconductor device structure 100 in some embodiments of the present disclosure. Figure 11 is a cross-sectional view illustrating an intermediate stage of forming the semiconductor device structure 100 along the cross-sectional line A-A' of Figure 10 . As shown, Figure 10 and Figure 11 a dielectric anti-reflective coating (DARC) layer 113 is formed on the (doped) second mask layer 107', and a patterned mask 115 is formed on the DARC layer 113. The corresponding steps are illustrated in steps S21 and S23 of the fabrication method 10 as shown in Figure 3Steps S19 and S21 in the fabrication method 10 shown.

[0104] In some embodiments, the DARC layer 113 comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the fabrication technique of the DARC layer 113 comprises a deposition process, such as a CVD process, a PVD process, a spin-coating process, or other applicable processes. Further, the composition and thickness of the DARC layer 113 can be adjusted to provide minimal reflection and high contrast at predetermined wavelengths used during subsequent lithography (photolithography) processes.

[0105] In addition, the patterned mask 115 has an opening structure 120. In some embodiments, the opening structure 120 is formed by performing an etching process using the patterned mask 115 as a mask. Figure 10 In a top view, the opening structure 120 has a meandering (or zigzag) pattern. In some embodiments, the meandering pattern of the opening structure 120 has a first line segment 120a and a second line segment 120b that are parallel to each other, and a connecting segment 120c that extends between the first line segment 120a and the second line segment 120b.

[0106] For example, the first line segment 120a and the second line segment 120b extend along an X direction, and the connecting segment 120c extends along a Y direction and physically connects the first line segment 120a and the second line segment 120b. In some embodiments, the X direction is perpendicular to the Y direction, and both the X direction and the Y direction are parallel to the upper surface of the semiconductor substrate 101. Further, in some embodiments, the connecting segment 120c has a width w along the X direction, and a shortest distance d between the first line segment 120a and the second line segment 120b is less than twice the width w of the connecting segment 120c. In some embodiments, the shortest distance d is in the Y direction.

[0107] Figure 12 is a top view schematic diagram illustrating an intermediate stage during the formation of the semiconductor device structure 100 in some embodiments of the present disclosure. Figure 13 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming the semiconductor device structure 100 along the cross-sectional line A-A’ in some embodiments of the present disclosure. Figure 12 is a cross-sectional view schematic diagram illustrating an intermediate stage of forming the semiconductor device structure 100 along the cross-sectional line A-A’ in some embodiments of the present disclosure. Figure 12 and Figure 13 As shown, an etching process is performed using the patterned mask 115 as a mask to form an opening structure 130, thereby exposing the conductive pad 103 and the semiconductor substrate 101. The corresponding step is illustrated as step S23 in the fabrication method 10 shown. Figure 3

[0108] ​In some embodiments, the etching process is a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the opening structure 130 is formed under and through the opening structure 120 of the patterned mask 115, the DARC layer 113, the (doped) second mask layer 107', and the first mask layer 105. In some embodiments, the opening structure 130 is formed by a wet etching process, a dry etching process, or a combination thereof. Figure 12 In some embodiments, the opening structure 130 has a meandering (or zigzag) pattern in a top view, which is similar to the opening structure 120 of the patterned mask 115. In some embodiments, the meandering structure of the opening structure 130 has a first line segment 130a and a second line segment 130b extending parallel to each other, and a connecting segment 130c extending between the first line segment 130a and the second line segment 130b.

[0109] For example, the first line segment 130a and the second line segment 130b extend along an X direction, and the connecting segment 130c extends along a Y direction and physically connects the first line segment 130a and the second line segment 130b. In some embodiments, the X direction is perpendicular to the Y direction, and both the X direction and the Y direction are parallel to the upper surface of the semiconductor substrate 101. Further, in some embodiments, the connecting segment 130c has a width w along the X direction, and a shortest distance d between the first line segment 130a and the second line segment 130b is less than twice the width w of the connecting segment 130c. In some embodiments, the shortest distance d is in the Y direction.

[0110] Figure 14 is a top view schematic diagram illustrating an intermediate stage of the semiconductor device structure 100 during formation of the semiconductor device structure 100 according to some embodiments of the present disclosure. Figure 15 is a cross-sectional view schematic diagram illustrating an intermediate stage of the semiconductor device structure 100 during formation of the semiconductor device structure 100 along the cross-sectional line A-A' of Figure 14 is a cross-sectional view schematic diagram illustrating an intermediate stage of the semiconductor device structure 100 during formation of the semiconductor device structure 100 along the cross-sectional line A-A' of Figure 14 and Figure 15 According to some embodiments, the patterned mask 115 and the DARC layer 113 are removed.

[0111] In some embodiments, an ashing process, a wet etching process, or other applicable removal process is used to remove the patterned mask 115 and the DARC layer 113. After the patterned mask 115 and the DARC layer 113 are removed, the remaining portions of the opening structure 130 having the first line segment 130a, the second line segment 130b, and the connecting segment 130c are left in the first mask layer 105 and the second mask layer 107'. Further, as shown in the top view of Figure 14 According to some embodiments, the edge E1 of the first line segment 130a of the opening structure 130 is substantially aligned with the edge E2 of the second line segment 130b of the opening structure 130 and the edge E3 of the connecting segment 130c of the opening structure 130.

[0112] Figure 16 is a top view schematic diagram illustrating an intermediate stage of semiconductor device structure 100 during formation in accordance with some embodiments of the present disclosure. Figure 17 is a cross-sectional view schematic diagram illustrating an intermediate stage of semiconductor device structure 100 during formation of conductive features 137 along cross-sectional line A-A’ in accordance with some embodiments of the present disclosure. Figure 16 is a cross-sectional view schematic diagram illustrating an intermediate stage of semiconductor device structure 100 during formation of conductive features 137 along cross-sectional line A-A’ in accordance with some embodiments of the present disclosure. Figure 16 and Figure 17 Barrier layer 133 is formed to line opening structure 130 and extend over second mask layer 107’, and conductive layer 135 is formed on barrier layer 133. In some embodiments, conductive layer 135 is separated from second mask layer 107’, first mask layer 105, conductive pads 103, and semiconductor substrate 101 by barrier layer 133.

[0113] In some embodiments, barrier layer 133 comprises titanium, titanium nitride (TiN), tantalum, tantalum nitride (TaN), cobalt tungsten (CoW), other applicable materials, or combinations thereof, and the fabrication technique of barrier layer 133 comprises a deposition process, such as a CVD process, a PVD process, an ALD process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, a plating process, or other applicable processes. In some embodiments, conductive layer 135 comprises copper, tungsten, aluminum, titanium, tantalum, gold, silver, or combinations thereof, or other applicable conductive materials. Some processes used to form conductive layer 135 are similar to or the same as those used to form barrier layer 133, and detailed descriptions thereof are not repeated herein.

[0114] Please refer back to Figure 1 and Figure 2 After formation of conductive layer 135, a planarization process is performed on barrier layer 133 and conductive layer 135 until second mask layer 107’ is exposed, so as to form conductive features 137 to fill opening structure 130. The corresponding step is illustrated as step S25 in fabrication method 10 as shown in Figure 3 In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process.

[0115] After formation of conductive features 137, semiconductor device structure 100 is obtained. Further, a dopant, such as carbon, is introduced into second mask layer 107 by implantation process 110 (please refer to Figure 9 ). Thus, the stress of second mask layer 107 can be reduced, which improves the overall device performance.

[0116] Figure 18 is a top view schematic diagram illustrating an intermediate stage of semiconductor device structure 100 after the steps of Figure 7 and Figure 8 in accordance with some embodiments of the present disclosure. Figure 19is a cross-sectional schematic view illustrating an intermediate stage of forming a semiconductor element structure 100 along a cross-sectional line A-A’ of Figure 18 some embodiments of the present disclosure. As shown in Figure 18 and Figure 19 , according to some embodiments, a DARC layer 113 is formed to cover the second mask layer 107 before the second mask layer 107 is doped by an implantation process. The corresponding step is illustrated as step S37 in the fabrication method 00 as shown in Figure 4 It should be understood that steps S31, S33 and S35 of the fabrication method 30 as shown in Figure 4 are respectively the same as steps S11, S13 and S15 of the fabrication method 10 as shown in Figure 3 , and the detailed description thereof will not be repeated herein.

[0117] Figure 20 is a cross-sectional schematic view illustrating an intermediate stage of performing an implantation process 210 during the formation of a semiconductor element structure after steps of Figure 18 and Figure 19 some embodiments of the present disclosure. In some embodiments, the implantation process 210 is performed to introduce a dopant into the second mask layer 107. The corresponding step is illustrated as step S39 in the fabrication method 00 as shown in Figure 4

[0118] In some embodiments, the dopant of the implantation process 210 penetrates through the DARC layer 113 to reach the second mask layer 107 so as to obtain (dope) a second mask layer 107’. In some embodiments, the dopant implanted into the second mask layer 107 comprises carbon.

[0119] By implanting a dopant (e.g. carbon) inside the second mask layer 107, the stress of the second mask layer 107 can be reduced, and the element performance of the final structure can be improved. After step S39, steps S41, S43 and S45 of the fabrication method 30 as shown in Figure 4 are respectively the same as steps S21, S23 and S25 of the fabrication method 10 as shown in Figure 3 , and the detailed description thereof will not be repeated herein.

[0120] ​Some embodiments of a semiconductor device structure 100 and methods of fabricating the same are provided. In some embodiments, the semiconductor device structure 100 includes a first mask layer 105 and a (doped) second mask layer 107 disposed on a semiconductor substrate 101, and a conductive feature 137 penetrating the first mask layer 105 and the (doped) second mask layer 107 to connect to a conductive pad 103 in the semiconductor substrate 101. Further, in fabricating the semiconductor device 100, an implantation process (e.g., implantation process 110 or 210) is performed to introduce a dopant species (e.g., carbon) into the second mask layer 107, thereby reducing the stress of the second mask layer 107. As a result, device performance can be improved.

[0121] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed on the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed on the first mask layer. The first mask layer and the second mask layer comprise different materials. The semiconductor device structure further includes a conductive feature penetrating the first mask layer and the second mask layer to connect to the conductive pad. In a top view, the conductive feature has a meandering pattern.

[0122] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed on the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed on the first mask layer, and a conductive feature disposed in the first mask layer and the second mask layer and electrically connected to the conductive pad. The conductive feature has a connection segment extending along a first direction, and a first line segment and a second line segment extending along a second direction. The first line segment and the second line segment are physically connected by the connection segment, and an edge of the connection segment is substantially aligned with an edge of the first line segment and an edge of the second line segment.

[0123] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device structure. The method includes forming a conductive pad in a semiconductor substrate, and forming a first mask layer on the semiconductor substrate and covering the conductive pad. The method also includes forming a second mask layer on the first mask layer, and performing an implantation process to introduce a dopant species into the second mask layer. The method further includes, after the implantation process is performed, forming an opening structure in the first mask layer and the second mask layer to expose the conductive pad. In a top view, the opening structure has a meandering pattern. In addition, the method includes filling the opening structure with a conductive feature.

[0124] Some embodiments of the present disclosure have many advantageous features. By performing an implant process to introduce a dopant species (e.g., carbon) into a masking layer surrounding a conductive feature, the stress of the masking layer is reduced, which improves overall device performance.

[0125] While the present disclosure and its advantages have been illustrated by description of various embodiments, it is understood that changes, substitutions, and alterations can be made by one skilled in the art without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented in different methodologies, and many of the individual steps can be implemented in other processes or combinations thereof.

[0126] Further, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily understand, the disclosure lends itself to various modifications, adaptations and variations in the implementation, process, machine, manufacture, composition of matter, means, methods and steps that are intended to be encompassed within the scope of the claims. Accordingly, the application is not to be restricted in scope only to the specific embodiments disclosed and can be practiced with other embodiments and in other ways.

Claims

1. A semiconductor device structure, comprising: a conductive pad disposed in a semiconductor substrate; a first masking layer disposed on the semiconductor substrate; a second masking layer disposed on the first masking layer, wherein the first masking layer and the second masking layer comprise different materials; and a conductive feature penetrating the first masking layer and the second masking layer to connect to the conductive pad, wherein the conductive feature has a serpentine pattern in a top view, wherein the serpentine pattern of the conductive feature comprises: a first line segment and a second line segment extending along a first direction in a top view; and a connecting segment extending along a second direction in a top view and physically connecting the first line segment and the second line segment, wherein the connecting segment has a width along the first direction, and a shortest distance between the first line segment and the second line segment is less than twice the width.

2. The semiconductor device structure of claim 1, wherein the second masking layer comprises a diamond-like carbon material having sp3 bonding.

3. The semiconductor device structure of claim 1, wherein the second masking layer is doped with carbon.

4. The semiconductor device structure of claim 1, wherein the conductive feature further comprises: a conductive layer; and a barrier layer separating the conductive layer from the conductive pad, the first masking layer, and the second masking layer.

5. The semiconductor device structure of claim 1, wherein the first direction is perpendicular to the second direction, and an edge of the connecting segment is substantially aligned with an edge of the first line segment and an edge of the second line segment in a top view.

6. A semiconductor device structure, comprising: a conductive pad disposed in a semiconductor substrate; a first masking layer disposed on the semiconductor substrate; a second masking layer disposed on the first masking layer; and a conductive feature disposed in the first masking layer and the second masking layer and electrically connected to the conductive pad, wherein the conductive feature has: a connecting segment extending along a first direction; and a first line segment and a second line segment extending along a second direction, wherein the first line segment and the second line segment are physically connected by the connecting segment, and an edge of the connecting segment is substantially aligned with an edge of the first line segment and an edge of the second line segment, wherein the serpentine pattern of the conductive feature comprises: a first line segment and a second line segment extending along a first direction in a top view; and a connecting segment extending along a second direction in a top view and physically connecting the first line segment and the second line segment, wherein the connecting segment has a width along the first direction, and a shortest distance between the first line segment and the second line segment is less than twice the width.

7. The semiconductor device structure of claim 6, wherein the first direction is perpendicular to the second direction.

8. The semiconductor device structure of claim 6, wherein the first direction and the second direction are parallel to an upper surface of the conductive feature. ​ ​ ​ ​ ​ 9. The semiconductor device structure of claim 6, wherein the connection segment has a width along the second direction, and a shortest distance between the first line segment and the second line segment is less than twice the width of the connection segment.

10. The semiconductor device structure of claim 6, wherein the first mask layer comprises silicon nitride or silicon oxynitride, the second mask layer comprises a diamond-like carbon material having sp3 bonding, and the second mask layer is doped with carbon.

11. A method of fabricating a semiconductor device structure, comprising: forming a conductive pad in a semiconductor substrate; forming a first mask layer on the semiconductor substrate and covering the conductive pad; forming a second mask layer on the first mask layer; performing an implantation process to introduce a dopant into the second mask layer; after the implantation process is performed, forming an opening structure in the first mask layer and the second mask layer to expose the conductive pad, wherein in a top view, the opening structure has a serpentine pattern; filling the opening structure with a conductive feature, wherein the serpentine pattern of the conductive feature includes: a first line segment and a second line segment extending along a first direction in a top view; and a connection segment extending along a second direction in a top view and physically connecting the first line segment and the second line segment, wherein the connection segment has a width along the first direction, and a shortest distance between the first line segment and the second line segment is less than twice the width of the connection segment.

12. The method of fabricating a semiconductor device structure of claim 11, wherein before the implantation process is performed, the first mask layer and the second mask layer comprise different materials.

13. The method of fabricating a semiconductor device structure of claim 11, wherein before the implantation process is performed, the second mask layer comprises a diamond-like carbon material having sp3 bonding.

14. The method of fabricating a semiconductor device structure of claim 11, wherein the dopant comprises carbon.

15. The method of fabricating a semiconductor device structure of claim 11, wherein filling the opening structure with the conductive feature includes: depositing a barrier layer to line the opening structure and extend on the second mask layer; forming a conductive layer in a remaining portion of the opening structure and on the barrier layer; and performing a planarization process on the barrier layer and the conductive layer until the second mask layer is exposed.

16. The method of fabricating a semiconductor device structure of claim 11, wherein the serpentine pattern of the opening structure includes: a first line segment and a second line segment extending parallel to each other; and a connection segment physically connecting the first line segment and the second line segment, wherein an edge of the connection segment is substantially aligned with an edge of the first line segment and an edge of the second line segment.

17. The method of fabricating a semiconductor device structure of claim 16, wherein an extension direction of the connection segment is perpendicular to an extension direction of the first line segment; and wherein the connection segment has a width along the extension direction of the first line segment, and a shortest distance between the first line segment and the second line segment is less than twice the width of the connection segment. ​ ​ 18. The method of claim 11, further comprising: forming a dielectric anti-reflective coating layer over the second masking layer; and forming a patterned mask over the dielectric anti-reflective coating layer, wherein the opening formation technique comprises performing an etching process using the patterned mask as a mask, and removing the patterned mask and the dielectric anti-reflective coating layer prior to formation of the conductive features.

19. The method of claim 18, wherein an implantation process is performed after formation of the dielectric anti-reflective coating layer.

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