Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device comprises: a substrate; a plurality of chips disposed on the substrate, each chip comprising a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection portions disposed on the substrate; a terminal extension layer disposed on the substrate, the terminal extension layer comprising a conductive material, wherein the plurality of fixed connection portions are disposed adjacent to the plurality of chips respectively; the semiconductor device further comprises a plurality of extended traces located in the terminal extension layer, the extended traces being used to electrically connect the plurality of chips; and an extended trace for electrically connecting two chips comprising at least a first trace segment and a second trace segment, the first trace segment being used to electrically connect a terminal of a chip to a fixed connection portion adjacent to the chip, and the second trace segment being used to connect two fixed connection portions between two chips.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In current semiconductor devices such as display devices, it is usually necessary to use a variety of different integrated circuits (abbreviated as IC), including but not limited to driver IC, touch IC and ROIC, etc. These chips are connected to the display backplane through different methods such as COF or COG. This traditional method is difficult to achieve an organic combination between display pixel units and different chips, and also occupies additional space outside the display backplane, making it difficult to achieve system miniaturization and integration. In addition, due to the low precision of PCB and FPC processes and the subsequent bonding process precision, the size of the pad of the chip pin after packaging will be relatively large, thereby reducing the feasibility of chip miniaturization.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] In one aspect, a semiconductor device is provided, comprising: a substrate; a chip disposed on the substrate, the chip comprising a chip body and a plurality of terminals disposed on the chip body; a terminal extension layer disposed on the substrate, the terminal extension layer comprising a conductive material, wherein the terminal extension layer and at least one terminal are located on the same side of the chip body, the semiconductor device further comprising a plurality of extension traces located in the terminal extension layer, the plurality of extension traces being electrically connected to the plurality of terminals, respectively, for leading out the plurality of terminals; and an orthographic projection of at least one extension trace on the substrate completely covers an orthographic projection of a terminal electrically connected to the extension trace on the substrate.

[0006] According to some exemplary embodiments, the semiconductor device also includes an adhesive layer, which is arranged between the substrate and the chip body and is used to fix the chip on the substrate; and the chip body includes a first surface, which faces or contacts the adhesive layer, and at least one terminal is arranged on a surface of the chip body other than the first surface.

[0007] According to some exemplary embodiments, the substrate includes a first substrate surface, the chip is arranged on the first substrate surface, the first substrate surface includes a first substrate edge; and the orthographic projection of at least one extended trace on the substrate is inclined relative to the first substrate edge.

[0008] According to some exemplary embodiments, the chip body has a second surface away from the substrate, the orthographic projection of the second surface on the substrate has a regular shape, the orthographic projection of the second surface on the substrate includes a first edge; and the first edge is inclined relative to the first substrate edge.

[0009] According to some exemplary embodiments, the at least one extended trace forms a first angle between an extension line of the orthographic projection on the substrate and an extension line of the first substrate edge, and the first angle is greater than 0° and less than 90°; and / or, a second angle is formed between an extension line of the first edge and an extension line of the first substrate edge, and the second angle is greater than 0° and less than 90°.

[0010] According to some exemplary embodiments, the substrate includes a first substrate surface, and the chip is arranged on the first substrate surface; the chip body of the chip includes a second surface, a first side surface and a second side surface, the second surface and the first surface are respectively located on opposite sides of the chip body, the first side surface and the second side surface are respectively located on side surfaces of the chip body, each of the first side surface and the second side surface connects the first surface and the second surface; and at least one of the first side surface and the second side surface is inclined relative to the first substrate surface.

[0011] According to some exemplary embodiments, at least one extended trace is in direct contact with at least one terminal, and a portion of the at least one extended trace is in direct contact with one of the first side surface and the second side surface.

[0012] According to some exemplary embodiments, the semiconductor device also includes a first planarization layer arranged on one side of the chip and covering the terminal; and the terminal extension layer is located on a side of the first planarization layer away from the chip, and one end of the extension trace is electrically connected to the terminal through a via or a groove passing through the first planarization layer.

[0013] According to some exemplary embodiments, the semiconductor device further includes a pad located on a side of the chip body close to the substrate, and an orthographic projection of the pad on the substrate at least partially overlaps with an orthographic projection of the chip body on the substrate.

[0014] According to some exemplary embodiments, the semiconductor device also includes a first planarization layer arranged on one side of the chip and covering the terminal, and a second planarization layer arranged on a side of the first planarization layer away from the substrate; the semiconductor device also includes a first routing line, the first routing line is located in the redistribution layer; and the redistribution layer is located on a side of the second planarization layer away from the chip, and one end of the first routing line is electrically connected to the extended routing line through a via or a groove passing through both the first planarization layer and the second planarization layer.

[0015] According to some exemplary embodiments, the semiconductor device further includes a functional device electrically connected to at least one terminal of the chip; and the functional device and the chip are located at different layers.

[0016] According to some exemplary embodiments, the semiconductor device includes a plurality of repeating units, and the plurality of repeating units are arranged in an array along a first direction and a second direction on the substrate; each repeating unit includes a plurality of the chips, and the plurality of chips located in each repeating unit are arranged in an array along the first direction and the second direction on the substrate, or at least a portion of the plurality of chips located in each repeating unit are arranged in an array along the first direction and the second direction on the substrate; and in at least two of the plurality of repeating units, the relative position of at least one chip in one repeating unit in the repeating unit is different from the relative position of a corresponding chip in another repeating unit in the other repeating unit; and / or, in at least two of the plurality of repeating units, the orientation of at least one chip in one repeating unit in the repeating unit is different from the orientation of a corresponding chip in another repeating unit in the other repeating unit.

[0017] According to some exemplary embodiments, in at least two of the multiple repeating units, the length of an extended routing line used to lead out at least one terminal of at least one chip in one repeating unit is not equal to the length of an extended routing line used to lead out a corresponding terminal of a corresponding chip in another repeating unit; and / or, in at least two of the multiple repeating units, the extension direction of an extended routing line used to lead out at least one terminal of at least one chip in one repeating unit is different from the extension direction of an extended routing line used to lead out a corresponding terminal of a corresponding chip in another repeating unit.

[0018] According to some exemplary embodiments, for two chips located in the same row along the first direction or the second direction, the chip body of each chip has a second surface away from the substrate, the orthographic projection of the second surface on the substrate has a regular shape, and a line between the geometric centers of the orthographic projections of the second surfaces of the chip bodies of the two chips on the substrate forms a third angle with the first direction or the second direction, and the third angle is greater than 0° and less than 90°.

[0019] According to some exemplary embodiments, the multiple terminals included in the chip are all located on the second surface of the chip body of the chip; or, the multiple terminals included in the chip are respectively located on the first side surface and the second side surface of the chip body of the chip; or, the multiple terminals included in the chip are respectively located on the first surface and the second surface of the chip body of the chip.

[0020] According to some exemplary embodiments, it is characterized in that the chip includes a first chip and a second chip, the first chip includes at least two first terminals, and the second chip includes at least two second terminals; wherein the first chip and the second chip are configured to implement different functions, the first chip includes at least one of a light-emitting chip and a sensor chip, and the second chip includes at least one of a sensor chip and a control chip; and one end of the at least one extended routing is electrically connected to the first chip, and the other end of the at least one extended routing is electrically connected to the second terminal.

[0021] According to some exemplary embodiments, the first chip includes a light emitting chip, and the first chip and the second chip are arranged on the same layer.

[0022] According to some exemplary embodiments, the first chip includes a light emitting chip, the first chip and the second chip are arranged in different layers; and the semiconductor device further includes a driving element, the driving element and the first chip are electrically connected through at least one extended trace.

[0023] According to some exemplary embodiments, the driving element is a driving chip, the orthographic projection of the driving chip on the substrate at least partially overlaps with the orthographic projection of the first chip on the substrate; and the first chip includes a main light-emitting surface, which is located on a side of the first chip away from the driving chip.

[0024] According to some exemplary embodiments, the driving element is a driving chip, the orthographic projection of the driving chip on the substrate does not overlap with the orthographic projection of the first chip on the substrate; and the first chip includes a main light-emitting surface, which is located on a side of the first chip close to the driving chip.

[0025] According to some exemplary embodiments, the semiconductor device further includes a protection layer, the protection layer is located on a side of the first chip away from the second chip, the protection layer covers the at least one terminal expansion layer and exposes a light emitting surface of the first chip.

[0026] According to some exemplary embodiments, the driving element includes a driving circuit for driving the first chip, the driving circuit includes at least a thin film transistor, the thin film transistor is located at a different layer from the first chip and the second chip; and the thin film transistor includes at least a source and a drain, the source or the drain is electrically connected to at least one extended trace through a via or a groove.

[0027] According to some exemplary embodiments, the first chip and the second chip are arranged in different layers; and the thin film transistor is located on a side of the first chip away from the substrate, and the second chip is located on a side of the thin film transistor away from the substrate.

[0028] According to some exemplary embodiments, the chip also includes a third chip, and the first chip, the second chip and the third chip are configured to implement different functions from each other; the semiconductor device includes at least one chipset, each chipset includes at least one second chip and at least one third chip; and a plurality of chipsets are electrically connected to a plurality of first chips in a one-to-one manner; or, one chipset is electrically connected to a plurality of first chips.

[0029] According to some exemplary embodiments, the first chip includes a sensor chip, a plurality of sensor chips are connected in series; and the second chip includes a control chip.

[0030] According to some exemplary embodiments, the sensor chip includes at least one of a transducer chip and a piezoelectric sensor chip.

[0031] According to some exemplary embodiments, each of the sensor chips includes a first electrode, a second electrode and a functional film sandwiched between the first electrode and the second electrode; the first electrodes of multiple sensor chips are located on the same layer, and the second electrodes of multiple sensor chips are located on the same layer; and in two adjacent sensor chips, the first electrode of one sensor chip is electrically connected to the second electrode of the other sensor chip through a via or a groove.

[0032] According to some exemplary embodiments, each of the sensor chips includes a first electrode, a second electrode and a functional film sandwiched between the first electrode and the second electrode; the semiconductor device includes a plurality of sensor chip groups and a plurality of conductive parts, each sensor chip group includes at least two sensor chips; the plurality of sensor chip groups are respectively arranged on the plurality of conductive parts, and the plurality of conductive parts are arranged at intervals; and in a sensor chip group, the first electrode of one sensor chip and the second electrode of the other sensor chip in any two adjacent sensor chips are in contact with the same conductive part.

[0033] According to some exemplary embodiments, the semiconductor device also includes a second planarization layer covering the multiple sensor chips and a second terminal extension layer arranged on a side of the second planarization layer away from the substrate, the second terminal extension layer including a plurality of second extension traces; and in two adjacent sensor chip groups, a first electrode of a sensor chip of one sensor chip group is electrically connected to a second electrode of a sensor chip of another sensor chip group through at least one second extension trace and a via or a groove passing through the second planarization layer.

[0034] According to some exemplary embodiments, each of the sensor chips includes a first electrode, a second electrode and a functional film sandwiched between the first electrode and the second electrode; the semiconductor device includes a plurality of sensor chip groups and at least one conductive part, each sensor chip group includes at least two sensor chips; at least two sensor chip groups are arranged on the same conductive part; and in a sensor chip group, at least two sensor chips are stacked and placed on the conductive part, the first electrode or the second electrode of a sensor chip closest to the conductive part is in contact with the conductive part, and the first electrode of one sensor chip of any two adjacent sensor chips is in contact with the second electrode of the other sensor chip.

[0035] According to some exemplary embodiments, the at least one chip also includes a control chip; the control chip and the multiple sensor chips are located on the same layer; the semiconductor device also includes a second planarization layer covering the multiple sensor chips and the control chip and a second terminal extension layer arranged on the side of the second planarization layer away from the substrate, the second terminal extension layer including multiple second extension traces; and a first electrode or a second electrode of a sensor chip closest to the control chip is electrically connected to a terminal of the control chip through at least one second extension trace and a via or a groove passing through the second planarization layer.

[0036] According to some exemplary embodiments, the semiconductor device also includes: a plurality of pixels disposed on the substrate, the plurality of pixels being arranged in an array along row and column directions; a gating chip, the gating chip including at least two ports; a plurality of row signal connection lines, one row signal connection line being electrically connected to a plurality of pixels located in the same row; a plurality of column signal connection lines, one column signal connection line being electrically connected to a plurality of pixels located in the same column; and a gating transistor, the first chip being electrically connected to the column signal connection line through the gating transistor, wherein the plurality of row signal connection lines are electrically connected to a plurality of ports of the gating chip through first extension lines, respectively, a plurality of first chips are electrically connected to a second chip through second extension lines, and the first extension lines and the second extension lines are located in the at least one terminal extension layer.

[0037] According to some exemplary embodiments, a display device is provided, the display device comprising: a substrate; a plurality of chips arranged on the substrate, wherein each first chip comprises at least two terminals, the chip comprises at least one selected from a light emitting diode chip, a sub-millimeter light emitting diode chip and a micro light emitting diode chip; a driving circuit for driving the chip, the driving circuit comprising at least one thin film transistor; and at least one terminal extension layer arranged on the substrate, the terminal extension layer comprising a conductive material, wherein the terminal extension layer and at least one terminal are located on the same side of the chip body, the semiconductor device further comprises a plurality of extension traces located in the at least one terminal extension layer, the plurality of extension traces are electrically connected to the plurality of terminals, respectively, for leading out the plurality of terminals; the orthographic projection of at least one extension trace on the substrate covers the orthographic projection of a terminal electrically connected to the extension trace on the substrate; and one end of the at least one extension trace is electrically connected to the thin film transistor of the driving circuit.

[0038] In another aspect, a method for manufacturing a semiconductor device is provided, the method comprising:

[0039] placing a chip on a substrate, wherein the chip comprises a chip body and a plurality of terminals disposed on the chip body; and

[0040] forming a terminal expansion layer on a side of the chip away from the substrate through a post-alignment process, wherein the terminal expansion layer comprises a conductive material,

[0041] Wherein, forming a terminal expansion layer on a side of the chip away from the substrate through a post-alignment process comprises:

[0042] taking a photo of the substrate on which the chip is disposed;

[0043] Use image recognition technology to determine the coordinates of multiple terminals and generate terminal graphics files;

[0044] forming a conductive material layer on a side of the chip away from the substrate; and

[0045] According to the graphic file, the conductive material layer is etched by a photolithography process to form a plurality of extended traces in the terminal extension layer,

[0046] The plurality of extended wirings are electrically connected to the plurality of terminals respectively, and are used to lead out the plurality of terminals; and

[0047] An orthographic projection of at least one extended trace on the substrate completely covers an orthographic projection of a terminal electrically connected to the extended trace on the substrate.

[0048] According to some exemplary embodiments, photographing the substrate on which the chip is disposed comprises:

[0049] Taking a picture of a first photographing area of ​​the substrate on which the chip is disposed; and

[0050] Taking a position calibration mark set on the substrate as the origin, the photographing device is translated at a fixed step distance to take a photograph of a second photographing area of ​​the substrate where the chip is set,

[0051] The number of photographing times is related to the distribution density of the chips, and at least one chip is arranged in each photographing area.

[0052] According to some exemplary embodiments, placing the chip on the substrate includes:

[0053] forming an adhesive layer on the substrate; and

[0054] The chip is transferred to the adhesive layer through a transfer process, so that the chip is fixed on the substrate through the adhesive layer.

[0055] According to some exemplary embodiments, the manufacturing method further comprises:

[0056] After forming at least one terminal expansion layer on a side of the plurality of chips away from the substrate through the post-alignment process, forming a driving element on a side of the terminal expansion layer away from the substrate,

[0057] Wherein, the driving element includes a driving chip or a driving circuit having a thin film transistor.

[0058] According to some exemplary embodiments, the manufacturing method further comprises:

[0059] Before placing a plurality of chips on a substrate, a driving element is formed on the substrate.

[0060] Wherein, the driving element includes a driving chip or a driving circuit having a thin film transistor.

[0061] According to some exemplary embodiments, forming at least one terminal expansion layer on a side of the plurality of chips away from the substrate through a post-alignment process includes:

[0062] A first terminal extension layer is directly formed on the chip, and a first extension trace located in the first terminal extension layer is formed by a photolithography process, so that one end of the first extension trace contacts the first terminal and a part of the first extension trace contacts the side wall of the chip.

[0063] According to some exemplary embodiments, the manufacturing method further includes: forming a first planarization layer on a side of the chip away from the substrate, the first planarization layer covering the terminals of the chip; and

[0064] A plurality of via holes or grooves are formed in the first planarization layer by a photolithography process, wherein the plurality of via holes or grooves respectively expose at least a portion of the terminals of the chip.

[0065] Wherein, forming a terminal expansion layer on a side of the chip away from the substrate by a post-alignment process comprises:

[0066] A terminal extension layer is formed on a side of the first planarization layer away from the substrate, and an extension trace is formed in the terminal extension layer through a post-alignment process, so that one end of the extension trace contacts the terminal through the via hole or the groove.

[0067] According to some exemplary embodiments, forming a terminal expansion layer on a side of the chip away from the substrate through a post alignment process includes:

[0068] forming a terminal expansion layer by the post alignment process;

[0069] forming a first planarization layer on a side of the terminal extension layer away from the substrate;

[0070] forming a plurality of via holes or grooves in the first planarization layer by a photolithography process, wherein the plurality of via holes or grooves expose at least a portion of the terminal expansion layer; and

[0071] forming a redistribution layer on a side of the first planarization layer away from the substrate,

[0072] Wherein, the manufacturing method further comprises:

[0073] The terminal expansion layer is used as a seed layer, and a metal layer is electrochemically plated to grow a conductive connection portion with a thickness equal to that of the first planarization layer in the multiple vias or grooves, wherein the conductive connection portion is used to electrically connect the terminal expansion layer and the redistribution layer.

[0074] According to some exemplary embodiments, the manufacturing method further comprises:

[0075] In the post-alignment process, the coordinate information of the defective point is determined by using image recognition technology; and

[0076] The conductive material layer is etched based on the coordinate information and by the photolithography process to form at least one extended wiring in the terminal extension layer for repairing the defective point.

[0077] On the other hand, a semiconductor device is provided, comprising: a substrate; a plurality of chips arranged on the substrate, each chip comprising a chip body and a plurality of terminals arranged on the chip body; a plurality of fixed connection parts arranged on the substrate; a terminal extension layer arranged on the substrate, the terminal extension layer comprising a conductive material, wherein the plurality of fixed connection parts are respectively arranged adjacent to the plurality of chips; the semiconductor device also comprises a plurality of extended routing lines located in the terminal extension layer, the extended routing lines are used to electrically connect the plurality of chips; and the extended routing lines used to electrically connect two chips comprise at least a first routing segment and a second routing segment, the first routing segment being used to electrically connect a terminal of a chip with a fixed connection part adjacent to the chip, and the second routing segment being used to connect two fixed connection parts between two chips.

[0078] According to some exemplary embodiments, at least one second routing segment extends along a first direction; and in two chips electrically connected by an extended routing including a second routing segment extending along the first direction, a relative position of one chip in the first direction is different from a relative position of the other chip in the first direction.

[0079] According to some exemplary embodiments, among two chips electrically connected via an extended routing line including at least one second routing line segment, at least one chip is tilted with respect to an extension line of the second routing line segment.

[0080] According to some exemplary embodiments, in two chips electrically connected by an extended routing line including at least one second routing line segment, an orientation of one chip relative to an extension line of the second routing line segment is different from an orientation of another chip relative to the extension line of the second routing line segment.

[0081] According to some exemplary embodiments, in two chips electrically connected by an extended routing including at least one second routing segment, the multiple terminals included in each chip include at least a first terminal and a second terminal; the second routing segment included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment included in the extended routing for electrically connecting the second terminals of the two chips are parallel to each other, and / or the second routing segment included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment included in the extended routing for electrically connecting the second terminals of the two chips are substantially equal in length.

[0082] According to some exemplary embodiments, at least one first routing segment and a second routing segment adjacent to and electrically connected to the first routing segment have an angle therebetween, and the angle is greater than 0° and less than 180°.

[0083] According to some exemplary embodiments, among two first routing segments adjacent to and electrically connected to the same second routing segment, an angle between one first routing segment and the second routing segment adjacent to and electrically connected thereto is different from an angle between another first routing segment and the second routing segment adjacent to and electrically connected thereto.

[0084] According to some exemplary embodiments, in two first routing segments electrically connected to a first terminal and a second terminal of the same chip, an angle between one first routing segment and a second routing segment adjacent to and electrically connected thereto is different from an angle between another first routing segment and a second routing segment adjacent to and electrically connected thereto.

[0085] According to some exemplary embodiments, a plurality of the first routing segments are located in a same layer; and the second routing segment and the first routing segment are located in a same layer or a different layer.

[0086] According to some exemplary embodiments, a display device is provided, the display device comprising: a substrate; a plurality of pixels disposed on the substrate, the plurality of pixels being arranged in an array along a first direction and a second direction; a plurality of chips disposed on the substrate, each chip comprising a chip body and a plurality of terminals disposed on the chip body; a plurality of fixed connection portions disposed on the substrate; at least one terminal extension layer disposed on the substrate, the terminal extension layer comprising a conductive material, wherein the plurality of fixed connection portions are respectively disposed adjacent to the plurality of chips; the semiconductor device further comprising a plurality of extended traces located in the at least one terminal extension layer, the extended traces being used to electrically connect the plurality of chips; the extended traces being used to electrically connect two chips comprising at least a first trace segment and a second trace segment, the first trace segment being used to electrically connect a terminal of a chip to a fixed connection portion adjacent to the chip, the second trace segment being used to connect two fixed connection portions between two chips; and at least one chip being inclined relative to the first direction and the second direction.

[0087] According to some exemplary embodiments, the plurality of chips are arranged in an array along a first direction and a second direction; and at least one first routing segment is inclined relative to the first direction and the second direction.

[0088] According to some exemplary embodiments, the second routing segment extends along the first direction or the second direction.

[0089] In another aspect, a method for manufacturing a semiconductor device is provided, the method comprising:

[0090] Placing a plurality of chips on a substrate, wherein each chip comprises a chip body and a plurality of terminals disposed on the chip body;

[0091] forming a plurality of fixed connection parts on the substrate; and

[0092] A terminal expansion layer is formed on a side of the plurality of chips away from the substrate through a post-alignment process, wherein the terminal expansion layer comprises a conductive material.

[0093] Wherein, forming a terminal expansion layer on a side of the plurality of chips away from the substrate through a post-alignment process comprises:

[0094] Taking a photo of the substrate provided with the plurality of chips and the plurality of fixed connection parts;

[0095] The coordinates of the terminals of each chip are determined by using image recognition technology to generate a graphic file of the terminals;

[0096] forming a conductive material layer on a side of the plurality of chips away from the substrate; and

[0097] According to the graphic file, the conductive material layer is etched by a photolithography process to form a plurality of extended traces in the terminal extension layer,

[0098] Among them, the extended routing is used to electrically connect the multiple chips, and the extended routing used to electrically connect two chips includes at least a first routing segment and a second routing segment, the first routing segment is used to electrically connect a terminal of a chip with a fixed connection part adjacent to the chip, and the second routing segment is used to connect two fixed connection parts between the two chips.

[0099] According to some exemplary embodiments, the step of generating a graphic file of the terminal includes:

[0100] Use image recognition technology to determine the coordinates of the terminals of each chip;

[0101] Reading preset coordinates of each fixed connection part; and

[0102] A graphic file of the terminal is generated according to the determined coordinates of the terminal of each chip and the read preset coordinates of each fixed connection portion.

[0103] According to some exemplary embodiments, photographing the substrate provided with the plurality of chips and the plurality of fixed connection parts comprises:

[0104] Taking a picture of a first photographing area of ​​the substrate where the plurality of chips and the plurality of fixed connection parts are disposed; and

[0105] Taking an integral absolute coordinate calibration mark disposed on the substrate as the origin, the photographing device is translated at a fixed stepping distance to photograph a second photographing area of ​​the substrate where the plurality of chips and the plurality of fixed connecting parts are disposed,

[0106] The number of photographing times is related to the distribution density of the chips, and at least one chip is arranged in each photographing area.

[0107] According to some exemplary embodiments, there is an overlapping photographing area between at least two photographing areas.

[0108] According to some exemplary embodiments, the manufacturing method further comprises:

[0109] forming an overall absolute coordinate calibration mark and a plurality of position calibration marks on the substrate,

[0110] Wherein, the multiple position calibration marks correspond one-to-one to the multiple photographing areas respectively.

[0111] On the other hand, a semiconductor device is provided, comprising: a first substrate and a second substrate arranged opposite to each other; a chip arranged on the first substrate, the chip comprising a chip body and a plurality of first terminals arranged on the chip body; a terminal extension layer arranged on the first substrate, the terminal extension layer comprising a conductive material; and a plurality of second terminals arranged on the second substrate, wherein the terminal extension layer and at least one first terminal are located on the same side of the chip body, the semiconductor device also comprises a plurality of extension traces located in the terminal extension layer, the plurality of extension traces are respectively electrically connected to the plurality of first terminals for leading out the plurality of first terminals; the orthographic projections of the plurality of extension traces on the first substrate completely cover the orthographic projections of the first terminals electrically connected to the extension traces on the first substrate; and the plurality of first terminals are respectively electrically connected to the plurality of second terminals through the plurality of extension traces, and the orthographic projections of the plurality of second terminals on the first substrate at least partially overlap with the orthographic projections of the plurality of extension traces on the first substrate.

[0112] According to some exemplary embodiments, the semiconductor device further includes a plurality of driving elements, wherein the plurality of driving elements are disposed on the second substrate, the plurality of second terminals are located on a side of the plurality of driving elements away from the second substrate, and the plurality of second terminals are electrically connected to the plurality of driving elements respectively.

[0113] According to some exemplary embodiments, the chip includes a plurality of first terminals that are all located on a side of the chip body of the chip away from the first substrate; and the semiconductor device also includes an adhesive layer, which is arranged between the first substrate and the chip body, for fixing the at least one chip on the first substrate.

[0114] According to some exemplary embodiments, the chip includes a plurality of first terminals respectively located on both sides of a chip body of the chip along a direction parallel to a first substrate surface of the first substrate, wherein the first substrate surface of the first substrate is a surface of the first substrate on which the chip is set; and the semiconductor device also includes an adhesive layer, which is arranged between the first substrate and the chip body, for fixing the chip on the first substrate.

[0115] According to some exemplary embodiments, the chip includes a plurality of first terminals respectively located on both sides of a chip body of the chip along a direction perpendicular to a first substrate surface of the first substrate, wherein the first substrate surface of the first substrate is a surface of the first substrate on which the chip is set; and the semiconductor device also includes an adhesive layer and a first conductive layer, the adhesive layer is arranged between the first substrate and the chip body, the first conductive layer is arranged between the adhesive layer and the chip, and the first conductive layer is electrically connected to at least one first terminal of the chip close to the first substrate.

[0116] According to some exemplary embodiments, the first substrate includes a first substrate surface, the chip is arranged on the first substrate surface, the first substrate surface includes a first substrate edge; and the orthographic projection of at least one extended trace on the first substrate is inclined relative to the first substrate edge.

[0117] According to some exemplary embodiments, the chip body has a second surface away from the first substrate, the orthographic projection of the second surface on the first substrate has a regular shape, the orthographic projection of the second surface on the first substrate includes a first edge; and the first edge is inclined relative to the edge of the first substrate.

[0118] In yet another aspect, a method for manufacturing a semiconductor device is provided, the method comprising:

[0119] Placing a chip on a first substrate, wherein the chip comprises a chip body and a plurality of first terminals disposed on the chip body;

[0120] forming a terminal expansion layer on a side of the chip away from the first substrate through a post-alignment process, wherein the terminal expansion layer comprises a conductive material;

[0121] forming a plurality of second terminals on a second substrate; and

[0122] assembling the first substrate and the second substrate so that the plurality of first terminals are electrically connected to the plurality of second terminals, respectively;

[0123] Wherein, forming a terminal expansion layer on a side of the chip away from the first substrate by a post-alignment process comprises:

[0124] taking a photo of the substrate on which the chip is disposed;

[0125] Using image recognition technology to determine the coordinates of the first terminal of the chip to generate a graphic file of the first terminal;

[0126] forming a conductive material layer on a side of the chip away from the first substrate; and

[0127] According to the graphic file, the conductive material layer is etched by a photolithography process to form a plurality of extended traces in the terminal extension layer,

[0128] The orthographic projections of the plurality of extended traces on the first substrate completely cover the orthographic projections of the first terminals electrically connected to the extended traces on the first substrate; and

[0129] The plurality of first terminals are electrically connected to the plurality of second terminals through the plurality of extended traces, respectively, and orthographic projections of the plurality of second terminals on the first substrate at least partially overlap with orthographic projections of the plurality of extended traces on the first substrate.

[0130] According to some exemplary embodiments, placing the chip on the first substrate includes:

[0131] forming an adhesive layer on the first substrate; and

[0132] The chip is transferred to the adhesive layer through a transfer process, so that the chip is fixed on the first substrate through the adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0133] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0134] Figure 1A block diagram of a display device according to some exemplary embodiments of the present disclosure is schematically shown.

[0135] Figure 2 is a schematic diagram schematically illustrating the arrangement of multiple chips in a display substrate according to an embodiment of the present disclosure.

[0136] FIG. 3A to FIG. 3C They are schematic diagrams schematically showing the relative positional relationship between the functional unit group and the display area in the display substrate according to the embodiments of the present disclosure.

[0137] Figure 4 The diagram schematically illustrates the alignment relationship between the terminal (pad) on the substrate and the terminal (pad) on the chip in the semiconductor device (eg, display substrate) according to the embodiment of the present disclosure.

[0138] FIG. 5A to FIG. 5D is a schematic diagram schematically illustrating some steps of a post-alignment process according to an embodiment of the present disclosure.

[0139] Fig. 6A and Figure 6B They are respectively a cross-sectional schematic diagram and a top view schematic diagram of a microchip according to an embodiment of the present disclosure.

[0140] Fig. 7A , Figure 7B and Figure 7C 1 and 2 are respectively a perspective view and a cross-sectional schematic diagram of a microchip and an extended trace in a terminal extension layer according to an embodiment of the present disclosure.

[0141] Fig. 8A , Figure 8B and Figure 8C Schematic cross-sectional views of a microchip and an extended trace in a terminal extension layer according to some embodiments of the present disclosure.

[0142] Fig. 9 FIG. 1 is a schematic diagram showing a structure formed by a chip first process according to an embodiment of the present disclosure.

[0143] Fig.10 is a schematic diagram showing a structure formed by a chip later process according to an embodiment of the present disclosure.

[0144] Fig.11A and Fig. 11B Schematic diagrams of exemplary arrangements of a chip and a display unit included in a display device according to some embodiments of the present disclosure.

[0145] FIG. 12A to FIG. 12F is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed.

[0146] FIG. 13A to FIG. 13G is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed.

[0147] Fig.14 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure, wherein the display device may be a large-size display device or a spliced ​​display device.

[0148] Fig.15 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure, schematically illustrating an implementation of upward light emission.

[0149] Fig.16 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure.

[0150] FIG. 17A to FIG. 17I is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed.

[0151] Fig.18 A schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is schematically shown, wherein terminals of a chip are located on two opposite sides of the chip.

[0152] FIG. 19A to FIG. 19H is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed, wherein terminals of a chip are located on the upper and lower surfaces of the chip.

[0153] FIG. 20A to FIG. 20F is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed, wherein a driving element of the display device includes a TFT driving circuit, and the manufacturing method is implemented by the above-mentioned chip first process.

[0154] Fig.21 yes Fig.20E A partial view of part I.

[0155] Fig. 22 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein an LED chip and other chips are located in different layers.

[0156] Fig.23 yes Fig. 22 A partial enlarged view of part II.

[0157] Fig.24is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein an LED chip and other chips are located in different layers.

[0158] FIG. 25A to FIG. 25F is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are executed, wherein a driving element of the display device includes a TFT driving circuit, and the manufacturing method is implemented by the above-mentioned chip later process.

[0159] Fig.26A and Fig.26B Schematic cross-sectional views of via holes of a display device according to embodiments of the present disclosure are schematically shown respectively.

[0160] Fig. 27 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the thin film transistor is a bottom-gate thin film transistor.

[0161] Fig.28A and Fig.28B They are respectively schematic block diagrams of acoustic sensors according to some embodiments of the present disclosure.

[0162] Fig.28C The diagram schematically shows how an acoustic sensor is arranged in a display according to some embodiments of the present disclosure.

[0163] Fig.29 is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure, wherein the sensor is a Si-based sensor.

[0164] Fig.30 The figure schematically shows the relationship between the increase factor of the output voltage and the number of transducers connected in series in the sensor according to the embodiment of the present disclosure.

[0165] Fig.31 is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric sensor including a piezoelectric film.

[0166] Fig.32 yes Fig.31 A partial enlarged view of part III.

[0167] FIG. 33A to FIG. 33C Schematic cross-sectional views respectively illustrate structures formed after some steps of a method for manufacturing a display device integrated with a sensor according to some embodiments of the present disclosure are executed, wherein the sensor is a piezoelectric sensor including a piezoelectric film.

[0168] Fig.34is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure.

[0169] FIG. 35A to FIG. 35E is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a semiconductor device (eg, a display device) according to an exemplary embodiment of the present disclosure are performed.

[0170] Fig.36A A top view schematically illustrates a process of forming a plurality of extended traces during a post-alignment process according to some embodiments of the present disclosure.

[0171] Fig.36B and Fig.36C Schematically illustrate top views of forming multiple extended traces during a post-alignment process according to some embodiments of the present disclosure.

[0172] Fig.37A and Fig.37B is along Fig.36B A cross-sectional view taken along line AA'.

[0173] Fig.38 A partial enlarged view of the wiring between two chips is schematically shown.

[0174] Fig.39A , Fig.39B and Fig.39C The photographing areas formed in the post-alignment process are schematically shown respectively.

[0175] FIG. 40A to FIG. 40C The arrangement of the driving chip and each pixel of the display device according to the embodiment of the present disclosure is schematically shown respectively.

[0176] Fig.41 The projection relationship between the chip and the pixel is schematically shown.

[0177] Fig.42 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure.

[0178] Fig.43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure.

[0179] Fig.44A and Fig.44B They are circuit connection diagrams of a display device including a gating chip according to embodiments of the present disclosure.

[0180] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0181] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0182] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0183] When an element is described as being "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on the other element, directly connected to the other element or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection and / or a fluid connection. In addition, the X-axis, the Y-axis and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0184] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named as a second element, and similarly, a second element may be named as a first element.

[0185] It should be understood that an integrated circuit (abbreviated as IC) is a way of miniaturizing circuits (including semiconductor devices, passive devices, etc.), for example, devices manufactured on the surface of a semiconductor wafer. For example, an integrated circuit can also be called a microcircuit, a wafer, a chip, etc. Usually, integrated circuits are made in large quantities on a large semiconductor wafer through multiple steps such as photolithography, and then divided into several small pieces. This small piece is called a chip, and each chip is a collection of integrated circuits. The semiconductor material used for the wafer is usually a single crystal of electronic grade silicon or other semiconductors (such as gallium arsenide).

[0186] It should be understood that a bare crystal (die in English, also called bare chip, bare chip, grain or bare die) is a small piece of integrated circuit made of semiconductor material and not packaged. The established functions of the integrated circuit are realized on this small piece of semiconductor.

[0187] It should be understood that in the field of integrated circuits, packaging is the process of assembling integrated circuits into chip final products, for example, placing the bare integrated circuit chip on a substrate that serves as a carrier, leading out the pins, and then fixing and packaging them into a whole. Specifically, the circuit pins on the bare integrated circuit chip are connected to the external connector with wires to facilitate the connection of other devices. The packaging structure not only plays the role of installing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance, but also connects the contacts on the chip to the pins of the packaging structure with wires, and these pins are connected to other devices through wires on the printed circuit board, thereby realizing the connection between the internal chip and the external circuit.

[0188] In this article, panel-level packaging technology refers to sticking semiconductor bare chips to a carrier, pulling out the required circuits on the endpoints of the bare chips to the redistribution layer (RDL for short), and then forming a package. There is no need for a packaging carrier, let alone wire bonding and bumps (Bump in English), thereby reducing production costs.

[0189] In this article, the digital exposure process refers to a direct-write or maskless lithography process, which can usually be implemented using a digital exposure machine. For example, a digital exposure process (i.e., without using a mask) can be used to form a wiring layer of the terminals electrically connected to the chip on a substrate. Specifically, multiple chips can be transferred to the substrate through a low-precision transfer process; the position of each terminal of the chip on the substrate can be read through Mapping, or the chip image can be obtained through optical detection, and then the position of each terminal can be obtained through an algorithm; after obtaining the position of each terminal, the coordinate information of each terminal is formed into a file that can be recognized by a digital exposure machine, and the digital exposure machine can implement an exposure process on the conductive layer according to the file to form a wiring layer of the terminals electrically connected to the chip. In the above process, the digital exposure process can automatically correct the position offset of each chip transferred to the substrate. For example, the accuracy of the digital exposure process can reach <1μm, so the process difficulty brought by bonding can be greatly reduced and the process accuracy can be improved.

[0190] In this document, the expression "terminal" refers to the part of the chip that is electrically connected to external leads, traces, electrodes, etc., including but not limited to the pad of the chip.

[0191] In this article, "post-alignment process" refers to a process for aligning the terminals (such as pads) of a chip. For example, in an embodiment of the present disclosure, multiple chips can be first transferred to a substrate through processes such as SMT or mass transfer, and then the position (such as the coordinate information of each pad), area and morphology of the pads of each chip transferred to the substrate are determined by image analysis technology. Based on the parameters and through high-precision composition processes such as photolithography, extended traces or leads electrically connected to the pads of each chip are formed to achieve bonding of each chip. It should be understood that since the post-alignment process includes high-precision composition processes such as photolithography, its accuracy will be higher than the accuracy of the mass transfer process. For example, the offset accuracy of the metal extension trace formed by the photolithography machine is generally less than 0.6 microns, while the accuracy of the current mass transfer equipment is about 5-10 microns. In an embodiment of the present disclosure, the post-alignment process can solve the problem of low transfer accuracy during mass transfer of microchips.

[0192] In addition, in this article, the "post-alignment process" can be used to repair bad points in addition to identifying the terminals of the chip for automatic wiring. For example, in the post-alignment process, bad points can be identified and their coordinate information can be obtained; then, based on the coordinate information and through high-precision patterning processes such as photolithography, extended traces or leads electrically connected to each bad point are formed to repair each bad point.

[0193] It should be noted that, in this article, the expression "bad point" includes a terminal having a break in its electrical connection path.

[0194] In this document, unless otherwise specified, the expression "position" or "relative position" refers to the position of a component such as a chip or a chip body in a spatial coordinate system, for example, in an XYZ coordinate system, it can be expressed by the coordinate values ​​of the X, Y, and Z axes. The expression "orientation" refers to the angle of a component such as a chip or a chip body relative to each coordinate axis in a spatial coordinate system, for example, in an XYZ coordinate system, it can be expressed by the angle relative to the X, Y, and Z axes.

[0195] For example, maskless lithography can be roughly divided into two categories: (1) charged particle maskless lithography, such as electron beam direct writing and ion beam lithography. (2) optical maskless technology, such as DMD maskless lithography, laser direct writing, interference lithography, diffraction optical element lithography, etc. Specifically, DMD maskless lithography is a technology derived from traditional optical lithography. Its exposure and imaging method is basically similar to traditional projection lithography. The difference is that digital DMD is used instead of traditional masks. The main principle is to input the required lithography pattern into the DMD chip through software through a computer, and change the rotation angle of the DMD chip micromirror according to the distribution of black and white pixels in the image, and irradiate the DMD chip with a collimated light source to form a light image consistent with the required pattern and project it onto the substrate surface, and realize large-area microstructure preparation by controlling the movement of the sample stage. Electron beam lithography (usually abbreviated as EBL) is a technology that uses electron beams to draw custom patterns on a surface covered with resist. The electron beam changes the solubility of the resist, and by immersing it in a solvent (i.e., developing), the exposed or unexposed areas of the resist can be selectively removed.

[0196] It should also be understood that wire bonding is a process that uses heat, pressure or ultrasonic energy to tightly weld metal bonding wires to substrate pads. For example, in IC packaging, wire bonding can be used to connect the semiconductor chip pads to the I / O bonding wires of the microelectronic package or the metal wiring pads on the substrate with metal filaments. The principle of wire bonding is to use heating, pressurization or ultrasonic waves to destroy the oxide layer and contamination on the surface to be welded, produce plastic deformation, and make the metal bonding wires closely contact with the surface to be welded, reach the range of attraction between atoms, and cause atomic diffusion between interfaces to form welding points.

[0197] Herein, the expression “light emitting chip” refers to a chip configured to emit light of a specific wavelength. For example, the light emitting chip may include a light emitting diode chip, including but not limited to a MiniLED chip or a MicroLED chip.

[0198] In this article, inorganic light emitting diode refers to a light emitting element made of inorganic materials, wherein LED refers to an inorganic light emitting element different from OLED. Specifically, inorganic light emitting elements may include sub-millimeter light emitting diodes (Mini Light Emitting Diode, abbreviated as MiniLED in English) and micro light emitting diodes (Micro Light Emitting Diode, abbreviated as MicroLED in English). Among them, micro light emitting diodes (i.e. MicroLED) refer to ultra-small light emitting diodes with a grain size of less than 100 microns, and sub-millimeter light emitting diodes (i.e. MiniLED) refer to small light emitting diodes with a grain size between MicroLED and traditional LED. For example, the grain size of MiniLED can be between 100 and 300 microns, and the grain size of MicroLED can be between 10 and 100 microns.

[0199] In this article, SMT or SMT process refers to surface mounting technology, and mass transfer or mass transfer process is a technology for transferring a large number of microchips to a target substrate. For example, common mass transfer technology includes the following steps: picking up microchips from a predetermined position with very high spatial accuracy and direction; moving these microchips to a predetermined position while maintaining the relative spatial position and direction of the microchips; and then, selectively distributing these microchips to the target substrate at the new position while maintaining the new relative position and direction.

[0200] In this article, PVDF refers to polyvinylidene fluoride material, which has piezoelectric properties.

[0201] Regarding the "chip size", the inventors have found through research that the chip increases by at least 20% relative to the original bare die size after packaging. At the same time, the various functional modules integrated in the chip also cause the chip size to increase. In the embodiments of the present disclosure, the chip size can be reduced by disassembling the functions of the chip and packaging the device including the chip (such as a display substrate). As the chip size decreases, the impact of defects on the chip yield on each wafer can be effectively reduced. Moreover, as the chip size decreases, the yield gradually increases, the equivalent diameter of a single wafer continues to increase, and the number of chips produced per wafer increases, which can greatly reduce the cost of the chip.

[0202] In this document, unless otherwise specified, the expressions "chip", "chip module", "microchip", "microchip" and the like refer to chips of relatively small size, for example, unpackaged micron-sized chips. Taking the display substrate as an example, the display substrate may include but is not limited to the following chips: sensor chip, control chip, logic operation chip, storage chip, driver chip, LED chip and other functional chips, and may also include more subdivided submodule chips such as digital-to-analog conversion circuit, amplifier circuit, comparator, counter, etc. It should be understood that the display substrate may include at least one of the above chips.

[0203] In this document, unless otherwise specified, the term "functional device" may include devices for realizing specific functions, which may include a single chip, a chipset consisting of multiple chips, or a circuit structure. For example, the functional device may include at least one of a thin film transistor and a sensor manufactured by a thin film process.

[0204] In this document, unless otherwise specifically stated, the expression "regular shape" refers to a regular shape, including but not limited to a rectangle, a rounded rectangle, a diamond, a square, a hexagon, an octagon, a circle, an ellipse, a rectangle, a triangle, etc.

[0205] Some exemplary embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate; a chip disposed on the substrate, the chip including a chip body and a plurality of terminals disposed on the chip body; a terminal extension layer disposed on the substrate, the terminal extension layer including a conductive material, wherein the terminal extension layer and at least one terminal are located on the same side of the chip body, the semiconductor device also includes a plurality of extension traces located in the terminal extension layer, the plurality of extension traces are electrically connected to the plurality of terminals, respectively, for leading out the plurality of terminals; and the orthographic projection of at least one extension trace on the substrate completely covers the orthographic projection of the terminal electrically connected to the extension trace on the substrate. In the semiconductor device, leading out the chip terminals through the terminal extension layer is beneficial to the bonding of the chip.

[0206] For example, the semiconductor device includes: a substrate; a plurality of chips arranged on the substrate, each chip including a chip body and a plurality of terminals arranged on the chip body; a plurality of fixed connection parts arranged on the substrate; a terminal extension layer arranged on the substrate, the terminal extension layer including a conductive material, wherein the plurality of fixed connection parts are respectively arranged adjacent to the plurality of chips; the semiconductor device also includes a plurality of extended traces located in the terminal extension layer, the extended traces are used to electrically connect the plurality of chips; and the extended traces used to electrically connect two chips include at least a first trace segment and a second trace segment, the first trace segment is used to electrically connect a terminal of a chip with a fixed connection part adjacent to the chip, and the second trace segment is used to connect two fixed connection parts between two chips. In the semiconductor device, by setting the fixed connection part, it is beneficial to realize the electrical connection between the various chips.

[0207] For example, the semiconductor device includes: a first substrate and a second substrate arranged oppositely; a chip arranged on the first substrate, the chip including a chip body and a plurality of first terminals arranged on the chip body; a terminal extension layer arranged on the first substrate, the terminal extension layer including a conductive material; and a plurality of second terminals arranged on the second substrate, wherein the terminal extension layer and at least one first terminal are located on the same side of the chip body, the semiconductor device also includes a plurality of extension traces located in the terminal extension layer, the plurality of extension traces are respectively electrically connected to the plurality of first terminals, and are used to lead out the plurality of first terminals; the orthographic projections of the plurality of extension traces on the first substrate completely cover the orthographic projections of the first terminals electrically connected to the extension traces on the first substrate; and the plurality of first terminals are respectively electrically connected to the plurality of second terminals through the plurality of extension traces, and the orthographic projections of the plurality of second terminals on the first substrate at least partially overlap with the orthographic projections of the plurality of extension traces on the first substrate. In the semiconductor device, leading out the terminals of the chip through the terminal extension layer is conducive to achieving bonding between the chip and other components.

[0208] It should be noted that, in this article, the exemplary embodiments of the present disclosure are mainly described by taking display devices such as display substrates, display panels and display devices as examples. The embodiments of the present disclosure are not limited to this, and can also be applied to other types of semiconductor devices including at least one chip. In this article, the types of chips include but are not limited to light-emitting chips, sensor chips, control chips and driver chips, for example, LED chips, analog circuit chips, digital circuit chips, memory chips, digital-to-analog conversion chips, sensor (sound, light, electricity, etc.) chips or other functional module chips.

[0209] For example, Figure 1Schematically shows a block diagram of a display device according to some exemplary embodiments of the present disclosure. Figure 1 In the embodiments of the present disclosure, the chip with integrated functions used for the display device can be split into multiple microchips, and each microchip can have fewer functions than the chip with integrated functions, that is, the chip with integrated functions can be split according to the functions, so that multiple microchips are arranged in the display device. It should be understood that the size of each microchip is smaller than the size of the chip with integrated functions. For example, each microchip can be an unpackaged micron-level chip. Accordingly, in this article, the size of the terminals on the microchip is smaller than the size of the terminals of the traditional chip. For example, the size of the terminals on the microchip is at the level of more than ten microns, and may even be less than 10 microns. In this way, the traditional bonding process cannot meet the dimensional accuracy of the terminals on the microchip; moreover, the accuracy of the existing mass transfer process cannot meet the dimensional accuracy of the terminals on the microchip.

[0210] For example, in the display device, multiple chips may be provided, and each chip may be used to implement a function. For example, the multiple chips may include an LED chip and display-related driver chips, storage chips, digital-to-analog conversion chips, and information processing chips. Figure 1 As shown, a control chip 1, a logic operation chip 2, a storage chip 3, a driver chip 4 and other functional chips 5 may be provided. The driver chip 4 may be electrically connected to the display unit 6.

[0211] For example, the display unit 6 may include one of an LCD display (liquid crystal display) unit, an OLED (organic light emitting diode) display unit, or an LED (inorganic light emitting diode) display unit.

[0212] Figure 2 is a schematic diagram schematically illustrating the arrangement of multiple chips in a display substrate according to an embodiment of the present disclosure. Figure 3A to Figure 3C They are schematic diagrams schematically showing the relative positional relationship between the functional unit group and the display area in the display substrate according to the embodiments of the present disclosure.

[0213] Combined with reference Figures 1 to 3C , multiple chips with specific functions can be interconnected to form a functional unit group CU. For example, a control chip 1, a logic operation chip 2, a storage chip 3, a driver chip 4 and other functional chips 5 can be interconnected to form a functional unit group CU.

[0214] For example, the display device may include a display substrate. The display substrate may include a display area AA and a non-display area NA. The display substrate may include a plurality of pixels PX located in the display area AA. For example, the plurality of functional unit groups CU may be periodically or non-periodically arranged on a base substrate of the display substrate. The plurality of functional unit groups CU may be located in the display area AA or in the non-display area NA. Optionally, some of the plurality of functional unit groups CU may be located in the display area AA, and others of the plurality of functional unit groups CU may be located in the non-display area NA.

[0215] For example, refer to Figure 3A , multiple functional unit groups CU can be respectively located in multiple pixels PX, for example, one functional unit group CU can be set in one pixel PX. Figure 3B , two or more pixels PX can share a functional unit group CU. Figure 3C , a functional unit group CU may be set in some pixels PX, and a functional unit group CU may not be set in other pixels PX.

[0216] For example, the functional unit group CU can be set only in a specific pixel PX to implement applications with low data volume requirements, such as eye tracking and other application scenarios.

[0217] For example, multiple functional unit groups CU can be interconnected as needed to achieve data interaction.

[0218] That is, the semiconductor device (e.g., display device) according to the embodiment of the present disclosure includes a plurality of chips arranged on a substrate. In the embodiment of the present disclosure, electrical connections within a chip, between a plurality of chips, and between a chip and a display unit can be achieved through a post-alignment process, solving the problem of microchip wiring accuracy.

[0219] Figure 4 Schematic diagram schematically showing the alignment relationship between the terminal (pad) on the substrate and the terminal (pad) on the chip in the semiconductor device (eg, display substrate) of the embodiment of the present disclosure. Figures 1 to 4 The above-mentioned multiple chips can be transferred to a substrate such as a substrate substrate through a mass transfer process. Through the mass transfer process, the terminal p2 on the substrate and the terminal p1 on the chip can be aligned. Limited by the accuracy of the mass transfer process, a certain alignment deviation may occur between the terminal p2 on the substrate and the terminal p1 on the chip.

[0220] It should be noted that in the embodiments of the present disclosure, the terminals on the chip (e.g., p1) and the terminals on the substrate (e.g., p2) do not need to overlap, and the terminals on the chip (e.g., p1) and the terminals on the substrate (e.g., p2) in at least a portion of the area are not in face-to-face contact. The "a certain alignment deviation may occur between the terminal p2 on the substrate and the terminal p1 on the chip" mentioned in the above description can be understood as the position deviation caused by the alignment deviation between the terminal p1 on the chip and its ideal position that may occur during the chip transfer process.

[0221] For example, Figure 4 Six pairs of terminals p2 on the substrate and terminals p1 on the chip are schematically shown in FIG. Figure 4 In the diagram, the small-sized dotted frame indicates the position of the terminal p2, and the large-sized dotted frame indicates the ideal position of the terminal p1 (i.e., the position of the terminal p1 that is precisely aligned with the terminal p2). For the convenience of description, the terminals are described as a first pair of terminals, a second pair of terminals, a third pair of terminals, a fourth pair of terminals, a fifth pair of terminals, and a sixth pair of terminals from top to bottom and from left to right. In the first pair of terminals, terminal p1 is located at its ideal position, in which case terminal p2 is precisely aligned with terminal p1; in the second pair of terminals, terminal p1 is offset to the left by a certain distance relative to its ideal position, resulting in terminal p1 being offset to the left by a certain distance relative to terminal p2; in the third pair of terminals, terminal p1 is offset upward by a certain distance relative to its ideal position, resulting in terminal p1 being offset upward by a certain distance relative to terminal p2; in the fourth pair of terminals, terminal p1 is offset to the right by a certain distance relative to its ideal position, resulting in terminal p1 being offset to the right and upward by a certain distance relative to terminal p2; in the fifth pair of terminals, terminal p1 is deflected clockwise by a certain angle relative to its ideal position, resulting in terminal p1 being deflected clockwise by a certain angle relative to terminal p2; in the sixth pair of terminals, terminal p1 is deflected counterclockwise by a certain angle relative to its ideal position, resulting in terminal p1 being deflected counterclockwise by a certain angle relative to terminal p2. That is to say, in the actual mass transfer process, the following situations may occur: terminal p1 is precisely aligned with terminal p2, terminal p1 is offset by a certain distance relative to terminal p2 along at least one of the first direction and the second direction, and terminal p1 is deflected by a certain angle relative to terminal p2.

[0222] Continue to refer to Figure 4The semiconductor device may include a plurality of repeating units PU, and the plurality of repeating units are arranged in an array on the substrate along a first direction D1 and a second direction D2. Each repeating unit PU may include a plurality of chips, and the plurality of chips in each repeating unit PU are arranged in an array on the substrate along a first direction D1 and a second direction D2, or at least a portion of the plurality of chips in each repeating unit are arranged in an array on the substrate along the first direction and the second direction.

[0223] It should be noted that, in the illustrated embodiment, two repeating units PU are schematically shown, and each repeating unit PU includes three chips. However, these numbers should not be regarded as limiting the embodiments of the present disclosure.

[0224] For example, in at least two of the multiple repeating units PU, the relative position of at least one chip in one repeating unit PU in the repeating unit is different from the relative position of a corresponding chip in another repeating unit in the other repeating unit.

[0225] In at least two of the plurality of repeating units PU, an orientation of at least one chip in one repeating unit in the repeating unit is different from an orientation of a corresponding chip in another repeating unit in the other repeating unit.

[0226] In at least two of the multiple repeating units PU, the length of the extended routing line used to lead out at least one terminal of at least one chip in one repeating unit is not equal to the length of the extended routing line used to lead out the corresponding terminal of the corresponding chip in another repeating unit.

[0227] In at least two of the multiple repeating units PU, an extension direction of an extended routing line used to lead out at least one terminal of at least one chip in one repeating unit is different from an extension direction of an extended routing line used to lead out a corresponding terminal of a corresponding chip in another repeating unit.

[0228] It should be noted that in the embodiments of the present disclosure, the expression "corresponding chips" can be understood as chips at corresponding positions in each repeating unit, for example, Figure 4 In the illustrated embodiment, the leftmost chip in one repeating unit located at the upper side and the leftmost chip in another repeating unit located at the lower side are corresponding chips to each other.

[0229] In an embodiment of the present disclosure, a post-alignment process may be used to form an extended trace located in a terminal extension layer (i.e., RDL) to electrically connect the terminal p1 and the terminal p2. For example, a photographic method may be used to identify the positions of the terminal p1 and the terminal p2, a photolithography pattern may be designed according to the positions of the terminal p1 and the terminal p2, and exposure may be performed using maskless photolithography technology to form a plurality of extended traces RL in the terminal extension layer RDL. Based on the designed photolithography pattern, the plurality of extended traces RL electrically connect the terminal p1 and the terminal p2 according to design requirements. In an embodiment of the present disclosure, electrical connections within a microchip and between microchips may be achieved without improving the alignment accuracy of the mass transfer process, thereby improving the wiring accuracy of the microchip.

[0230] Figure 5A to Figure 5D Schematic diagram schematically illustrating some steps of the post-alignment process according to an embodiment of the present disclosure. Figure 5A , multiple chips CP can be formed on the carrier board SUB1, for example, multiple chips CP can be formed on the carrier board SUB1 in an array, or multiple chips CP can be formed on the carrier board SUB1 non-periodically. For example, the "chip CP" here can be the above-mentioned microchip, including but not limited to the above-mentioned LED chip, control chip 1, logic operation chip 2, storage chip 3, driver chip 4 and other functional chips 5.

[0231] Reference Figure 5B , multiple chips CP are transferred to the substrate SUB2 through a mass transfer process. For example, an adhesive layer AD1 may be provided on the substrate SUB2. The adhesive layer AD1 may play a role in fixing the chip. The adhesive layer AD1 may be a whole surface or a patterned layer. Then, multiple extended traces may be formed through a post-alignment process. Specifically, refer to Figure 5C , a metal layer ML1 and a photoresist layer PR1 may be deposited on the chip CP, and then, a patterned photoresist layer PR1 may be formed through a patterning process. Figure 5D , the metal layer ML1 is etched to form a patterned metal layer ML1, the patterned metal layer ML1 is the terminal extension layer RDL, and the multiple patterns formed in the terminal extension layer RDL are formed into multiple extension lines RL to electrically connect the various terminals.

[0232] For example, in Figure 5C In the illustrated embodiment, the patterning process includes but is not limited to sub-micron exposure technologies such as digital exposure machine, laser direct writing, and EBL.

[0233] In the embodiments of the present disclosure, the chip can be transferred to the substrate through a mass transfer process with low position accuracy, and then the chip with low position accuracy can be identified and analyzed through a post-alignment process. For example, the terminal p1 of the chip and the terminal p2 of the substrate can be identified and analyzed by taking photos and image recognition methods to determine the relative position relationship between the terminals. Based on the results of the identification and analysis, an automatic wiring file is generated. Figure 5C In the composition process shown, the photoresist layer PR1 can be patterned according to the automatic wiring file. In this way, automatic wiring and high-precision chip bonding can be achieved, and the integration of microchips and display units can be realized. In addition, the post-alignment process also has at least the following advantages: the accuracy of the post-alignment process depends on the alignment accuracy of optical exposure, and the alignment accuracy of optical exposure is much higher than the alignment accuracy of mass transfer process, which is more suitable for the bonding of microchips; and the post-alignment process adopts exposure, development, and etching processes, which is more suitable for large-area, high-efficiency batch chip bonding.

[0234] For example, the shapes and functions of the chips on the same substrate may be the same or different. The pins of the terminals p1 of the chip are upward and the number is greater than or equal to 2, and the sizes and morphologies of the terminals p1 may be the same or different. Fig. 6A and Figure 6B 1 and 2 are respectively a cross-sectional schematic diagram and a top view schematic diagram of a microchip according to an embodiment of the present disclosure. Fig. 6A As shown, on the same substrate SUB2, multiple chips CP are arranged, and the functions of the multiple chips CP may be different. The shapes of the multiple chips CP in the cross-sectional view and the top view may be different. For example, referring to Fig. 6A , the chip CP can be in various shapes such as rectangle, trapezoid, etc. in the cross-sectional view. Figure 6B , the chip CP can present various shapes such as trapezoid, rectangle, diamond, triangle, circle, ellipse, etc. in the top view.

[0235] Fig. 7A , Figure 7B and Figure 7C 1 and 2 are perspective views and cross-sectional views of the microchip and the extended traces in the terminal extension layer according to an embodiment of the present disclosure, respectively. Fig. 7A and Figure 7B As shown in FIG. 1 , the chip CP has a trapezoidal shape in the cross-sectional view. In other words, at least one side of the chip CP is relatively flat, that is, the slope angle of at least one side of the chip CP is less than 90°, for example, less than 70°. In this case, an extended trace can be directly led out from the terminal p1 of the chip CP, such as Figure 7BAs shown, the extended trace RL led out from the terminal p1 of the chip CP can be formed on the side with a slope angle less than 90°. For example, a terminal extension layer and at least one redistribution layer can be provided. For the convenience of description, they are respectively referred to as the terminal extension layer RDL1 and the redistribution layer RDL2. Correspondingly, the extended traces located in the terminal extension layer RDL1 and the redistribution layer RDL2 are respectively referred to as the extended trace RL1 and the first trace RL2. Fig. 7A As shown, a planarization layer PLN1 can be set between the terminal extension layer RDL1 and the redistribution layer RDL2. The extension line RL1 is directly led out from the terminal p1 of the chip CP. The first line RL2 is electrically connected to the extension line RL1 through a via penetrating the planarization layer PLN1. In this way, the terminal of the chip can be led out, which is beneficial to the electrical connection between the various terminals of the chip.

[0236] like Figure 7C As shown, the chip CP has a roughly rectangular shape in the cross-sectional view. In other words, the side of the chip CP is steeper, that is, the slope angle of the side of the chip CP is substantially equal to 90° or close to 90°, for example, in the range of 70° to 90°. In this case, it is not suitable to form the extended trace directly on the side of the chip CP, that is, it is not suitable to directly lead out the extended trace from the terminal p1 of the chip CP. A planarization layer PLN1 may be first formed on the side of the chip CP away from the substrate, and the height of the planarization layer PLN1 is greater than the height of the chip CP, so that the planarization layer PLN1 can cover the chip CP and the terminal p1 thereon. Then, the extended trace RL1 is formed by a post-alignment process. As shown Figure 7C As shown, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a chip CP disposed on the adhesive layer AD1, a planarization layer PLN1 disposed on a side of the chip CP away from the substrate, and an extended trace RL1 disposed on a side of the planarization layer PLN1 away from the substrate. The extended trace RL1 may be electrically connected to the terminal p1 through a via penetrating the planarization layer PLN1. In this way, the terminal of the chip may be led out, which is beneficial to the electrical connection between the various terminals of the chip.

[0237] Combined with reference Fig.32 In the case where the chip CP has a substantially rectangular shape in a cross-sectional view, a planarization layer may be formed on at least one side of the chip CP to form a side having a smaller slope. Fig. 7A and Figure 7B Similarly, extended traces may be formed on the side of the planarization layer having a smaller slope.

[0238] It should be noted that the planarization layer PLN1 can have a single-layer or multi-layer structure.

[0239] Fig. 8A , Figure 8B and Figure 8C Schematic diagrams of cross sections of a microchip and an extended trace in a terminal extension layer according to some embodiments of the present disclosure. Fig. 8A As shown, in the semiconductor device according to the embodiment of the present disclosure, a plurality of chips CP are arranged on the substrate SUB2, and there is a height difference between at least two chips CP. For the convenience of description, the two chips with the height difference are respectively referred to as chip CP1 and chip CP2.

[0240] like Fig. 8A As shown, when the height difference between chip CP1 and chip CP2 is less than the process limit of the post-alignment exposure process in the vertical direction, wiring can be achieved through a one-step post-alignment process, that is, a terminal extension layer RDL1 is formed through a one-step post-alignment process, and a plurality of extension traces RL1 located in the terminal extension layer RDL1 can lead out the terminals of chip CP1 and chip CP2. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, chips CP1 and CP2 disposed on the adhesive layer AD1, a planarization layer PLN1 disposed on the side of the chip CP1 and CP2 away from the substrate, and a terminal extension layer RDL1 disposed on the side of the planarization layer PLN1 away from the substrate. A plurality of extension traces RL1 are disposed in the terminal extension layer RDL1. The height of the planarization layer PLN1 is greater than the height of each of the chips CP1 and CP2. A portion of the extended trace RL1 can be electrically connected to the terminal p1 of the chip CP1 through a via penetrating the planarization layer PLN1, and another portion of the extended trace RL1 can be electrically connected to the terminal p1 of the chip CP2 through a via penetrating the planarization layer PLN1. In this way, the terminals of the chip CP1 and the chip CP2 can be brought out, which is beneficial to the electrical connection between the terminals of the chips. Similarly, the terminals of multiple chips can be brought out, which is beneficial to the electrical connection between the terminals of multiple chips.

[0241] like Figure 8BAs shown, when the height difference between chip CP1 and chip CP2 is greater than the process limit of the post-alignment exposure process in the vertical direction, wiring can be achieved through at least two steps of post-alignment process, that is, the thin chip CP1 is first subjected to post-alignment process and wiring, and then the chip CP2 with different thickness ranges (for example, thicker) is subjected to post-alignment process and wiring in sequence. A planarization layer needs to be added between the latter post-alignment process and the former post-alignment process. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, chips CP1 and CP2 disposed on the adhesive layer AD1, a planarization layer PLN1 disposed on a side of the chip CP1 away from the substrate, a terminal extension layer RDL1 disposed on a side of the planarization layer PLN1 away from the substrate, a planarization layer PLN2 disposed on a side of the terminal extension layer RDL1 away from the substrate, and a rewiring layer RDL2 disposed on a side of the planarization layer PLN2 away from the substrate. An extension trace RL1 is disposed in the terminal extension layer RDL1, and a first trace RL2 is disposed in the rewiring layer RDL2. The extended trace RL1 can be electrically connected to the terminal p1 of the chip CP1 through a via hole penetrating the planarization layer PLN1, and the first trace RL2 can be electrically connected to the terminal p1 of the chip CP2 through a via hole penetrating the planarization layer PLN2. In this way, the terminals of the chip CP1 and the chip CP2 can be brought out, which is beneficial to the electrical connection between the various terminals of the chip.

[0242] like Figure 8CAs shown, when the height difference between chip CP1 and chip CP2 is greater than the process limit of the post-alignment exposure process in the vertical direction, a pad can be prepared on the substrate first, wherein the height difference of the chip - the process limit of the post-alignment exposure process in the vertical direction ≤ the height of the pad ≤ the height difference of the chip; then, wiring can be achieved through a one-step post-alignment process. For example, the semiconductor device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a pad PS disposed on the adhesive layer AD1, a chip CP2, a chip CP1 disposed on the pad PS, a planarization layer PLN1 disposed on the side of the chip CP1 and CP2 away from the substrate, and a terminal extension layer RDL1 disposed on the side of the planarization layer PLN1 away from the substrate. A plurality of extension traces RL1 are disposed in the terminal extension layer RDL1. The height of the planarization layer PLN1 is greater than the height of each of the chips CP1 and CP2, that is, the height of the planarization layer PLN1 away from the surface of the substrate SUB2 is greater than the height of each of the chips CP1 and CP2 away from the surface of the substrate SUB2. The orthographic projection of chip CP1 on the substrate is located within the orthographic projection of pad PS on the substrate, and the area of ​​the orthographic projection of chip CP1 on the substrate is smaller than the area of ​​the orthographic projection of pad PS on the substrate. In this way, the alignment accuracy between chip CP1 and pad PS does not need to be high, which is conducive to placing chip CP1 on pad PS. A portion of the extended trace RL1 can be electrically connected to the terminal p1 of chip CP1 through a via penetrating the planarization layer PLN1, and another portion of the extended trace RL1 can be electrically connected to the terminal p1 of chip CP2 through a via penetrating the planarization layer PLN1. In this way, the terminals of chip CP1 and chip CP2 can be brought out, which is conducive to the electrical connection between the various terminals of the chip.

[0243] It should be noted that in Figure 8C In the illustrated embodiment, the height of the substrate PS may also be slightly greater than the height difference of the chip. For example, the difference between the height of the substrate PS and the height difference of the chip may be less than the process limit of the post-alignment exposure process in the vertical direction.

[0244] In the embodiments of the present disclosure, the chip may be formed on the substrate by using a chip first process or a chip later process. For example, if the semiconductor device is a display device, the chip may be formed first and then a driving unit of the display device may be formed, i.e., a chip first process; or, the driving unit of the display device may be formed first and then the chip may be formed, i.e., a chip later process.

[0245] Reference Figures 4 to 8CIn an embodiment of the present disclosure, the chip may include a chip body CPM and a plurality of terminals p1, p2 disposed on the chip body CPM. The chip body CPM may include a first surface CPM1, a second surface CPM2, a first side surface CPM3, and a second side surface CPM4, wherein the second surface CPM2 and the first surface CPM1 are respectively located on opposite sides of the chip body, the first side surface CPM3 and the second side surface CPM4 are respectively located on side surfaces of the chip body, each of the first side surface CPM3 and the second side surface CPM4 connects the first surface CPM1 and the second surface CPM2, the first surface CPM1 faces or contacts the adhesive layer AD1, and at least one terminal p1, p2 is disposed on a surface (e.g., CPM2, CPM3, CPM4) of the chip body other than the first surface CPM1.

[0246] like Figure 4 and Fig. 6A As shown, the substrate may include a first substrate surface SUBP, the chip is arranged on the first substrate surface SUBP, and the first substrate surface SUBP includes a first substrate edge SUBP1.

[0247] In an embodiment of the present disclosure, an orthographic projection of at least one extended line RL on the substrate is inclined relative to the first substrate edge SUBP1.

[0248] For example, the orthographic projection of the second surface CPM2 on the substrate has a regular shape, such as Figure 6B As shown, the regular shape includes, but is not limited to, rectangle, rounded rectangle, rhombus, square, hexagon, octagon, circle, ellipse, rectangle, triangle, etc. Figure 4 As shown, the orthographic projection of the second surface CPM2 on the substrate includes a first edge CPM21. The first edge CPM21 is inclined relative to the first substrate edge SUBP1.

[0249] For example, a first angle is formed between an extension line of an orthographic projection of the at least one extended trace RL on the substrate and an extension line of the first substrate edge SUBP1, and the first angle is greater than 0° and less than 90°.

[0250] For example, a second angle is formed between an extension line of the first edge CPM21 and an extension line of the first substrate edge SUBPI, and the second angle is greater than 0° and less than 90°.

[0251] In conventional semiconductor devices and their manufacturing processes, the orientation of the chip relative to the substrate cannot be deflected or can only be deflected at a small angle, for example, the deflection angle needs to be less than 10°. In this way, the effective bonding of the various terminals of the chip can be guaranteed. In the embodiment of the present disclosure, the orientation of the chip relative to the substrate can be deflected at a certain angle, and the deflection angle can be between 0° and 90°, for example, between 0° and 50°, between 1° and 60°, greater than 10° and less than 90°, and can be about 10°, about 20°, about 30°, about 40°, about 15°, about 25°, about 35°, about 45°, about 50°, about 60°, about 70°, about 80°, etc. That is, in the embodiment of the present disclosure, the chip can be deflected at a larger angle relative to the substrate, for example, it can be greater than 10°. In the embodiment of the present disclosure, even if the chip is deflected at a larger angle relative to the substrate, an extended wiring layer can still be formed through a subsequent post-alignment process to achieve effective bonding of the chip and avoid the formation of bad points.

[0252] Fig. 9 FIG. 1 is a schematic diagram showing a structure formed by a chip first process according to an embodiment of the present disclosure. Fig.10 is a schematic diagram showing a structure formed by a chip later process according to an embodiment of the present disclosure.

[0253] like Fig. 9As shown, the display device may include a substrate SUB2, an adhesive layer AD1 disposed on the substrate SUB2, a chip CP1 disposed on the adhesive layer AD1, a terminal extension layer RDL1 disposed on a side of the chip CP1 away from the substrate, a planarization layer PLN1 disposed on a side of the terminal extension layer RDL1 away from the substrate, a redistribution layer RDL2 disposed on a side of the planarization layer PLN1 away from the substrate, a planarization layer PLN2 disposed on a side of the redistribution layer RDL2 away from the substrate, and a redistribution layer RDL3 and a driving unit DRU disposed on a side of the planarization layer PLN2 away from the substrate. An extension line RL1 is disposed in the terminal extension layer RDL1, a first line RL2 is disposed in the redistribution layer RDL2, and a second line RL3 is disposed in the redistribution layer RDL3. For example, at least a portion of the extension line RL1 is disposed on the side wall of the chip CP1 and is directly electrically connected to the terminal p1 of the chip CP1. The first line RL2 can be electrically connected to the extended line RL1 through a via hole penetrating the planarization layer PLN1, and the second line RL3 can be electrically connected to the first line RL2 through a via hole penetrating the planarization layer PLN2. For example, the second line RL3 and the drive unit DRU can be located in the same layer, and the second line RL3 can be electrically connected to the drive unit DRU. In this way, the terminal of the chip CPI can be brought out, and the electrical connection between the chip CP1 and the drive unit DRU can be realized. In this embodiment, the chip CP1 is closer to the substrate SUB2 than the drive unit DRU. In actual manufacturing, the chip CP1 can be formed on the substrate SUB2 first, and then a plurality of terminal extension layers are formed by a post-alignment process, and then the drive unit DRU is formed. It should be understood that the processing accuracy of a microchip is usually higher than the processing accuracy of a drive unit such as a thin film transistor. In this embodiment, after the chip is transferred to the substrate, a post-alignment process is used for bonding integration, which is conducive to avoiding the barriers of the processing technology of the drive unit such as a thin film transistor, thereby achieving high-resolution display.

[0254] Alternatively, if Fig.10As shown, the display device may include a substrate SUB2, a driving unit DRU arranged on the substrate SUB2, a planarization layer PLN1 arranged on a side of the driving unit DRU away from the substrate, a terminal extension layer RDL1 arranged on a side of the planarization layer PLN1 away from the substrate, an adhesive layer AD1 arranged on a side of the terminal extension layer RDL1 away from the substrate, a chip CP1 arranged on the adhesive layer AD1, and a redistribution layer RDL2 arranged on a side of the chip CP1 away from the substrate. An extension line RL1 is arranged in the terminal extension layer RDL1, and a first line RL2 is arranged in the redistribution layer RDL2. For example, at least a portion of the first line RL2 is arranged on the side wall of the chip CP1 and is directly electrically connected to the terminal p1 of the chip CP1. The first line RL2 can be electrically connected to the extension line RL1 through a via hole penetrating the adhesive layer AD1, and the extension line RL1 can be electrically connected to the driving unit DRU through a via hole penetrating the planarization layer PLN1. In this way, the electrical connection between the chip CP1 and the driving unit DRU can be achieved. In this embodiment, the chip CP1 is further away from the substrate SUB2 than the driving unit DRU. In actual manufacturing, the driving unit DRU can be formed on the substrate SUB2 first, and then the terminal expansion layer is formed by a post-alignment process, and then the chip CP1 is formed. In this embodiment, the driving unit such as a thin film transistor is first transferred or prepared on the substrate, and then the chip is transferred to the substrate, so as to avoid the processing process of the driving unit such as a thin film transistor affecting the chip performance.

[0255] In the embodiments of the present disclosure, the driving unit DRU includes but is not limited to a thin film transistor (TFT) driving circuit, a MOS driving circuit, a driving chip (IC), etc. For example, the driving unit or driving element can be used to provide an electrical signal to the LED chip to control its luminous brightness. For example, in some examples, the driving unit or driving element can be a plurality of pixel driving circuits connected one-to-one with each light-emitting diode chip, or a plurality of microchips connected one-to-one with each light-emitting diode chip, etc., which can control each LED chip to emit different brightness grayscales. It should be noted that the specific circuit structure of the driving unit or driving element can be set according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0256] Below, some exemplary embodiments of the present disclosure are further described by taking the semiconductor device as a display device as an example.

[0257] Fig.11A and Fig. 11B Schematic diagrams of exemplary arrangements of chips and display units included in a display device according to some embodiments of the present disclosure. For example, the chip CP1 may be a driver chip for driving the display unit, and the display unit DU may be an LED chip that can emit light.

[0258] Reference Fig.11A , a pixel may include three LED chips, for example, corresponding to R, G, and B sub-pixels. One chip CP1 may correspond to one pixel, that is, one driver chip is used to drive one pixel. Fig. 11B One chip CP1 can correspond to multiple pixels, that is, one driving chip is used to drive multiple pixels. Through such an arrangement, the driving chip can be used to drive multiple pixels in an active matrix mode (AM mode).

[0259] Reference Fig.11A , a plurality of light emitting diodes are arranged in an array along a first direction X and a second direction Y. For example, the first direction X is a row direction and the second direction Y is a column direction. Of course, the embodiments of the present disclosure are not limited thereto, and the first direction and the second direction can be any direction, as long as the first direction and the second direction intersect. Furthermore, the plurality of LED chips are not limited to being arranged along a straight line, and can also be arranged along a curve, along a ring, or in any manner, which can be determined according to actual needs, and the embodiments of the present disclosure are not limited thereto.

[0260] It should be noted that, in the embodiment of the present disclosure, the chip CP1 is not limited to a driver chip for driving a display unit, but may also include a control chip, a logic operation chip, a storage chip, and other functional chips.

[0261] In this document, for the convenience of description, the chip used to drive or control the LED is referred to as chip CP1, and the LED chip used to emit light is referred to as CP3.

[0262] According to the size of the chip CP1 , the method for manufacturing the display device according to the embodiment of the present disclosure may include at least two process routes.

[0263] FIG. 12A to FIG. 12F It is a schematic cross-sectional view of a structure formed after some steps of the method for manufacturing a display device according to an exemplary embodiment of the present disclosure are executed. In the case where the size of the chip CP1 is relatively small, the method for manufacturing a display device according to an exemplary embodiment of the present disclosure may include at least the following steps. It should be noted that the case where the size of the chip CP1 is relatively small may include: the size of the chip CP1 is substantially equal to or smaller than the size of the LED chip, or in other words, the ratio of the area of ​​the orthographic projection of the chip CP1 on the substrate to the area of ​​the orthographic projection of the LED chip on the substrate is less than or equal to 1.2.

[0264] Reference Fig. 12A , an adhesive layer AD1 is coated or pasted on the substrate SUB2. For example, the substrate SUB2 may be a glass substrate. The material of the adhesive layer AD1 may include hot melt adhesive, laser curing adhesive or ultraviolet curing adhesive.

[0265] Reference Fig. 12B, the driver chip CP1 and / or the LED chip CP3 are transferred to the substrate SUB2 through SMT or mass transfer process, and fixed on the substrate through the adhesive layer AD1.

[0266] For example, the driving chip CP1 and the LED chip CP3 may both be located on the adhesive layer AD1 , and the terminals p1 of the driving chip CP1 and the LED chip CP3 may face upward, ie, be located on the side of the chip away from the substrate.

[0267] For example, the driving chip CP1 may adopt a Si-based CMOS process, which is not limited in the embodiments of the present disclosure.

[0268] Reference Fig. 12C A passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.

[0269] For example, the passivation layer PVX1 may include materials such as silicon dioxide for insulation and increasing the adhesion of the cover layer OC1. The planarization layer PLN1 may include resin materials for filling the step difference between the driver chip CP1 and the LED chip CP3 and other chips to achieve planarization. Optionally, in other embodiments, the passivation layer PVX1 may not be prepared.

[0270] Optionally, a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 away from the substrate. For example, the passivation layer PVX2 may include materials such as silicon nitride to isolate water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal expansion layer.

[0271] Reference Fig.12D , take a photo of the substrate (which can be called a backplane) on which the chip is formed, and use image recognition technology to determine the position of the terminal p1 of each driver chip CP1 and LED chip CP3 set on the backplane, and generate a graphic file of the opening of the terminal area (i.e., pad area) according to the corresponding logic. Next, apply photoresist on the backplane, and pattern the photoresist by digital direct writing or digital exposure machine according to the above graphic file, and then etch the passivation layer PVX2, the planarization layer PLN1 and the part of the passivation layer PVX2 not covered by the pattern of the photoresist to form a via VH3 that exposes a part of the terminal p1 of each driver chip CP1 and LED chip CP3. Optionally, the passivation layer PVX2, the planarization layer PLN1 and the part of the passivation layer PVX2 located above the terminal can also be directly etched with EBL to form a via VH3 that exposes a part of the terminal p1 of each driver chip CP1 and LED chip CP3.

[0272] Reference Fig.12E, a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, according to the connection relationship of each terminal and based on the previously determined positions of the terminals p1 of each driver chip CP1 and LED chip CP3, a graphic file of the terminal extension layer RDL1 is automatically generated. The terminal extension layer RDL1 is patterned by digital exposure or EBL to form a plurality of extension lines RL1. That is, through the post-alignment process, an extension line RL1 for electrically connecting each chip is formed in the terminal extension layer RDL1.

[0273] For example, the terminal expansion layer RDL1 may include a single film layer structure or a stacked structure composed of multiple film layers. In the case where the terminal expansion layer RDL1 includes a single film layer structure, the terminal expansion layer RDL1 may include a metal material such as copper (Cu). In the case where the terminal expansion layer RDL1 includes a stacked structure composed of multiple film layers, the terminal expansion layer RDL1 may include materials such as titanium / aluminum / titanium (Ti / Al / Ti), molybdenum aluminum molybdenum (Mo / Al / Mo), etc.

[0274] Optionally, refer to Fig.12F After completing the above post-alignment process, a redistribution layer RDL2 can be prepared according to the requirements of line interconnection.

[0275] For example, a cover layer PLN2 may be formed on a side of the terminal expansion layer RDL1 away from the substrate. Then, a redistribution layer RDL2 may be formed on a side of the cover layer PLN2 away from the substrate.

[0276] For example, the redistribution layer RDL2 may be prepared by a conventional photolithography process to form first traces RL2 for electrically connecting various chips in the redistribution layer RDL2. The embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL2 may also be prepared by a post-alignment process.

[0277] For example, the covering layer PLN2 may include silicon nitride, silicon oxide, or a stacked structure of silicon nitride and silicon oxide, or may include a polymer material, for isolating and insulating the terminal extension layer RDL1 and the redistribution layer RDL2.

[0278] For example, according to routing requirements, third-layer wiring, fourth-layer wiring, etc. can also be prepared, and the embodiments of the present disclosure are not particularly limited here.

[0279] Reference Fig.12FAccording to some embodiments of the present disclosure, the semiconductor device may be a display device, which may include: a substrate SUB2; an adhesive layer AD1 disposed on the substrate SUB2; a plurality of chips CP1 and CP3 disposed on the adhesive layer AD1 away from the substrate, each chip may include at least one terminal p1; a passivation layer PVX1 disposed on the side of the plurality of chips CP1 and CP3 away from the substrate; a planarization layer PLN1 disposed on the side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on the side of the planarization layer PLN1 away from the substrate; a terminal extension layer RDL1 disposed on the side of the passivation layer PVX2 away from the substrate; a cover layer PLN2 disposed on the side of the terminal extension layer RDL1 away from the substrate; and a redistribution layer RDL2 disposed on the side of the cover layer PLN2 away from the substrate. A plurality of extension traces RL1 are located in the terminal extension layer RDL1, and a plurality of first traces RL2 are located in the redistribution layer RDL2.

[0280] For example, multiple chips CP1 and CP3 may be located in the same layer, that is, the surfaces of chips CP1 and CP3 facing the substrate may contact the adhesive layer AD1. Some terminals p1 in chips CP1 and CP3 may be electrically connected through multiple extended traces RL1. Other terminals p1 in chips CP1 and CP3 may be electrically connected through multiple first traces RL2.

[0281] FIG. 13A to FIG. 13G It is a schematic cross-sectional view of a structure formed after some steps of the method for manufacturing a display device according to an exemplary embodiment of the present disclosure are executed. In the case where the size of the chip CP1 is relatively large, the method for manufacturing a display device according to the exemplary embodiment of the present disclosure may include at least the following steps. It should be noted that the case where the size of the chip CP1 is relatively large may include: the size of the chip CP1 is larger than the size of the LED chip, or in other words, the ratio of the area of ​​the orthographic projection of the chip CP1 on the substrate to the area of ​​the orthographic projection of the LED chip on the substrate is greater than 1.2.

[0282] Reference Fig.13A , an adhesive layer AD1 is coated or pasted on the substrate SUB2.

[0283] Reference Fig. 13B , the LED chip CP3 is transferred to the substrate SUB2 through SMT or mass transfer process, and fixed on the substrate through the adhesive layer AD1.

[0284] For example, the terminal p1 of the LED chip CP3 may face upward, that is, be located on a side of the chip away from the substrate.

[0285] Reference Fig. 13C A passivation layer PVX1 is deposited on the side of the driving chip CP1 and the LED chip CP3 away from the substrate, and a planarization layer PLN1 is coated on the side of the passivation layer PVX1 away from the substrate.

[0286] Optionally, a passivation layer PVX2 may be formed on a side of the planarization layer PLN1 away from the substrate.

[0287] Reference Fig.13D , take a photo of the substrate (which can be called a backplane) on which the chip is formed, and use image recognition technology to determine the position of the terminal p1 of each LED chip CP3 set on the backplane, and generate a graphic file of the opening of the terminal area (i.e., the pad area) according to the corresponding logic. Next, apply photoresist on the backplane, and pattern the photoresist by digital direct writing or digital exposure machine according to the above graphic file, and then etch the passivation layer PVX2, the planarization layer PLN1 and the part of the passivation layer PVX2 not covered by the pattern of the photoresist to form a via VH3 that exposes a part of the terminal p1 of each LED chip CP3. Optionally, the passivation layer PVX2, the planarization layer PLN1 and the part of the passivation layer PVX2 located above the terminal can also be directly etched with EBL to form a via VH3 that exposes a part of the terminal p1 of each LED chip CP3.

[0288] Reference Fig.13E , a terminal extension layer RDL1 is prepared on the side of the passivation layer PVX2 away from the substrate. Then, according to the connection relationship of each terminal and based on the previously determined position of the terminal p1 of each LED chip CP3, a graphic file of the terminal extension layer RDL1 is automatically generated. The terminal extension layer RDL1 is patterned by digital exposure or EBL to form a plurality of extension traces RL1. That is, through the post-alignment process, an extension trace RL1 for electrically connecting each chip is formed in the terminal extension layer RDL1.

[0289] Optionally, refer to Fig.13F After completing the above post-alignment process, a redistribution layer RDL2 can be prepared according to the requirements of line interconnection.

[0290] For example, a cover layer PLN2 may be formed on a side of the terminal expansion layer RDL1 away from the substrate. Then, a redistribution layer RDL2 may be formed on a side of the cover layer PLN2 away from the substrate.

[0291] For example, the redistribution layer RDL2 may be prepared by a conventional photolithography process to form first traces RL2 for electrically connecting various chips in the redistribution layer RDL2. The embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL2 may be prepared by a post-alignment process.

[0292] For example, according to routing requirements, third-layer wiring, fourth-layer wiring, etc. can also be prepared, and the embodiments of the present disclosure are not particularly limited here.

[0293] Reference Figure 13G, the driver chip CP1 is transferred to the substrate SUB2 through SMT or mass transfer process. For example, the terminal p1 of the driver chip CP1 can be electrically connected to the first trace RL2 located in the redistribution layer RDL2 through eutectic soldering, solder paste soldering, conductive glue, etc., so as to realize the electrical connection between the driver chip CP1 and the LED chip CP3.

[0294] Reference Figure 13G According to some embodiments of the present disclosure, the semiconductor device may be a display device, which may include: a substrate SUB2; an adhesive layer AD1 disposed on the substrate SUB2; a plurality of LED chips CP3 disposed on the adhesive layer AD1 away from the substrate, each LED chip CP3 may include at least one terminal p1; a passivation layer PVX1 disposed on the side of the plurality of LED chips CP3 away from the substrate; a planarization layer PLN1 disposed on the side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on the side of the planarization layer PLN1 away from the substrate; a terminal extension layer RDL1 disposed on the side of the passivation layer PVX2 away from the substrate; a cover layer PLN2 disposed on the side of the terminal extension layer RDL1 away from the substrate; a redistribution layer RDL2 disposed on the side of the cover layer PLN2 away from the substrate; and at least one chip CP1 disposed on the side of the redistribution layer RDL2 away from the substrate. A plurality of extension traces RL1 are located in the terminal extension layer RDL1, and a plurality of first traces RL2 are located in the redistribution layer RDL2.

[0295] For example, the chip CP1 and the chip CP3 may be located in different layers. A plurality of LED chips CP3 may be located in the same layer and all contact the adhesive layer AD1. The driver chip CP1 may be located on the side of the plurality of LED chips CP3 away from the substrate. The LED chip CP3 located in the lower layer is electrically connected to the driver chip CP1 located in the upper layer through the extended trace RL1 and the first trace RL2.

[0296] Fig.14 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure, wherein the display device may be a large-size display device or a spliced ​​display device. Figure 13G and Fig.14 , you can Figure 13GA binding area BND for electrically connecting a circuit board (such as a flexible circuit board FPC) is provided between the two structures shown. In the embodiment of the present disclosure, the binding area BND does not need to be punched or wired, and the binding area BND is on the back side of the light-emitting area of ​​the LED, which is conducive to achieving seamless splicing display. Moreover, there is no need to set an extended routing area at the edge of the display device, so that the edge size of the formed display device is only related to the cutting process edge of the substrate. For example, in the case of a laser cutting process, the width of the laser cutting edge can be controlled within 20 microns, and the width of the heat-affected zone can be less than 50 microns. Therefore, a smaller frame can be achieved, and the four sides of the display device can be made equal in width, which is conducive to application in splicing display.

[0297] Return to reference Figure 13G , the main light-emitting surface of the LED can face the substrate SUB2, that is, the driver chip CP1 can be located on the back of the light-emitting side of the LED, so that the driver chip CP1 does not occupy the area of ​​the light-emitting area, that is, the positive projection of the driver chip CP1 on the substrate SUB2 can overlap at least partially with the positive projection of the LED chip CP3 on the substrate SUB2. Therefore, multiple driver chips CP1 can be arranged at a small interval, which is conducive to achieving high-resolution display.

[0298] It should be noted that the embodiments of the present disclosure are not limited to the implementation mode of emitting light downward. Fig.15 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure, schematically illustrating an implementation of emitting light upward. Fig.15 , the LED chip CP3 can emit light upward, that is, the driver chip CP1 can be located on the light-emitting side of the LED. That is, the orthographic projection of the driver chip CP1 on the substrate SUB2 does not overlap with the orthographic projection of the LED chip CP3 on the substrate SUB2.

[0299] Fig.16 is a schematic cross-sectional view of a semiconductor device (eg, a display device) according to some embodiments of the present disclosure. Figure 13G and Fig.16 , the display device may further include: an adhesive layer AD2 disposed on the side of the redistribution layer RDL2 away from the substrate; a driver chip CP1 disposed on the side of the adhesive layer AD2 away from the substrate; a passivation layer PVX3 disposed on the side of the driver chip CP1 away from the substrate; a planarization layer PLN3 disposed on the side of the passivation layer PVX3 away from the substrate; and a redistribution layer RDL3 disposed on the side of the planarization layer PLN3 away from the substrate. A plurality of second traces RL3 may be disposed in the redistribution layer RDL3. A plurality of terminals p1 of the driver chip CP1 may face upward, i.e., face the side away from the substrate. The driver chip CP1 is disposed on the adhesive layer AD2, which is beneficial to the fixation of the driver chip CP1.

[0300] For example, the process of preparing the redistribution layer RDL3 and the second trace RL3 may be similar to the process of preparing the terminal extension layer RDL1 and the extension trace RL1 , that is, the redistribution layer RDL3 and the second trace RL3 may also be prepared by a post-alignment process.

[0301] The driver chip CP1 can be electrically connected to the first line RL2 through the second line RL3, the first line RL2 is electrically connected to the extended line RL1, and the extended line RL1 is electrically connected to the terminal p1 of the LED chip CP3. In this way, the electrical connection between the driver chip CP1 and the LED chip CP3 can be achieved.

[0302] Next, some exemplary embodiments of the present disclosure are described in detail by taking a display device as an example.

[0303] FIG. 17A to FIG. 17I is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed.

[0304] Reference Fig.17A and Fig. 17B , an adhesive layer AD1 is coated or pasted on the substrate SUB2. For example, the substrate SUB2 can be a glass substrate, a polyimide (PI) substrate or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in the subsequent process to remove the substrate SUB2.

[0305] For example, in the embodiments of the present disclosure, the material of the substrate may include but is not limited to glass, quartz, plastic, silicon, polyimide, etc. The terminal may be a columnar structure. The material of the terminal may include a conductive material, such as a metal material, etc. Specifically, it may be at least one or a combination of at least two selected from gold, silver, copper, aluminum, molybdenum, gold alloy, silver alloy, copper alloy, aluminum alloy, molybdenum alloy, etc., and the embodiments of the present disclosure are not limited to this.

[0306] Then, the LED chip CP3 and / or the functional element CP4 are transferred to the substrate SUB2 through SMT or mass transfer process, and fixed on the substrate through the adhesive layer AD1.

[0307] For example, the LED chip CP3 and the functional element CP4 can both be located on the adhesive layer AD1, and the terminals p1 of the LED chip CP3 and the functional element CP4 can face upward, that is, located on the side of the chip away from the substrate. For example, the functional element CP4 here can be the above-mentioned microchip, which is used to achieve specific functions, including but not limited to control chips, storage chips, logic chips, sensor chips, etc.

[0308] Reference Fig. 17B and Fig. 17C , take a photo of the substrate (which can be called a backplane) on which the LED chip CP3 and the functional element CP4 are provided, and use image recognition technology to determine the coordinates and areas of the terminals p1 of each LED chip CP3 and the functional element CP4 provided on the backplane, and generate a graphic file of the terminal area (i.e., the pad area). Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form a terminal extension layer RDL1. A plurality of extended traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extended traces RL1 can be electrically connected to the terminals p1 of each LED chip CP3 and the functional element CP4, respectively, to lead out each terminal p1. That is, through the post-alignment process, an extended trace RL1 for electrically connecting each chip is formed in the terminal extension layer RDL1.

[0309] For example, the terminal expansion layer RDL1 may include a single film layer structure or a stacked structure composed of multiple film layers. In the case where the terminal expansion layer RDL1 includes a single film layer structure, the terminal expansion layer RDL1 may include a metal material such as copper (Cu). In the case where the terminal expansion layer RDL1 includes a stacked structure composed of multiple film layers, the terminal expansion layer RDL1 may include materials such as titanium / aluminum / titanium (Ti / Al / Ti), molybdenum aluminum molybdenum (Mo / Al / Mo), etc.

[0310] Reference Fig.17D , a planarization layer PLN1 is coated on the side of the terminal expansion layer RDL1 away from the substrate.

[0311] For example, the planarization layer PLN1 may include a resin material for filling the step difference between each LED chip CP3 and the functional element CP4 to achieve planarization.

[0312] Optionally, a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 away from the substrate. For example, the passivation layer PVX2 may include materials such as silicon nitride to isolate water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal expansion layer.

[0313] Continue to refer to Fig.17D, a via hole penetrating the planarization layer PLN1 and the passivation layer PVX2 can be formed to expose at least a portion of each extended trace RL1. Then, a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed by a patterning process including steps such as coating photoresist, exposure, development, and etching. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the above-mentioned via holes, respectively, to further lead out each terminal p1.

[0314] Reference Fig.17E , an adhesive layer AD2 is formed on the side of the redistribution layer RDL2 away from the substrate. Then, a driving element DRU is formed on the side of the adhesive layer AD2 away from the substrate. The driving element DRU can be fixed on the substrate through the adhesive layer AD2.

[0315] For example, the driving element DRU may include a driving chip CP1, which may be transferred to the substrate SUB2 through SMT or mass transfer process and fixed to the substrate through an adhesive layer AD2. For another example, the driving element DRU may include electronic components such as thin film transistors, that is, a plurality of thin film transistors may be formed on the substrate SUB2 through a TFT manufacturing process.

[0316] Next, a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate. For example, the planarization layer PLN2 may include a resin material to fill the step difference between each driving element DRU to achieve planarization.

[0317] Then, vias can be formed through the planarization layer PLN2 and the adhesive layer AD2 to expose at least a portion of each first wiring RL2. A metal layer is deposited on the side of the planarization layer PLN2 away from the substrate, and a redistribution layer RDL3 is formed by a patterning process including coating photoresist, exposure, development, etching and other steps. For example, a plurality of second wirings RL3 are formed in the redistribution layer RDL3. The plurality of second wirings RL3 can be electrically connected to the plurality of first wirings RL2 through the above-mentioned vias, respectively, to further lead out the respective terminals p1, and electrically connect the driving element DRU with the respective LED chips CP3 and the respective functional elements CP4.

[0318] Reference Fig.17F A planarization layer PLN3 is formed on the side of the redistribution layer RDL3 away from the substrate. Then, the substrate SUB4 is attached to the surface of the planarization layer PLN3 away from the substrate SUB2 through the adhesive layer AD3.

[0319] Reference Figure 17G , the substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation or UV dissociation.

[0320] Reference Fig.17H A protective layer PTL is coated on the side of each LED chip CP3 and each functional element CP4 away from the substrate SUB4.

[0321] Reference Fig.17I , a patterning process is performed on the protective layer PTL to expose the surfaces of each LED chip CP3 and each functional element CP4 close to the protective layer PTL. In this way, the protective layer PTL can protect the metal layer of the extended trace RL1, for example, so that the metal layer is not exposed to the air. At the same time, the main light-emitting surface of each LED chip CP3 and the functional surface of each functional element CP4 can be exposed, which is conducive to emitting light and realizing their respective functions.

[0322] It should be noted that, in the embodiments of the present disclosure, the step of performing a patterning process on the protective layer PTL is optional. For example, in some embodiments, at least a portion of the surface of the chip or functional element facing the protective layer PTL may not be exposed, and in this case, it is not necessary to perform a patterning process on the portion of the protective layer PTL corresponding to these chips or functional elements.

[0323] For example, the protection layer PTL may include an insulating layer, that is, play a role of insulation.

[0324] In the above embodiment, the terminal p1 of each chip is located on one surface of the chip. For example, the LED chip CP3 includes at least two terminals p1, and the at least two terminals p1 are both located on the surface of the LED chip CP3 away from the light emitting surface, that is, on the back side of the light emitting side. However, the embodiments of the present disclosure are not limited to such a terminal arrangement.

[0325] Fig.18 Schematically illustrates a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure, wherein the terminals of a chip are located on two opposite sides of the chip. Fig.18 The chip CP includes at least two terminals p1, and the at least two terminals p1 are respectively located on two opposite sides of the chip CP. The chip CP includes a surface facing the substrate SUB2 (i.e. Fig.18 The two opposite sides of the chip CP are located on both sides of the lower surface. Fig.18 The chip CP shown in the figure may be the LED chip CP3 and / or the functional element CP4 mentioned above.

[0326] exist Fig.18 In the illustrated embodiment, the extended trace RL1 in the terminal extended layer RDL1 may also be electrically connected to at least two terminals p1 respectively, so as to lead out the terminals p1 of the chip.

[0327] FIG. 19A to FIG. 19H is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed, wherein terminals of a chip are located on the upper and lower surfaces of the chip.

[0328] Reference Fig.19A , an adhesive layer AD1 is coated or pasted on the substrate SUB2. For example, the substrate SUB2 can be a glass substrate, a polyimide (PI) substrate or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in the subsequent process to remove the substrate SUB2.

[0329] Next, a conductive layer CDL1 is formed on the side of the adhesive layer AD1 away from the substrate. For example, the conductive layer CDL1 may include conductive materials such as metal and conductive oxide.

[0330] An adhesive layer AD2 is formed on the side of the conductive layer CDL1 away from the substrate. For example, the adhesive layer AD2 may be adhesive and may be evaporated by heating and reflowing. For example, the adhesive layer AD2 may include a solder resist.

[0331] Then, the chip CP (eg, LED chip CP3 and / or functional element CP4) is transferred to the substrate SUB2 by SMT or mass transfer process. Fig.19A As shown, the chip CP has terminals on the surface close to the substrate SUB2 (i.e., the lower surface in the figure) and the surface away from the substrate SUB2 (i.e., the upper surface in the figure). Here, for the convenience of description, the terminal located on the lower surface is referred to as terminal p11, and the terminal located on the upper surface is referred to as terminal p12.

[0332] Reference Fig.19B By heating and reflowing, the adhesive layer AD2 is evaporated, so that the terminal p11 can be electrically connected to the conductive layer ADL1. In this way, the chip CP is well connected to the conductive layer ADL1 below.

[0333] Reference Fig.19C A passivation layer PVX1 is formed on a side of the chip CP away from the substrate, and a planarization layer PLN1 is formed on a side of the passivation layer PVX1 away from the substrate.

[0334] Reference Fig.19C and Fig.19D, take a photo of the substrate (which can be called a backplane) on which the chip CP is provided, and use image recognition technology to determine the coordinates and area of ​​the terminal p12 of each chip CP provided on the backplane, and generate a graphic file of the terminal area (i.e., the pad area). Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or a digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form a terminal extension layer RDL1. A plurality of extended traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extended traces RL1 can be electrically connected to the terminals p12 of each chip CP respectively through vias to lead out each terminal p12. That is, through the post-alignment process, an extended trace RL1 for electrically connecting each chip is formed in the terminal extension layer RDL1.

[0335] Reference Fig.19E , an adhesive layer AD3 is formed on the side of the terminal expansion layer RDL1 away from the substrate. Next, a driving element DRU is formed on the side of the adhesive layer AD3 away from the substrate. The driving element DRU can be fixed on the substrate through the adhesive layer AD3.

[0336] Next, a planarization layer PLN2 is formed on the side of the driving element DRU away from the substrate.

[0337] Then, vias can be formed through the planarization layer PLN2 and / or the adhesive layer AD3 to expose at least a portion of the terminals of each extended trace RL1 and the driving element DRU. A metal layer is deposited on the side of the planarization layer PLN2 away from the substrate, and a redistribution layer RDL2 is formed by a patterning process including steps such as coating photoresist, exposure, development, and etching. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the above-mentioned vias, respectively, to further lead out each terminal p12, and electrically connect the driving element DRU to each chip CP.

[0338] Reference Fig.19F A planarization layer PLN3 is formed on the side of the redistribution layer RDL2 away from the substrate. Then, the substrate SUB4 is attached to the surface of the planarization layer PLN3 away from the substrate SUB2 through the adhesive layer AD4.

[0339] Reference Figure 19G , the substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation or UV dissociation.

[0340] Reference Fig.19H, a protective layer PTL is coated on the side of the conductive layer CDL1 away from the substrate SUB4. Then, a patterning process is performed on the protective layer PTL to expose a portion of the conductive layer CDL1 (e.g., a portion corresponding to each chip CP) close to the surface of the protective layer PTL. In this way, the terminal p11 of the chip CP can be led out through the exposed portion of the conductive layer CDL1.

[0341] Next, some exemplary embodiments of the present disclosure are described in detail by further taking the semiconductor device as a display device and the driving element of the display device including a TFT driving circuit as an example.

[0342] FIG. 20A to FIG. 20F is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are performed, wherein a driving element of the display device includes a TFT driving circuit, and the manufacturing method is implemented by the above-mentioned chip first process.

[0343] Reference Fig. 20A , an adhesive layer AD1 is coated or pasted on the substrate SUB2. For example, the substrate SUB2 can be a glass substrate, a polyimide (PI) substrate or a quartz substrate. The adhesive layer AD1 can be made of laser dissociation glue, temperature change dissociation glue, UV dissociation glue, etc., so that it can be peeled off by a specific means in the subsequent process to remove the substrate SUB2.

[0344] Reference Fig. 20B , multiple chips CP are transferred to the substrate SUB2 through SMT or mass transfer process, and fixed on the substrate through the adhesive layer AD1. For example, the multiple chips CP may include but are not limited to LED chips, driver chips, memory chips, control chips, digital-to-analog conversion chips, information processing chips, sensor chips, etc. For example, the LED chip may be an LED chip with a sapphire substrate removed, and the driver chip, memory chip, control chip, digital-to-analog conversion chip, information processing chip, and sensor chip may be Si-based chips, which may be bare chips without a packaging structure, and the height of the chip may be less than 100 microns.

[0345] exist Fig. 20B In the embodiment of the present invention, four chips are schematically shown. For the convenience of description, the four chips are respectively referred to as chips CP1, CP2, CP3 and CP4. For example, chip CP1 may be a control chip, chip CP2 may be a storage chip, chip CP3 may be an LED chip, and chip CP4 may be a sensor chip. It should be understood that the embodiments of the present invention are not limited to Fig. 20B Arrangement shown.

[0346] For example, the chips CP1, CP2, CP3, CP4 may all be located on the adhesive layer AD1, and the terminal p1 of each chip CP1, CP2, CP3, CP4 may face upward, ie, be located on the side of the chip away from the substrate.

[0347] Reference Fig. 20C , take a photo of the substrate (which can be called a backplane) on which the chips CP1, CP2, CP3, and CP4 are arranged, and use image recognition technology to determine the coordinates and area of ​​the terminals p1 of each chip CP1, CP2, CP3, and CP4 arranged on the backplane, and generate a graphic file of the terminal area (i.e., the pad area). Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form a terminal expansion layer RDL1. A plurality of extended traces RL1 are formed in the terminal expansion layer RDL1, and the plurality of extended traces RL1 can be electrically connected to the terminals p1 of each chip CP1, CP2, CP3, and CP4, respectively, to lead out each terminal p1. That is, through the post-alignment process, an extended trace RL1 for electrically connecting each chip is formed in the terminal expansion layer RDL1.

[0348] Continue to refer to Fig. 20C , a planarization layer PLN1 is coated on the side of the terminal expansion layer RDL1 away from the substrate.

[0349] Optionally, a passivation layer PVX1 may be prepared on the side of the planarization layer PLN1 close to the substrate, and a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 away from the substrate. For example, the passivation layer PVX1 and the passivation layer PVX2 may include materials such as silicon nitride and silicon oxide to isolate water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the terminal expansion layer.

[0350] Continue to refer to Fig. 20C , a via hole VH1 penetrating the passivation layer PVX1 , the planarization layer PLN1 , and the passivation layer PVX2 may be formed to expose at least a portion of each extended trace RL1 .

[0351] In some embodiments of the present disclosure, the planarization layer PLN1 may include resin materials, such as polyimide (PI) and other materials, which are used to fill the step differences between the chips CP1, CP2, CP3, and CP4 to achieve planarization.

[0352] In some embodiments of the present disclosure, the planarization layer PLN1 may include a planarization material that can be cured at low temperature, such as an acrylic resin material. The cost of the planarization material that can be cured at low temperature is lower than that of the polyimide material, which is beneficial to reduce the cost of the product.

[0353] It should also be noted that after the chip transfer is completed, a planarization material that can be cured at low temperature is used, and then a low-temperature oxide TFT process or other semiconductor devices that can be manufactured at low temperature can be used to complete the production of the entire TFT device. For example, the curing temperature of the planarization material that can be cured at low temperature can be less than 250°C, and accordingly, the TFT device can be prepared at less than 250°C in the TFT process, so that the risk of high temperature in the TFT process damaging the performance of the microchip can be reduced.

[0354] For example, the thickness of the planarization layer PLN1 is higher than the maximum height of each chip CP1, CP2, CP3, CP4 by more than 10 micrometers.

[0355] Reference Fig.20D A metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed by a patterning process including coating photoresist, exposure, development, etching, etc. For example, a plurality of first wiring lines RL2 are formed in the redistribution layer RDL2. The plurality of first wiring lines RL2 can be electrically connected to the plurality of extended wiring lines RL1 through the above-mentioned vias, respectively, so as to further lead out the respective terminals p1.

[0356] Fig.26A and Fig.26B Schematic cross-sectional views of via holes of a display device according to embodiments of the present disclosure are schematically shown respectively.

[0357] In the process of forming the redistribution layer RDL2, a portion of the metal layer needs to be deposited in the via hole VH1, so that the plurality of first traces RL2 in the redistribution layer RDL2 can be electrically connected to the plurality of extension traces RL1 in the terminal extension layer RDL1 through the via hole VH1. In this case, a conventional organic material can be used to form an insulating layer between the terminal extension layer RDL1 and the redistribution layer RDL2. Fig.26A The shape of the via hole VH1 in the cross-sectional view is an inverted trapezoidal shape, so as to facilitate a portion of the metal layer to be deposited in the via hole VH1.

[0358] Optionally, in some embodiments of the present disclosure, the terminal expansion layer RDL1 can be used as a seed layer, and the metal layer (for example, a copper layer) can be plated by electrochemical means or chemical plating. In this way, a metal layer with a thickness equal to the combination of the passivation layer PVX1, the planarization layer PLN1 and the passivation layer PVX2 can be grown in the via VH1 to fill the via VH1, so that the multiple first routing lines RL2 located in the redistribution layer RDL2 can be electrically connected to the multiple extension routing lines RL1 located in the terminal expansion layer RDL1 through the via VH1 respectively.

[0359] In this case, a high temperature resistant organic material can be used to form an insulating layer between the terminal expansion layer RDL1 and the redistribution layer RDL2. On this basis, a relatively vertical via hole can be formed by using a hard mask layer-exposure development-dry etching-removal of the hard mask layer. Fig.26B , the shape of the via hole VH1 in the cross-sectional view may be a rectangle. That is, the opening area of ​​the via hole VH1 on the side close to the terminal expansion layer RDL1 is substantially equal to the opening area of ​​the via hole VH1 on the side close to the redistribution layer RDL2. Therefore, in this embodiment, the profile requirements for the via hole are relatively low, and a via hole with an opening size of less than 10 microns can be formed, which is beneficial to improving the PPI of the display device.

[0360] It should be noted that the number of routing layers can be increased according to the circuit logic design requirements. For example, redistribution layers RDL3 and RDL4 can be formed on the side of the redistribution layer RDL2 away from the substrate, and an insulating layer can be used to isolate and insulate two adjacent routing layers.

[0361] In this way, a backplane including chips CP1, CP2, CP3, CP4 and a terminal expansion layer is formed, and then a driving element including a TFT driving circuit can be formed on the backplane. That is, in this embodiment, the display device is formed using a chip first process.

[0362] Fig.21 yes Fig.20E For example, refer to Fig.20E and Fig.21 , a barrier layer BRL and a buffer layer BFL may be formed in sequence on the side of the redistribution layer RDL2 away from the substrate. Then, a film layer structure of a TFT may be formed on the side of the buffer layer BFL away from the substrate. For example, an active layer, a gate insulating layer GI1, a conductive layer CDL1, a gate insulating layer GI2, a conductive layer CDL2, an interlayer dielectric layer IDL and a conductive layer CDL3 may be formed in sequence on the side of the buffer layer BFL away from the substrate. For example, a TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, a gate of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, another electrode of the storage capacitor may be located in the conductive layer CDL2, and a source and a drain of the thin film transistor may be located in the conductive layer CDL3. For example, a plurality of second routing lines RL3 may be located in the conductive layer CDL3. The second routing line RL3 may be electrically connected to the first routing line RL2 through a via penetrating the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric layer IDL. The source and drain of the thin film transistor may be electrically connected to the source region and the drain region of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 , and the interlayer dielectric layer IDL.

[0363] For example, a planarization layer PLN2 may be formed on a side of the conductive layer CDL3 away from the substrate.

[0364] It should be understood that in this embodiment, a known TFT manufacturing process may be used to form a driving element including a TFT driving circuit, which will not be described in detail herein.

[0365] It should be noted that, in the embodiments of the present disclosure, the thin film transistors included in the above-mentioned TFT driving circuit may include but are not limited to polysilicon TFT, low-temperature polysilicon TFT, oxide TFT and the like.

[0366] For example, as mentioned above, in conjunction with reference FIG. 17F to FIG. 17I , the substrate SUB4 can be attached to the surface of the planarization layer PLN3 away from the substrate SUB2 through the adhesive layer AD3. The substrate SUB2 is separated from the devices formed thereon by laser dissociation, temperature dissociation or UV dissociation. A protective layer PTL is coated on the side of each chip CP1, CP2, CP3, CP4 away from the substrate SUB4. A composition process is performed on the protective layer PTL to expose the surface of each chip CP1, CP2, CP3, CP4 close to the protective layer PTL. In this way, the protective layer PTL can protect the metal layer of the extended trace RL1, for example, so that the metal layer can be not exposed to the air. At the same time, the functional surface of each chip CP1, CP2, CP3, CP4 can be exposed, which is conducive to realizing the function of each chip.

[0367] Fig.20F is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure. Fig.20F , Fig.20E and Fig.21According to some embodiments of the present disclosure, the semiconductor device may be a display device, for example, the display device may be a μLED display device. It may include: a substrate SUB4; an adhesive layer AD3 disposed on the substrate SUB4; a planarization layer PLN2 disposed on the side of the adhesive layer AD3 away from the substrate; a conductive layer CDL3 disposed on the side of the planarization layer PLN2 away from the substrate; an interlayer dielectric layer IDL disposed on the side of the conductive layer CDL3 away from the substrate; a conductive layer CDL2 disposed on the side of the interlayer dielectric layer IDL away from the substrate; a gate insulating layer GI2 disposed on the side of the conductive layer CDL2 away from the substrate; a conductive layer CDL1 disposed on the side of the gate insulating layer GI2 away from the substrate; an active layer ACT disposed on the side of the conductive layer CDL1 away from the substrate; and a buffer layer BF disposed on the side of the active layer ACT away from the substrate. L; a barrier layer BRL arranged on the side of the buffer layer BFL away from the substrate; a redistribution layer RDL2 arranged on the side of the barrier layer BRL away from the substrate; a passivation layer PVX2 arranged on the side of the redistribution layer RDL2 away from the substrate; a planarization layer PLN1 arranged on the side of the passivation layer PVX2 away from the substrate; a passivation layer PVX1 arranged on the side of the planarization layer PLN1 away from the substrate; a terminal extension layer RDL1 arranged on the side of the passivation layer PVX1 away from the substrate; a plurality of chips CP1, CP2, CP3, CP4 arranged on the side of the terminal extension layer RDL1 away from the substrate; and a protection layer PTL arranged on the side of the chips CP1, CP2, CP3, CP4 away from the substrate.

[0368] For example, the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, the other electrode of the storage capacitor may be located in the conductive layer CDL2, and the source and drain of the thin film transistor may be located in the conductive layer CDL3.

[0369] For example, a plurality of extended traces RL1 may be located in the terminal extension layer RDL1. A plurality of first traces RL2 may be located in the redistribution layer RDL2. A plurality of second traces RL3 may be located in the conductive layer CDL3. Each of the chips CP1, CP2, CP3, and CP4 may include at least one terminal p1. The terminals p1 of each chip CP1, CP2, CP3, and CP4 are led out through the extended trace RL1. A plurality of first traces RL2 may be electrically connected to a plurality of extended traces RL1 respectively through vias penetrating the passivation layer PVX1, the planarization layer PLN1, and the passivation layer PVX2. A plurality of second traces RL3 may be electrically connected to a first trace RL2 respectively through vias penetrating the gate insulation layer GI1, the gate insulation layer GI2, and the interlayer dielectric layer IDL. The source and drain of the thin film transistor may be electrically connected to the source region and the drain region of the active layer through vias penetrating the gate insulation layer GI1, the gate insulation layer GI2, and the interlayer dielectric layer IDL. In this way, electrical connection between the TFT driving circuit and the chip can be achieved, as well as electrical connection between multiple chips.

[0370] Fig. 22 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein an LED chip and other chips are located in different layers. Fig.23 yes Fig. 22 A partial enlarged view of part II in FIG. Fig. 22 and Fig.23 Considering the differences in process and performance (such as temperature resistance) between LED chips and display-related and sensor-related Si-based chips, LED chips and other chips can be arranged on different sides of the TFT. For example, the LED chip can be arranged on the side of the thin film transistor close to the substrate SUB2, and other chips can be arranged on the side of the thin film transistor away from the substrate SUB2. In this embodiment, the chips CP1, CP2, and CP4 located in the upper layer can be electrically connected to the LED chip CP3 located in the lower layer through a plurality of second traces RL3 located in the redistribution layer RDL3.

[0371] Specifically, the display device can be a μLED (i.e., miniLED) display device, which can include: a substrate SUB2; an adhesive layer AD1 arranged on the substrate SUB2; an LED chip CP3 arranged on the side of the adhesive layer AD1 away from the substrate; a terminal extension layer RDL1 arranged on the side of the LED chip CP3 away from the substrate; a passivation layer PVX1 arranged on the side of the terminal extension layer RDL1 away from the substrate; a planarization layer PLN1 arranged on the side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 arranged on the side of the planarization layer PLN1 away from the substrate; a redistribution layer RDL2 arranged on the side of the passivation layer PVX2 away from the substrate; a blocking layer BRL and / or a buffer layer BFL arranged on the side of the redistribution layer RDL2 away from the substrate; an active layer ACT arranged on the side of the buffer layer BFL away from the substrate; a gate insulating layer G arranged on the side of the active layer ACT away from the substrate. I1; a conductive layer CDL1 arranged on a side of the gate insulating layer GI1 away from the substrate; a gate insulating layer GI2 arranged on a side of the conductive layer CDL1 away from the substrate; a conductive layer CDL2 arranged on a side of the gate insulating layer GI2 away from the substrate; an interlayer dielectric layer IDL arranged on a side of the conductive layer CDL2 away from the substrate; a conductive layer CDL3 arranged on a side of the interlayer dielectric layer IDL away from the substrate; a planarization layer PLN2 arranged on a side of the conductive layer CDL3 away from the substrate; an adhesive layer AD2 arranged on a side of the planarization layer PLN2 away from the substrate; a plurality of chips CP1, CP2, CP4 arranged on a side of the adhesive layer AD2 away from the substrate; a redistribution layer RDL3 arranged on a side of the plurality of chips CP1, CP2, CP4 away from the substrate; a passivation layer PVX3 arranged on a side of the redistribution layer RDL3 away from the substrate; a planarization layer PLN3 arranged on a side of the passivation layer PVX3 away from the substrate.

[0372] For example, the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, the other electrode of the storage capacitor may be located in the conductive layer CDL2, and the source and drain of the thin film transistor may be located in the conductive layer CDL3.

[0373] For example, a plurality of extended traces RL1 may be located in the terminal extension layer RDL1. A plurality of first traces RL2 may be located in the redistribution layer RDL2. A plurality of second traces RL3 may be located in the conductive layer CDL3. A plurality of third traces RL4 may be located in the redistribution layer RDL3. Each of the chips CP1, CP2, CP3, and CP4 may include at least one terminal p1. The terminals p1 of each chip CP1, CP2, and CP4 may be led out through the second trace RL3. The terminals p1 of the chips CP1, CP2, and CP4 may be electrically connected through the second trace RL3. At least one third trace RL4 may be electrically connected to at least one of the second trace RL3, the source electrode, and the drain electrode of the thin film transistor through a via hole penetrating the adhesive layer AD2 and the planarization layer PLN2. A plurality of first traces RL2 may be electrically connected to a plurality of extended traces RL1 through via holes penetrating the passivation layer PVX1, the planarization layer PLN1, and the passivation layer PVX2, respectively. The plurality of second lines RL3 can be electrically connected to the first lines RL2 respectively through vias penetrating the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric layer IDL. The source and drain of the thin film transistor can be electrically connected to the source region and the drain region of the active layer through vias penetrating the gate insulating layer GI1, the gate insulating layer GI2 and the interlayer dielectric layer IDL. In this way, the electrical connection between the TFT driving circuit and the chip can be realized, and the electrical connection between the plurality of chips can be realized.

[0374] In this embodiment, the chips CP1, CP2, CP4 and the LED chip CP3 are located on opposite sides of the thin film transistor. By using multiple terminal extension layers formed by the post-alignment process, electrical connection between the TFT driving circuit and the chip, and electrical connection between multiple chips can still be achieved.

[0375] Fig.24 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the LED chip and other chips are located in different layers. Fig.24 , multiple terminal expansion layers can be set to realize the electrical connection between multiple chips CP1, CP2, CP4 located in the upper layer. For example, a terminal expansion layer RDL4 and a passivation layer PVX4 can be set between the passivation layer PVX3 and the planarization layer PLN3. The passivation layer PVX4 is set on the side of the planarization layer PLN3 away from the substrate SUB4, and the terminal expansion layer RDL4 is set between the passivation layer PVX4 and the passivation layer PVX3. Multiple extended traces RL5 can be located in the terminal expansion layer RDL4.

[0376] For example, the chips CP1, CP2, and CP4 may include at least three terminals p1. The third trace RL4 in the redistribution layer RDL3 may lead out the terminals p1 on both sides. The extended trace RL5 in the terminal extension layer RDL4 may electrically connect the terminal p1 in the middle of one chip with the terminal p1 in the middle of another chip.

[0377] By setting up multiple terminal expansion layers, it is beneficial to realize the electrical connection between multiple chips CP1, CP2, CP4 located in the upper layer. It should be understood that more terminal expansion layers can be set according to the actual wiring needs to realize the electrical connection between multiple chips CP1, CP2, CP4 located in the upper layer.

[0378] FIG. 25A to FIG. 25F is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a display device according to an exemplary embodiment of the present disclosure are executed, wherein a driving element of the display device includes a TFT driving circuit, and the manufacturing method is implemented by the above-mentioned chip later process.

[0379] Reference Fig.25A , a TFT driving circuit can be formed on the substrate SUB2. For example, in the embodiment of the present disclosure, the thin film transistor in the above-mentioned TFT driving circuit may include but is not limited to polysilicon TFT, low-temperature polysilicon TFT, oxide TFT, etc. Taking the polysilicon TFT process as an example, a barrier layer BRL and a buffer layer BFL can be formed in sequence on the substrate SUB4. Then, a film layer structure of a TFT can be formed on the side of the buffer layer BFL away from the substrate. For example, an active layer ACT, a gate insulating layer GI1, a conductive layer CDL1, a gate insulating layer GI2, a conductive layer CDL2, an interlayer dielectric layer IDL and a conductive layer CDL3 can be formed in sequence on the side of the buffer layer BFL away from the substrate. For example, the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (ie, TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, the other electrode of the storage capacitor may be located in the conductive layer CDL2, and the source and drain of the thin film transistor may be located in the conductive layer CDL3. For example, a plurality of second traces RL3 may be located in the conductive layer CDL3. The source and drain of the thin film transistor may be electrically connected to the source region and the drain region of the active layer through via holes penetrating the gate insulating layer GI1 , the gate insulating layer GI2 , and the interlayer dielectric layer IDL.

[0380] For example, a planarization layer PLN1 may be formed on a side of the conductive layer CDL3 away from the substrate, and a conductive layer CDL4 may be formed on a side of the planarization layer PLN1 away from the substrate. For example, a plurality of third routing lines RL4 may be located in the conductive layer CDL4. The plurality of third routing lines RL4 may be electrically connected to the plurality of second routing lines RL3 and the source and drain of the thin film transistor through via holes penetrating the planarization layer PLN1, respectively.

[0381] It should be understood that in this embodiment, a known TFT manufacturing process may be used to form a driving element including a TFT driving circuit, which will not be described in detail herein.

[0382] Thus, in this embodiment, a TFT driving circuit is first formed on the substrate SUB4, and then various chips and at least one terminal expansion layer are formed on the backplane formed with the TFT driving circuit, that is, the display device is formed using a chip later process.

[0383] Reference Fig.25B and Fig.25C , an adhesive layer AD2 is formed on the side of the conductive layer CDL4 away from the substrate. Then, multiple chips CP are transferred to the substrate SUB4 through SMT or mass transfer process, and fixed on the substrate SUB4 through the adhesive layer AD2. Each chip CP may include at least two terminals p1. In the illustrated embodiment, the terminal p1 of each chip CP faces upward, that is, toward the side of the chip away from the substrate SUB4.

[0384] For example, the plurality of chips CP may include but are not limited to LED chips, driver chips, memory chips, control chips, digital-to-analog conversion chips, information processing chips, sensor chips, etc. For example, the LED chip may be an LED chip with a sapphire substrate removed, and the driver chip, memory chip, control chip, digital-to-analog conversion chip, information processing chip, and sensor chip may be Si-based chips, which may be bare chips without a packaging structure. Fig.25C In the embodiment of the present invention, four chips are schematically shown. For the convenience of description, the four chips are respectively referred to as chips CP1, CP2, CP3 and CP4. For example, chip CP1 may be a control chip, chip CP2 may be a storage chip, chip CP3 may be an LED chip, and chip CP4 may be a sensor chip. It should be understood that the embodiments of the present invention are not limited to Fig.25C Arrangement shown.

[0385] For example, the substrate SUB4 may be a glass substrate, a polyimide (ie, PI) substrate, or a quartz substrate.

[0386] For example, the adhesive layer AD2 may include but is not limited to adhesive materials such as thermal adhesive, laser curing adhesive, photoresist, and UV curing adhesive.

[0387] Reference Fig.25D A patterning process may be used to form a plurality of via holes VH2 in the adhesive layer AD2 to expose at least a portion of the third trace RL4 located in the conductive layer CDL4. For example, the patterning process here may use a known photolithography process, including the steps of photoresist coating, exposure, development, and etching, and a mask may be used during the exposure process.

[0388] Reference Fig.25E , take a photo of the substrate (which can be called a backplane) on which the chips CP1, CP2, CP3, and CP4 are arranged, and use image recognition technology to determine the coordinates and area of ​​the terminals p1 of each chip CP1, CP2, CP3, and CP4 arranged on the backplane, and generate a graphic file of the terminal area (i.e., the pad area). Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form a terminal expansion layer RDL1. A plurality of extended traces RL1 are formed in the terminal expansion layer RDL1, and the plurality of extended traces RL1 can be electrically connected to the terminals p1 of each chip CP1, CP2, CP3, and CP4, respectively, to lead out each terminal p1. That is, through the post-alignment process, an extended trace RL1 for electrically connecting each chip is formed in the terminal expansion layer RDL1.

[0389] For example, at least one extended line RL1 can be electrically connected to the TFT driving circuit through a third line RL4 located in the conductive layer CDL4, for example, electrically connected to the source or drain of the thin film transistor. At least one extended line RL1 can also be electrically connected to at least two of the chips CP1, CP2, CP3, and CP4. In this way, electrical connection between the TFT driving circuit and the chip can be achieved, as well as electrical connection between multiple chips.

[0390] Reference Fig.25F , a passivation layer PVX1 and a planarization layer PLN2 may be sequentially formed on a side of the terminal expansion layer RDL1 away from the substrate.

[0391] It should be noted that the number of routing layers can be increased according to circuit logic design requirements. For example, redistribution layers RDL2 and RDL3 can be formed on the side of the terminal expansion layer RDL1 away from the substrate, and an insulating layer can be used to isolate and insulate two adjacent routing layers.

[0392] Reference Fig.25FAccording to some embodiments of the present disclosure, the semiconductor device may be a display device, for example, the display device may be a μLED display device. It may include: a substrate SUB4; a barrier layer BRL disposed on the substrate SUB4; a buffer layer BFL disposed on the barrier layer BRL away from the substrate; an active layer ACT disposed on the buffer layer BFL away from the substrate; a gate insulating layer GI1 disposed on the active layer ACT away from the substrate; a conductive layer CDL1 disposed on the gate insulating layer GI1 away from the substrate; a gate insulating layer GI2 disposed on the conductive layer CDL1 away from the substrate; a conductive layer CDL2 disposed on the gate insulating layer GI2 away from the substrate; an interlayer dielectric layer IDL disposed on the conductive layer CDL2 away from the substrate ; a conductive layer CDL3 arranged on a side of the interlayer dielectric layer IDL away from the substrate; a planarization layer PLN1 arranged on a side of the conductive layer CDL3 away from the substrate; a conductive layer CDL4 arranged on a side of the planarization layer PLN1 away from the substrate; an adhesive layer AD2 arranged on a side of the conductive layer CDL4 away from the substrate; a plurality of chips arranged on a side of the adhesive layer AD2 away from the substrate; a terminal expansion layer RDL1 arranged on a side of the plurality of chips away from the substrate; a passivation layer PVX1 arranged on a side of the terminal expansion layer RDL1 away from the substrate; and a planarization layer PLN2 arranged on a side of the passivation layer PVX1 away from the substrate.

[0393] For example, the TFT driving circuit may include at least one thin film transistor and at least one storage capacitor, the gate of the thin film transistor (i.e., TFT) and one electrode of the storage capacitor may be located in the conductive layer CDL1, the other electrode of the storage capacitor may be located in the conductive layer CDL2, and the source and drain of the thin film transistor may be located in the conductive layer CDL3.

[0394] For example, a plurality of extended traces RL1 may be located in the terminal extension layer RDL1. Each of the chips CP1, CP2, CP3, CP4 may include at least one terminal p1. The terminals p1 of the respective chips CP1, CP2, CP3, CP4 are led out through the extended traces RL1.

[0395] A plurality of second routing lines RL3 may be located in the conductive layer CDL3. The source and drain of the thin film transistor may be electrically connected to the source region and drain region of the active layer through vias penetrating the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer dielectric layer IDL. A plurality of third routing lines RL4 may be located in the conductive layer CDL4. The plurality of third routing lines RL4 may be electrically connected to the plurality of second routing lines RL3 and the source and drain of the thin film transistor through vias penetrating the planarization layer PLN1, respectively.

[0396] For example, at least one extended line RL1 can be electrically connected to the TFT driving circuit through a third line RL4 located in the conductive layer CDL4, for example, electrically connected to the source or drain of the thin film transistor. At least one extended line RL1 can also be electrically connected to at least two of the chips CP1, CP2, CP3, and CP4. In this way, electrical connection between the TFT driving circuit and the chip can be achieved, as well as electrical connection between multiple chips.

[0397] In the above embodiments, the thin film transistor is a top-gate thin film transistor, but it should be understood that the embodiments of the present disclosure are not limited thereto. For example, the thin film transistor may also be a bottom-gate thin film transistor, for example, using a back channel etching structure (ie, a BCE TFT).

[0398] Fig. 27 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure, wherein the thin film transistor is a bottom-gate thin film transistor. Fig. 27 In the process of forming the film structure of the TFT on the side of the buffer layer BFL away from the substrate, the gate material layer CDL1 can be prepared first, then the gate insulating layer GI1 can be formed, and then the active layer ACT can be formed. For example, the gate material layer CDL1 can include materials such as Mo / Al / Mo or Mo / Cu, and the thickness can be 3000 to 6000 angstroms. The gate insulating layer GI1 can include silicon nitride or silicon oxide, and the thickness can be 2000 to 5000 angstroms. The active layer ACT can include oxide semiconductor materials such as IGZO, IGTO, IZO, etc., and the thickness can be 300 to 1000 angstroms.

[0399] The following will describe in detail the application of the semiconductor device according to the embodiment of the present disclosure in the sensor scenario in conjunction with the accompanying drawings. It should be noted that in the following description, the structure of the semiconductor device applied to the sensor scenario will be mainly described, and its manufacturing process can refer to the above description, which will not be repeated here.

[0400] In the embodiments of the present disclosure, the chip with integrated functions is functionally split to become multiple microchips. In the sensor application scenario, more chips can be set in the front-end part to improve the ability to collect information, and these front-end microchips can share the control chip in the back-end part (such as the control part). Through chip splitting and partial function enhancement, it is conducive to optimizing the function of the sensor device.

[0401] For example, with the increasing demand for giant display screens, 3D displays, virtual reality, etc., the demand for spatial detection technology for objects is also increasing. For example, it is necessary to detect objects at multiple depths and multiple positions to realize a smart display screen with integrated multi-region spatial detection. For example, in existing spatial detection technologies, external module solutions are usually adopted. That is, the sensor used for spatial detection is usually placed in the middle of the upper frame of the display or on the desktop in front of the display. The application space is limited and there is a blind spot for recognition. For existing 2D displays, people can realize gesture control by standing in the optimal recognition range. However, for 3D displays, the display images are distributed in multiple levels and multiple positions, and the experience that users want is to touch virtual objects at different positions. Therefore, the device solution for integrating sensors and display elements for spatial detection has gradually become one of the important topics of concern to R&D personnel.

[0402] In the following embodiments, an acoustic sensor is taken as an example to describe a device solution for integrating a sensor for space detection with a display element according to an embodiment of the present disclosure.

[0403] In the embodiments of the present disclosure, the acoustic sensor may be functionally split to form a plurality of microchips. For example, the acoustic sensor may include at least a signal acquisition chip and a signal processing chip. Fig.28A 28 are schematic block diagrams of acoustic sensors according to some embodiments of the present disclosure, Fig.28C The arrangement of acoustic sensors in a display according to some embodiments of the present disclosure is schematically shown. Fig.28A and Fig.28B By functionally splitting the acoustic sensor, multiple microchips can be formed. For example, multiple signal acquisition chips SNC1 can be set in an acoustic sensor, and the multiple signal acquisition chips SNC1 can be electrically connected to at least one signal processing chip. Multiple signal acquisition chips SNC1 can be connected in series to increase the signal-to-noise ratio of the collected signal, thereby increasing the signal detection sensitivity and achieving long-distance detection.

[0404] For example, a signal processing chip may include an LC filter circuit, an amplifier circuit, a digital-to-analog conversion circuit, and a control circuit. The LC filter circuit may filter the signal collected by the signal acquisition chip. The amplifier circuit may amplify, rectify, and perform other processing on the filtered signal. The digital-to-analog conversion circuit may perform digital-to-analog conversion on the amplified signal. The control circuit may receive the digital-to-analog converted signal and perform corresponding control functions based on the signal.

[0405] Optionally, the signal processing chip can also be functionally split so that one signal processing chip can include multiple microchips, for example, the LC filter circuit, the amplifier circuit, the digital-to-analog conversion circuit and the control circuit can form independent microchips respectively, so that the microchips can be flexibly arranged. That is, the acoustic sensor can include an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3 and a control chip SNP4.

[0406] For example, a plurality of signal acquisition chips SNC1 can be connected in series with each other and then electrically connected to an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3 and a control chip SNP4. A plurality of signal acquisition chips SNC1, an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3 and a control chip SNP4 can be arranged in a straight line, such as Fig.28A As shown. In this way, the acoustic sensor SR1 with such an arrangement can be set in the middle of the upper frame of the display. Multiple signal acquisition chips SNC1, LC filter chips SNP1, amplifier chips SNP2, digital-to-analog conversion chips SNP3 and control chips SNP4 can be arranged in a rectangle, such as Fig.28B As shown. In this way, the acoustic sensor SR2 with such an arrangement can be set in the display area of ​​the display. In the embodiment of the present disclosure, the sensor can be placed in the display area of ​​the display, and can also be placed on the frame of the display. Moreover, since the sensor is split into multiple microchips, the sensor can be flexibly arranged. For example, the sensor can be arranged in a row, a circle, a serpentine, a rectangular area, a circular area, an elliptical area, etc.; multiple microchips can be densely arranged in a blank area, and multiple microchips can be inserted in the gaps between pixels. In other words, the sensor according to the embodiment of the present disclosure can be flexibly arranged on the display, which improves the device performance and installation flexibility, thereby solving the detection limitations of existing devices and the problem that they can only be placed in an external module manner.

[0407] In an embodiment of the present disclosure, the sensor may be a Si-based sensor. For example, the signal acquisition chip may include a transducer for collecting acoustic signals and converting them into electrical signals. Fig.29 is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure, wherein the sensor is a Si-based sensor. Fig.29, the display device may include a substrate SUB5; a driving element disposed on the substrate SUB5; a planarization layer PLN1 disposed on a side of the driving element away from the substrate; a conductive layer CDL4 disposed on a side of the planarization layer PLN1 away from the substrate; a planarization layer PLN2 disposed on a side of the conductive layer CDL4 away from the substrate; a passivation layer PVX1 disposed on a side of the planarization layer PLN2 away from the substrate; a terminal expansion layer RDL1 disposed on a side of the passivation layer PVX1 away from the substrate; a passivation layer PVX2 disposed on a side of the terminal expansion layer RDL1 away from the substrate; and a plurality of chips disposed on a side of the passivation layer PVX2 away from the substrate. For example, the plurality of chips may be a signal acquisition chip SNC1, an LC filter chip SNP1, an amplifier chip SNP2, a digital-to-analog conversion chip SNP3, and a control chip SNP4 of the sensor.

[0408] Multiple extended traces RL1 may be located in the terminal extension layer RDL1. Multiple signal acquisition chips SNC1 may be connected in series through multiple extended traces RL1, and multiple extended traces RL1 may also electrically connect multiple signal acquisition chips SNC1, LC filter chip SNP1, amplifier chip SNP2, digital-to-analog conversion chip SNP3 and control chip SNP4 connected in series in sequence.

[0409] In this embodiment, the driving element may include the above-mentioned TFT driving circuit. The specific film layer structure may refer to the above description and will not be described in detail here.

[0410] Fig.30 The figure schematically shows the relationship between the increase factor of the output voltage and the number of transducers connected in series in the sensor according to the embodiment of the present disclosure. Fig.30 In the embodiment of the present disclosure, the transducer and other signal processing circuits such as filtering and amplification are separated, and multiple transducers are connected in series to increase the amount of received signals, such as Fig.30 As shown, the signal is then filtered and amplified. In this way, the device sensitivity can be increased to achieve detection at a longer distance. In addition, in the embodiment of the present disclosure, the signal processing chip can be placed closely with the transducer to reduce RC load and noise, increase signal detection sensitivity, and thus facilitate detection at a longer distance.

[0411] It should be noted that in Fig.29 In the embodiment shown, the TFT backplane and the terminal extension layer are first made, and then the chip is bonded. However, the embodiments of the present disclosure are not limited to this, and the individual chips can be bonded side by side / stacked, with the chip facing down or facing up (i.e., face down / up), with chip priority or RDL priority (i.e., die first / RDL first). The types of substrate SUB5 include, but are not limited to, glass substrate, PCB, FPC, etc.

[0412] Fig.31 is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure, wherein the sensor is a piezoelectric sensor including a piezoelectric film. Fig.31 In this embodiment, a plurality of piezoelectric sensing units are manufactured on a backplane including a TFT driving circuit, the plurality of piezoelectric sensing units are connected in series and bonded to a signal processing chip.

[0413] It should be noted that, in this embodiment, "piezoelectric film" is used for illustration, but the embodiments of the present disclosure are not limited thereto. For example, the sensor chip included in the semiconductor device according to the embodiment of the present disclosure may include other types of sensors, and the sensor may include other types of functional films. That is, in this article, the expression "functional film" includes but is not limited to piezoelectric film.

[0414] Specifically, the display device may include a substrate SUB5; a driving element arranged on the substrate SUB5; a planarization layer PLN1 arranged on a side of the driving element away from the substrate; a conductive layer CDL4 arranged on a side of the planarization layer PLN1 away from the substrate; a piezoelectric film PVL arranged on a side of the conductive layer CDL4 away from the substrate; and a conductive layer CDL5 arranged on a side of the piezoelectric film PVL away from the substrate.

[0415] The piezoelectric sensing unit includes a first electrode E1, a second electrode E2, and a piezoelectric film PVL sandwiched between the first electrode E1 and the second electrode E2. For example, the piezoelectric film PVL can be a PVDF piezoelectric film. A plurality of first electrodes E1 are located in the conductive layer CDL4, and a plurality of second electrodes E2 are located in the conductive layer CDL5. The first electrode E1 and the second electrode E2 of each piezoelectric sensing unit are arranged oppositely and spaced apart.

[0416] Fig.32 yes Fig.31 A partial enlarged view of part III in FIG. Fig.31 and Fig.32 In two adjacent piezoelectric sensing units, the first electrode E1 of one piezoelectric sensing unit is electrically connected to the second electrode E2 of the other piezoelectric sensing unit through a via hole or a groove. In this way, multiple piezoelectric sensing units can be connected in series.

[0417] In the process of forming multiple piezoelectric sensing units, a conductive layer may be deposited first, and multiple first electrodes E1 may be formed through a patterning process; then, a PVDF piezoelectric film layer may be spin-coated, and the PVDF piezoelectric film layer may be cured and dry-etched to form a patterned PVDF piezoelectric film; then, a conductive layer may be deposited, and multiple second electrodes E2 may be formed through a patterning process. For example, the thickness of the PVDF piezoelectric film layer is relatively thick, such as several micrometers, so a flat layer may be made on the piezoelectric film layer, and then the second electrodes E2 may be formed.

[0418] The signal processing chip may include at least two terminals p1. For example, the terminals p1 may face downward, one terminal p1 may be electrically connected to a first electrode E1 of an adjacent piezoelectric sensing unit, and the other terminal p1 may be electrically connected to an extended trace in the conductive layer CDL4.

[0419] FIG. 33A to FIG. 33C Schematic cross-sectional views respectively illustrate structures formed after some steps of a method for manufacturing a display device integrated with a sensor according to some embodiments of the present disclosure are executed, wherein the sensor is a piezoelectric sensor including a piezoelectric film.

[0420] Reference Fig.33A , the piezoelectric sensor can be manufactured individually, and then multiple piezoelectric sensing units can be formed by cutting.

[0421] Reference Fig.33B , a backplane including a TFT driving circuit can be manufactured separately, for example, the backplane includes a substrate SUB5; a driving element disposed on the substrate SUB5; and a planarization layer PLN1 disposed on a side of the driving element away from the substrate. For example, a conductive layer CDL4 can be formed on a side of the planarization layer PLN1 away from the substrate.

[0422] Reference Fig.33C , multiple piezoelectric sensing units and chips are placed on the back plate. For example, at least two conductive parts are formed in the conductive layer CDL4, and at least two conductive parts are arranged at intervals. Two adjacent piezoelectric sensing units are placed on the same conductive part in a manner of opposite polarity. In the two piezoelectric sensing units placed on the same conductive part, the first electrode E1 of one piezoelectric sensing unit and the second electrode E2 of the other piezoelectric sensing unit are in electrical contact with the conductive layer CDL4.

[0423] Continue to refer to Fig.33C, a planarization layer PLN2 is formed on the side of the multiple piezoelectric sensing units and the chip away from the substrate, and a redistribution layer RDL2 is formed on the side of the planarization layer PLN2 away from the substrate. Multiple first traces RL2 are formed in the redistribution layer RDL2. In two piezoelectric sensing units placed on different conductive parts, the second electrode E2 of one piezoelectric sensing unit is electrically connected to the first electrode E1 of the other piezoelectric sensing unit through a first trace RL2. In this way, multiple piezoelectric sensing units can be connected in series.

[0424] The signal processing chip may include at least two terminals p1. For example, the terminals p1 may face upward, one terminal p1 may be electrically connected to a second electrode E2 of an adjacent piezoelectric sensing unit through a first trace RL2, and the other terminal p1 may be electrically connected to an extended trace in the redistribution layer RDL2.

[0425] Fig.34 is a schematic cross-sectional view of a display device integrated with a sensor according to some embodiments of the present disclosure. Fig.34 , multiple piezoelectric sensing units can be arranged in a stacked and bonded manner. For example, one piezoelectric sensing unit is placed on the above-mentioned conductive portion, with its first electrode E1 in contact with the conductive portion and its second electrode E2 facing upward; another piezoelectric sensing unit is placed on the piezoelectric sensing unit, with the first electrode E1 of the other piezoelectric sensing unit in contact with the second electrode E2 of the above-mentioned piezoelectric sensing unit. In this way, multiple piezoelectric sensing units can also be connected in series.

[0426] In this embodiment, by manufacturing the piezoelectric sensor separately, the possible incompatibility problem of production lines can be solved, and the formation of vias in the thick piezoelectric film layer is avoided, the odd-even polarization problem is solved, and the process requirements of the piezoelectric film are reduced.

[0427] In the above embodiments, the driving circuit of the TFT driving element and each chip are arranged on the same substrate, and the chip first and chip later processes are used as examples for detailed description. However, the embodiments of the present disclosure are not limited thereto. For example, the driving circuit of the TFT driving element and each chip can be manufactured on different substrates, and then the semiconductor device is formed by a cell-matching method.

[0428] FIG. 35A to FIG. 35E is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a semiconductor device (eg, a display device) according to an exemplary embodiment of the present disclosure are performed.

[0429] Reference Fig.35A , an adhesive layer AD1 is coated or pasted on the substrate SUB7.

[0430] Reference Fig.35B, each chip (such as LED chip CP3 and functional element CP4) is transferred to the substrate SUB7 through SMT or mass transfer process, and fixed on the substrate through the adhesive layer AD1.

[0431] For example, each chip may be located on the adhesive layer AD1 , and the terminal p1 of each chip may face upward, that is, be located on a side of the chip away from the substrate.

[0432] The substrate (which can be called a backplane) provided with the LED chip CP3 and the functional element CP4 is photographed, and the coordinates and areas of the terminals p1 of each LED chip CP3 and the functional element CP4 provided on the backplane are determined by image recognition technology, and a graphic file of the terminal area (i.e., the pad area) is generated. Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by a digital direct writing or a digital exposure machine according to the above-mentioned graphic file. Then, according to the patterned photoresist, the metal layer is etched to form a terminal extension layer RDL1. A plurality of extension traces RL1 are formed in the terminal extension layer RDL1, and the plurality of extension traces RL1 can be electrically connected to the terminals p1 of each LED chip CP3 and the functional element CP4, respectively, to lead out each terminal p1. That is, through the post-alignment process, an extension trace RL1 for electrically connecting each chip is formed in the terminal extension layer RDL1.

[0433] Reference Fig.35C , a planarization layer PLN1 is coated on the side of the terminal expansion layer RDL1 away from the substrate.

[0434] For example, the planarization layer PLN1 may include a resin material for filling the step difference between each LED chip CP3 and the functional element CP4 to achieve planarization.

[0435] Optionally, a passivation layer PVX2 may be prepared on the side of the planarization layer PLN1 away from the substrate. For example, the passivation layer PVX2 may include materials such as silicon nitride to isolate water vapor in the planarization layer PLN1 and prevent the water vapor in the planarization layer PLN1 from corroding the upper terminal expansion layer.

[0436] Continue to refer to Fig.35C , a via hole penetrating the planarization layer PLN1 and the passivation layer PVX2 can be formed to expose at least a portion of each extended trace RL1. Then, a metal layer is deposited on the side of the passivation layer PVX2 away from the substrate, and a redistribution layer RDL2 is formed by a patterning process including steps such as coating photoresist, exposure, development, and etching. For example, a plurality of first traces RL2 are formed in the redistribution layer RDL2. The plurality of first traces RL2 can be electrically connected to the plurality of extended traces RL1 through the above-mentioned via holes, respectively, to further lead out each terminal p1.

[0437] Optionally, refer to Fig.35C After completing the above post-alignment process, a redistribution layer RDL3 can be prepared according to the requirements of line interconnection.

[0438] For example, a cover layer PLN2 may be formed on a side of the redistribution layer RDL2 that is away from the substrate. Then, a redistribution layer RDL3 may be formed on a side of the cover layer PLN2 that is away from the substrate.

[0439] For example, the redistribution layer RDL3 may be prepared by a conventional photolithography process to form a second trace RL3 for electrically connecting various chips in the redistribution layer RDL3. The embodiments of the present disclosure are not limited thereto, and the redistribution layer RDL3 may also be prepared by a post-alignment process.

[0440] For example, according to the requirements for extended routing, fourth-layer wiring, fifth-layer wiring, etc. may also be prepared, and the embodiments of the present disclosure are not particularly limited here.

[0441] Reference Fig.35D , prepare a backplane including a TFT driving element. For example, the backplane may include a substrate SUB8; a driving element disposed on the substrate SUB8; and a plurality of terminals p2 disposed on a side of the driving element away from the substrate.

[0442] Reference Fig.35E The backplane and the substrate SUB7 on which the chip is disposed are assembled. For example, the plurality of terminals p2 on the backplane are electrically connected to the plurality of second traces RL3 in the redistribution layer RDL3, respectively, to achieve electrical connection between the driving element and the chip.

[0443] As described above, in the embodiments of the present disclosure, the chips can be arranged with a certain degree of accuracy first, and then the position, area, and morphology of the chips and terminals (i.e., pads) can be identified and analyzed through a post-alignment process, and combined with a photolithography process, high-precision automatic wiring and chip bonding can be achieved. Through the post-alignment process, the bonding accuracy of the microchip can be improved, which is beneficial to the integration of the chip with other circuits. Moreover, since the post-alignment process is provided, the requirements for the accuracy of the chip transfer process can be reduced, which is beneficial to reducing the difficulty of the chip transfer process. In addition, the automatic wiring process can simultaneously perform high-precision bonding on a large number of chips transferred in a large area, which improves the bonding efficiency and is more suitable for large-scale, large-area chip bonding.

[0444] Fig.36A A schematic diagram shows a top view of forming multiple extended traces during a post-alignment process according to some embodiments of the present disclosure. Fig.36A In the illustrated embodiment, a display device is taken as an example to illustrate a partial top view of a display substrate. Fig.36AA plurality of pixels PX are disposed on the substrate SUB9. For example, the plurality of pixels PX may include but are not limited to display pixels for realizing a display function, sensor pixels for realizing a detection function, etc. The display pixels include but are not limited to display elements such as OLED, microLED, miniLED, LCD, etc.

[0445] A plurality of chips CP are also arranged on the substrate SUB9. For example, the plurality of chips CP can be transferred to the substrate SUB9 by SMT or mass transfer process. Then, the post-alignment process can be used to form a plurality of extended traces RL1 to electrically connect the plurality of chips CP. Specifically, a substrate (which can be referred to as a backplane) on which the chip CP is arranged is photographed, and image recognition technology is used to determine the coordinates, area, morphology and other parameters of the terminal p11 of each chip CP arranged on the backplane, and a graphic file of the terminal area (i.e., pad area) is generated. For example, Fig.36A The photographing area PTA corresponding to each chip CP is schematically shown. According to the coordinates of the terminal p11 of each chip CP relative to the origin on the substrate SUB9, the coordinates of the terminal p11 of each chip CP can be determined; and the area and morphology of the terminal p11 of each chip CP can be determined by using image recognition technology.

[0446] In addition, during the process of image recognition and analysis, the visual graphics on the backplane can be judged and detected to identify the broken connections on the backplane, repair the bad points on the backplane using the metal extension routing of the post-alignment process, and screen out the chips that cannot be connected due to excessive offset after transfer. For example, image recognition technology can be used to determine the coordinate information of each bad point.

[0447] Next, a metal layer is deposited on the entire backplane, a photoresist is coated on the metal layer, and the photoresist is patterned by digital direct writing or a digital exposure machine according to the above-mentioned graphic file. Then, the metal layer is etched according to the patterned photoresist to form a terminal expansion layer RDL1. A plurality of extended traces RL1 are formed in the terminal expansion layer RDL1, and the plurality of extended traces RL1 can be electrically connected to the terminals p11 of each chip CP through vias, respectively, so as to lead out each terminal p11. That is, through the post-alignment process, an extended trace RL1 for electrically connecting each chip is formed in the terminal expansion layer RDL1.

[0448] For example, refer to Fig.36A The software can determine the automatic wiring path according to the coordinates of the terminal p11 of each chip CP and the actual transfer situation of the chip on each substrate. For example, in the process of determining the automatic wiring path, it can be considered to avoid functional areas such as display pixels, so that the wiring path is distributed in the gap area between pixels, thereby electrically connecting each chip.

[0449] For example, the photoresist can be patterned by digital direct writing or digital exposure machine according to the coordinate information of each defective point. Then, the metal layer is etched according to the patterned photoresist to form the terminal expansion layer RDL1. A plurality of extension lines RL1 are formed in the terminal expansion layer RDL1, and the plurality of extension lines RL1 can be electrically connected to each defective point through vias to repair each defective point.

[0450] Fig.39A , Fig.39B and Fig.39C The photographing areas formed in the post-alignment process are schematically shown respectively. Fig.39A , the chips on the backplane can be densely packed chips on the whole screen, for example, microLED chips in a display device. In this case, the microscope takes a position mark (MARK) on the entire backplane as the origin, takes pictures at a fixed step distance, and then moves to the next picture area. The actual number of pictures depends on the size of the backplane and the density of the chips. One or more chips can be set in a picture area. Fig.39B , the chips are not densely packed on the backplane, that is, the number of chips is small. In this case, the photographing area can be the area around the ideal position of the chip. The coverage of a photographing area can be larger than the possible offset range of the chip to ensure that the chip is in the photographing area. A calibration mark (MARK) can be made on the backplane as the origin to determine the actual coordinates of the chip after transfer. Fig.39C , a regularly arranged position calibration mark (MARK1) can be made on the backplane. The position between the position calibration mark (MARK1) in each single image and the overall absolute coordinate calibration mark (MARK0) of the backplane is relatively fixed, which is used to convert the chip position in each single image into the absolute position coordinate relative to the entire backplane. When there are multiple chips in a single shooting area and the arrangement density is large, in order to prevent the adjacent images from being completely close together due to the machine movement error and to avoid the edge image distortion problem caused by the lens imaging method of a single image, overlapping shooting areas can be made between adjacent shooting areas to ensure that the images of all chips are completely captured. Since there is a position calibration mark (MARK1) in each single image, there is no need to stitch images when performing image recognition on the chip coordinates. It is only necessary to calculate the coordinates of the chip position in the single image relative to the position calibration mark (MARK1) in the single image after image recognition, and convert the position relationship between the position calibration mark (MARK1) in the single image and the overall absolute coordinate calibration mark (MARK0) of the backplane to obtain the absolute coordinates of the chip position in the single image relative to the overall absolute coordinate calibration mark (MARK0) of the backplane.

[0451] Fig.36B and Fig.36CSchematically illustrate top views of forming multiple extended traces during a post-alignment process according to some embodiments of the present disclosure. Fig.37A and Fig.37B is along Fig.36B A cross-sectional view taken along line AA'. Fig.38 A partial enlarged view of the wiring between two chips is schematically shown.

[0452] Reference Fig.36B and Fig.38 In the embodiment of the present disclosure, a plurality of fixed connection parts 12 may be provided on the substrate SUB9. For example, at least two fixed connection parts 12 may be provided near the location of each chip CP. The extended trace for electrically connecting two chips CP may include at least a first trace segment RL11 connecting a terminal p1 of one chip with a fixed connection part 12 adjacent to the chip, a second trace segment RL12 for connecting two fixed connection parts 12 between two chips, and a third trace segment RL13 for connecting a terminal p1 of another chip with a fixed connection part 12 adjacent to the other chip.

[0453] It should be noted that, in this embodiment, for the convenience of description, the expressions such as the first routing segment, the second routing segment and the third routing segment are used. It should be understood that the first routing segment and the third routing segment are both used to electrically connect a terminal of the chip and a fixed connection part, so they can both be called the first routing segment; the second routing segment is used to electrically connect two fixed connections. That is to say, in this article, the expressions such as the first routing segment and the second routing segment can also be used to distinguish different parts of an extended routing.

[0454] For example, each chip CP may have a mark that can distinguish different pads from a picture, and the actual coordinates of each chip are calculated and determined by the image after being photographed and analyzed. The mark on the chip may include but is not limited to the morphology, shape, size, direction and other features of the pad on the chip. Optionally, special features can be made to distinguish pads of different chips.

[0455] For example, the second line segment RL12 can be fabricated on the backplane using a conventional photolithography process, and the post-alignment process only forms the first line segment RL11 and the third line segment RL13. Fig.37A , the first routing segment RL11 and the third routing segment RL13 may be located in the terminal expansion layer RDL1 , and the second routing segment RL12 is located in a layer different from the terminal expansion layer RDL1 .

[0456] For example, the first routing segment RL11, the second routing segment RL12, and the third routing segment RL13 may all be formed by a post-alignment process. Fig.37BThe first routing segment RL11, the second routing segment RL12 and the third routing segment RL13 may be located in the terminal extension layer RDL1. That is, the first routing segment RL11, the second routing segment RL12 and the third routing segment RL13 may be metal extension routings on the same layer.

[0457] For example, the spacing between the fixed connection portion 12 and the center of the ideal transfer position of the chip can be greater than the maximum offset that may occur during the chip transfer process. For example, when the maximum offset that may occur during the chip transfer process is about 10 microns, the spacing between the fixed connection portion 12 and the center of the ideal transfer position of the chip is greater than 10 microns.

[0458] It should be understood that the wiring paths between the various fixed connection parts 12 are relatively fixed. For example, for the same product, the wiring paths between the various fixed connection parts 12 can be set to be the same, that is, the wiring paths of the second routing segments RL12 are the same. In this way, when calculating and determining the wiring path, it is not necessary to calculate the wiring paths of the various second routing segments RL12, thereby reducing the complexity of automatic wiring. When determining the wiring path, the wiring path between the terminal of each chip and the fixed connection part can be accurately calculated based on the actual position of each chip after transfer, that is, the wiring path is partially updated according to the actual position of the chip, which is conducive to improving the accuracy and efficiency of automatic wiring.

[0459] Combined with reference Figure 4 , Fig.36B and Fig.36C , at least one second routing segment RL12 extends along the first direction or the second direction; and in two chips electrically connected by an extended routing including a second routing segment extending along the first direction or the second direction, a relative position of one chip in the first direction is different from a relative position of the other chip in the first direction.

[0460] For example, among two chips electrically connected by an extended line including at least one second line segment, at least one chip is tilted relative to an extension line of the second line segment RL12. Fig.36C The 4 chips shown in .

[0461] For example, in two chips electrically connected by an extended trace including at least one second trace segment, the orientation of one chip relative to the extension of the second trace segment RL12 is different from the orientation of the other chip relative to the extension of the second trace segment RL12. Fig.36B The two chips on the left are shown in FIG.

[0462] For example, in two chips electrically connected by an extended trace including at least one second trace segment, each chip includes a plurality of terminals including at least a first terminal (eg, Fig.36B , Fig.36C The left terminal of the chip shown in FIG) and the second terminal (eg Fig.36B , Fig.36C The second routing segment RL12 included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment RL12 included in the extended routing for electrically connecting the second terminals of the two chips are parallel to each other, and / or the second routing segment RL12 included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment RL12 included in the extended routing for electrically connecting the second terminals of the two chips are substantially equal in length.

[0463] For example, at least one first routing segment RL11 or RL13 has an angle with the second routing segment RL12 adjacent to and electrically connected to it, and the angle is greater than 0° and less than 180°.

[0464] For example, in two first routing segments RL11 and RL13 adjacent to and electrically connected to the same second routing segment RL12, the angle between one first routing segment RL113 and the second routing segment RL12 adjacent to and electrically connected to it is different from the angle between another first routing segment RL13 and the second routing segment RL12 adjacent to and electrically connected to it.

[0465] For example, in two first routing segments electrically connected to the first terminal and the second terminal of the same chip, the angle between one first routing segment RL11 and the second routing segment RL12 adjacent to and electrically connected to it is different from the angle between another first routing segment RL11 and the second routing segment RL12 adjacent to and electrically connected to it.

[0466] For example, the second routing segment RL12 between each fixed connection part 12 can be set as a bus shared by different products based on the common characteristics of the products, such as transfer accuracy deviation or chip connection method, or electrically connected to the enabling circuit on the chip or backplane to make it an intelligent bus with enabling function.

[0467] Combined with reference Fig.36B and Fig.36C For the same product, the actual positions of the chips may be different due to the accuracy of the transfer process. Since the fixed connection part 12 is provided, the paths of the second routing segments RL12 between the fixed connection parts 12 can be the same. When calculating the actual wiring path, only the paths of the first routing segment RL11 and the third routing segment RL13 need to be updated.

[0468] In an embodiment of the present disclosure, the semiconductor device may be a display device. The driving element of the display device may be provided in the form of a driving chip. FIG. 40A to FIG. 40CThe arrangement of the driving chip and each pixel of the display device according to the embodiment of the present disclosure is schematically shown respectively.

[0469] For example, a driver chip CP1 used as a driver element may be electrically connected to a portion corresponding to a pixel so that the driver chip CP1 may drive a plurality of pixels PX. That is, in the embodiments of the present disclosure, it is not necessary to provide a driver circuit on the backplane. For example, the plurality of pixels PX may include, but are not limited to, display pixels for realizing a display function, sensor pixels for realizing a detection function, etc. The display pixels include, but are not limited to, display elements such as OLED, microLED, miniLED, and LCD.

[0470] Reference Fig.40A , a chip CP may include at least 2 terminals p1, for example, 4 terminals p1. At least 2 pixels PX, for example, 4 pixels PX may be arranged around a chip CP. The 4 terminals p1 of a chip CP are electrically connected to the 4 pixels PX surrounding it through the extended trace RL7 respectively. For example, if the pixel PX is a display pixel, then one terminal p1 of a chip CP is electrically connected to the anode of the display pixel through the extended trace RL7, and the chip CP can supply a driving signal to the display pixel. If the pixel PX is a sensor pixel, then one terminal p1 of a chip CP is electrically connected to an electrode of the sensor pixel through the extended trace RL7, and the chip CP can receive the sensing signal from the sensor pixel and perform certain processing (such as filtering, amplification).

[0471] For example, a plurality of chips CP may be electrically connected to the master control chip CP10 via an extended line RL8.

[0472] For example, corresponding to display pixels, the chip CP may be a driver chip; corresponding to sensor pixels, the chip CP may be a power amplifier chip, and the master control chip CP10 may be an ADC chip.

[0473] In the embodiment of the present disclosure, the extended trace RL7 and the extended trace RL8 may be located in the same terminal extension layer, or the extended trace RL7 and the extended trace RL8 may be located in different terminal extension layers. For example, the extended trace RL7 and the extended trace RL8 may be formed by the above-mentioned post-alignment process.

[0474] The wiring method of each extended routing RL7 and RL8 can be determined according to the spacing between the chips. If the distance between the chips is relatively close, for example, the spacing is a spacing of multiple pixel sizes, a direct extended routing method can be adopted according to the actual coordinates of the chip. If the spacing between the chips is relatively far and the connecting path is relatively complex, a method combining fixed extended routing and flexible extended routing proposed in the above embodiment can be adopted. For example, the extended routing RL8 between the chips can adopt a fixed extended routing method, and the extended routing RL7 between the chip and the pixel can adopt a flexible extended routing method.

[0475] For example, a master control chip CP10 and a plurality of chips CP may form a chipset, and one or more such chipsets may be disposed on the backplane.

[0476] It should be noted that the corresponding relationship between the number of chips CP with driving circuits and pixels PX can be determined based on the PPI of the display device and the extended routing space that can be provided. For example, the chips CP and pixels PX can be made to correspond one-to-one, or one chip CP can correspond to all pixels PX on the backplane.

[0477] Reference Fig.40B , the pixels PX on the backplane can be different types of pixels, for example, the pixels PX can include red sub-pixels (i.e., R sub-pixels), green sub-pixels (i.e., G sub-pixels) and blue sub-pixels (i.e., B sub-pixels). In this case, one chip CP can have 6 terminals p1 (i.e., 6 interfaces). The 6 terminals p1 are electrically connected to the R / G / B sub-pixels of two pixels through the extended traces RL7.

[0478] Reference Fig.40C , the backplane can be provided with both the display pixels and the sensor pixels. In this case, a chip CP can have interfaces (i.e., terminals) with different functions such as a driving interface and a power amplifier interface. Through the above-mentioned post-alignment process, the position of the chip pad is determined after image recognition, and the chip CP is correctly connected to each pixel PX. For example, the display pixel PX can be electrically connected to the terminal p11 of the chip CP, and the sensor pixel PX can be electrically connected to the terminal p12 of the chip CP.

[0479] In an embodiment of the present disclosure, the display device may include a light-emitting element. For example, the light-emitting element may be a top-emitting light-emitting element, and the chip CP may be disposed below the light-emitting element; or the light-emitting element may be a bottom-emitting light-emitting element, and the chip CP may be disposed above the light-emitting element. Fig.41 The schematic diagram shows the projection relationship between the chip and the pixel. Fig.41, the orthographic projection of the chip CP on the substrate may partially overlap with the orthographic projections of the plurality of pixels PX on the substrate. In this way, a display device with a higher PPI may be realized.

[0480] In the embodiments of the present disclosure, a chip driving method on a smaller scale can be realized. In addition, since multiple master control chips can be provided, the master control chip can also be electrically connected to a higher-level control chip, so that each area can be controlled separately.

[0481] In an embodiment of the present disclosure, the display device may include a gate chip CP12 disposed on the backplane. For example, the gate chip CP12 may include a gate TFT or a gate-level circuit. Fig.42 4 is a schematic diagram of a gate TFT of a gate chip according to an embodiment of the present disclosure. Fig.43 is a partial plan view of a display device including a gate chip according to an embodiment of the present disclosure. Fig.44A and Fig.44B They are circuit connection diagrams of a display device including a gating chip according to embodiments of the present disclosure.

[0482] Combined with reference Figures 42 to 44B , the display device may include a gating chip CP12, a chip CP and a master control chip CP10. One of the gating chips CP12 may include at least 2 ports (for example, 4 ports MUX1 / MUX2 / MUX3 / MUX4), and one of the chips CP may include at least 2 terminals p1 (for example, 4 terminals p1). Multiple pixels PX located in the same row may be electrically connected through a row signal connection line L1, and multiple pixels PX located in the same column may be electrically connected through a column signal connection line L2. Multiple ports MUX1 to MUX4 of a gating chip CP12 may be electrically connected to multiple row signal connection lines L1 through an extended line RL13, respectively. A terminal p1 of a chip CP may be electrically connected to multiple pixels in the same column through multiple gating TFTs, respectively. The gating chip CP12 and multiple chips CP may also be electrically connected to the master control chip CP10 through an extended line RL14. For example, multiple gating chips, at least one master control chip and multiple chips may form a chipset, and multiple such chipsets may be provided on the backplane.

[0483] For example, under the control of a row selection signal sent by a port of the selection chip CP12, the pixels of a certain row can be controlled to be turned on. Under the control of a column selection signal, the corresponding chip CP can be controlled to send a driving signal to the pixels of a certain column. In this way, the pixels on the backplane can be displayed and controlled separately in different areas under the control of the selection signal.

[0484] Similarly, for example, the pixel PX may include but is not limited to display pixels for realizing a display function, sensor pixels for realizing a detection function, etc. The display pixel includes but is not limited to display elements such as OLED, microLED, miniLED, LCD, etc.

[0485] For example, corresponding to display pixels, the chip CP may be a driver chip; corresponding to sensor pixels, the chip CP may be a power amplifier chip, and the master control chip CP10 may be an ADC chip.

[0486] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figure.

[0487] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0488] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; A plurality of chips disposed on the substrate, each chip comprising a chip body and a plurality of terminals disposed on the chip body; A plurality of fixed connection parts disposed on the substrate; A terminal expansion layer is provided on the substrate, wherein the terminal expansion layer comprises a conductive material, Wherein, the plurality of fixed connection parts are respectively arranged adjacent to the plurality of chips; The semiconductor device further comprises a plurality of extension traces located in the terminal extension layer, the extension traces being used to electrically connect the plurality of chips; and The extended routing line for electrically connecting two chips includes at least a first routing segment and a second routing segment, wherein the first routing segment is used to electrically connect a terminal of a chip with a fixed connection portion adjacent to the chip, and the second routing segment is used to connect two fixed connection portions between the two chips, and the path of the second routing segment is fixed.

2. The semiconductor device according to claim 1, wherein: At least one second routing segment extends along the first direction; and Of the two chips electrically connected by the extended routing line including the second routing line segment extending along the first direction, a relative position of one chip in the first direction is different from a relative position of the other chip in the first direction.

3. The semiconductor device according to claim 1 or 2, characterized in that: Among the two chips electrically connected through the extended routing line including at least one second routing line segment, at least one chip is inclined with respect to an extended line of the second routing line segment.

4. The semiconductor device according to claim 3, wherein: In two chips electrically connected by an extended routing line including at least one second routing line segment, an orientation of one chip relative to an extension line of the second routing line segment is different from an orientation of another chip relative to the extension line of the second routing line segment.

5. The semiconductor device according to claim 1, 2 or 4, characterized in that: In two chips electrically connected by an extended trace including at least one second trace segment, the plurality of terminals included in each chip include at least a first terminal and a second terminal; The second routing segment included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment included in the extended routing for electrically connecting the second terminals of the two chips are parallel to each other, and / or the second routing segment included in the extended routing for electrically connecting the first terminals of the two chips and the second routing segment included in the extended routing for electrically connecting the second terminals of the two chips are substantially equal in length.

6. The semiconductor device according to claim 1, 2 or 4, characterized in that: An included angle is formed between at least one first routing segment and a second routing segment adjacent to and electrically connected to the first routing segment, and the included angle is greater than 0° and less than 180°.

7. The semiconductor device according to claim 6, wherein: Among two first routing segments adjacent to and electrically connected to the same second routing segment, an angle between one first routing segment and the second routing segment adjacent to and electrically connected thereto is different from an angle between another first routing segment and the second routing segment adjacent to and electrically connected thereto.

8. The semiconductor device according to claim 6, wherein: In two first routing segments electrically connected to the first terminal and the second terminal of the same chip, the angle between one first routing segment and the second routing segment adjacent and electrically connected thereto is different from the angle between the other first routing segment and the second routing segment adjacent and electrically connected thereto.

9. The semiconductor device according to claim 1, 2 or 4, characterized in that: A plurality of the first routing segments are located in the same layer; and The second routing segment and the first routing segment are located in the same layer or in a different layer.

10. The semiconductor device according to claim 1, wherein: The plurality of chips are arranged in an array along a first direction and a second direction; and At least one first routing segment is inclined relative to the first direction and the second direction.

11. The semiconductor device according to claim 10, wherein: The second routing segment extends along the first direction or the second direction.

12. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Placing a plurality of chips on a substrate, wherein each chip comprises a chip body and a plurality of terminals disposed on the chip body; forming a plurality of fixed connection parts on the substrate; and A terminal expansion layer is formed on a side of the plurality of chips away from the substrate through a post-alignment process, wherein the terminal expansion layer comprises a conductive material. Wherein, forming a terminal expansion layer on a side of the plurality of chips away from the substrate through a post-alignment process comprises: Taking a photo of the substrate provided with the plurality of chips and the plurality of fixed connection parts; The coordinates of the terminals of each chip are determined by using image recognition technology to generate a graphic file of the terminals; forming a conductive material layer on a side of the plurality of chips away from the substrate; and According to the graphic file, the conductive material layer is etched by a photolithography process to form a plurality of extended traces in the terminal extension layer, Among them, the extended routing is used to electrically connect the multiple chips, and the extended routing used to electrically connect two chips includes at least a first routing segment and a second routing segment, the first routing segment is used to electrically connect a terminal of a chip with a fixed connection part adjacent to the chip, and the second routing segment is used to connect two fixed connection parts between the two chips, and the path of the second routing segment is fixed.

13. The manufacturing method according to claim 12, characterized in that: The step of generating a graphic file of a terminal comprises: Use image recognition technology to determine the coordinates of the terminals of each chip; Reading preset coordinates of each fixed connection part; and A graphic file of the terminal is generated according to the determined coordinates of the terminal of each chip and the read preset coordinates of each fixed connection portion.

14. The manufacturing method according to claim 12 or 13, characterized in that: The photographing of the substrate provided with the plurality of chips and the plurality of fixed connection parts comprises: Taking a picture of a first photographing area of ​​the substrate where the plurality of chips and the plurality of fixed connection parts are disposed; and Taking an integral absolute coordinate calibration mark disposed on the substrate as the origin, the photographing device is translated at a fixed stepping distance to photograph a second photographing area of ​​the substrate where the plurality of chips and the plurality of fixed connecting parts are disposed, The number of photographing times is related to the distribution density of the chips, and at least one chip is arranged in each photographing area.

15. The manufacturing method according to claim 14, characterized in that: There is an overlapping photographing area between at least two photographing areas.

16. The manufacturing method according to claim 14, characterized in that: The manufacturing method further comprises: forming an overall absolute coordinate calibration mark and a plurality of position calibration marks on the substrate, Wherein, the multiple position calibration marks correspond one-to-one to the multiple photographing areas respectively.

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