Wiring structure between chips and wiring method between chips

Abstract

The present invention provides a wiring structure between chips and a wiring method between chips. The wiring structure between chips includes a wiring layer located on a substrate, and a plurality of wiring paths are embedded in the wiring layer. In addition, a first chip and a second chip are located on the wiring layer and are connected through the wiring paths. The gap between the first chip and the second chip is along a first direction, and the interface edges of the first chip and the second chip extend along a second direction perpendicular to the first direction. Each wiring path includes parallel first straight portions to connect to the interface edges. The first straight portions have an inclination angle other than 0° and 90° with respect to the first direction.

Description

Technical Field

[0001] The present invention relates to an interface between two integrated circuit (IC) chips for data communication, and particularly to a wiring structure between integrated circuit chips and a wiring method between chips. Background Art

[0002] Digital electronic devices based on semiconductor integrated circuits, such as mobile phones, digital cameras, personal digital assistants (PDAs), etc., are designed to have more powerful functionality to adapt to various applications in the modern digital world. However, with the trend of semiconductor manufacturing, digital electronic devices are intended to be smaller and lighter while having improved functionality and higher performance. Semiconductor devices can be packaged as 2.5D semiconductor devices, in which several circuit chips can be integrated into a larger integrated circuit, and connectors, interposers, or redistribution layers (RDLs) are commonly used to connect between chips.

[0003] Proposed integrated fan-out (InFO) and chip-on-wafer-on-substrate (CoWoS) packaging technologies are commonly used to package multiple chips assembled side by side.

[0004] In one example, in an entire electronic circuit, a main circuit fabricated as a master die may need to be connected to multiple slave dies. Based on the conditions of the packaging technology, the gap between chips is fixed. The wiring structure between chips needs to be set within the gap. In other words, under the requirements of packaging, the gap has maximum and minimum limitations. An overly large gap may result in a large packaging volume, which is generally not desired. An overly small gap may lead to a small packaging volume but is difficult to manufacture.

[0005] Due to the limited size of the gap, the number of paths of the wiring structure may be limited. Here, each path is used to connect two contact components, which are, for example, pads of two chips to be connected. The wiring structure usually formed in the physical layer of the chip often acts as an interface bus, and the number of its paths often corresponds to the size of the interface bus. The wiring structure is often fabricated in an interposer or a redistribution layer. The chips to be connected are disposed on the interposer or the redistribution layer. The wiring structure connects the contact components between the chips and acts as an interface bus. When the chips are designed to have more functions, the number of paths of the wiring structure will increase significantly to transmit more information through the interface bus.

[0006] Since the gap between chips is limited by packaging technology, the number of paths may also be limited by an inappropriate wiring structure. How to design the wiring structure to increase the size of the interface bus remains an issue to be improved. Summary of the Invention

[0007] The present invention is directed to a wiring structure between chips, and the number of wiring paths thereof is less limited by the gap between chips.

[0008] The present invention is directed to a wiring method between chips, enabling the wiring paths to be less limited by the gap between chips.

[0009] According to an embodiment of the present invention, the wiring structure between chips includes a wiring layer, a first chip, and a second chip. The wiring layer is located on a substrate, and a plurality of wiring paths are embedded in the wiring layer. The first chip and the second chip are located on the wiring layer and are connected by a plurality of wiring paths. The gap between the first chip and the second chip is along a first direction, and the interface edges of the first chip and the second chip extend along a second direction perpendicular to the first direction. Each wiring path is connected between the interface edge of the first chip and the interface edge of the second chip, and each wiring path sequentially includes a first straight portion, a second straight portion, and a third straight portion. Each wiring path has the same line width and line length. The first straight portion and the third straight portion extend along the first direction. Each second straight portion has a first inclination angle other than 0° and 90° with respect to the first direction. The joining interfaces of the first straight portion and the second straight portion and the joining interfaces of the second straight portion and the third straight portion have an angle with the second direction to maintain the same line width.

[0010] According to an embodiment of the present invention, the wiring method between chips includes the following steps: disposing a wiring layer on a substrate, wherein a plurality of wiring paths are embedded in the wiring layer; and disposing a first chip and a second chip on the wiring layer, the first chip and the second chip being connected by a plurality of wiring paths. The gap between the first chip and the second chip is along a first direction, and the interface edges of the first chip and the second chip extend along a second direction perpendicular to the first direction. Each wiring path is connected between the interface edge of the first chip and the interface edge of the second chip, and each wiring path sequentially includes a first straight portion, a second straight portion, and a third straight portion, and has the same line width and line length, wherein the first straight portion and the third straight portion extend along the first direction. Each second straight portion has a first inclination angle other than 0° and 90° with respect to the first direction. The joining interfaces of the first straight portion and the second straight portion and the joining interfaces of the second straight portion and the third straight portion have an angle with the second direction to maintain the same line width.

[0011] Based on the above, the wiring method between chips of the present invention can enable a more free layout of the connections between chips and make the wiring path less restricted by the gap between chips. In addition, the wiring structure between chips of the present invention has a slanted wiring path with an appropriate tilt angle, so the number of wiring paths is less restricted by the gap between chips.

[0012] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and detailed descriptions are made in conjunction with the accompanying drawings as follows. Description of the Drawings

[0013] Figure 1 is a schematic cross-sectional view of a 2.5D semiconductor device stack structure with an interface according to an embodiment of the present invention;

[0014] Figure 2 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0015] Figure 3 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0016] Figure 4 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0017] Figure 5 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0018] Figure 6 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0019] Figure 7 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0020] Figure 8 is a schematic diagram of the joining mechanism of two straight-line portions in a wiring structure according to an embodiment of the present invention;

[0021] Figure 9 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention;

[0022] Figure 10 is a schematic diagram of a wiring structure between two groups of chips according to an embodiment of the present invention;

[0023] Figure 11 is a schematic diagram of the improvement effect of the wiring structure between chips according to an embodiment of the present invention.

[0024] Description of the Reference Numerals

[0025] 50: Platform

[0026] 100: Encapsulation substrate

[0027] 102: Through-hole

[0028] 104: Bottom solder ball

[0029] 106: Top contact assembly

[0030] 110: Trace layer

[0031] 112: Through-silicon via

[0032] 114: Interconnect wiring

[0033] 116: Contact assembly

[0034] 120: Memory chip

[0035] 130: Processing chip

[0036] 140, 170, 170A: Wiring structure

[0037] 142, 172: Gap

[0038] 144, 174: Displacement

[0039] 150, 160, 180: Chip

[0040] 152, 162, 182, 182a, 182b, 182c: Interface edge

[0041] 300: First straight part

[0042] 302, 402, 502: Line pitch

[0043] 304, 404, 504: Line width

[0044] 350, 450, 1350, 1450: Bonding interface

[0045] 400: Third straight part

[0046] 500: Second straight part

[0047] 600: Circuit area

[0048] 602: Functional area

[0049] 1500: Spacing

[0050] X, Y: Direction

[0051] θ: Included angle Detailed implementation manners

[0052] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0053] The present invention relates to an interface between two integrated circuit (IC) chips for data communication. Depending on the packaging process adopted, the contact components of the two chips are correspondingly connected through a connection interface such as an interposer or a redistribution layer (RDL). The wiring structure is embedded in the interposer or the redistribution layer. The contact components are, for example, pads or bumps, but the present invention is not limited thereto.

[0054] Several embodiments are provided below to describe the present invention, but the present invention is not limited to the described embodiments.

[0055] The entire integrated circuit can be manufactured as a semiconductor device through a semiconductor process, and the semiconductor device can be manufactured based on a stacked structure of 2.5D semiconductor devices. In one embodiment, the interface on the chip for receiving data may include a frame decoding circuit associated with a de-serialized circuit. In one embodiment, the interface in the semiconductor structure is integrated into the circuit of the entire chip. The chips communicating with each other are, for example, a main chip with processing circuitry and a slave chip with a storage chip. In other words, the type of chip is not limited to a specific type. However, the communication between the chips is through an interface with a wiring structure, and the wiring structure includes a plurality of wiring paths.

[0056] First, the manufacture of a general semiconductor will be described. Figure 1 is a cross-sectional schematic view of a stacked structure of 2.5D semiconductor devices with an interface according to an embodiment of the present invention. Refer to Figure 1, a CoWoS or InFO platform 50 with an expected IC structure is formed based on 2.5D packaging technology. The CoWoS or InFO platform 50 may include a packaging substrate 100 having bottom solder balls 104 and top contact components 106. Through-holes 102 may be used to connect from the bottom solder balls 104 to the top contact components 106. In addition, a wiring layer 110 may be further formed on the substrate 100. The wiring layer 110 is, for example, an interposer or a redistribution layer connected to the contact component 106. A wiring structure 140 having a wiring path is embedded in the wiring layer 110 for connection purposes. The wiring layer 110 may include through-silicon vias (TSVs) 112, interconnect wirings 114, and contact components 116. Here, depending on the process adopted, the contact component 116 may be a through-hole or a contact component or any suitable connection structure for terminal-to-terminal contact. The present invention does not limit the contact component 116 to a specific type.

[0057] In practical applications, additional chips (for example: processing chip 130 and storage chip 120 or other suitable chips, the present invention is not limited thereto) may also be implemented on the CoWoS or InFO platform 50. The processing chip 130 and the storage chip 120 are connected through the wiring structure 140 embedded in the wiring layer 110.

[0058] The wiring structure 140 may have various wiring methods. The present invention studies conventional wiring structures and further provides improved wiring structures to accommodate more wiring paths in the gaps between chips under the limitations of the packaging process.

[0059] Figure 2 is a schematic diagram of the wiring structure between chips according to an embodiment of the present invention. Refer to Figure 2 , chip 150 and chip 160 are connected via the wiring structure 140. Due to the packaging process, the gap 142 in the X direction is fixed. However, the displacement 144 in the Y direction between chip 150 and chip 160 is adjustable. Chip 150 has an interface edge 152, which is a part of the physical layer of chip 150. The interface edge 152 includes a plurality of contact components, and the plurality of contact components form a pad pattern for external connection. Similarly, chip 160 has an interface edge 162, which is a part of the physical layer of chip 160. The interface edge 152 and the interface edge 162 are connected through the wiring structure 140, and the interface edge 152 and the interface edge 162 include the same number of contact components, serving as a parallel bus for communication between chip 150 and chip 160.

[0060] Each wiring path in the wiring structure 140 may include three parts in a direct manner. The middle part extends along the Y direction in the gap 142. Both ends of the middle part are connected to the parts extending along the X direction. Under the limitation of the encapsulation process for the gap 142, the displacement 144 can be set relatively freely. In this embodiment, the size of the gap 142 is fixed. Since the gap between the middle parts of the wiring paths is also limited by the encapsulation process, the gap 142 cannot accommodate a large number of wiring paths without limit. Thus, the number of wiring paths in the wiring structure 140 is also limited.

[0061] Figure 3 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention. Refer to Figure 3 In another direct design of the wiring structure 140, the wiring paths are arranged to be inclined at 45° with respect to the X direction. The length of the wiring paths may be shorter, but the gap 142 and the displacement 144 have the same width. In this embodiment, the displacement 144 is fixed.

[0062] Figure 4 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention. Refer to Figure 4 In the wiring structure 170, the wiring paths may include wiring paths parallel to each other and the wiring paths are inclined at any angle other than 0° and 90° with respect to the X direction. The inclination angle of the wiring paths in the wiring structure 170 with respect to the X direction is not particularly limited. In this embodiment, as shown by the arrow in Figure 4 , in this way, the chip 160 can move closer to the chip 150 in the X direction. The original gap 142 can be reduced to the gap 172. In this embodiment, the inclination angle of the wiring paths in the wiring structure 170 with respect to the X direction is greater than 45°. In other words, the position of the chip 180 having the interface edge 182 on the substrate can be adjusted relatively freely in the X direction without being limited by the gap 142.

[0063] In one embodiment, the chip 150 may be the main chip, which is set at a fixed position, and the chip 180 is the slave chip, which is set around the chip 150. The position of the chip 180 can be adjusted more flexibly, but the present invention is not limited thereto. The chip 150 can also move within an allowable range.

[0064] Figure 5 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention. Refer to Figure 5 Compared with Figure 3 , the original displacement 144 in the Y direction can be adjusted to the displacement 174 according to the position of the chip 180.

[0065] As in the foregoing embodiments, the routing path of the wiring structure 170 has an inclination angle with respect to the X direction greater than 45°. In one embodiment, the inclination angle of the routing path of the wiring structure 170 may be less than 45°. For example, the inclination angle may be between 10° and 80°, so that the chip 180 can be located at a suitable position less restricted by the X direction and / or the Y direction.

[0066] Figure 6 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention. Referring to Figure 6 , the routing path of the wiring structure 170 may further include a portion 170A according to actual requirements, which extends along the X direction from the interface edge 152 of the chip 150. In addition, the portion 170A may also be provided on the chip 180; or, provided on both the chip 150 and the chip 180 at the same time.

[0067] As pointed out, signals are transmitted in parallel through the wiring structure 170. In order to prevent the signal transmission quality from being affected by the deviation caused by the line effects of the wiring structure (such as line length or RC resonance between lines), the line length, line width, and wire pitch need to be further considered.

[0068] Figure 7 is a schematic diagram of a wiring structure between chips according to an embodiment of the present invention. Referring to Figure 7 , the present invention explores some line effects. A routing path may sequentially include a first straight portion 300, a second straight portion 500, and a third straight portion 400. In one embodiment, the first straight portion 300 may involve the interface edge of one chip, and the third straight portion 400 may involve the interface edge of another chip, but it is part of the entire routing path.

[0069] The first straight portion 300 may have a single wire pitch 302 and a line width 304. Similarly, like the first straight portion 300, the third straight portion 400 may have a single wire pitch 402 and a line width 404. Here, the joining interface 350 between the first straight portion 300 and the second straight portion 500 generally extends along the Y direction. The joining interface 450 between the third straight portion 400 and the second straight portion 500 also generally extends along the Y direction. If the second straight portion 500 with an inclination angle is connected to the first straight portion 300 and the third straight portion 400, the wire pitch 502 and the line width 504 of the second straight portion 500 will be reduced.

[0070] The above Figure 7 situation may affect the quality of the transmitted signal. It is desirable to maintain the same line width and wire pitch of the routing path. To have this feature, the joining interfaces 350 and 450 need to be adjusted.

[0071] Figure 8 is a schematic diagram of the joining mechanism of two straight portions in a wiring structure according to an embodiment of the present invention. Referring to Figure 8 , taking the joining interface 1350 between the first straight portion 300 and the second straight portion 500 as an example, the included angle between the first straight portion 300 and the second straight portion 500 is θ, and the joining interface 1350 is disposed on the center line of the included angle θ (which can be referred to as: Angle bisector). In this way, the first straight portion 300 and the second straight portion 500 can have the same line width.

[0072] Figure 8 The mechanism of Figure 7 can be applied to Figure 9 is a schematic diagram of the wiring structure between chips according to an embodiment of the present invention.

[0073] Referring to Figure 9 , the entire wiring path can sequentially include a first straight portion 300, a second straight portion 500, and a third straight portion 400 from one chip to another chip. In one embodiment, the first straight portion 300 and the third straight portion 400 can be implemented at the interface edge of the chip, but the present invention is not limited thereto. In one embodiment, the first straight portion 300, the second straight portion 500, and the third straight portion 400 can be implemented in an interposer.

[0074] Regarding the wiring path in the line region 600, the joining interface 1350 between the first straight portion 300 and the second straight portion 500 can be set according to the Figure 8 mechanism, and the joining interface 1450 between the third straight portion 400 and the second straight portion 500 can also be set by the same mechanism. Therefore, the line width 304, the line width 504, and the line width 404 are all the same, and the line pitch 302, the line pitch 502, and the line pitch 402 are also all the same.

[0075] In one embodiment, in order to make the wiring paths have the same length, the lengths of the second straight portions 500 can be set to be the same. Based on the same mechanism, the length of the third straight portion 400 gradually decreases relative to the Y direction. The parallel second straight portions 500 can have the same length and / or line pitch 502. However, the length of the first straight portion 300 of the wiring path can gradually increase in the Y direction. On the contrary, the length of the third straight portion 400 can gradually decrease in the Y direction. Since the gap between the chips is limited in the X direction, the length of a third straight portion 400 may be reduced to zero, and a certain number of designs of the third straight portion 400 can be achieved. Then, another line region 600 can be set by the same mechanism.

[0076] In other words, the wiring path can be divided into two groups corresponding to the two line regions 600. In order to make the line pitch of the two line regions 600 the same, the pitch 1500 can be appropriately set according to the geometric conditions of the wiring path with an inclination angle. In one embodiment, in order to make the line pitch between the last wiring path of one line region 600 and the first wiring path of the next line region 600 the same, the pitch 1500 is set to the difference between the line pitch 502 and the line width 504. In this way, the functional region 602 at the interface edge can be set between the two line regions 600. The functional region 602 can include, for example, power pads and / or ground pads, but does not include the digital signals transmitted in the line region 600.

[0077] In one embodiment, the length of the first straight portion 300 can allow appropriate displacement in different line regions to obtain the desired pitch 1500. In other words, this geometric parameter can be adjusted depending on the inclination angle of the second straight portion 500 so that the line width can be maintained the same, and the line pitch of each line region can also be maintained the same. In addition, the pitch 1500 is set so that the line pitch between the two line regions 600 is also the same.

[0078] In one embodiment, taking the transmission of 8-bit data as an example, 4 bits are set as one regional line 600, and the power / ground pads are arranged in the functional region 602 between the two line regions 600. Therefore, the signal quality of this 8-bit data can be relatively consistent.

[0079] In the overall circuit, for the general application of the wiring structure 170, a group of chips 150 and a group of chips 180 can be connected and arranged on the wiring layer 110. Figure 10 It is a schematic diagram of the wiring structure between two groups of chips according to an embodiment of the present invention.

[0080] Refer to Figure 10 , a group of chips 150 is to be connected to the chip 180. The chip 180 has a plurality of interface edges 182a, 182b, and 182c. Each chip 150 includes an interface edge 152 as described above. In one embodiment, the chip 180 can be the main chip, which has a fixed position. However, the interface edges 182a, 182b, and 182c can be appropriately adjusted in the Y direction according to the packaging process. The wiring structure 170 with the inclined wiring path as described above can connect the chip 150 and the chip 180. In this embodiment, the interface edge 182a and the interface edge 182c can be appropriately displaced along the Y direction, for example, but the present invention is not limited thereto. In one embodiment, the interface edges 182a, 182b, and 182c can belong to different chips.

[0081] The interface edge of the semiconductor structure includes, for example, contact components arranged in the pad pattern. When the capabilities of the chip increase, the number of contact components corresponding to the wiring path components can also be freely increased according to the increase in the communication bus.

[0082] Figure 11 It is a schematic diagram of the improvement effect of the wiring structure between chips according to an embodiment of the present invention. Referring to Figure 8 , based on Figure 4 or Figure 9 's mechanism, the interface edge 182 can be adjusted to be closer to the periphery of the chip 180.

[0083] In the previous description, the wiring structure 170 with an inclined portion can be adapted to the connection between the interface edges of the chips. Due to the 2.5D packaging process, the peripheries of the chips 150 and 180 may be fixed, but the positions of the interface edges 152 and 182 can be adjusted. The number of wiring paths of the wiring structure is not limited by the gap 142 in the X direction.

[0084] The present invention also provides a method for arranging the wiring structure between chips. This method includes setting a wiring layer on a substrate, wherein a plurality of wiring paths are embedded in the wiring layer, and setting a first chip and a second chip on the wiring layer. The first chip and the second chip are connected through a plurality of wiring paths. The gap between the first chip and the second chip is along a first direction (e.g., the X direction), and the interface edges of the first chip and the second chip extend along a second direction (e.g., the Y direction) perpendicular to the first direction. Each wiring path includes parallel first straight portions to connect to the interface edges. The first straight portions have an inclination angle other than 0° and 90° with respect to the first direction.

[0085] The wiring structure between chips has inclined wiring paths with appropriate inclination angles, which can make the connection between chips have a more free arrangement. And the number of wiring paths is less restricted by the gap 142 in the X direction.

[0086] In summary, the wiring method between chips of the present invention can make the connection between chips have a more free arrangement and make the wiring paths less restricted by the gap between chips.

[0087] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wiring structure between chips, characterized in that, Comprising: A wiring layer located on a substrate, in which a plurality of wiring paths are embedded; And A first chip and a second chip located on the wiring layer and connected through the plurality of wiring paths, Wherein the gap between the first chip and the second chip is along a first direction, and the interface edges of the first chip and the second chip extend along a second direction perpendicular to the first direction, Wherein each of the plurality of wiring paths is connected between the interface edge of the first chip and the interface edge of the second chip, and each of the plurality of wiring paths sequentially includes a first straight portion, a second straight portion and a third straight portion, and each of the plurality of wiring paths has the same line width and line length, wherein the first straight portion and the third straight portion extend along the first direction, Wherein each of the second straight portions has a first inclination angle other than 0° and 90° with respect to the first direction, Wherein there is an included angle between the joining interface of the first straight portion and the second straight portion and the joining interface of the second straight portion and the third straight portion and the second direction, so as to maintain the same line width.

2. The wiring structure according to claim 1, characterized in that, Each joining interface of the first straight portion and the second straight portion is located on the center line of the angle formed between the first straight portion and the second straight portion, and each joining interface of the second straight portion and the third straight portion is located on the center line of the angle formed between the second straight portion and the third straight portion.

3. The wiring structure according to claim 1, characterized in that, The line pitch between two adjacent ones of the plurality of wiring paths is the same.

4. The wiring structure according to claim 1, characterized in that, The lengths of the second straight portions are the same.

5. The wiring structure according to claim 4, characterized in that, When the length of the first straight portion gradually increases in the second direction, the length of the third straight portion relatively gradually decreases in the second direction; when the length of the first straight portion gradually decreases in the second direction, the length of the third straight portion relatively gradually increases in the second direction.

6. The wiring structure according to claim 5, characterized in that, When the length of the first straight portion increases to a limit length, the next first straight portion is reduced to a certain length.

7. The wiring structure according to claim 1, characterized in that, The plurality of wiring paths are divided into a first group and a second group, The interface edge of the first chip and the interface edge of the second chip are each divided into two wiring regions corresponding to the first group and the second group, and The interface edge of the first chip and the interface edge of the second chip each include a functional region not connected to the wiring paths.

8. The wiring structure according to claim 7, characterized in that, The functional region includes a power supply and / or a ground region.

9. The wiring structure according to claim 7, characterized in that, The lengths of the second straight portions are the same. When the lengths of the first straight portions of the first group and the second group gradually increase in the second direction, the lengths of the third straight portions of the first group and the second group relatively gradually decrease in the second direction; when the lengths of the first straight portions of the first group and the second group gradually decrease in the second direction, the lengths of the third straight portions of the first group and the second group relatively gradually increase in the second direction.

10. The wiring structure according to claim 9, characterized in that, The length of the first straight-line portion of the first group is increased to a limit length, and the length of the first straight-line portion of the second group increases from small to large.

11. The wiring structure according to claim 10, characterized in that, The length of the first straight-line portion of the initial second group is a preset length, which is the same as the line pitch of the first straight-line portion of the last first group.

12. A wiring method between chips, characterized in that, Comprising: A wiring layer is disposed on a substrate, and a plurality of wiring paths are embedded in the wiring layer; And A first chip and a second chip are disposed on the wiring layer, and the first chip and the second chip are connected through the plurality of wiring paths, wherein the gap between the first chip and the second chip is along a first direction, and the interface edges of the first chip and the second chip extend along a second direction perpendicular to the first direction, wherein each of the plurality of wiring paths is between the interface edge of the first chip and the interface edge of the second chip, and each of the plurality of wiring paths sequentially includes a first straight-line portion, a second straight-line portion, and a third straight-line portion, and each of the plurality of wiring paths has the same line width and line length, wherein the first straight-line portion and the third straight-line portion extend along the first direction, wherein each of the second straight-line portions has a first inclination angle other than 0° and 90° with respect to the first direction, wherein there is an included angle between the joining interface of the first straight-line portion and the second straight-line portion and the joining interface of the second straight-line portion and the third straight-line portion and the second direction, so as to maintain the same line width.

13. The wiring method according to claim 12, wherein The joining interface of each of the first straight-line portions and the second straight-line portions is located on the center line of the angle formed between the first straight-line portion and the second straight-line portion, and the joining interface of each of the second straight-line portions and the third straight-line portions is located on the center line of the angle formed between the second straight-line portion and the third straight-line portion.

14. The wiring method according to claim 12, wherein The line pitch between two adjacent ones of the wiring paths is the same.

15. The wiring method according to claim 12, wherein The lengths of the second straight-line portions are the same.

16. The wiring method according to claim 15, wherein When the length of the first straight-line portion gradually increases in the second direction, the length of the third straight-line portion gradually decreases conversely in the second direction; when the length of the first straight-line portion gradually decreases in the second direction, the length of the third straight-line portion gradually increases conversely in the second direction.

17. The wiring method according to claim 16, wherein When the length of the first straight-line portion increases to a limit length, the next first straight-line portion is reduced to a certain length.

18. The wiring method according to claim 12, wherein The plurality of wiring paths are divided into a first group and a second group, the interface edges of the first chip and the second chip are each divided into two wiring regions corresponding to the first group and the second group, and the interface edges of the first chip and the second chip each include a functional region not connected to the wiring paths.

19. The wiring method according to claim 18, wherein The functional region includes a power supply and / or a ground region.

20. The wiring method according to claim 18, wherein The lengths of the second straight portions are the same. When the lengths of the first straight portions of the first group and the second group gradually increase in the second direction, the lengths of the third straight portions of the first group and the second group gradually decrease relatively in the second direction; when the lengths of the first straight portions of the first group and the second group gradually decrease in the second direction, the lengths of the third straight portions of the first group and the second group gradually increase relatively in the second direction.

21. The wiring method according to claim 20, wherein The length of the first straight portion of the first group increases to a limit length, and the length of the first straight portion of the second group increases from small to large.

22. The wiring method according to claim 21, wherein The length of the first straight portion of the starting second group is a preset length, which is the same as the line distance of the first straight portion of the last first group.

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