Level shifting circuit

Abstract

The application discloses a level conversion circuit which is composed of NMOS tubes, PMOS tubes and an inverter, and comprises an input end and two differential output ends; the NMOS tubes comprise six NMOS tubes of NM0-NM5; the PMOS tubes comprise eight PMOS tubes of PM0-PM7; the level conversion circuit has lower power consumption in various working states by forming a new circuit through high-voltage NMOS and PMOS.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit design, and in particular to a level conversion circuit. Background Technology

[0002] When designing circuits, level mismatches often occur, and the most common solution is to add a level conversion chip.

[0003] As a widely used circuit, traditional level conversion circuits have a high combined overhead of delay and energy during the level conversion process, such as... Figure 1 As shown, a high-performance level shifting circuit with low overall overhead is proposed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a level conversion circuit with low overall overhead.

[0005] To solve the above problems, the present invention provides a level conversion circuit, which is composed of an NMOS transistor, a PMOS transistor and an inverter, and includes an input terminal and two differential output terminals.

[0006] The NMOS transistors comprise 6 NMOS transistors, NM0 to NM5, and the PMOS transistors comprise 8 PMOS transistors, PM0 to PM7.

[0007] The input terminal is the input interface of the entire level conversion circuit. The input terminal is connected to the gate of NM4 and the input terminal of the inverter. The input terminal is also connected to the gate of PM2. The output terminal of the inverter is connected to the gate of NM5 and the gate of PM3. The inverter inverts the signal input to the input terminal and enters the next stage circuit, finally forming the second output terminal in the differential output terminal.

[0008] In the PMOS transistor, the source and drain of PM2, PM4, and PM6 are connected in series. The drain of PM6 is connected to the drain of NM2, and the source of NM2 is connected to the drain of NM4. The source of NM4 is grounded.

[0009] The sources of PM0, PM1, PM2, and PM3 are connected to the power supply VDDH. The gate of PM0 is connected to the gate of NM2 and to the series node of PM6. The drain of PM0 is connected to the drain of NM0, and the source of NM0 is grounded.

[0010] The node connected in series with PM0 and NM0 is the first output terminal OUT of the level conversion circuit.

[0011] PM3 is connected in series with PM5, PM7, NM3, and NM5, with the source of NM5 grounded.

[0012] The connection nodes of PM6 and NM2 are simultaneously connected to the gate of PM5, and the connection nodes of PM7 and NM3 are simultaneously connected to the gate of PM4; the connection nodes of NM2 and NM4 are simultaneously connected to the gates of NM0 and PM6, and the connection nodes of NM3 and NM5 are simultaneously connected to the gates of PM7 and NM1.

[0013] The connection nodes of PM5 and PM7 are simultaneously connected to the gates of PM1 and NM3. The drain and source of PM1 and NM1 are connected in series, and their connection node forms the second output terminal OUTN of the level conversion circuit. The source of NM1 is grounded.

[0014] Furthermore, the inverter is also connected to a power supply VDD, the voltage of which is lower than VDDH.

[0015] Furthermore, the MOSFETs NM0 to NM5 and PM0 to PM7 are all high-voltage MOSFETs.

[0016] Furthermore, when the input signal is low, the first output of the level conversion circuit outputs a high level.

[0017] Furthermore, when the input signal changes from low to high level, the first output of the level conversion circuit outputs a high level.

[0018] A terminal includes the aforementioned level conversion circuit.

[0019] The level conversion circuit described in this invention forms a new circuit using high-voltage NMOS and PMOS, resulting in lower power consumption under various operating conditions. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an existing level conversion circuit.

[0021] Figure 2 This is a schematic diagram of the level conversion circuit of the present invention. Detailed Implementation

[0022] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0024] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0025] The level conversion circuit described in this invention, such as Figure 2 As shown, it includes 6 NMOS transistors (NM0-NM5) and 8 PMOS transistors (PM0-PM7). All of the NMOS and PMOS transistors are high-voltage MOS transistors.

[0026] The power supply includes two power supplies, VDDH and VDD, where VDDH has a higher voltage than VDD. The level conversion circuit includes a first output terminal OUT and a second output terminal OUTN. The second output terminal OUTN outputs a signal opposite to the first output terminal OUT.

[0027] The input terminal IN serves as the input interface for the entire level conversion circuit. IN is connected to the gate of NM4 and the input terminal of the inverter, and also to the gate of PM2. The output terminal of the inverter is connected to the gates of NM5 and PM3. The inverter inverts the signal input to the input terminal before it enters the next stage circuit, ultimately forming the second output terminal in the differential output circuit. One input signal is directly transmitted to the gates of NM4 and PM2, while the other signal is simultaneously transmitted to the gates of NM5 and PM3 after passing through the inverter.

[0028] In the PMOS transistor, the source and drain of PM2, PM4, and PM6 are connected in series. The drain of PM6 is connected to the drain of NM2, and the source of NM2 is connected to the drain of NM4. The source of NM4 is grounded.

[0029] The sources of PM0, PM1, PM2, and PM3 are connected to the power supply VDDH. The gate of PM0 is connected to the gate of NM2 and to the series node of PM6. The drain of PM0 is connected to the drain of NM0, and the source of NM0 is grounded.

[0030] The node connected in series with PM0 and NM0 is the first output terminal OUT of the level conversion circuit.

[0031] PM3 is connected in series with PM5, PM7, NM3, and NM5, with the source of NM5 grounded.

[0032] The connection nodes of PM6 and NM2 are simultaneously connected to the gate of PM5, and the connection nodes of PM7 and NM3 are simultaneously connected to the gate of PM4; the connection nodes of NM2 and NM4 are simultaneously connected to the gates of NM0 and PM6, and the connection nodes of NM3 and NM5 are simultaneously connected to the gates of PM7 and NM1.

[0033] The connection nodes of PM5 and PM7 are simultaneously connected to the gates of PM1 and NM3. The drain and source of PM1 and NM1 are connected in series, and their connection node forms the second output terminal of the level conversion circuit. The source of NM1 is grounded.

[0034] Continue to refer to Figure 2 The level conversion circuit described above contains several connection nodes: A, B, C...F, and the node voltages during operation are as follows:

[0035] When the input signal IN is low, NM4 is off and NM5 is on. PM2 and PM3 are both on, but PM3 has a threshold voltage drop, so the voltages at points A and B are quickly pulled up to VDDH and VDDH-VDD, respectively. Point H is pulled down to zero. Points D and H are separated by an NMOS transistor and a PMOS transistor connected by a diode. Compared to the case where point B is VDDH, the current of PM5 is further reduced during the process of pulling the voltage at point E up to VDDH due to the voltage drop at point B. This causes the voltage at point D to be pulled down to the threshold voltage Vthp (threshold voltage of the PMOS transistor) more quickly, but the pull-down speed is still slower than at point H. Since PM7 has a significant substrate bias effect while NM3 has almost no substrate bias effect, PM7 has a higher threshold voltage. PM7 is off and NM3 is weakly on, and the voltage at point F drops to zero potential. Similarly, it can be deduced that the potential at point G is pulled up to VDDH-Vthn (the threshold voltage of the NMOS transistor), and the potentials at points C and E are both pulled up to VDDH. Therefore, PM0 is turned on, NM0 is turned off, and the first output terminal OUT of the level conversion circuit is at a high level.

[0036] When the input signal IN changes from low to high, NM4 turns on and NM5 turns off. PM2 and PM3 both turn on, but PM2 has a threshold voltage drop, so the voltages at points A and B are quickly pulled up to VDDH-VDD and VDDH, respectively. Point G is pulled down from VDDH-Vthn. Due to the blocking effect of NM2 and PM6 (PM6 is weakly on, NM2 is weakly off), the voltage drop at point C lags behind that at point G. Therefore, for the PM0 and NM0 branches, NM0 can quickly turn off, while PM0 turns on later, resulting in a very small short-circuit current in this branch. Similarly, the presence of NM2 and PM6 is equivalent to inserting a large resistor between NM4 and PM2, making the short-circuit current in this path very small as well. When point E is pulled down, PM5 turns on, point D is pulled high first, and then points F and H are pulled high. Similarly, for the PM1 and NM1 branches, PM1 turns off first, then NM1 turns on later, resulting in a very small short-circuit current flowing through this branch. Note that during the voltage rise at point F, the conduction current of PM4 is much smaller than when the voltage at point A is VDDH, so point C can be pulled down more quickly, but the pull-down speed is much slower than at point G. After the input IN goes high, the first output terminal OUT also goes high. Compared to existing designs, the current of the level conversion circuit of this invention is very small, which further reduces power consumption.

[0037] When the input IN signal changes from high to low level, similar to the process described above, the output of the level conversion circuit becomes low level, and the short-circuit current in this process is also very small.

[0038] Therefore, under various operating conditions, the level conversion circuit provided by this invention has a smaller current draw during operation.

[0039] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A level conversion circuit, characterized in that: The level conversion circuit consists of an NMOS transistor, a PMOS transistor, and an inverter, and includes one input terminal and two differential output terminals. The NMOS transistors comprise 6 NMOS transistors, NM0 to NM5, and the PMOS transistors comprise 8 PMOS transistors, PM0 to PM7. The input terminal is the input interface of the entire level conversion circuit. The input terminal is connected to the gate of NM4 and the input terminal of the inverter. The input terminal is also connected to the gate of PM2. The output terminal of the inverter is connected to the gate of NM5 and the gate of PM3. The inverter inverts the signal input to the input terminal and enters the next stage circuit, finally forming the second output terminal in the differential output terminal. In the PMOS transistor, the source and drain of PM2, PM4, and PM6 are connected in series. The drain of PM6 is connected to the drain of NM2, and the source of NM2 is connected to the drain of NM4. The source of NM4 is grounded. The sources of PM0, PM1, PM2, and PM3 are connected to the power supply VDDH. The gate of PM0 is connected to the gate of NM2 and to the source of PM6. The drain of PM0 is connected to the drain of NM0, and the source of NM0 is grounded. The node where PM0 and NM0 are connected in series is the first output terminal of the level conversion circuit; PM3, PM5, and PM7 are connected in series with their source and drain terminals connected in sequence. The drain of PM7 is connected to the drain of NM3, and the source of NM3 is connected to the drain of NM5. The source of NM5 is grounded. The connection nodes of PM6 and NM2 are simultaneously connected to the gate of PM5, and the connection nodes of PM7 and NM3 are simultaneously connected to the gate of PM4; the connection nodes of NM2 and NM4 are simultaneously connected to the gates of NM0 and PM6, and the connection nodes of NM3 and NM5 are simultaneously connected to the gates of PM7 and NM1. The connection nodes of PM5 and PM7 are simultaneously connected to the gates of PM1 and NM3. The drain and source of PM1 and NM1 are connected in series, and their connection node forms the second output terminal of the level conversion circuit. The source of NM1 is grounded.

2. The level conversion circuit as described in claim 1, characterized in that: The inverter is also connected to a power supply VDD, the voltage of which is lower than VDDH.

3. The level conversion circuit as described in claim 1, characterized in that: The MOSFETs NM0 to NM5 and PM0 to PM7 are all high-voltage MOSFETs.

4. The level conversion circuit as described in claim 1, characterized in that: When the input signal changes from low to high, the first output of the level conversion circuit outputs a high level.

5. A terminal, characterized in that: Includes the level conversion circuit according to any one of claims 1 to 4.

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