Lock detection circuit and phase-locked loop with lock detection function

Abstract

This invention relates to a lock detection circuit and a phase-locked loop (PLL) with lock detection function. The circuit compares the pulse widths of the two output pulse signals from the phase detector in the PLL and outputs a pulse width difference signal. A threshold judgment circuit then determines whether the pulse width difference is greater than a threshold. If it is greater, the PLL's locking is not as expected; if it is less than or equal to the threshold, the locking result is within the expected range. A first signal and a second signal are output to characterize this situation. The lock determination unit ultimately determines whether the PLL is locked based on the first and second signals. The lock determination unit can determine that the PLL is not locked upon receiving the first signal, or it can monitor the number of times the first signal occurs within a preset time period. If the number of occurrences exceeds the preset number, the PLL is determined to be not locked; otherwise, it is determined to be locked. This implementation method offers high detection accuracy.

Description

Technical Field

[0001] This invention relates to the field of lock detection technology, and in particular to a lock detection circuit and a phase-locked loop with lock detection function. Background Technology

[0002] Charge pump phase-locked loops are widely used in wireless communication, frequency synthesizers, and clock recovery circuits due to their high stability, large capture range, and ease of integration.

[0003] Phase-locked loop (PLL) lock-in detection is crucial for monitoring the operating characteristics of PLLs. Traditional analog lock-in detection methods utilize the phase difference output by a phase detector to generate pulse signals and charge / discharge an external capacitor to achieve lock-in detection.

[0004] However, the applicant found during implementation that this locking detection method requires a long time to complete the output of a stable level signal, otherwise the locking detection will be inaccurate. Summary of the Invention

[0005] Therefore, it is necessary to provide a lock detection circuit and a phase-locked loop with lock detection function to solve the problem of inaccurate detection results of the above-mentioned lock detection scheme.

[0006] In a first aspect, embodiments of this application provide a lock detection circuit, including:

[0007] The pulse width comparison circuit has a first input terminal for receiving the first pulse signal output from the phase detector in the phase-locked loop, and a second input terminal for receiving the second pulse signal output from the phase detector, and is used to output a pulse width difference signal; the pulse width difference signal is used to characterize the pulse width difference between the first pulse signal and the second pulse signal.

[0008] The threshold judgment circuit has its input terminal connected to the output terminal of the pulse width comparison circuit. The threshold judgment circuit is used to determine whether the pulse width difference between the two pulse signals is greater than the threshold and output a first signal. It is also used to determine whether the pulse width difference between the two pulse signals is less than or equal to the threshold and output a second signal.

[0009] The lock-up detector has its input terminal connected to the output terminal of the threshold judgment circuit, and is used to output a judgment result signal based on the first signal and the second signal. The judgment result signal is used to characterize whether the phase-locked loop is locked.

[0010] In one embodiment, the first signal is a pulse signal, and the judgment result includes a third signal and a fourth signal. The third signal is used to indicate that the phase-locked loop is locked, and the fourth signal is used to indicate that the phase-locked loop is not locked. The locking judgment device includes:

[0011] A pulse counter, whose input is connected to the output of a threshold judgment circuit, is used to calculate the number of pulses of the first signal;

[0012] The locking judgment module has its input terminal connected to the output terminal of the pulse counter. It is used to output a third signal when the number of pulses within a preset time period is less than or equal to a preset number of times; and / or to output a fourth signal when the number of pulses within a preset time period is greater than a preset number of times.

[0013] In one embodiment, the pulse width comparison circuit includes:

[0014] The first XOR logic device has its input terminal used to receive the two pulse signals output by the phase detector, and its output terminal connected to the input terminal of the threshold judgment circuit.

[0015] In one embodiment, the threshold determination circuit includes:

[0016] The delay module's input is connected to the output of the pulse width comparator circuit;

[0017] The first logic device has its first input terminal connected to the output terminal of the pulse width comparator circuit, its second input terminal connected to the output terminal of the delay module, and its output terminal connected to the input terminal of the lock-in detector.

[0018] In one embodiment, the pulse counter includes:

[0019] The frequency divider has its input connected to the output of the threshold judgment circuit and its output connected to the input of the lock judgment circuit. The preset time period is related to the operating parameters of the frequency divider.

[0020] In one embodiment, the locking determination module includes:

[0021] The input terminal of the shift register is connected to the output terminal of the pulse counter.

[0022] The judge has its input connected to the output of the shift register and is used to generate and output a judgment result signal based on the signal output from the shift register.

[0023] In one embodiment, the pulse counter is 2. N Frequency divider, where N is a positive integer greater than or equal to 1; the decision unit includes:

[0024] At least one first XOR NOT logic device, the two input terminals of each first XOR NOT logic device are respectively connected to the output terminals of two adjacent shift registers, and the input terminals of different first XOR NOT logic devices are connected to the output terminals of different shift registers;

[0025] The second AND logic device has its input terminal connected to the output terminal of each first XOR NOT logic device, and is used to output the judgment result signal.

[0026] In one embodiment, the pulse counter is a divider; there are eight shift registers, and the judge includes:

[0027] The second XOR NOT logic device, each of the two input terminals of the second XOR NOT logic device is connected one-to-one to the output terminals of two adjacent shift registers, and the input terminals of different second XOR NOT logic devices are the output terminals of different shift registers;

[0028] The third AND logic device, each of the two input terminals of the third AND logic device is connected one-to-one to the output terminals of two adjacent second XOR NOT logic devices, and the input terminals of different third AND logic devices are connected to the output terminals of different second XOR NOT logic devices.

[0029] The fourth AND logic device has its input terminal connected to the output terminal of each third AND logic device and is used to output the judgment result signal.

[0030] Secondly, embodiments of this application provide a phase-locked loop (PLL) with a lock detection function, comprising:

[0031] The aforementioned locking detection circuit;

[0032] The phase detector has a reference signal connected to its first input terminal;

[0033] The input of the loop filter is connected to the output of the phase detector.

[0034] A voltage-controlled oscillator, with its input connected to the output of a loop filter;

[0035] The feedback loop has its input terminal connected to the output terminal of the voltage-controlled oscillator and its input terminal connected to the second input terminal of the phase detector.

[0036] In one embodiment, the phase-locked loop with lock detection function further includes:

[0037] The charge pump has two input terminals connected to the two output terminals of the phase detector, and its output terminal is connected to the input terminal of the loop filter.

[0038] The aforementioned lock detection circuit and phase-locked loop with lock detection function have at least the following beneficial effects:

[0039] This locking detection circuit compares the pulse widths of the two output pulse signals from the phase detector in the phase-locked loop (PLL) and outputs a pulse width difference signal that characterizes the degree of difference in the widths of the two pulse signals. A threshold judgment circuit then determines whether the width difference between the two pulse signals exceeds a threshold. If it does, the locking of the PLL is not as expected; if it is less than or equal to the threshold, the locking result is within the expected range. A first signal and a second signal are output to represent this situation. Finally, a locking determiner uses the first and second signals output by the threshold judgment circuit to determine whether the PLL is locked. The locking determiner can determine that the PLL is not locked upon receiving the first signal, or it can monitor the number of times the first signal occurs within a preset time period. If the number of occurrences exceeds the preset number, the PLL is determined to be not locked; otherwise, it is determined to be locked. This implementation method offers high detection accuracy. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the locking detection circuit in one embodiment;

[0042] Figure 2 This is a schematic diagram of the locking detection circuit in one embodiment;

[0043] Figure 3 This is a schematic diagram of the locking detection circuit in one embodiment;

[0044] Figure 4 This is a schematic diagram of the locking detection circuit in one embodiment;

[0045] Figure 5 This is a schematic diagram of the locking detection circuit in one embodiment;

[0046] Figure 6 This is a schematic diagram of the locking detection circuit in one embodiment;

[0047] Figure 7 This is a schematic diagram of the phase-locked loop in one embodiment. Detailed Implementation

[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0050] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0051] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0053] To address the aforementioned problems, in one embodiment of this application, as follows: Figure 1 As shown, a lock detection circuit is provided, including: a pulse width comparison circuit 20, a threshold judgment circuit 40, and a lock judgment unit 60. The first input terminal of the pulse width comparison circuit 20 is used to receive a first pulse signal output from the phase detector in the phase lock unit, and the second input terminal of the pulse width comparison circuit 20 is used to receive a second pulse signal output from the phase detector and to output a pulse width difference signal; the pulse width difference signal is used to characterize the pulse width difference between the first pulse signal and the second pulse signal.

[0054] The input terminal of the threshold judgment circuit 40 is connected to the output terminal of the pulse width comparison circuit 20. The threshold judgment circuit 40 is used to output a first signal when the pulse width difference between the two pulse signals is greater than the threshold, and to output a second signal when the pulse width difference between the two pulse signals is less than or equal to the threshold.

[0055] The input terminal of the lock-up detector 60 is connected to the output terminal of the threshold judgment circuit 40, and is used to output a judgment result signal based on the first signal and the second signal. The judgment result signal is used to characterize whether the phase-locked loop is locked.

[0056] Specifically, the lock detection circuit compares the pulse widths of the two output pulse signals from the phase detector in the phase-locked loop (PLL) and outputs a pulse width difference signal that characterizes the degree of difference in the widths of the two pulse signals. Then, the threshold judgment circuit 40 determines whether the width difference between the two pulse signals is greater than a threshold value based on this pulse width difference signal. If it is greater than the threshold, it indicates that the locking status of the PLL is not as expected; if it is less than or equal to the threshold, it indicates that the locking result of the PLL is within the expected allowable error range, and outputs a first signal and a second signal respectively to characterize this situation. Finally, the lock judgment unit 60 determines whether the PLL is locked based on the first signal and the second signal output by the threshold judgment circuit 40. Compared with traditional technology, this method does not require a relatively long time to complete the output of a stable level to ensure the accuracy of the lock detection, resulting in high reliability.

[0057] In one embodiment, such as Figure 2 As shown, the first signal is a pulse signal, and the judgment result includes a third signal and a fourth signal. The third signal is used to indicate that the phase-locked loop (PLL) is locked, and the fourth signal is used to indicate that the PLL is not locked. The lock judgment unit 60 may include a pulse counter 62 and a lock judgment module 64. However, it should be noted that at any given time, the judgment result can only be one of the third signal or the fourth signal. The judgment result here includes both the third signal and the fourth signal, and those skilled in the art should understand that the judgment result signal has these two possibilities.

[0058] The pulse counter 62 is connected to the output of the threshold judgment circuit 40, and is used to calculate the number of pulses of the first signal. The lock judgment module 64 is connected to the output of the pulse counter 62, and is used to output a third signal when the number of pulses within a preset time period is less than or equal to a preset number of times. And / or, the lock judgment module 64 is used to output a fourth signal when the number of pulses within a preset time period is greater than a preset number of times.

[0059] For some electrical devices, the brief appearance of the first signal (pulse width difference exceeding the allowable error range) may cause occasional lock-up anomalies in the phase-locked loop (PLL), but this does not affect the normal operation of the device being measured. To avoid immediately determining the PLL failure upon the appearance of the first signal and subsequently implementing power-off controls, which reduces device efficiency and impacts user experience, the lock-up detector 60 determines whether the PLL is locked by monitoring the number of first signal occurrences within a preset time period. Through a fault-tolerant mechanism, the PLL is only considered unlocked if the number of pulses for the first signal exceeds the preset number. Otherwise, it is considered locked. This implementation ensures high-precision measurement results while maintaining a good user experience.

[0060] In one embodiment, the pulse width comparison circuit 20 includes: a first XOR logic device 22, with its input terminal used to receive two pulse signals output by the phase detector, and its output terminal connected to the input terminal of the threshold judgment circuit 40.

[0061] When the two input signal levels of an XOR logic device are the same, it outputs a low level (0); when the two input signal levels are different, it outputs a high level (1). By using an XOR logic device, at a certain moment, when the two pulse signals output by the phase detector are the same, the XOR logic device outputs a low level (0); when the levels are different, the XOR logic device outputs a high level (1). Based on the duration of the high and low levels in the output signal of the first XOR logic device 22, the difference in pulse width between the two output pulse signals of the phase detector within one pulse period can be determined. The first XOR logic device 22 transmits its output signal to the threshold judgment circuit 40 for further judgment.

[0062] In one embodiment, such as Figure 3 As shown, the threshold determination circuit 40 may include a delay module and a first AND logic device 44.

[0063] The input terminal of the delay module is connected to the output terminal of the pulse width comparison circuit 20; the first input terminal of the first AND logic device 44 is connected to the output terminal of the pulse width comparison circuit 20; the second input terminal of the first AND logic device 44 is connected to the output terminal of the delay module; and the output terminal of the first AND logic device 44 is connected to the input terminal of the lock detector 60.

[0064] The delay module delays the pulse signal output by the pulse width comparison circuit 20 by the time corresponding to the aforementioned threshold. If the pulse width difference signal exceeds the threshold, there is an overlapping signal period between the pulse width difference signal and the pulse signal output by the delay module. During this signal period, the output of the logic device 44 is at a high level (1). Conversely, if the duration of the pulse width difference signal is less than or equal to the threshold, there is no overlap between the pulse width difference signal and the output pulse signal of the delay module, and the output is at a low level (0).

[0065] In one embodiment, the pulse counter 62 includes a frequency divider 622. The input of the frequency divider 622 is connected to the output of the threshold judgment circuit 40, and the output of the frequency divider 622 is connected to the input of the lock detection unit 60. The preset time period is related to the operating parameters of the frequency divider 622. The frequency divider 622 is used to count the number of pulses to achieve measurement, counting, and control functions, while also performing frequency division. Here, the frequency divider 622 does not refer to the frequency divider 622 in the phase-locked loop, but rather to the frequency divider 622 used for lock detection. Based on this frequency divider 622, the output signal of the threshold judgment circuit 40 is divided and counted. When the first signal is detected, the frequency divider 622 counts once, accumulating the count over the preset time period. At the end of the preset time period, the frequency divider 622 is reset to 0, and pulse counting for the occurrence of the first signal in the next preset time period begins.

[0066] In one embodiment, such as Figure 4 As shown, the lock determination module 64 includes a shift register 642 and a determiner 644. The input of the shift register 642 is connected to the output of the pulse counter 62. The input of the determiner 644 is connected to the output of the shift register 642, and the determiner 644 is used to generate and output a determination result signal based on the signal output from the shift register 642.

[0067] The shift register 642 shifts the pulse signal under the action of the shift pulse signal (REFCLK as shown in the figure). The output signal of the frequency divider 622, which is connected to the input of the shift register 642, is stored under the action of shifting. The judge 644 determines whether to lock based on the signal stored in the shift register 642 and determines the relationship between the number of pulses and the preset number of times within the preset time period.

[0068] In one embodiment, such as Figure 5 As shown, pulse counter 62 is 2 NFrequency divider 622, where N is a positive integer greater than or equal to 1; Judge 644 includes: at least one first XOR logic device 6442, whose two inputs are respectively connected to the outputs of two adjacent shift registers 642, and the inputs of different first XOR logic devices 6442 are connected to the outputs of different shift registers 642. A second AND logic device 6444, whose input is connected to the output of each first XOR logic device 6442, is used to output the judgment result signal. A 2n N Frequency divider 622 reduces the number of registers and lowers cost through multiplexing. Furthermore, frequency division reduces the number of shift operations required by shift register 642 within the same time frame, thus reducing the computational requirements and further lowering costs. The number of shift registers 642 is related to 2... N Frequency divider 622 is matched; the preset time period is related to N and the number of shift registers 642. Specifically, when the two input signal levels of the XOR NOT logic device are the same, the output is high (1); when the two input signal levels are different, the output is low (0).

[0069] like Figure 5 As shown, using 2 N In the frequency divider 622, XOR and AND logic devices can be used for judgment. The two inputs of each first XOR logic device 6442 are connected to the outputs Q of two adjacent shift registers 642. When the outputs Q of the two adjacent shift registers 642 are the same, the first XOR logic device 6442 outputs a low level (1); otherwise, it outputs a high level (0). When the pulse signal width difference has not exceeded the threshold, within a preset time period, the outputs of each shift register are the same, and the outputs of the first XOR logic device 6442 are all high level (1). At this time, the second AND logic device 6444 outputs a high level, indicating locking. Conversely, when the second AND logic device 6444 outputs a low level (0), it indicates unlocking.

[0070] Of course, a NOT logic device can also be connected to the output of the second AND logic device 6444. The output signal of the NOT logic device can be used to represent whether it is locked. In this case, due to the addition of the NOT logic, the output of the NOT logic device is low when it is locked and high when it is unlocked. Based on the examples in the embodiments of this application, those skilled in the art can reasonably understand that an XOR NOT logic device can be used to replace each second XOR device. Due to the addition of the NOT logic, the output of the second AND logic device 6444 is low (0) when it is unlocked and high (1) when it is locked.

[0071] In one embodiment, the pulse counter 62 is a frequency divider 622; there are eight shift registers 642; and the judge 644 includes: a second XOR logic device 6446, the two inputs of each second XOR logic device 6446 being connected one-to-one to the outputs of two adjacent shift registers 642, and the inputs of different second XOR logic devices 6446 being connected to the outputs of different shift registers 642; a third AND logic device 6448, the two inputs of each third AND logic device 6448 being connected one-to-one to the outputs of two adjacent second XOR logic devices 6446, and the inputs of different third AND logic devices 6448 being connected to the outputs of different second XOR logic devices 6446; and a fourth AND logic device 6449, the inputs of which are connected to the outputs of each third AND logic device 6448, and are used to output the judgment result signal.

[0072] For commonly used electrical components, eight shift registers (642) are sufficient to determine whether the number of pulses of the first signal within a preset time period exceeds a preset number. Therefore, if... Figure 6 As shown, in one embodiment, the pulse counter 62 can be a frequency divider 622, working in conjunction with an 8-bit shift register 642, a second XOR logic device 6446, a third AND logic device 6448, and a fourth AND logic device 6449 to achieve lock detection. For example, when the pulse width value does not exceed the threshold, the outputs of each shift register remain consistent within a preset time period. Therefore, the outputs of each second XOR logic device 6446 are high level 1, and the output of the third AND logic device 6448 is also high level 1. At this time, the output of the fourth AND logic device 6449 is also high level 1. A high level 1 indicates successful lock-up; conversely, a low level 0 indicates that the phase-locked loop (PLL) is not locked.

[0073] Similar to the description in the above embodiments, a NOT logic device can be connected to the output of the fourth AND logic device 6449, and the output signal of the NOT logic device can be used as the judgment result signal. In this case, due to the addition of the NOT logic, when the output of the fourth AND logic device 6449 is low, it indicates that the phase-locked loop is locked; conversely, when the output of the fourth AND logic device 6449 is high, it indicates that the phase-locked loop is not locked.

[0074] Secondly, embodiments of this application provide a phase-locked loop (PLL) with a lock detection function, such as... Figure 7 As shown, the circuit includes: the aforementioned lock detection circuit 2, phase detector 4, loop filter 6, voltage-controlled oscillator 8, and feedback circuit 9. The first input terminal of the phase detector 4 is connected to a reference signal. The input terminal of the loop filter 6 is connected to the output terminal of the phase detector 4. The input terminal of the voltage-controlled oscillator 8 is connected to the output terminal of the loop filter 6. The input terminal of the feedback loop is connected to the output terminal of the voltage-controlled oscillator 8, and the input terminal of the feedback loop is connected to the second input terminal of the phase detector 4.

[0075] The lock-in detection circuit 2 can be understood by referring to the description in the above embodiments, and will not be repeated here. The phase detector 4 is a device capable of identifying the phase difference of the input signal; it is a circuit that establishes a definite relationship between the output voltage and the phase difference between the two input signals. Specifically, using the input reference signal, the frequency and phase of the oscillation signal within the loop formed by the phase detector 4, loop filter 6, voltage-controlled oscillator 8, and feedback circuit 9 are controlled to achieve automatic tracking of the output signal frequency to the input signal frequency. To maintain a constant frequency, the phase difference must not change. If a phase difference change occurs, the voltage-controlled oscillator 8 needs to be controlled until the phase difference is restored, thus achieving phase locking.

[0076] The phase-locked loop (PLL) provided in this application embodiment can achieve self-detection of lock. When the PLL is used for line synchronization and frame synchronization of a television receiver, if it is determined that the PLL is not locked, it will affect the use of the television receiver and other equipment. At this time, the determination result signal is output to inform the user of the unlocked state. For example, it can be sent to the controller, which controls the voltage-controlled oscillator 8 until the phase difference is restored, thereby achieving phase re-locking and restoring the normal use of the television receiver and other equipment.

[0077] In one embodiment, the phase-locked loop (PLL) with lock-in detection function further includes a charge pump. The two input terminals of the charge pump are connected one-to-one with the two output terminals of the phase detector 4, and the output terminals are connected to the input terminals of the loop filter 6. The charge pump generates a pump current based on the two output pulse signals of the phase detector 4. This pump current is filtered by the loop filter 6 and further transmitted to the voltage-controlled oscillator 8. The voltage-controlled oscillator 8 generates a phase-locked signal based on the filtered pump current, thereby measuring the amplitude and phase of the oscillating electrical signal, with the phase relative to the aforementioned reference signal.

[0078] The phase-locked loop (PLL) with a charge pump and a lock detection circuit 2 provided in this application embodiment not only has a large capture range and is easy to integrate, but also has a lock detection capability. It can output a fourth signal when it is not locked, so that the PLL can be known to be unlocked, thereby formulating further solutions to put the PLL back into the locked state.

[0079] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A locking detection circuit, characterized in that, include: The pulse width comparison circuit has a first input terminal for receiving the first pulse signal output by the phase detector in the phase lock-in, and a second input terminal for receiving the second pulse signal output by the phase detector, and for outputting a pulse width difference signal. The pulse width difference signal is used to characterize the pulse width difference between the first pulse signal and the second pulse signal; A threshold judgment circuit is provided, with its input terminal connected to the output terminal of the pulse width comparison circuit. The threshold judgment circuit is used to output a first signal when it determines that the pulse width difference between the two pulse signals is greater than a threshold, and to output a second signal when it determines that the pulse width difference between the two pulse signals is less than or equal to the threshold. A lock determination unit, with its input terminal connected to the output terminal of a threshold judgment circuit, is used to output a judgment result signal based on the first signal and the second signal. The judgment result signal is used to characterize whether the phase-locked loop is locked. The first signal is a pulse signal, and the judgment result includes a third signal and a fourth signal. The third signal is used to characterize that the phase-locked loop is locked, and the fourth signal is used to characterize that the phase-locked loop is not locked. The lock determination unit includes: A pulse counter, the input of which is connected to the output of the threshold judgment circuit, is used to calculate the number of pulses of the first signal; The locking judgment module has its input terminal connected to the output terminal of the pulse counter, and is used to output the third signal when the number of pulses within a preset time period is less than or equal to a preset number; and / or to output the fourth signal when the number of pulses within the preset time period is greater than the preset number; The locking determination module includes: The input terminal of the shift register is connected to the output terminal of the pulse counter; The judge has its input connected to the output of the shift register and is used to generate and output the judgment result signal based on the signal output by the shift register.

2. The locking detection circuit according to claim 1, characterized in that, The pulse width comparison circuit includes: The first XOR logic device has an input terminal for receiving the two pulse signals output by the phase detector, and an output terminal connected to the input terminal of the threshold judgment circuit.

3. The locking detection circuit according to claim 1, characterized in that, The threshold determination circuit includes: The delay module has its input terminal connected to the output terminal of the pulse width comparison circuit; The first AND logic device has a first input terminal connected to the output terminal of the pulse width comparison circuit, a second input terminal connected to the output terminal of the delay module, and an output terminal connected to the input terminal of the lock-in detector.

4. The locking detection circuit according to claim 1, characterized in that, The pulse counter includes: The frequency divider has its input terminal connected to the output terminal of the threshold judgment circuit and its output terminal connected to the input terminal of the lock judgment device. The preset time period is related to the operating parameters of the frequency divider.

5. The locking detection circuit according to claim 1, characterized in that, The pulse counter is 2. N Frequency divider, where N is a positive integer greater than or equal to 1; the judge includes: At least one first XOR NOT logic device, wherein the two input terminals of each first XOR NOT logic device are respectively connected to the output terminals of two adjacent shift registers, and the input terminals of different first XOR NOT logic devices are connected to the output terminals of different shift registers; The second AND logic device has its input terminal connected to the output terminal of each of the first XOR NOT logic devices, and is used to output the judgment result signal.

6. The locking detection circuit according to claim 1, characterized in that, The pulse counter is a frequency divider; the shift register has eight bits; the judgment unit includes: The second XOR NOT logic device, wherein the two input terminals of each second XOR NOT logic device are respectively connected to the output terminals of two adjacent shift registers, and the input terminals of different second XOR NOT logic devices are different from the output terminals of the shift registers; The third AND logic device, wherein the two input terminals of each third AND logic device are connected one-to-one to the output terminals of two adjacent second XOR NOT logic devices, and the input terminals of different third AND logic devices are connected to the output terminals of different second XOR NOT logic devices; The fourth AND logic device has its input terminal connected to the output terminal of each of the third AND logic devices, and is used to output the judgment result signal.

7. A phase-locked loop with a locking detection function, characterized in that, include: The locking detection circuit according to any one of claims 1-6; The phase detector has a reference signal connected to its first input terminal; A loop filter, the input of which is connected to the output of the phase detector; A voltage-controlled oscillator, the input of which is connected to the output of the loop filter; The feedback loop has its input terminal connected to the output terminal of the voltage-controlled oscillator and its input terminal connected to the second input terminal of the phase detector.

8. The phase-locked loop with locking detection function according to claim 7, characterized in that, Also includes: The charge pump has two input terminals that are connected one-to-one with the two output terminals of the phase detector, and the output terminals are connected to the input terminals of the loop filter.

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