Method for manufacturing a composite structure comprising a thin layer made of single-crystalline SiC located on a carrier substrate made of SiC

Abstract

The present invention relates to a method for manufacturing a composite structure comprising a thin layer made of single-crystalline silicon carbide disposed on a carrier substrate made of silicon carbide, the method comprising: step a) of providing a donor substrate made of single-crystalline SiC, the donor substrate comprising a donor layer produced by epitaxial growth on an initial substrate, the donor layer exhibiting a crystal defect density lower than that of the initial substrate; step b) of implanting light species ions into the donor layer to form a buried fragile plane, thereby defining a thin layer between the buried fragile plane and the free surface of the donor layer; step c) of successively forming n carrier layers, where n is greater than or equal to 2; the n carrier layers are successively arranged on the donor layer one after another and form a carrier substrate; each forming step comprises chemical vapor deposition at a temperature between 400 °C and 1100 °C to form a carrier layer made of polycrystalline SiC; performing chemical vapor deposition n times at n different temperatures; step d) of separating along the buried fragile plane, on the one hand, to form a composite structure comprising the thin layer on the carrier substrate and, on the other hand, to form the remaining part of the donor substrate; step e) of mechanically and / or chemically treating the composite structure.

Description

Technical Field

[0001] The invention relates to the field of semiconductor materials for microelectronic components. The invention relates in particular to a method for producing a composite structure comprising a thin layer made of single-crystalline silicon carbide on a carrier substrate made of silicon carbide. Background Art

[0002] Interest in silicon carbide (SiC) has increased significantly over the past few years because of the semiconductor material's ability to improve energy processing capabilities. SiC is increasingly being used to create novel power devices to meet the needs of emerging areas of electronics, such as electric vehicles in particular.

[0003] Power devices and integrated power systems based on single-crystal silicon carbide are able to manage higher power densities and have smaller active area sizes than their traditional counterparts made of silicon. To further limit the size of power devices on SiC, it is advantageous to manufacture vertical components rather than lateral components. To do this, the SiC structure must allow vertical conduction between electrodes arranged on the front surface of the structure and electrodes arranged on the rear surface.

[0004] However, single-crystal SiC substrates intended for use in the microelectronics industry are still expensive and difficult to supply in larger sizes. Therefore, it is advantageous to adopt thin layer transfer solutions to produce composite structures, which usually include a thin layer made of single-crystal SiC on a less expensive carrier substrate. One well-known thin layer transfer solution is Smart Cut TM Process, the Smart Cut TM The process is based on the implantation of light ions and the assembly by direct bonding. This process makes it possible, for example, to manufacture a composite structure comprising a thin layer made of single-crystalline SiC (c-SiC), taken from a donor substrate made of c-SiC, in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), and allowing vertical conduction. However, it remains difficult to produce high-quality direct bonding by molecular adhesion between the two substrates, c-SiC and p-SiC, because it is complex to manage the surface state and roughness of the substrates.

[0005] Various methods derived from this process are also known in the prior art. For example, in (ECS Transactions (Transactions of the Electrochemical Society), 86(5), 3 - 21, 2018) by F. Mu et al., after activating the surface to be assembled by bombarding with argon, direct bonding (SAB: "Surface Activated Bonding") is employed: This treatment before bonding generates a very high density of side bonds, which promotes the formation of covalent bonds at the assembly interface, thus generating a high bonding energy. However, this method exhibits the drawback of generating an amorphous layer on the surface of the donor substrate made of single-crystal SiC, which adversely affects the vertical conductivity between the thin layer made of c-SiC and the carrier substrate made of p-SiC.

[0006] Solutions to this problem have been proposed. Specifically, in the document EP 3168862, doping agent entities are injected into the amorphous layer to restore its electrical properties. The main drawback of this method is its complexity and the resulting cost.

[0007] Furthermore, the document US8436363 is known, which describes a method for manufacturing a composite structure including a thin layer made of c-SiC disposed on a metal carrier substrate, the thermal expansion coefficient of the metal carrier substrate matching that of the thin layer. This manufacturing method includes the following steps:

[0008] - Forming a buried fragile plane in the c-SiC donor substrate, defining a thin layer between the buried fragile plane and the front surface of the donor substrate,

[0009] - Depositing a metal layer, for example made of tungsten or made of molybdenum, on the front surface of the donor substrate to form a carrier substrate with a sufficient thickness to be used as a reinforcement,

[0010] - Separating along the buried fragile plane, on the one hand, to form a composite structure including the metal carrier substrate and the thin layer made of c-SiC, and on the other hand, to form the remaining part of the donor substrate made of c-SiC.

[0011] However, when the material forming the carrier substrate is p-SiC which needs to be deposited at a temperature above 1200 °C (the usual temperature for manufacturing p-SiC), this manufacturing method is incompatible. Specifically, at these high temperatures, the growth kinetics of the cavities present in the buried fragile plane is faster than the growth kinetics of the layer made of p-SiC, and the thickness required for the hardening effect is not reached before the occurrence of a blistering phenomenon (related to the deformation of the layer directly above the cavities).

[0012] Regardless of the layer transfer technique used, the additional problem lies in providing a composite structure including a very high-quality thin layer made of c-SiC, in particular without extended defects (or showing a very low density thereof), which defects are liable to affect the performance quality and reliability of power devices intended to be fabricated on said thin layer. Summary of the Invention

[0013] Subject Matter of the Invention

[0014] The present invention relates to an alternative solution to the prior art and aims to overcome the above-mentioned drawbacks completely or partially. The present invention particularly relates to a method for manufacturing a composite structure including a thin layer made of high-quality c-SiC disposed on a carrier substrate made of polycrystalline SiC.

[0015] The present invention relates to a method for manufacturing a composite structure including a thin layer made of single-crystalline silicon carbide disposed on a carrier substrate made of silicon carbide. The method includes:

[0016] Step a) of providing a donor substrate made of single-crystalline silicon carbide, the donor substrate including a donor layer produced by epitaxial growth on an initial substrate, the donor layer showing a density of crystal defects lower than that of the initial substrate,

[0017] Step b) of implanting light solid ions into the donor layer to form a buried fragile plane, thereby defining a thin layer between the buried fragile plane and the free surface of the donor layer,

[0018] Step c) of successively forming n carrier layers, where n is greater than or equal to 2; the n carrier layers are successively disposed on the donor layer one by one and form a carrier substrate; each forming step includes chemical vapor deposition at a temperature between 400 °C and 1100 °C to form a carrier layer made of polycrystalline silicon carbide; the chemical vapor deposition is carried out n times at n different temperatures,

[0019] Step d) of separating along the buried fragile plane, on the one hand to form a composite structure including the thin layer on the carrier substrate, and on the other hand to form the remaining part of the donor substrate,

[0020] Step e) of mechanically and / or chemically treating the composite structure to smooth the free surface of the thin layer and / or to correct the thickness uniformity of the composite structure.

[0021] According to other advantageous and non-limiting features of the present invention obtained separately or according to any technically available combination:

[0022] · Performing the deposition of step c) at a temperature between 600 °C and 900 °C, actually even preferably between 700 °C and 800 °C;

[0023] · The deposition in step c) is based on atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition techniques;

[0024] · The n depositions in step c) are performed at n increasing temperatures;

[0025] · The n depositions in step c) are performed at n decreasing temperatures;

[0026] · At least two of the n carrier layers deposited in step c) exhibit different doping levels;

[0027] · At the end of the deposition in step c), the carrier substrate exhibits a thickness greater than or equal to 50 microns, greater than or equal to 100 microns, and in fact even greater than or equal to 200 microns;

[0028] · Step a) includes forming a single crystal conversion layer on the initial substrate before the epitaxial growth of the donor layer to convert the basal plane dislocation type defects of the initial substrate into edge dislocation type defects of the epitaxial layer;

[0029] · In step a), the epitaxial growth of the donor layer is performed at a temperature greater than 1200 °C, preferably between 1500 °C and 1650 °C;

[0030] · In step c), at least one of the steps of forming the n carrier layers includes an annealing performed after the chemical vapor deposition of the step, and the annealing temperature is higher than the deposition temperature and lower than the separation temperature liable to cause the separation in step d);

[0031] · Between step c) and step d), chemical etching, mechanical grinding and / or chemical mechanical polishing are applied to the free surface of the carrier substrate;

[0032] · After the separation in step d), a new chemical vapor deposition is performed to thicken the carrier substrate;

[0033] · Step e) includes performing chemical mechanical polishing on the front and back surfaces of the composite structure simultaneously;

[0034] · The manufacturing method includes a step of repairing the remaining part of the donor substrate for the purpose of reusing it as the initial substrate or the donor substrate. Description of the Drawings

[0035] Other features and advantages of the present invention will become apparent from the following detailed description of the present invention with reference to the accompanying drawings, in which:

[0036] Figure 1 Figure 1 shows a composite structure prepared according to a manufacturing method based on the present invention;​​

[0037] Figure 2a

[0038] Figure 2b

[0039] [Figure 2c(i)]

[0040] [Figure 2c(ii)]

[0041] [Figure 2c(iii)]

[0042] Figure 2d

[0043] Figure 2e

[0044] Figure 2f Figures 2a to 2f shows the steps of the manufacturing method according to the present invention;

[0045] Figure 3a

[0046] Figure 3b Figure 3a and Figure 3b shows the steps of the manufacturing method according to the present invention. Detailed Description

[0047] In the description part, the same reference numerals in the drawings may be used for the same type of elements. These figures are diagrammatic representations for ease of reading and are not drawn to scale. Specifically, the thickness of these layers along the z-axis is not in proportion to the lateral dimensions along the x-axis and y-axis; and the relative thicknesses of these layers with respect to each other need not be considered in the drawings.

[0048] The present invention relates to a method for manufacturing a composite structure 1 comprising a thin layer 10 made of single-crystalline silicon carbide disposed on a carrier substrate 20 made of silicon carbide ( Figure 1 ). The carrier substrate 20 is advantageously polycrystalline ("p-SiC" will subsequently be used to refer to polycrystalline SiC).

[0049] The method first includes step a) of providing a donor substrate 111 made of single-crystalline silicon carbide. In the following description, "c-SiC" will be used to refer to single-crystalline silicon carbide.

[0050] The donor substrate 111 includes an initial substrate 11 made of c-SiC ( Figure 2a ​​​​​​​​​​​​​​)。The initial substrate 11 is preferably provided in the form of a wafer having a diameter of 100 mm, 150 mm, 200 mm, actually even 300 mm or even 450 mm and a thickness generally between 300 microns and 800 microns. It exhibits a front surface 11a and a back surface 11b. The surface roughness of the front surface 11a is advantageously selected to be less than 1 nm Ra (average roughness), which is measured by atomic force microscopy (AFM) with a scan of 20 microns × 20 microns.

[0051] The donor substrate 111 also includes a donor layer 110 made of c-SiC, which is produced by epitaxial growth on the initial substrate 11. The epitaxial growth step is carried out so that the donor layer 110 exhibits a lower crystal defect density than the crystal defect density of the initial substrate 11.

[0052] For example, the initial substrate 11 made of c-SiC is of the 4H polytype or 6H polytype, exhibits a cut angle of less than or equal to 4.0° ± 0.5° with respect to the <11-20> crystal axis, and has a density of threading dislocations (microtubes) of less than or equal to 5 / cm 2 , actually even less than 1 / cm 2 . The N (nitrogen) type doping exhibits a resistivity preferably between 0.015 ohm.cm and 0.030 ohm.cm. It is possible to select an initial substrate 11 that exhibits a lower density of basal plane dislocation type defects or BPD type defects (generally less than or equal to 3000 / cm 2 ). c-SiC substrates exhibiting a BPD density of approximately 1500 / cm 2 are reasonably available, which facilitates their supply.

[0053] To meet the specifications required for the vertical components to be fabricated on the said thin layer 10, it is desirable for the donor layer 110 to exhibit a better crystal quality than the initial substrate 11. The thin layer 10 made of c-SiC of the composite structure 1 will be formed from the donor layer 110 at the end of the method that is the subject of the present invention. This is because there are various types of extended defects in the layer or substrate made of c-SiC. These extended defects can affect the performance quality and reliability of the components. In particular, BPD type defects are fatal for bipolar components: specifically, when the energy available for electron-hole pair recombination is present, Shockley stacking faults (SSF) extend from the dislocations. The extension of the SSF stacking faults in the active region of the component results in an increase in the on-state resistance of the component.

[0054] Therefore, the donor layer 110 made of c-SiC is prepared to exhibit a density of less than or equal to 1 / cm 2The density of BPD-type defects.

[0055] To this end, the epitaxial growth of the donor layer 110 is carried out at a temperature greater than 1200 °C (preferably between 1500 °C and 1650 °C). The precursors used are silane (SiH 4 ), propane (C 3 H 8 ), or ethylene (C 2 H 4 ); the carrier gas can be hydrogen, with or without argon.

[0056] A low content of BPD defects in the donor layer 110 is obtained by facilitating the conversion of the BPD defects present in the initial substrate 11 into threading edge dislocations (TEDs) in the epitaxial layer.

[0057] According to a specific embodiment, step a) includes: before growing the donor layer 110, forming a single-crystal conversion layer 13 preferably made of c-SiC on the initial substrate 11. The purpose of the conversion layer 13 is to maximize the conversion of the BPD-type defects of the initial substrate 11 into TED-type defects ( Figure 3a ). To this end, it is advantageous to select a low cut angle close to 4° for the initial substrate 11 made of c-SiC, increase the in-situ etching performed before epitaxial growth, achieve a high growth rate (usually greater than 5 μm / h), and finally select the growth conditions for the single-crystal conversion layer 13 (the C / Si ratio in the precursor flow is close to 1).

[0058] Subsequently, the epitaxial growth of the donor layer 110 can be carried out on the conversion layer 13 ( Figure 3b ). According to this specific embodiment, a donor layer 110 made of c-SiC can also be obtained, which exhibits a density of BPD-type defects less than or equal to 1 / cm 2 , and in fact even less than 0.1 / cm 2 . In addition, at the end of the method according to the invention, the probability of bipolar degradation (the probability that holes reach below the BPD / TED conversion point) can be neglected (<0.1%), and the single-crystal conversion layer 13 is not intended to be transferred to the composite structure 1. The prior art aimed at reducing bipolar degradation includes incorporating a recombination layer (nitrogen doping exceeding 1 E 18 at / cm 3 ) between the conversion layer and the active layer. This layer can have a thickness of 10 μm and a density greater than 5 E 18 / cm 3At the cost of the concentration, the probability of the presence of holes is reduced to 0.1% relative to the basic structure that does not include this recombination layer. In the present invention, since the single crystal conversion layer 13 is not transferred, the probability that holes reach the nucleation point (point de nucléation) of bipolar degradation (BPD-TED conversion point or any BPD point) is at least less than 0.1%, and in fact even close to 0%.

[0059] It should be noted that a conventional cleaning or etching procedure of the initial substrate 11 can be performed before epitaxial growth, which is intended to remove all or part of the particles, metallic or organic contaminants, or native oxide layer that may be present on its front surface 11a.

[0060] The manufacturing method according to the present invention further includes step b) of implanting light entity ions into the donor layer 110 to a predetermined depth representing the desired thickness of the thin layer 10. It should be noted that the depth will always remain less than the thickness of the donor layer 110. This implantation creates a buried fragile plane 12 in the donor layer 110, which defines the thin layer 10 between the buried fragile plane 12 and the free surface 11a of the donor layer 110 ( Figure 2b ).

[0061] The implanted light entities are preferably hydrogen, helium, or a co-implant of these two entities. As is known from the reference Smart Cut TM process, these light entities will form microcavities around the predetermined depth, and the microcavities are distributed in a thin layer parallel to the free surface 11a of the donor layer 110 (i.e., parallel to the (x, y) plane in the figure). For simplicity, this thin layer is called the buried fragile plane 12.

[0062] The energy for implanting the light entities is selected such that a determined depth in the donor substrate 111 is reached.

[0063] Generally, hydrogen ions will be implanted with an energy between 10 keV and 250 keV and an incorporation amount between 5 E 16 / cm 2 and 1 E 17 / cm 2 to define a thin layer 10 having a thickness of approximately 100 nm to 1500 nm.

[0064] It should be noted that a protective layer can be deposited on the free surface 11a of the donor layer 110 before the ion implantation step. For example, this protective layer can be composed of a material such as silicon oxide or silicon nitride.

[0065] The method according to the invention then comprises the step of successively forming n carrier layers 20', where n is greater than or equal to 2, and advantageously greater than or equal to 3. The n carrier layers 20' are arranged successively one on top of the other on the free surface 11a of the donor layer 110; they form the carrier substrate 20. In other words, the first carrier layer 20' is in direct contact with the front surface 11a of the donor layer 110, then the second carrier layer 20' is in contact with the first carrier layer, and so on for the n carrier layers 20', until the carrier substrate 20 is obtained (Figure 2c(i), Figure 2c(ii), Figure 2c(iii)).

[0066] Each forming step comprises chemical vapor deposition (CVD) to form a carrier layer 20' made of polycrystalline silicon carbide.

[0067] Each CVD deposition is carried out at a temperature between 400 °C and 1100 °C, and preferably at a temperature between 600 °C and 900 °C, and in fact even advantageously at a temperature between 700 °C and 800 °C. Advantageously, the deposition of step c) is based on atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) techniques.

[0068] According to the invention, the n depositions of step c) are carried out at n different temperatures. This makes it possible to improve the quality of the carrier substrate 20 resulting from the superposition of the n carrier layers 20', as will be stated subsequently with reference to two embodiments.

[0069] Preferably, each carrier layer 20' exhibits a thickness less than or equal to 150 μm, less than or equal to 100 μm, and in fact even less than or equal to 50 μm.

[0070] According to the first embodiment, the n depositions of step c) are carried out at n increasing temperatures. For example, four depositions can be carried out successively in a temperature range from 700 °C to 1000 °C. It should be noted that the thicknesses of the carrier layers 20' deposited during the successive depositions can be the same or different.

[0071] The advantage of this embodiment is that it limits the thermal budget applied to the donor substrate 111 at the start of the formation of the carrier layers 20' (i.e., when the hardening effect of these layers is not strong): thus, the risk of damage to the donor layer 110 due to the growth of cavities in the buried fragile plane 12 leading to blistering is greatly reduced.

[0072] In addition, even if the crystalline quality of the first deposited carrier layer 20' is reduced (due to the lower deposition temperature), the subsequent depositions carried out at elevated temperatures make it possible to recover (at least partially) and / or improve the crystallinity of the first deposition.

[0073] Preferably, the highest temperature (i.e., the temperature applied during the last n depositions) is lower than the temperature that may be applied in the subsequent step d) for performing the separation.

[0074] According to the second embodiment, the n depositions in step c) are performed at n decreasing temperatures. For example, three to five depositions can be sequentially performed in a temperature range from 1000 °C to 700 °C.

[0075] Advantageously, the highest temperature (i.e., the temperature applied during the first deposition) is lower than the temperature expected in the subsequent step d) for performing the separation.

[0076] This second embodiment aims to form a first carrier layer 20' with very good crystallization quality on the donor layer 110 to enhance the conductivity of the interface between the two layers. The quality of the subsequent carrier layers 20' will probably be worse (given the lower deposition temperature), but the reduced deposition temperature makes it possible to limit the growth of cavities in the buried fragile plane 12 until the desired thickness of the carrier substrate 20 is reached. It can also be considered that the carrier layers 20' deposited at increasingly lower temperatures will generate increasingly smaller thermo-mechanical stresses during cooling to ambient temperature.

[0077] Optionally, in one or other of the described embodiments, at least one of the n steps of forming the carrier layer 20' includes annealing performed after chemical vapor deposition. Advantageously, the annealing temperature will be selected to be higher than the deposition temperature and lower than the separation temperature that may be applied during the subsequent step d) of separating along the buried fragile plane 12.

[0078] Generally, regardless of the embodiment adopted, the thermal budget applied to the stack 211 during any one of the n steps of forming the carrier layer 20' is less than the thermal budget that causes the growth of cavities in the buried fragile plane 12 (which may deform the thin layer 10 and the n carrier layers 20' formed above).

[0079] Furthermore, the total thermal budget applied to the stack 211 during the n steps of forming the carrier layer 20' remains less than the thermal budget that causes spontaneous separation along the buried fragile plane 12.

[0080] Step c) of the method advantageously defines a non-insulating interface between the donor layer 110 and the first carrier layer 20' deposited during the first CVD deposition. In other words, step c) is performed so that at least in the final composite structure 1, an interface between the donor layer 110 and the first carrier layer 20' can form a conductive interface: for example, usually less than 1 mohm.cm 2The specific interfacial resistivity will be the target. Advantageously, to ensure the conductivity of the interface, the removal of the native oxide present on the free surface 11a of the donor layer 110 is carried out via a wet or dry route by deoxidation with HF (hydrofluoric acid).

[0081] Before deoxidation and / or the formation of the first carrier layer 20', a cleaning procedure can be applied to the donor substrate 111 to remove all or part of the particulate, metallic, or organic contaminants that may be present on its free surface.

[0082] Advantageously, the carrier layer 20' deposited during the first CVD deposition exhibits a high doping level to further enhance the conductivity of the interface with the donor substrate 111. Generally, the first deposited carrier layer 20' can exhibit a doping concentration of between 1 E 14 / cm 3 and 1 E 22 / cm 3 for N-type or P-type dopants. The next carrier layers 20' to be deposited can exhibit different concentrations and / or different types of dopants. Thus, at least two of the n carrier layers 20' deposited in step c) can exhibit different doping levels.

[0083] The deposition parameters of step c) are advantageously determined such that the carrier substrate 20 exhibits good conductivity (i.e., less than or equal to 0.03 ohm.cm, and in fact even less than or equal to 0.01 ohm.cm), a high thermal conductivity (i.e., greater than or equal to 150 W.m -1 .K -1 , and in fact even greater than or equal to 200 W.m -1 .K -1 ) and a thermal expansion coefficient similar to that of the thin layer 10 (i.e., generally between 3.8 E -6 / K and 4.2 E -6 / K at room temperature). To obtain these properties, the carrier substrate 20 preferably exhibits the following structural characteristics: a polycrystalline structure, 3C SiC-type grains, a 111 orientation, an average size in the plane of the substrate of 1 μm to 50 μm, and N-type doping for a final resistivity of less than or equal to 0.03 ohm.cm.

[0084] At the end of step c), the carrier substrate 20 exhibits a thickness greater than or equal to 10 microns, greater than or equal to 50 microns, greater than or equal to 100 microns, and in fact even greater than or equal to 200 microns. The stack 211 produced by step c) includes the carrier substrate 20 disposed on the donor substrate 111.

[0085] The method according to the invention then comprises a step d) of separating along the buried weak plane 12, on the one hand in order to form the composite structure 1 and on the other hand in order to form the remaining part 111' of the donor substrate ( Figure 2d ).

[0086] According to an advantageous embodiment, the separation step d) is carried out by applying a heat treatment to the stack 211 at a separation temperature higher than the deposition temperature of step c) and the annealing temperature (if carried out). This is because the microcavities present in the buried weak plane 12 follow the growth kinetics until the onset of a fracture wave which will propagate throughout the buried weak plane 12 and cause the separation between the composite structure 1 and the remaining part of the initial substrate 111'. In fact, depending on the implantation conditions of step b), the temperature can be between 950 °C and 1200 °C, preferably between 1000 °C and 1200 °C.

[0087] According to an alternative embodiment, the separation step d) is carried out by applying a mechanical stress to the stack 211. For example, the stress can be applied by inserting a tool (such as a blade or bevel shape) close to the buried weak plane 12. For example, the separation stress can be about a few GPa, preferably greater than 2 GPa.

[0088] It should be noted that after the separation of step d), it is optionally possible to plan to carry out at least one new CVD deposition in order to further thicken the carrier substrate 20.

[0089] After step d), a composite structure 1 is obtained comprising a thin layer 10 made of single-crystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline silicon carbide.

[0090] As is known per se, at the end of the separation step d), the free surface 10a of the thin layer 10 of the composite structure 1 exhibits a surface roughness between 5 nm RMS and 100 nm RMS (measured by means of an atomic force microscope (AFM) with a scan of 20 µm × 20 µm).

[0091] Thus, a step e) of mechanically and / or chemically treating the composite structure 1 is provided in order to smooth the free surface 10a of the thin layer 10 and / or to correct the thickness uniformity of the structure 1 ( Figure 2e ).

[0092] Step e) may include chemical mechanical polishing (CMP) of the free surface 10a of the thin layer 10 (typically removing about 50 nm to 1000 nm of material) to obtain a final roughness of less than 0.5 nm RMS (on a 20×20 μm AFM field), and in fact even less than 0.3 nm. Step e) may also include chemical or plasma (cleaning or etching) treatments (e.g., SC1 / SC2 cleaning (standard clean 1, standard clean 2) and / or HF (hydrofluoric acid) type or N 2 , Ar, CF 4 etc. cleaning, plasma cleaning) to further improve the quality of the free surface 10a of the thin layer 10.

[0093] In addition, step e) may include chemical mechanical polishing (CMP) and / or chemical treatment (etching or cleaning) and / or mechanical treatment (grinding) of the back surface 20b of the carrier substrate 20. Such treatment makes it possible to improve the uniformity of the thickness of the carrier substrate 20 and also to improve the roughness of its back surface 20b. To fabricate a vertical component, a roughness of less than 0.5 nm RMS (measured by using an atomic force microscope (AFM) on a 20 micron×20 micron field) is required, and for this purpose, at least one metal electrode will be present on the back surface 20b of the composite substrate 1.

[0094] It should be noted that these treatments applied to the back surface 20b of the carrier substrate 20 can optionally be carried out before the separation step d) (i.e., before the front surface 10a of the composite structure 1 is exposed) to limit its contamination, especially during contaminating or restrictive treatments such as chemical etching or mechanical polishing (or mechanical grinding).

[0095] During this step e), polishing or grinding can also be performed on the edges of the composite structure 1 to make the shape of its circular profile and the shape of the edge scrap compatible with the requirements of the microelectronic manufacturing method.

[0096] According to an advantageous embodiment, the chemical mechanical treatment step e) includes simultaneous polishing (CMP) of the front surface 10a and the back surface 20b of the composite structure 1 to smooth the structure 1 and improve the uniformity of the thickness of the structure 1. The polishing parameters between the front surface 10a and the back surface 20b can be different, so that the smoothing of the c-SiC surface and the p-SiC surface generally requires different consumables. When the carrier substrate 20 is made of p-SiC, the mechanical component of the polishing is particularly beneficial to the back surface 20b to limit the preferential attack of the chemical composition of the polishing on the grain boundaries. For example, in order to highlight the mechanical component, polishing parameters such as rotational speed (plate and polishing head), pressure, concentration, and the physical properties of the abrasive (i.e., the diameter of the diamond nanoparticles is between about 10 nm and 1 μm) can be modified.

[0097] Still according to an advantageous embodiment, after step e), a step e') of performing a heat treatment at a temperature between 1000 °C and 1800 °C for about one hour and up to several hours is carried out. The purpose of this step is to stabilize the composite structure 1 by repairing the structural or surface defects still present in and / or on the thin layer 10, and, if appropriate, to make the composite structure 1 compatible with the high-temperature heat treatment required for manufacturing components on the thin layer 10 subsequently by changing the crystal structure of the carrier substrate 20.

[0098] The method according to the invention may include a step f) of epitaxially growing an additional layer 10' of single-crystalline silicon carbide on the thin layer 10 of the composite structure 1 ( Figure 2f ). This step is applied when the component manufacturing requires a working layer 100 of a relatively large thickness (usually about 5 μm to 50 μm). The epitaxial conditions may optionally be selected to be similar to the epitaxial conditions of step a), preferably at a lower temperature, to limit the stress induced in the working layer 100 (which corresponds to the assembly of the thin layer 10 and the additional layer 10') due to the heterogeneous materials of the composite structure 1.

[0099] Finally, the manufacturing method may include a step of repairing the remaining part 111' of the donor substrate for the purpose of reusing it as the initial substrate 11 or the donor substrate 111. Such a repair step is based on one or more treatments of the surface 110'a ( Figure 2d ) by surface or edge chemical mechanical polishing, and / or by mechanical grinding, and / or by dry or wet chemical etching. Preferably, the thickness of the donor layer 110 formed in step a) is defined such that the remaining part 111' of the donor substrate 111 can be reused as the donor substrate 111 at least twice. Preferably, when there is a conversion layer 13, care is taken to keep the layer intact, that is, to always keep a part of the donor layer 10 on the remaining part 111' of the donor substrate. Thus, when the part of the donor layer 10 is not sufficient to prepare the composite structure 1, only the epitaxial growth step of the donor layer 10 is necessary, and the previous growth step of the conversion layer 13 is unnecessary.

[0100] Example:

[0101] According to a non-limiting exemplary embodiment, the initial substrate 11 is a 4H polytype c-SiC wafer, oriented at 4.0° ± 0.5° with respect to the <11-20> axis, having a diameter of 150 mm and a thickness of 350 μm.

[0102] Before the epitaxial growth of the donor layer 110 made of c-SiC, a conventional RCA-type cleaning procedure (Standard Clean 1 + Standard Clean 2) is performed on the initial substrate 11, followed by Caro's acid (a mixture of sulfuric acid and hydrogen peroxide), and then HF (hydrofluoric acid).

[0103] In the epitaxial chamber at a temperature of 1650 °C, growth is performed using precursors such as silane (SiH 4 ) and propane (C 3 H 8 ) or ethylene (C 2 H 4 ) to produce a donor layer 110 made of c-SiC with a thickness of 30 µm (growth rate: 10 µm / h). The donor layer exhibits a density of BPD defects of approximately 1 / cm 2 .

[0104] Hydrogen ions are implanted through the free surface of the donor layer 110 at an energy of 150 keV and an implantation dose of 6 E 16 H + / cm 2 . A buried weak plane 12 is thus created at a depth of approximately 800 nm in the donor layer 110.

[0105] An RCA + Caro's acid type cleaning procedure is performed on the donor substrate 111 to remove potential contaminants on the free surface of the donor layer 110.

[0106] On the donor layer 110 at a temperature of 700 °C, using the methylsilane (MS) (CH 3 SiH 3 ) precursor, the first LPCVD deposition is performed for 60 minutes at a pressure of 3.7 Torr to achieve a thickness of 50 µm for the first carrier layer 20'. Under these conditions, the support layer 20' is made of polycrystalline SiC.

[0107] On the first carrier layer 20' at a temperature of 800 °C, using the MS precursor, the second LPCVD deposition is performed for 30 minutes at a pressure of 4 Torr to achieve a thickness of 100 µm for the second carrier layer 20' made of p-SiC.

[0108] On the second carrier layer 20' at a temperature of 850 °C, using the MS precursor, the third LPCVD deposition is performed for 45 minutes at a pressure of 4 Torr to achieve a thickness of 250 µm for the third carrier layer 20' made of p-SiC.

[0109] The carrier substrate 20 formed by stacking three carrier layers 20' exhibits a thickness of 400 µm.

[0110] Subsequently, an annealing at 1000 °C for 50 minutes is applied to the stack 211 formed by the donor substrate 111 and the carrier substrate 20. During said annealing, separation is performed at the layer burying the fragile plane 12. At the end of this separation step d), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the remaining part 111' of the donor substrate.

[0111] At the rear surface 20b of the carrier substrate 20, a thickness of approximately 50 micrometers is removed. Then, double-sided polishing is performed to restore the surface roughness of the rear surface 20b of the thin layer 10 and the carrier substrate 20.

[0112] Of course, the present invention is not limited to the described embodiments and examples, and alternative embodiments can be introduced without departing from the scope of the present invention defined by the claims.

Claims

1. A method for manufacturing a composite structure (1) comprising a thin layer (10) made of single-crystalline silicon carbide disposed on a carrier substrate (20) made of silicon carbide, the method comprising: step a) of providing a donor substrate (111) made of single-crystalline silicon carbide, the donor substrate (111) comprising a donor layer (110) produced by epitaxial growth on an initial substrate (11), the donor layer (110) exhibiting a density of crystal defects lower than that of the initial substrate (11); step b) of implanting light solid ions into the donor layer (110) to form a buried fragile plane (12), thereby defining a thin layer (10) between the buried fragile plane (12) and the free surface of the donor layer (110); step c) of sequentially forming n carrier layers (20'), where n is greater than or equal to 2; the n carrier layers (20') are arranged on the donor layer (110) in sequence with each other and form the carrier substrate (20); each forming step includes chemical vapor deposition at a temperature between 400 °C and 1100 °C to form a carrier layer (20') made of polycrystalline silicon carbide; the n chemical vapor depositions are performed at n different temperatures; step d) of separating along the buried fragile plane (12), on the one hand, to form a composite structure (1) comprising the thin layer (10) on the carrier substrate (20), and on the other hand, to form the remaining part (111') of the donor substrate; step e) of mechanically and / or chemically treating the composite structure (1) to smooth the free surface (10a) of the thin layer (10) and / or to correct the thickness uniformity of the composite structure (1).

2. The manufacturing method according to the preceding claim, wherein, the deposition of step c) is performed at a temperature between 600 °C and 900 °C, actually even preferably between 700 °C and 800 °C.

3. The manufacturing method according to any one of the preceding claims, wherein, the deposition of step c) is based on atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition techniques.

4. The manufacturing method according to one of the preceding claims, wherein, the n depositions of step c) are performed at n increasing temperatures.

5. The manufacturing method according to one of claims 1 to 3, wherein, the n depositions of step c) are performed at n decreasing temperatures.

6. The manufacturing method according to one of the preceding claims, wherein, at least two of the n carrier layers (20') deposited in step c) exhibit different doping levels.

7. The manufacturing method according to one of the preceding claims, wherein, at the end of the deposition of step c), the carrier substrate (20) exhibits a thickness greater than or equal to 50 microns, greater than or equal to 100 microns, actually even greater than or equal to 200 microns.

8. The manufacturing method according to one of the preceding claims, wherein, Step a) includes forming a single-crystal conversion layer (13) on the initial substrate (11) before epitaxial growth of the donor layer (110) to convert basal plane dislocation-type defects of the initial substrate (11) into epitaxial layer edge dislocation-type defects.

9. The manufacturing method according to one of the preceding claims, wherein, in step a), the epitaxial growth of the donor layer (110) is carried out at a temperature greater than 1200 °C, preferably between 1500 °C and 1650 °C.

10. The manufacturing method according to one of the preceding claims, wherein, in step c), at least one of the steps of forming the n carrier layers (20') includes annealing performed after chemical vapor deposition of the step, and the annealing temperature is higher than the deposition temperature and lower than the separation temperature liable to cause the separation in step d).

11. The manufacturing method according to one of the preceding claims, wherein, between step c) and step d), chemical etching, mechanical grinding, and / or chemical mechanical polishing are applied to the rear surface (20b) of the carrier substrate (20).

12. The manufacturing method according to one of the preceding claims, wherein, after the separation in step d), a new chemical vapor deposition is carried out to thicken the carrier substrate (20).

13. The manufacturing method according to one of the preceding claims, wherein, step e) includes simultaneously performing chemical mechanical polishing on the front surface (10a) and the rear surface (20b) of the composite structure (1).

14. The manufacturing method according to one of the preceding claims, which includes a step of repairing the remaining part (111') of the donor substrate for the purpose of reusing it as the initial substrate (11) or the donor substrate (111).

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