Calibratable Invasive Semiconductor Brain-Computer Interface Channel Circuit and Brain-Computer Device

Abstract

The present invention provides a calibratable invasive semiconductor brain-computer interface channel circuit and an invasive semiconductor brain-computer device, relating to the field of integrated circuits. It includes: a voltage-current conversion unit that converts the received electroencephalogram signal into a corresponding current signal and transmits it to an oscillator conversion unit; the oscillator conversion unit converts the current signal into an oscillation signal and a phase signal with a corresponding relationship; a counting unit counts the oscillation signal to obtain the corresponding number of oscillations; at the end of the integration period, a Gray code to binary unit samples the number of oscillations to obtain a coarse quantization code value, and a phase sampling unit samples the phase signal, so that a decoding unit decodes the sampling result of the phase sampling unit to obtain a fine quantization code value; a calibration unit calibrates the coarse quantization code value and the fine quantization code value to obtain a quantization result. The present invention improves the reliability of analog-to-digital conversion of invasive semiconductor brain-computer devices and greatly reduces the pixel area and power consumption of invasive semiconductor brain-computer devices.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular, to a calibratable invasive semiconductor brain-computer interface channel circuit and an invasive semiconductor brain-computer device. Background Art

[0002] A brain-computer interface system can be used to detect the brain potential changes that occur when neurons trigger thoughts or actions, convert these signals into digital signals, and transmit them to machines such as wheelchairs, prosthetics, signal analysis systems, etc. It can be used for: ① better understanding the mechanisms of some brain diseases: Alzheimer's disease, Parkinson's disease, epilepsy, autism, etc. ② reconstructing sensory or motor functions: cochlear implants for deaf patients, prosthetics for amputees, wheelchairs for paralyzed patients, etc.

[0003] The invasive brain-computer interface in the brain-computer interface system can detect the potential changes of individual neurons in the brain and obtain more information. However, implanting electrodes into the brain requires ensuring their safety. Therefore, in order to protect the brain, it is necessary to minimize the size of the invasive object, minimize noise as much as possible, and reduce power consumption as much as possible to suppress electrode heating. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a calibratable invasive semiconductor brain-computer interface channel circuit and an invasive semiconductor brain-computer device that solve the above problems or partially solve the above problems.

[0005] In the first aspect of the embodiments of the present invention, a calibratable invasive semiconductor brain-computer interface channel circuit is provided. The invasive semiconductor brain-computer interface channel circuit includes: a plurality of single channels and a base. Each single channel includes: a voltage-current conversion unit, an oscillator conversion unit, and a counting unit;

[0006] The base includes: a Gray code to binary unit, a phase sampling unit, a decoding unit, and a calibration unit;

[0007] The voltage-current conversion unit converts the received electroencephalogram signal into a corresponding current signal and transmits it to the oscillator conversion unit;

[0008] The oscillator conversion unit converts the current signal into an oscillation signal and a phase signal with a corresponding relationship;

[0009] The counting unit counts the oscillation signal to obtain a corresponding number of oscillations;

[0010] At the end of the integration period, the Gray code to binary unit samples the number of oscillations to obtain a coarse quantization code value and transmits the coarse quantization code value to the calibration unit;

[0011] At the end of the integration period, the phase sampling unit samples the phase signal, so that the decoding unit decodes the sampling result of the phase sampling unit to obtain a fine quantization code value, and transmits the fine quantization code value to the calibration unit;

[0012] The calibration unit calibrates the coarse quantization code value and the fine quantization code value to obtain a quantization result, and the quantization result characterizes the analog-to-digital conversion result of the electroencephalogram signal;

[0013] Wherein, a plurality of the single channels correspond to one base, that is, the oscillation times and phase signals obtained by each of the plurality of single channels are respectively sampled by the Gray code to binary unit and the phase sampling unit in one base.

[0014] Optionally, the voltage-current conversion unit includes: a high-pass filter, a transconductance module;

[0015] The high-pass filter receives the electroencephalogram signal, filters the electroencephalogram signal to obtain an accurate voltage signal and transmits it to the transconductance module;

[0016] The transconductance module converts the accurate voltage into a corresponding current signal and transmits it to the oscillator conversion unit.

[0017] Optionally, the oscillator conversion unit includes: a multi-stage differential inverter, and the multi-stage differential inverter forms a ring oscillator structure;

[0018] The number of stages of the multi-stage differential inverter is determined by the number of bits of fine quantization, and the number of bits of fine quantization is equal to the number of stages of the multi-stage differential inverter;

[0019] The multi-stage differential inverter receives the current signal and generates the oscillation signal according to the current signal. The magnitude of the current signal is different, the frequency of the generated oscillation signal is different, and the corresponding number of oscillations is also different;

[0020] The multi-stage differential inverter receives the current signal and generates the phase signal according to the current signal. During the oscillation process of the multi-stage differential inverter, when in different phases, the levels of the two output points of each stage of the inverter are different.

[0021] Optionally, the structure of the multi-stage differential inverter includes: an RS flip-flop composed of a plurality of AND gates, or an RS flip-flop composed of a plurality of OR gates, or a single-ended inverter composed of a plurality of single-ended inverters;

[0022] Among them, for multi-stage differential inverters with different structures, the level relationships of each point of each stage of the inverter are different. The duty cycle of the RS flip-flop composed of a plurality of AND gates is slightly greater than 1 / 2, and the duty cycle of the RS flip-flop composed of a plurality of OR gates is slightly less than 1 / 2.

[0023] Optionally, if the number of bits of the quantization is 4, and the structure of the multi-stage double-ended inverter is an RS flip-flop composed of the multiple AND gates, then the structure of the multi-stage double-ended inverter is an RS flip-flop composed of 4 AND gates;

[0024] The RS trigger composed of the four AND gates has a level relationship between each point during the oscillation operation: A<1:8> represents the level of the eight output points of the four AND gates, which cycles in sequence with 16 states. When the level is high, its code value is regarded as "1", and when the level is low, its code value is regarded as "0". Then A<1:8> is repeated according to the 16 code values, and A<1:8> is repeated in sequence. <7> As the benchmark, when A <7> One oscillation is regarded as one cycle of the oscillator conversion unit, and the A<1:8> code value corresponding to the first phase of one cycle is: 01010101, the second code value is: 11010101, and the remaining code values ​​are deduced by analogy.

[0025] Optionally, the transconductance module operates in a subthreshold region to reduce power consumption; the transconductance module comprises: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NOMS tube, and a third NMOS tube, wherein the second PMOS tube, the third PMOS tube, the second NOMS tube, and the third NMOS tube together constitute a small transconductance unit;

[0026] The gate of the second PMOS tube and the gate of the second NMOS tube both receive the precise voltage;

[0027] The source of the second PMOS tube and the source of the third PMOS tube are both connected to the drain of the first PMOS tube;

[0028] The gate of the first PMOS tube and the gate of the fourth PMOS tube both receive a first bias voltage;

[0029] The source of the first PMOS tube and the source of the fourth PMOS tube both receive a high level VDD;

[0030] The drain of the second PMOS tube and the drain of the second NMOS tube are both connected to the gate of the first NMOS tube;

[0031] Grounding of the source of the first NMOS tube;

[0032] The source of the second NMOS tube and the source of the third NMOS tube are both connected to the drain of the first NMOS tube;

[0033] The gate of the third PMOS tube and the gate of the third NMOS tube both receive a reference voltage;

[0034] The drains of the third PMOS transistor and the third NMOS transistor output the output current of the small transconductance unit, and are both connected to the drain of the fourth PMOS transistor;

[0035] The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor;

[0036] The gate of the fifth PMOS transistor receives a second bias voltage, and the drain of the fifth PMOS transistor outputs the current signal.

[0037] Optionally, the counting unit includes: a horizontal displacement module and a Gray code counter;

[0038] The horizontal displacement module boosts the amplitude of the oscillation signal and transmits the oscillation signal with the boosted amplitude to the Gray code counter;

[0039] The Gray code counter counts the oscillation signal with the boosted amplitude to obtain the corresponding number of oscillations;

[0040] In addition to outputting integer bits, the Gray code counter can also output a 1 / 2 bit, and the output 1 / 2 bit is used for the calibration process of the calibration unit.

[0041] Optionally, the Gray code to binary unit samples the number of oscillations, lagging behind the phase sampling unit sampling the phase signal;

[0042] When the 1 / 2 bit output by the Gray code counter is 0, the corresponding margin is 0 to 0.5, that is, corresponding to the 1st phase to the 8th phase;

[0043] When the 1 / 2 bit output by the Gray code counter is 1, the corresponding margin is 0.5 to 1, that is, corresponding to the 9th phase to the 16th phase;

[0044] The Gray code to binary unit samples the number of oscillations, lagging behind the phase sampling unit sampling the phase signal, such that the coarse quantization code value lags behind the fine quantization code value. When the 1 / 2 bit output by the Gray code counter is 1, that is, when the fine quantization code value D<4:1> is 0000 to 0111, the 1 / 2 bit output by the Gray code counter is 1;

[0045] The calibration unit determines whether an error code occurs based on whether D<4> in the fine quantization code value and the 1 / 2 bit output by the Gray code counter are both 1. When an error code occurs, the coarse quantization code value is incremented by 1, otherwise the coarse quantization code value remains unchanged.

[0046] Optionally, the current signal I CCO has the following expression:

[0047] ΔI C0 = (gm P1 + gm P2 + gm N1 + gm N1 )ΔV N = Gm*ΔV N

[0048] I CCO = I C0 + Gm*ΔV N

[0049] Wherein, ΔI C0 is the output current of the small transconductance unit, gm P1 , gm P2 , gm N1 , gm N2 are the small-signal transconductances of the second PMOS transistor, the third PMOS transistor, the second NMOS transistor, and the third NMOS transistor respectively, Gm = gm P1 + gm P2 + gm N1 + gm N2 , ΔV N is the change amount of the precise voltage, and I C0 is the bias current.

[0050] In the second aspect of the embodiments of the present invention, an invasive semiconductor brain-computer device is provided, and the invasive semiconductor brain-computer device includes the invasive semiconductor brain-computer interface channel circuit according to any one of the first aspect.

[0051] For the calibratable invasive semiconductor brain-computer interface channel circuit provided by the present invention, the voltage-current conversion unit converts the received electroencephalogram signal into a corresponding current signal and transmits it to the oscillator conversion unit; the oscillator conversion unit converts the current signal into an oscillation signal and a phase signal with a corresponding relationship; the counting unit counts the oscillation signal to obtain a corresponding number of oscillations.

[0052] At the end of the integration period, the Gray code to binary unit samples the number of oscillations to obtain a coarse quantization code value and transmits the coarse quantization code value to the calibration unit; at the end of the integration period, the phase sampling unit samples the phase signal so that the decoding unit decodes the sampling result of the phase sampling unit to obtain a fine quantization code value and transmits the fine quantization code value to the calibration unit; the calibration unit calibrates the coarse quantization code value and the fine quantization code value to obtain a quantization result, and the quantization result represents the analog-to-digital conversion result of the electroencephalogram signal.

[0053] The present invention directly uses a phase sampling unit to sample a phase signal to achieve fine quantization. Essentially, the fine quantization process is built on top of the coarse quantization process, but the entire circuit only adds the sampling process without increasing the complexity of the entire circuit, reducing the pixel area and power consumption. In addition, it also has a self-calibration function, improving the reliability of the data. While overall improving the reliability of the analog-to-digital conversion of invasive semiconductor brain-computer devices, it extremely reduces the pixel area and power consumption of the semiconductor brain-computer devices and suppresses electrode heating. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0055] Figure 1 is a schematic structural diagram of a preferred high-pass filter and transconductance module in an embodiment of the present invention;

[0056] Figure 2 is a schematic structural diagram of a preferred calibratable invasive semiconductor brain-computer interface channel circuit in an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of the level relationship between points A<1> to A<8> during the oscillation operation of an RS flip-flop composed of 4 AND gates in an embodiment of the present invention;

[0058] Figure 4 is the corresponding relationship between the code values corresponding to the levels A<1:8> and the coarse quantization code values in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0060] The calibratable invasive semiconductor brain-computer interface channel circuit of the present invention includes: multiple single channels and a base. Each single channel includes: a voltage-current conversion unit, an oscillator conversion unit, and a counting unit. The base includes: a Gray code-to-binary unit, a phase sampling unit, a decoding unit, and a calibration unit. Generally, an invasive semiconductor brain-computer uses a needle to penetrate into the human brain to obtain electroencephalogram (EEG) signals. The front end of the needle is provided with a very large number of single channels to fully obtain multi-directional and different types of EEG signals in the brain. The volume of the rear end of the needle is relatively large compared to the front end, which is not conducive to penetrating the brain. Therefore, the base is arranged at the rear end of the needle. Generally, multiple single channels correspond to one base, that is, the oscillation times and phase signals obtained by each single channel among the multiple single channels are respectively sampled by the Gray code-to-binary unit and the phase sampling unit in one base. Specifically, how many single channels correspond to one base can be determined according to actual needs. For example, 128 single channels correspond to 1 base, 64 single channels correspond to 1 base, etc.

[0061] In the embodiment of the present invention, during the working process of the calibratable invasive semiconductor brain-computer interface channel circuit, the voltage-current conversion unit converts the received EEG signal into a corresponding current signal and transmits it to the oscillator conversion unit; the oscillator conversion unit converts the current signal into an oscillation signal and a phase signal with a corresponding relationship. The counting unit counts the oscillation signal to obtain the corresponding oscillation times.

[0062] At the end of the integration period, the Gray code-to-binary unit samples the oscillation times to obtain a coarse quantization code value and transmits the coarse quantization code value to the calibration unit; at the same time, at the end of the integration period, the phase sampling unit samples the phase signal, so that the decoding unit decodes the sampling result of the phase sampling unit to obtain a fine quantization code value and transmits the fine quantization code value to the calibration unit; the calibration unit calibrates the coarse quantization code value and the fine quantization code value to obtain a quantization result, and this quantization result represents the analog-to-digital conversion result of the EEG signal.

[0063] To more clearly illustrate the calibratable invasive semiconductor brain-computer interface channel circuit of the embodiment of the present invention, the following takes a relatively optimal structural form as an example to illustrate the calibratable invasive semiconductor brain-computer interface channel circuit of the embodiment of the present invention. For example: the voltage-current conversion unit includes: a high-pass filter, a transconductance module; the oscillator conversion unit includes: a multi-stage differential inverter, and the multi-stage differential inverter forms a ring oscillator structure; the counting unit includes: a horizontal displacement module and a Gray code counter.

[0064] For a single channel, there is the following working mode: the high-pass filter (H-P) receives the EEG signal, filters the EEG signal, and filters out the unwanted low-frequency stimulus artifacts in the EEG signal, so as to obtain an accurate voltage signal V NAnd it is transmitted to the transconductance module. Since signals less than 1 Hz need to be filtered out, the resistance value in the high-pass filter needs to reach the order of hundreds of megohms. Generally, pseudo-resistors are used to replace the resistors to reduce the area of the high-pass filter.

[0065] The transconductance module converts the precise voltage V N into a corresponding current signal I CCO and transmits it to the oscillator conversion unit. The transconductance module operates in the subthreshold region to reduce power consumption. Refer to Figure 1 which shows a schematic structural diagram of a preferred high-pass filter and transconductance module in an embodiment of the present invention. Figure 1 It includes: a high-pass filter H-P and a transconductance module. Among them, the high-pass filter H-P receives the electroencephalogram signal V in and the reference voltage signal V CM , uses the capacitor C and the pseudo-resistor R pseudo for filtering to obtain the precise voltage signal V N and transmits it to the transconductance module.

[0066] A preferred transconductance module in an embodiment of the present invention includes: a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, a first NMOS transistor NN0, a second NOMS transistor MN1, and a third NMOS transistor MN2.

[0067] The gates of the second PMOS transistor MP1 and the second NMOS transistor MN1 both receive the precise voltage V N ; the sources of the second PMOS transistor MN1 and the third PMOS transistor MP2 are both connected to the drain of the first PMOS transistor MP0; the gates of the first PMOS transistor MN0 and the fourth PMOS transistor MP3 both receive the first bias voltage V B1 .

[0068] The sources of the first PMOS transistor MP0 and the fourth PMOS transistor MP3 both receive the high level VDD; the drains of the second PMOS transistor MP1 and the second NMOS transistor MN1 are both connected to the gate of the first NMOS transistor MN0; the source of the first NMOS transistor MN0 is grounded. The sources of the second NMOS transistor MN1 and the third NMOS transistor MN2 are both connected to the drain of the first NMOS transistor MN0.

[0069] The gates of the third PMOS transistor MP2 and the third NMOS transistor MN2 both receive the reference voltage V CM ; the drains of the third PMOS transistor MP2 and the third NMOS transistor MN2 output the output current ΔI C0 of the transconductance and are both connected to the drain of the fourth PMOS transistor MP3.

[0070] The drain of the fourth PMOS transistor MP3 is connected to the source of the fifth PMOS transistor MP4; the gate of the fifth PMOS transistor MP4 receives the second bias voltage V B3 , and the drain of the fifth PMOS transistor MP4 outputs a current signal I CCO .

[0071] Based on the above structure, it can be known that the current signal I CCO has the following expression:

[0072] ΔI C0 =(gm P1 +gm P2 +gm N1 +gm N1 )ΔV N =Gm*ΔV N

[0073] I CCO =I C0 +Gm*ΔV N

[0074] where, ΔI C0 is the output current of the small transconductance unit, gm P1 , gm P2 , gm N1 , gm N2 are the small-signal transconductances of the second PMOS transistor, the third PMOS transistor, the second NMOS transistor, and the third NMOS transistor respectively, Gm = gm P1 +gm P2 +gm N1 +gm N2 , ΔV N is the change amount of the precise voltage, and I C0 is the bias current.

[0075] The oscillator conversion unit includes: a multi-stage differential inverter, and the multi-stage differential inverter forms a ring oscillator structure; the number of stages of the multi-stage differential inverter is determined by the number of bits of quantization, and the number of bits of quantization is equal to the number of stages of the multi-stage differential inverter; the multi-stage differential inverter receives the current signal I CCO , and generates an oscillation signal according to the current signal I CCO . Different magnitudes of the current signal I CCO generate oscillation signals with different frequencies, and the corresponding number of oscillation times is also different.

[0076] At the same time, the multi-stage differential inverter receives the current signal I CCO , and generates a phase signal according to the current signal I CCO . During the oscillation process of the multi-stage differential inverter, when it is in different phases, the levels of the two output points of each stage of the inverter are different.

[0077] In an embodiment of the present invention, the structure of the multi-stage dual-terminal inverter includes: an RS flip-flop composed of multiple AND gates, or an RS flip-flop composed of multiple OR gates, or a dual-terminal inverter composed of multiple single-terminal inverters; wherein, for multi-stage dual-terminal inverters with different structures, the level relationships of each point of each stage inverter are different. The duty cycle of the RS flip-flop composed of multiple AND gates is slightly greater than 1 / 2, and the duty cycle of the RS flip-flop composed of multiple OR gates is slightly less than 1 / 2.

[0078] Taking the case where the number of bits of fine quantization is 4 and the structure of the multi-stage dual-terminal inverter is an RS flip-flop composed of multiple AND gates as an example, the structure of the multi-stage dual-terminal inverter is an RS flip-flop composed of 4 AND gates. For the RS flip-flop composed of 4 AND gates, the level relationships between each point during the oscillation operation are as follows: Let A<1:8> represent the levels of the 8 output points of the 4 AND gates, which cycle in order with 16 states. When the level is high, its code value is regarded as "1", and when the level is low, its code value is regarded as "0". Then A<1:8> cycles and repeats according to 16 groups of code values. Taking A<7> as a reference, when A<7> oscillates once, it is regarded as one cycle of the oscillator conversion unit. Then the code value of A<1:8> corresponding to the first phase of one cycle is: 01010101, and the second code value is: 11010101, and the remaining code values are deduced by analogy.

[0079] In an embodiment of the present invention, since the Gray code counter belongs to digital circuits, and the oscillation signal generated by the oscillation unit is an analog signal, its value cannot meet the requirements of digital circuits, resulting in the inability of the Gray code counter to count the oscillation signal. Therefore, a horizontal displacement module is required to increase the amplitude of the oscillation signal and transmit the oscillation signal with increased amplitude to the Gray code counter. The Gray code counter counts the oscillation signal with increased amplitude to obtain the corresponding number of oscillation times. In addition to outputting integer bits, the Gray code counter can also output a 1 / 2 bit, and this output 1 / 2 bit is used for the calibration process of the calibration unit.

[0080] According to the current signal I CCO With different magnitudes, the frequencies of the oscillation signals are also different. For the integration period T, according to the conservation of charge, there is:

[0081]

[0082] where n is the number of oscillation times of the oscillation signal generated by the oscillator conversion unit within the integration period T, is the remaining phase, Q u is the amount of charge transferred by the oscillator conversion unit for one oscillation, which is a fixed value. The oscillation signal of the oscillator conversion unit records the number of oscillation times K through the Gray code counter.

[0083] At the end of the integration period T, the base will sample the code value of the Gray code counter and convert it into a binary code value through the Gray code to binary unit, that is, the coarse quantization code value. The reason for using the Gray code counter is that only one bit of the Gray code value will flip during one count, and the flipping probability is half that of the binary counter. This can not only reduce power consumption but also reduce the error rate. At the same time, the Gray code counter can output 1 / 2 bits, which can be used for subsequent calibration processes.

[0084] Since the Gray code to binary unit samples the code value of the Gray code counter and needs to pass through the horizontal displacement module and the Gray code counter, while the phase sampling unit directly samples the phase signal, the Gray code to binary unit samples the oscillation times, lagging behind the phase sampling unit sampling the phase signal. Taking the aforementioned 4-bit fine quantization as an example: when the 1 / 2 bit output by the Gray code counter is 0, the corresponding margin is 0 to 0.5, that is, corresponding to the 1st phase to the 8th phase; when the 1 / 2 bit output by the Gray code counter is 1, the corresponding margin is 0.5 to 1, that is, corresponding to the 9th phase to the 16th phase.

[0085] The Gray code to binary unit samples the oscillation times, lagging behind the phase sampling unit sampling the phase signal, which makes the coarse quantization code value lag behind the fine quantization code value. When the 1 / 2 bit output by the Gray code counter is 1, that is, when the fine quantization code value D<4:1> is 0000 to 0111, the 1 / 2 bit output by the Gray code counter is 1; the calibration unit determines whether an error occurs based on whether D<4> in the fine quantization code value and the 1 / 2 bit output by the Gray code counter are both 1 at the same time. When an error occurs, the coarse quantization code value is incremented by 1, otherwise the coarse quantization code value remains unchanged.

[0086] In addition, for determining whether an error occurs, other methods can also be used. For example: since the delay of the horizontal displacement module and the Gray code counter is limited, the maximum delay may not exceed the time of two or three phases. It can also be determined whether there is an error by judging whether the 1 / 2 bit output by the Gray code is 1 and whether the fine quantization code value D<4:1> is in the first two (0000 to 0001) or the first three (0000 to 0010) phases.

[0087] Refer to Figure 2 , which exemplarily shows the structural schematic diagram of the preferred calibratable invasive semiconductor brain-computer interface channel circuit of the embodiment of the present invention. Figure 1 The same structures that are currently known are not specifically described. The calibratable invasive semiconductor brain-computer interface channel circuit includes: a single channel 10, a base 20. Figure 1 In

[0088] The single channel 10 includes: a high-pass filter H-P, a transconductance module GM, an oscillator conversion unit CCO composed of an RS flip-flop formed by 4 AND gates, a level shift module Level Shift, and a Gray code counter G. The base 20 includes: a phase sampling unit Psu, a Gray code to binary unit G-B, a decoding unit Du, and a calibration unit Cau.

[0089] The electroencephalogram signal Vin first passes through the high-pass filter H-P to filter out the unwanted low-frequency stimulus artifacts in the electroencephalogram signal to obtain the precise voltage V N . Since signals less than 1 Hz need to be filtered out, the resistance value in H-P needs to reach the order of hundreds of megohms. Generally, a pseudo-resistor ( Figure 1 R in pseudo ) is used to replace the resistor to reduce the area of the high-pass filter H-P. This precise voltage signal V N is then converted into the corresponding current signal I through the transconductance module GM CCO . The current signal I CCO is transmitted to the oscillator conversion unit CCO.

[0090] The oscillator conversion unit CCO generates an oscillation signal and a phase signal. For example, Figure 2 taking the fine quantization bit number as 4 as an example, the oscillator conversion unit CCO at this time is a ring oscillator structure composed of 4 stages of differential inverters, that is, an RS flip-flop formed by 4 AND gates. The two output points of each AND gate are represented by A<1> to A<8> respectively. The level relationship between points A<1> to A<8> during the oscillation operation of the RS flip-flop formed by 4 AND gates is as Figure 3 shown, and the corresponding relationship between the code values corresponding to the levels A<1:8> and the coarse quantization code values is as Figure 4 shown. The levels A<1:8> corresponding to the phase signal cycle in sequence in 16 states. When the level is high, its code value is regarded as "1", and when the level is low, its code value is regarded as "0", then A<1:8> cycles and repeats according to 16 groups of code values. Taking A<7> as the reference, when A<7> oscillates once, it is regarded as one cycle of the oscillator conversion unit. Then the A<1:8> code value corresponding to the first phase of one cycle is: 01010101, and the second code value is: 11010101. The rest can be obtained by analogy to get the code values corresponding to all 16 states. Among them, D<4:1> represents which phase the A<1:8> code value corresponds to, that is, the fine quantization code value. When the integration period T ends, the phase sampling unit Psu samples the levels of each point of A<1:8> and transmits them to the decoding unit Du for decoding to obtain the 4-bit fine quantization code value ( Figure 2 D<4:1> in

[0091] For coarse quantization, after the amplitude of the oscillation signal is increased by the level shift module Level Shift, the Gray code counter G counts the number of oscillations of the oscillation signal with the increased amplitude. At the end of the integration period T, the Gray code to binary unit G-B samples the code value of the Gray code counter ( Figure 2 G<13:5> in), and converts it to a binary code value ( Figure 2 B<13:5> in), which is the coarse quantization code value.

[0092] The 4-bit code value D<4:1> of the fine quantization and the coarse quantization code value B<13:5> are transmitted to the calibration voltage Cau together. It can be Figure 2 known that the phase sampling unit Psu directly samples the phase signal. When the Gray code to binary unit G-B samples, the oscillation signal needs to pass through the level shift module Level Shift and the Gray code counter G. Although the sampling in the coarse quantization process and the fine quantization process is carried out simultaneously, due to the inherent delay of the level shift module Level Shift and the Gray code counter G, the coarse quantization code value may generate error codes, and the calibration unit Cau is required to eliminate this error code.

[0093] As described above, the sampling of the coarse quantization code value lags behind the sampling of the fine quantization code value. Therefore, only the lagging situation needs to be considered, that is, the fine quantization code value is already in a new oscillation period, but the oscillation count has not been incremented by 1. The 1 / 2 bit output by the Gray code counter G ( Figure 2 Flag is used to represent the flag bit corresponding to the output 1 / 2 bit in) is 1, that is, when the fine quantization code value D<4:1> is 0000 to 0111, the 1 / 2 bit output by the Gray code counter G is 1; the calibration unit Cau determines whether an error code occurs based on whether D<4> in the fine quantization code value and the 1 / 2 bit output by the Gray code counter G are both 1 at the same time. When an error code occurs, the coarse quantization code value is incremented by 1, otherwise the coarse quantization code value remains unchanged.

[0094] Based on the above-mentioned calibratable invasive semiconductor brain-computer interface channel circuit, an embodiment of the present invention further proposes an invasive semiconductor brain-computer device, and the infrared detection device includes the calibratable invasive semiconductor brain-computer interface channel circuit described in any one of the above.

[0095] Through the above examples, the calibratable invasive semiconductor brain-computer interface channel circuit provided by the present invention directly samples the phase signal by using the phase sampling unit to achieve fine quantization. In essence, the fine quantization process is established on the basis of the coarse quantization process, but only the sampling process is added to the entire circuit without increasing the complexity of the entire circuit, reducing the pixel area and power consumption. In addition, it also has a self-calibration function, improving the reliability of the data. While improving the reliability of analog-to-digital conversion of invasive semiconductor brain-computer devices as a whole, it extremely reduces the pixel area and power consumption of semiconductor brain-computer devices, and suppresses electrode heating.

[0096] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0097] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims. These all fall within the protection scope of the present invention.

Claims

1. A calibratable invasive semiconductor brain-computer interface channel circuit, characterized in that, the invasive semiconductor brain-computer interface channel circuit includes: a plurality of single channels and a base, and each single channel includes: a voltage-current conversion unit, an oscillator conversion unit, and a counting unit; the base includes: a Gray code to binary unit, a phase sampling unit, a decoding unit, and a calibration unit; the voltage-current conversion unit converts the received electroencephalogram signal into a corresponding current signal and transmits it to the oscillator conversion unit; the oscillator conversion unit converts the current signal into an oscillation signal and a phase signal with a corresponding relationship; the counting unit counts the oscillation signal to obtain a corresponding number of oscillations; at the end of the integration period, the Gray code to binary unit samples the number of oscillations to obtain a coarse quantization code value and transmits the coarse quantization code value to the calibration unit; at the end of the integration period, the phase sampling unit samples the phase signal so that the decoding unit decodes the sampling result of the phase sampling unit to obtain a fine quantization code value and transmits the fine quantization code value to the calibration unit; the calibration unit calibrates the coarse quantization code value and the fine quantization code value to obtain a quantization result, and the quantization result represents the analog-to-digital conversion result of the electroencephalogram signal; wherein, a plurality of the single channels correspond to one base, that is, the number of oscillations and the phase signal obtained by each of the plurality of single channels are respectively sampled by the Gray code to binary unit and the phase sampling unit in one base; wherein, the voltage-current conversion unit includes: a transconductance module, and the transconductance module operates in the subthreshold region to reduce power consumption; the transconductance module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. Among them, the second PMOS transistor, the third PMOS transistor, the second NMOS transistor, and the third NMOS transistor together form a small transconductance unit; the gates of the second PMOS transistor and the second NMOS transistor both receive a precise voltage; the sources of the second PMOS transistor and the third PMOS transistor are both connected to the drain of the first PMOS transistor; the gates of the first PMOS transistor and the fourth PMOS transistor both receive a first bias voltage; the sources of the first PMOS transistor and the fourth PMOS transistor both receive a high level VDD; the drains of the second PMOS transistor and the second NMOS transistor are both connected to the gate of the first NMOS transistor; the source of the first NMOS transistor is grounded; the sources of the second NMOS transistor and the third NMOS transistor are both connected to the drain of the first NMOS transistor; The gates of the third PMOS transistor and the third NMOS transistor both receive a reference voltage; the drains of the third PMOS transistor and the third NMOS transistor output the output current of the small transconductance unit and are both connected to the drain of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor; the gate of the fifth PMOS transistor receives a second bias voltage, and the drain of the fifth PMOS transistor outputs the current signal.

2. The invasive semiconductor brain-computer interface channel circuit according to claim 1, wherein, the voltage-current conversion unit further includes: a high-pass filter; the high-pass filter receives the electroencephalogram signal, filters the electroencephalogram signal to obtain an accurate voltage signal and transmits it to the transconductance module; the transconductance module converts the accurate voltage into a corresponding current signal and transmits it to the oscillator conversion unit.

3. The invasive semiconductor brain-computer interface channel circuit according to claim 2, wherein, the oscillator conversion unit includes: a multi-stage differential inverter, and the multi-stage differential inverter forms a ring oscillator structure; the number of stages of the multi-stage differential inverter is determined by the number of bits of fine quantization, and the number of bits of fine quantization is equal to the number of stages of the multi-stage differential inverter; the multi-stage differential inverter receives the current signal and generates the oscillation signal according to the current signal. The magnitude of the current signal is different, the frequency of the generated oscillation signal is different, and the corresponding number of oscillation times is also different; the multi-stage differential inverter receives the current signal and generates the phase signal according to the current signal. During the oscillation process of the multi-stage differential inverter, when it is in different phases, the levels of the two output points of each stage of the inverter are different.

4. The invasive semiconductor brain-computer interface channel circuit according to claim 3, wherein, the structure of the multi-stage differential inverter includes: an RS flip-flop composed of multiple AND gates, or an RS flip-flop composed of multiple OR gates, or a differential inverter composed of multiple single-ended inverters; wherein, for multi-stage differential inverters with different structures, the level relationships of each point of each stage of the inverter are different. The duty cycle of the RS flip-flop composed of multiple AND gates is slightly greater than 1 / 2, and the duty cycle of the RS flip-flop composed of multiple OR gates is slightly less than 1 / 2.

5. The invasive semiconductor brain-computer interface channel circuit according to claim 4, wherein, if the number of bits of fine quantization is 4 and the structure of the multi-stage differential inverter is the RS flip-flop composed of multiple AND gates, then the structure of the multi-stage differential inverter is an RS flip-flop composed of 4 AND gates; For the RS flip-flop composed of the four AND gates, the level relationships among various points during the oscillation operation are as follows: Let A<1:8> represent the levels of the eight output points of the four AND gates, which cycle in sequence through 16 states. When the level is high, its code value is regarded as "1", and when the level is low, its code value is regarded as "0". Then A<1:8> cycles and repeats according to 16 groups of code values. Taking A<7> as the reference, when A<7> oscillates once, it is regarded as one cycle of the oscillator conversion unit. The code value of A<1:8> corresponding to the first phase of one cycle is: 01010101, the second code value is: 11010101, and the remaining code values can be deduced by analogy.

6. The invasive semiconductor brain-computer interface channel circuit according to claim 5, wherein, the counting unit includes: a horizontal displacement module and a Gray code counter; the horizontal displacement module boosts the amplitude of the oscillation signal and transmits the oscillation signal with the boosted amplitude to the Gray code counter; the Gray code counter counts the oscillation signal with the boosted amplitude to obtain the corresponding number of oscillation times; in addition to outputting integer bits, the Gray code counter can also output a 1 / 2 bit, and this output 1 / 2 bit is used for the calibration process of the calibration unit.

7. The invasive semiconductor brain-computer interface channel circuit according to claim 6, wherein, the Gray code to binary unit samples the number of oscillation times, lagging behind the phase sampling unit in sampling the phase signal; when the 1 / 2 bit output by the Gray code counter is 0, the corresponding margin is 0 to 0.5, that is, corresponding to the 1st phase to the 8th phase; when the 1 / 2 bit output by the Gray code counter is 1, the corresponding margin is 0.5 to 1, that is, corresponding to the 9th phase to the 16th phase; the Gray code to binary unit samples the number of oscillation times, lagging behind the phase sampling unit in sampling the phase signal, such that the coarse quantization code value lags behind the fine quantization code value. When the 1 / 2 bit output by the Gray code counter is 1, that is, when the fine quantization code value D<4:1> is 0000 to 0111, the 1 / 2 bit output by the Gray code counter is 1; the calibration unit determines whether an error code occurs based on whether D<4> in the fine quantization code value and the 1 / 2 bit output by the Gray code counter are both 1. When an error code occurs, the coarse quantization code value is incremented by 1, and vice versa, the coarse quantization code value remains unchanged.

8. The invasive semiconductor brain-computer interface channel circuit according to claim 1, wherein, The current signal I CCO has the following expression: ΔI C0 = (gm P1 + gm P2 + gm N1 + gm N1 ) ΔV N = Gm * ΔV N I CCO = I C0 + Gm * ΔV N Among them, ΔI C0 is the output current of the small transconductance unit, gm P1 , gm P2 , gm N1 , gm N2 are the small-signal transconductances of the second PMOS transistor, the third PMOS transistor, the second NMOS transistor, and the third NMOS transistor respectively, Gm = gm P1 + gm P2 + gm N1 + gm N2 , ΔV N is the change amount of the precise voltage, I C0 is the bias current.

9. An invasive semiconductor brain-computer device, wherein, the invasive semiconductor brain-computer device includes the invasive semiconductor brain-computer interface channel circuit according to any one of claims 1-8.

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