Layout of a content-addressable memory cell structure

Abstract

The present invention provides a layout of a content addressable memory cell structure, including a transfer transistor pattern, which includes first to fifth transfer transistor patterns; a pull-down transistor pattern, which includes first and second pull-down transistor patterns; a pull-up transistor pattern, which includes first and second pull-up transistor patterns; the first, fourth transfer transistor patterns and the first pull-down transistor pattern are distributed in sequence, and the active region patterns of the first, fourth transfer transistor patterns and the first pull-down transistor pattern are connected together; the second pull-down transistor pattern, the fifth and third transfer transistor patterns are distributed in sequence, and the active region patterns of the second pull-down transistor pattern, the fifth, second and third transfer transistor patterns are connected together; the first and second pull-up transistor patterns are respectively arranged on one side of the first pull-down transistor pattern and the first pull-up transistor pattern, so that the transfer transistor pattern, the pull-down transistor pattern and the pull-up transistor pattern are asymmetrically distributed. The layout of the present invention uses an asymmetric layout structure, and the overall power consumption of the manufactured content addressable memory is lower.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a layout of a content addressable memory cell structure. Background Art

[0002] CAM is a special type of memory. That is, content addressable memory. Each memory cell of a CAM contains an embedded comparison logic. The data written into the CAM is compared with each data stored internally, and the addresses of all internal data identical to the port data are returned. Generally speaking, RAM (random access memory) is a memory cell that reads and writes data according to an address, while CAM is exactly the opposite. It returns the address that matches the content of the port data. CAM has a wide range of applications, such as the address switching table in a router, the Cache controller (Tag array) of a CPU, etc.

[0003] A CAM cell is formed by adding transistors that perform a matching function to a standard SRAM (static random access memory) cell structure. Multiple CAM cells included in the same word are connected to the same match line. The match line is pre-charged or pulled up to a high level to serve as a distributed pseudo-NMOS gate, and the key is placed on the bit line.

[0004] A schematic structural diagram of a 9-transistor content addressable memory in the prior art is as Figure 1 shown. Among them, the first pull-down transistor pattern M1 and the second pull-down transistor pattern M3 are N-type pull-down transistors, the first pull-up transistor pattern M2 and the second pull-up transistor pattern M4 are P-type pull-up transistors, the fourth transfer transistor pattern M5, the fifth transfer transistor pattern M6, the first transfer transistor pattern N1, the second transfer transistor pattern N2, and the third transfer transistor pattern N3 are N-type transfer transistors. The key and the cell data are exclusive-ORed through the first transfer transistor pattern N1 and the second transfer transistor pattern N2. If the key and the cell data are different, then the third transfer transistor pattern N3 is turned on, pulling down the level of the match line to a low level. However, the gate of the third transfer transistor pattern N3 is a reduced high logic level. The specific working principle and truth table are shown in Figure 2 and Figure 3 .

[0005] The content addressable memory in the prior art has a relatively high power consumption and requires a new layout structure to reduce its power consumption. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a layout of a content addressable memory cell structure, which is used to solve the problem that the content addressable memory in the prior art has a relatively high power consumption and requires a new layout structure to reduce its power consumption.

[0007] To achieve the above and other related objectives, the present invention provides a layout of a content-addressable memory cell structure, including:

[0008] Transfer tube patterns, which include a first transfer tube pattern, a fourth transfer tube pattern, a fifth transfer tube pattern, a second transfer tube pattern, and a third transfer tube pattern;

[0009] Pull-down tube patterns, which include a first pull-down tube pattern and a second pull-down tube pattern;

[0010] Pull-up tube patterns, which include a first pull-up tube pattern and a second pull-up tube pattern;

[0011] Among them, the first transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are three additional transfer tubes relative to the prior art transistor content-addressable memory cell structure. Through the first transfer tube pattern and the second transfer tube pattern, the key and the cell data are exclusive-ORed. If the key and the cell data are different, then the third transfer tube pattern is turned on, pulling down the level of the match line to a low level.

[0012] The transfer tube patterns, the pull-down tube patterns, and the pull-up tube patterns respectively include: active region patterns and polysilicon patterns spanning across the active region patterns; contact hole patterns located on the active region patterns and distributed on one side of the polysilicon patterns;

[0013] The first transfer tube pattern, the fourth transfer tube pattern, and the first pull-down tube pattern are distributed from top to bottom in sequence, and the active region patterns of the first transfer tube pattern, the fourth transfer tube pattern, and the first pull-down tube pattern are connected together; the second pull-down tube pattern, the fifth transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are distributed from top to bottom in sequence, and the active region patterns of the second pull-down tube pattern, the fifth transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are connected together; the first pull-up tube pattern and the second pull-up tube pattern are respectively arranged on one side of the first pull-down tube pattern and the first pull-up tube pattern, that is, the first pull-up tube pattern is located on the right side of the first pull-down tube pattern, and the second pull-up tube pattern is located on the left side of the second pull-down tube pattern, so that the transfer tube patterns, the pull-down tube patterns, and the pull-up tube patterns are asymmetrically distributed.

[0014] Preferably, the fourth transfer tube pattern, the fifth transfer tube pattern, the first transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are all N-type transfer tube patterns.

[0015] Preferably, the first pull-up tube pattern and the second pull-up tube pattern are both P-type pull-up tube patterns.

[0016] Preferably, both the first pull-down tube pattern and the second pull-down tube pattern are N-type pull-down tube patterns.

[0017] Preferably, the layout further includes a metal layer pattern for connecting the transfer tube pattern, the pull-down tube pattern, and the pull-up tube pattern.

[0018] Preferably, the metal layer pattern includes: a first bit line pattern for connecting the fourth transfer tube pattern and the first transfer tube pattern; a second bit line pattern for connecting the fifth transfer tube pattern and the second transfer tube pattern; a word line pattern for connecting the fourth transfer tube pattern and the fifth transfer tube pattern and connected to the first and second bit line patterns; a matching line pattern for connecting the third transfer tube pattern and connected to the first and second bit lines.

[0019] Preferably, the first pull-down tube pattern, the first pull-up tube pattern, the second pull-down tube pattern, the second pull-up tube pattern, the fifth transfer tube pattern, the fourth transfer tube pattern, the first transfer tube pattern, and the second transfer tube pattern are symmetrically distributed.

[0020] Preferably, the active region pattern in the transfer tube pattern, the pull-down tube pattern, and the pull-up tube pattern is the active region pattern in the SRA structure.

[0021] Preferably, the layout structure is a content addressable memory cell based on a low-power process at the 14-nanometer technology node.

[0022] As described above, the layout of the content addressable memory cell structure of the present invention has the following beneficial effects:

[0023] The present invention designs a layout structure of an addressing memory cell device based on a fin process platform. Like an ordinary static random access memory, it can read or write when given an address and data, but it also performs a matching operation and can be used in the increasingly popular artificial intelligence applications; the content addressable memory cell structure fabricated through the layout of the present invention can be used as a translation lookaside buffer for supporting virtual memory in a microprocessor; the layout of the present invention uses an asymmetric layout structure, resulting in a lower overall power consumption of the content addressable memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shows a schematic circuit diagram of a 9-transistor content addressable memory in the prior art;

[0025] Figure 2 Shows a schematic diagram of the principle of a content addressable memory in the prior art;

[0026] Figure 3 Shows a schematic diagram of the truth value of a content addressable memory in the prior art;

[0027] Figure 4 Shown is a layout schematic diagram of the content addressable memory of the present invention. Specific Embodiments

[0028] The following uses specific examples to illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] Please refer to Figure 4 , the present invention provides a layout of a content addressable memory cell structure, including:

[0030] Transfer tube patterns, the transfer tube patterns include a first transfer tube pattern N1, a fourth transfer tube pattern M5, a fifth transfer tube pattern M6, a second transfer tube pattern N2, and a third transfer tube pattern N3;

[0031] Pull-down tube patterns, the pull-down tube patterns include a first pull-down tube pattern M1 and a second pull-down tube pattern M3;

[0032] Pull-up tube patterns, the pull-up tube patterns include a first pull-up tube pattern M2 and a second pull-up tube pattern M4;

[0033] Among them, the first transfer tube pattern N1, the second transfer tube pattern N2, and the third transfer tube pattern N3 are three additional transfer tube patterns added to the 6-transistor content addressable memory cell structure. Through the first transfer tube pattern N1 and the second transfer tube pattern N2, the key and the cell data are exclusive-ORed. If the key and the cell data are different, then the third transfer tube pattern N3 conducts, pulling down the level of the match line to a low level, but the gate of the third transfer tube pattern N3 is a decreasing high logic level. The specific working principle and truth table are shown in Figure 2 and Figure 3 .

[0034] In an alternative embodiment, the active region pattern 02 in the transfer tube pattern, the pull-down tube pattern, and the pull-up tube pattern is the active region pattern 02 in the SRAM structure.

[0035] In an alternative embodiment, the fourth transfer tube pattern M5, the fifth transfer tube pattern M6, the first transfer tube pattern N1, the second transfer tube pattern N2, and the third transfer tube pattern N3 are all N-type transfer tube patterns.

[0036] In an alternative embodiment, the first pull-up tube pattern M2 and the second pull-up tube pattern M4 are both P-type pull-up tube patterns.

[0037] In an alternative embodiment, both the first pull-down tube pattern M1 and the second pull-down tube pattern M3 are N-type pull-down tube patterns.

[0038] The transfer tube pattern, the pull-down tube pattern, and the up-tube pattern respectively include: an active region pattern 02 and a polysilicon pattern 03 spanning across the active region pattern 02; contact hole patterns located on the active region pattern 02 and distributed on one side of the polysilicon pattern 03;

[0039] The first transfer tube pattern N1, the fourth transfer tube pattern M5, and the first pull-down tube pattern M1 are sequentially distributed, and the active region patterns 02 of the first transfer tube pattern N1, the fourth transfer tube pattern M5, and the first pull-down tube pattern M1 are connected together; the second pull-down tube pattern M3, the fifth transfer tube pattern M6, the second transfer tube pattern N2, and the third transfer tube pattern N3 are sequentially distributed, and the active region patterns 02 of the second pull-down tube pattern M3, the fifth transfer tube pattern M6, the second transfer tube pattern N2, and the third transfer tube pattern N3 are connected together; the first up-tube pattern M2 and the second up-tube pattern M4 are respectively arranged on one side of the first pull-down tube pattern M1 and the first up-tube pattern M2, such that the transfer tube pattern, the pull-down tube pattern, and the up-tube pattern, namely, the nine transistor patterns of the first transfer tube pattern N1, the fourth transfer tube pattern M5, the fifth transfer tube pattern M6, the second transfer tube pattern N2, the third transfer tube pattern N3, the first pull-down tube pattern M1, the second pull-down tube pattern M3, the first up-tube pattern M2, and the second up-tube pattern M4 are asymmetrically distributed.

[0040] In an alternative embodiment, the first pull-down tube pattern M1, the first up-tube pattern M2, the second pull-down tube pattern M3, the second up-tube pattern M4, the fourth transfer tube pattern M5, the fifth transfer tube pattern M6, the first transfer tube pattern N1, and the second transfer tube pattern N2 are symmetrically distributed.

[0041] In an alternative embodiment, for the positional distribution of the transfer tube pattern, the pull-down tube pattern, and the up-tube pattern, with reference to the layout of the 6-transistor content-addressable memory cell structure in the prior art, the fourth transfer tube pattern M5, the first pull-down tube pattern M1, and the first up-tube pattern M2 can be drawn, and then the centrosymmetric second up-tube pattern M4, the second pull-down tube pattern M3, and the fifth transfer tube pattern M6 can be mirrored, and then the first transfer tube pattern N1, the second transfer tube pattern N2, and the third transfer tube pattern N3 can be drawn.

[0042] In an alternative embodiment, the layout further includes a metal layer pattern 01, and the metal layer pattern 01 is used to connect the transfer tube pattern, the pull-down tube pattern, and the up-tube pattern.

[0043] In an alternative embodiment, when accessing the SRAM, the word line is set to a high level, enabling the two transistors for controlling the switches in each basic cell to turn on, connecting the basic cell to the bit line. The metal layer pattern 01 includes: a first bit line pattern for connecting the fourth transfer transistor pattern M5 and the first transfer transistor pattern N1; a second bit line pattern for connecting the fifth transfer transistor pattern M6 and the second transfer transistor pattern N2; a word line pattern for connecting the fourth transfer transistor pattern M5 and the fifth transfer transistor pattern M6 and connected to the first and second bit line patterns; a matching line pattern for connecting the third transfer transistor pattern N3 and connected to the first and second bit lines.

[0044] In an alternative embodiment, the layout structure is a content addressable memory cell based on a low-power process at the 14-nanometer technology node.

[0045] That is to say, in the 9-transistor content addressable memory of this embodiment, based on the static random access memory cell of the fin process, the layout implementation of the content addressable storage device is completed, and the smallest array of the complete SRAM device layout is drawn. Based on the existing 6-transistor SRAM cell structure, three transfer transistors are added to form a 9-transistor content addressable storage device cell (such as Figure 1 ). The first pull-down transistor pattern M1, the first pull-up transistor pattern M2, the second pull-down transistor pattern M3, the second pull-up transistor pattern M4, the fourth transfer transistor pattern M5, the fifth transfer transistor pattern M6, the first transfer transistor pattern N1, and the second transfer transistor pattern N2 are symmetrically distributed. Among the transfer transistor pattern, the pull-down transistor pattern, and the pull-up transistor pattern, the nine transistor patterns of the first transfer transistor pattern N1, the fourth transfer transistor pattern M5, the fifth transfer transistor pattern M6, the second transfer transistor pattern N2, the third transfer transistor pattern N3, the first pull-down transistor pattern M1, the second pull-down transistor pattern M3, the first pull-up transistor pattern M2, and the second pull-up transistor pattern M4 are asymmetrically distributed. Its layout area is about twice that of a common 6-transistor SRAM cell, but on the basis of maintaining the original read and write functions, a matching operation is added. The matching operation can be used to find each word containing a given keyword in the CAM, and then output through the selected matching line. In the later stage, the layout of a 10-transistor content addressable storage device can also be drawn.

[0046] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] In summary, the present invention designs a layout structure of an addressing memory cell device based on a fin process platform. Like an ordinary static random access memory, it can read or write when given an address and data, but it also performs a matching operation and can be used in the increasingly popular artificial intelligence applications; the content-addressable memory cell structure fabricated by the layout of the present invention can be used as a translation lookaside buffer for supporting virtual memory in a microprocessor; the layout of the present invention uses an asymmetric layout structure, resulting in a lower overall power consumption of the fabricated content-addressable memory. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A layout of a content-addressable memory cell structure, characterized in that, At least including: A transfer tube pattern, the transfer tube pattern including first to fifth transfer tube patterns; A pull-down tube pattern, the pull-down tube pattern including a first pull-down tube pattern and a second pull-down tube pattern; A rising tube pattern, the rising tube pattern including a first rising tube pattern and a second rising tube pattern; The transfer tube pattern, the pull-down tube pattern, and the rising tube pattern respectively include: an active region pattern and a polysilicon pattern spanning across the active region pattern; contact hole patterns located on the active region pattern and distributed on one side of the polysilicon pattern; The first transfer tube pattern, the fourth transfer tube pattern, and the first pull-down tube pattern are sequentially distributed, and the active region patterns of the first transfer tube pattern, the fourth transfer tube pattern, and the first pull-down tube pattern are connected together; the second pull-down tube pattern, the fifth transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are sequentially distributed, and the active region patterns of the second pull-down tube pattern, the fifth transfer tube pattern, the second transfer tube pattern, and the third transfer tube pattern are connected together; the first rising tube pattern and the second rising tube pattern are respectively arranged on one side of the first pull-down tube pattern and the first rising tube pattern, such that the transfer tube pattern, the pull-down tube pattern, and the rising tube pattern are asymmetrically distributed.

2. The layout of the content-addressable memory cell structure according to claim 1, wherein: The first to fifth transfer tube patterns are all N-type transfer tube patterns.

3. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The first rising tube pattern and the second rising tube pattern are both P-type rising tube patterns.

4. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The first pull-down tube pattern and the second pull-down tube pattern are both N-type pull-down tube patterns.

5. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The layout further includes a metal layer pattern, the metal layer pattern being used to connect the transfer tube pattern, the pull-down tube pattern, and the rising tube pattern.

6. The layout of the content-addressable memory cell structure according to claim 5, characterized in that: The metal layer pattern includes: a first bit line pattern for connecting the fourth transfer tube pattern and the first transfer tube pattern; a second bit line pattern for connecting the fifth transfer tube pattern and the second transfer tube pattern; a word line pattern for connecting the fourth transfer tube pattern and the fifth transfer tube pattern and connected to the first and second bit line patterns; a matching line pattern for connecting the third transfer tube pattern and connected to the first and second bit lines.

7. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The first and second pull-down tube patterns, the first and second rising tube patterns, the first, second, fourth, and fifth transfer tube patterns are symmetrically distributed.

8. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The active region patterns in the transfer tube pattern, the pull-down tube pattern, and the rising tube pattern are active region patterns in an SRA structure.

9. The layout of the content-addressable memory cell structure according to claim 1, characterized in that: The layout structure is a content addressable memory cell based on a low-power process at a 14-nanometer technology node.

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