Wafer calibration method
By setting grid-like feature patterns and positioning points on the wafer and establishing a grid coordinate system, the problem of inaccurate calibration of large-size chip wafers is solved, accurate positioning and calibration of chips of different sizes are achieved, and the accuracy and uniqueness of wafer calibration are ensured.
Patent Information
- Application Number
- CN202210629214.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-30
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2042-05-30
AI Technical Summary
When the chip size is large, the existing wafer calibration method is difficult to select enough feature patterns on the wafer for positioning calibration, resulting in inaccurate calibration.
Multiple chips are arrayed on the wafer, and characteristic patterns are set between the diagonals of adjacent chips to form a grid arrangement. A grid coordinate system is established, and four positioning points distributed in a square are set as alignment marks. These positioning points are used to calibrate the wafer.
It achieves accurate positioning of chip wafers of different sizes, improves the accuracy and uniqueness of wafer calibration, and meets the requirements of online process defect monitoring of chips of various sizes.
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Figure CN115101466B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a wafer calibration method. Background Art
[0002] In wafer fabrication plants, defect monitoring is an essential and critical component of in-line processes. Existing defect monitoring typically requires the establishment of a defect scanning program that monitors defects at different process nodes during online tape-out in real time, thereby enabling monitoring of process and product yield.
[0003] An important prerequisite for defect monitoring is to ensure the accuracy and uniqueness of the chip position calibration on the wafer. However, the necessary condition for the current chip position calibration method is that there are a sufficient number of feature patterns with the same shape in a specific position on the wafer. Figure 1 The wafer calibration principle commonly used in current defect scanning machines is as follows: two initial points a1 and a2 are manually set within a preselected frame 11 of a specific size (e.g., 60mm×20mm). The defect scanning machine uses initial points a1 and a2 as starting points, with the spacing between initial points a1 and a2 being a unit length d. Multiple feature patterns A with equal spacing are selected on the straight line containing initial points a1 and a2 as positioning points a3, a4, and a5. Multiple feature patterns A with equal spacing in the same row (including at least initial points a1 and a2 and positioning points a3, a4, and a5) are then used as alignment marks 12 to complete the horizontal positioning calibration of the wafer 1. Specifically, the specifications of the alignment mark 12 (Alignment Mask Specifications) include: all feature patterns A constituting the alignment mark 12 are located within the preselected frame 11; the spacing between any two adjacent feature patterns A is equal (both are the unit length d); the number of feature patterns A is at least five, and all feature patterns A are located on the same straight line; and all feature patterns A are clear and have the same shape and size.
[0004] As mentioned above, in the wafer calibration principle currently used, a necessary condition for achieving alignment is that there are enough repeated feature patterns in a specific position of the wafer. Figure 2 When the size of the chip 21 is small, there are more chips 21 arranged on the wafer 2, and the number of corresponding characteristic patterns A is large. Therefore, in the subsequent process of setting the alignment mark, the alignment mark for wafer alignment can be easily selected in the pre-selection box 22. However, see Figure 3 When the size of the chip 31 is large, there are fewer chips 31 arranged on the wafer 3, and the number of corresponding characteristic patterns A is small. Therefore, in the subsequent process of setting the alignment mark, it is difficult to select the alignment mark suitable for wafer alignment in the pre-selection box 32, and thus the positioning calibration of the wafer cannot be achieved.
[0005] In view of this, a method is needed to meet the positioning requirements of chip wafers of different sizes and realize online process defect monitoring for chip wafers of various sizes. Summary of the Invention
[0006] The object of the present invention is to provide a wafer calibration method to meet the wafer positioning requirements of chips with different sizes and ensure the accuracy of the wafer calibration results.
[0007] In order to achieve the above object, the present invention provides a wafer calibration method, comprising:
[0008] Providing a wafer, wherein a plurality of chips are arranged in an array on the wafer, feature patterns are provided between diagonal portions of adjacent chips, and all feature patterns are arranged in a grid pattern;
[0009] Establishing a grid coordinate system, setting four positioning points distributed in a square on the wafer, wherein the alignment mark of the wafer includes all the positioning points; and
[0010] Wafer calibration is performed using the alignment marks.
[0011] Optionally, one positioning point is provided in each of the four sector-shaped areas into which the wafer is equally divided, and the positioning point is located in the area between one quarter of the radius and three quarters of the radius of the wafer.
[0012] Optionally, the method for setting the positioning point includes:
[0013] The maximum number of characteristic patterns in a single row is set to a first set value, and the maximum number of characteristic patterns in a single column is set to a second set value;
[0014] Four different position coordinates are calculated according to the first set value and the second set value, and the characteristic patterns corresponding to the four position coordinates are the positioning points.
[0015] Optionally, the ratio of the first setting value to the second setting value is greater than or equal to one.
[0016] Optionally, after establishing the grid coordinate system and before setting the first set value and the second set value, the method further includes:
[0017] Setting two characteristic patterns located at the diagonal of the same chip as starting points, and obtaining the coordinates of the two starting points;
[0018] The horizontal unit length and the vertical unit length of the chip are calculated according to the coordinates of the two starting points.
[0019] Optionally, the four different position coordinates are (P1, Q1), (P1, Q2), (P2, Q1), and (P2, Q2), and the method for calculating the position coordinates includes:
[0020] Q1=M / 4;
[0021] Q2=M-Q1+m;
[0022] P1=N / 4;
[0023] P2=N-P1+n;
[0024] Wherein, M is a first set value, N is a second set value, m is a transverse unit length of the chip, n is a longitudinal unit length of the chip, and the rounding method is used to take integers for P1 and Q1.
[0025] Optionally, after setting the starting point and before setting the first set value and the second set value, the method further includes:
[0026] Get the position coordinates corresponding to all feature graphics.
[0027] Optionally, all characteristic graphics have the same shape and size.
[0028] Optionally, the shape of the characteristic pattern includes a cross.
[0029] Optionally, the wafer calibration method is used for wafer calibration of a defect scanning machine.
[0030] In summary, the present invention provides a wafer calibration method. Multiple chips are arrayed on a wafer, with characteristic patterns disposed diagonally between adjacent chips. All characteristic patterns are arranged in a grid pattern. A grid coordinate system is then established, and four positioning points are disposed in a square pattern on the wafer. The wafer's alignment marks include all of these positioning points, and wafer calibration is performed using these alignment marks. The present invention establishes a grid coordinate system on the wafer, disposing four positioning points in a square pattern to obtain the wafer's alignment marks. This method satisfies the wafer positioning requirements for chips of different sizes and ensures the certainty and uniqueness of wafer calibration.
[0031] Furthermore, the present invention calculates the position coordinates of the positioning point based on a first set value representing the maximum number of single-row feature patterns, a second set value representing the maximum number of single-column feature patterns, and the horizontal unit length and vertical unit length of the chip on the wafer, so that a positioning point is set in each of the four sector-shaped areas into which the wafer is evenly divided, and the positioning point is located near half the radius of the wafer surface, thereby improving the accuracy of the wafer calibration results. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1A schematic diagram of a wafer calibration;
[0033] Figure 2 A schematic diagram of the calibration of a small chip wafer;
[0034] Figure 3 A schematic diagram of the calibration of a large chip wafer;
[0035] Figure 4 A flowchart of a wafer calibration method provided by one embodiment of the present invention;
[0036] Figures 5 to 8 A schematic diagram of wafer calibration corresponding to each step in the wafer calibration method provided in one embodiment of the present invention;
[0037] in:
[0038] 1-wafer; 11-preselection frame; 12-alignment mark;
[0039] 2-wafer; 21-chip; 22-preselection box;
[0040] 3-wafer; 31-chip; 32-preselection box;
[0041] 4-wafer; 41-chip; 42-dicing road; 43-alignment mark;
[0042] A-characteristic pattern; a1, a2-starting points; a3, a4, a5-positioning points;
[0043] B-characteristic figure; b1, b2-starting points; b3, b4, b5, b6-positioning points. DETAILED DESCRIPTION
[0044] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.
[0045] Figure 4 This is a flow chart of a wafer calibration method provided by an embodiment of the present invention. Figure 4 The wafer calibration method described in this embodiment includes:
[0046] Step S01: providing a wafer, on which a plurality of chips are arrayed, with feature patterns arranged between diagonal portions of adjacent chips, and all feature patterns arranged in a grid pattern;
[0047] Step S02: establishing a grid coordinate system, setting four positioning points distributed in a square on the wafer, wherein the alignment mark of the wafer includes all the positioning points; and
[0048] Step S03: calibrating the wafer using the alignment marks.
[0049] Figures 5 to 8 The wafer calibration diagram corresponding to each step in the wafer calibration method provided in this embodiment is shown below. Figures 5 to 8 The wafer calibration method described in this embodiment is described in detail.
[0050] First, see Figure 5 , execute step S01, provide a wafer 4, on which a plurality of chips 41 are arranged in an array, and a characteristic pattern B is provided between the diagonals of adjacent chips 41, and all the characteristic patterns B are arranged in a grid shape. In this embodiment, all the characteristic patterns B are of the same shape and size, and the shape of the characteristic patterns B is a cross. In other embodiments of the present invention, the shape of the characteristic pattern B can be set to other regular or irregular patterns according to actual needs, and the present invention is not limited to this. It should be noted that the area between adjacent chips 41 is the cutting road 42 of the wafer 4, and the characteristic pattern B is set in the cutting road 42, and the length b1 of the characteristic pattern B is less than the lateral width w1 of the cutting road 42, and the width b2 of the characteristic pattern B is less than the longitudinal width w2 of the cutting road 42.
[0051] Next, see Figures 6 to 8 , execute step S02 to establish a grid coordinate system, set four positioning points distributed in a square on the wafer 4, and the alignment mark 43 of the wafer 4 includes all the positioning points. In this embodiment, the origin O(0,0) of the grid coordinate system is set outside the wafer 4. In other embodiments of the present invention, the origin O of the grid coordinate system can be set inside the wafer 4 or at any other position according to actual needs, and the present invention is not limited to this. In this embodiment, all the characteristic patterns B are arranged in a grid of four rows and five columns. In other embodiments of the present invention, the number of rows and columns of the grid arrangement of the characteristic patterns B is related to the arrangement method of the chips 41 on the wafer 4.
[0052] Specifically, the positioning points are set using the four-point calibration method, which includes the following steps.
[0053] First, see Figure 6 , set the two characteristic patterns B located at the diagonal of the same chip 41 (the chip 41 can be any chip 41 in the wafer 4) as the starting point, for example Figure 6The starting points b1 and b2 in the chip 41 are obtained, and the coordinates of the two starting points b1 and b2 are obtained, namely b1(2,2) and b2(3,3). The horizontal unit length m and the vertical unit length n of the chip 41 are calculated based on the coordinates of the two starting points b1 and b2. Specifically, the horizontal unit length m is the absolute value of the difference between the horizontal coordinates of the starting points b1 and b2, namely m=|2-3|=1, and the vertical unit length m is the absolute value of the difference between the vertical coordinates of the starting points b1 and b2, namely n=|2-3|=1.
[0054] Next, the maximum number of single-row feature graphics B is set to a first set value M, and the maximum number of single-column feature graphics B is set to a second set value N. Optionally, the position coordinates corresponding to all feature graphics B can be obtained by a defect scanning machine, and the first set value M and the second set value N can be calculated based on the position coordinates of all feature graphics B. In this embodiment, the maximum number of single-row feature graphics B is 5, and the maximum number of single-column feature graphics B is 4, so M=5, N=4. It should be noted that the smallest unit of a wafer is a chip, so the minimum requirement for exposing a complete chip is that the ratio of the first setting value M to the second setting value N is greater than or equal to one, that is, M / N≥1.
[0055] Then, see Figure 7 and Figure 8 , four different position coordinates are calculated based on the first set value M and the second set value N, and the characteristic patterns B corresponding to the four position coordinates are the positioning points. In this embodiment, the four different position coordinates are (P1, Q1), (P1, Q2), (P2, Q1), and (P2, Q2). The method for calculating the position coordinates includes:
[0056] Q1=M / 4;
[0057] Q2=M-Q1+m;
[0058] P1=N / 4;
[0059] P2=N-P1+n;
[0060] Wherein, M is the first set value, N is the second set value, m is the horizontal unit length, n is the vertical unit length, and the rounding method is used to take integers for P1 and Q1.
[0061] Exemplarily, the first set value M=5, the second set value N=4, the transverse unit length m of the chip 41=1, and the longitudinal unit length n of the chip 41=1. Therefore, Q1=5 / 4=1.25, and rounding Q1 by the rounding up method ultimately yields Q1=2, Q2=5-2+1=4; similarly, P1=4 / 4=1, and rounding P1 by the rounding up method ultimately yields P1=1, P2=4-1+1=4. Accordingly, the position coordinates of positioning point b3 are (1,2), the position coordinates of positioning point b4 are (1,4), the position coordinates of positioning point b5 are (4,2), and the position coordinates of positioning point b6 are (4,4). The positioning points b3, b4, b5, and b6 constitute the alignment mark 43.
[0062] Next, continue reading Figure 7 and Figure 8 , execute step S03, and use the alignment mark 43 to calibrate the wafer. In this embodiment, it can be seen from the position coordinates of all the positioning points in the alignment mark 43 that the positioning points b3, b4, b5 and b6 are distributed in a square. In the four sector-shaped areas into which the wafer 4 is divided, one positioning point is provided in each sector-shaped area, and all the positioning points are located at half the radius of the wafer 4, so that the alignment mark 43 can meet the positioning requirements of each position in the wafer 4, thereby ensuring the accuracy of the calibration results at different positions in the wafer. Since three points can determine a plane, the defect scanning machine can perform positioning calibration (Alignment) on the wafer 4 according to the alignment mark 43, thereby ensuring the certainty and uniqueness of the wafer calibration. Optionally, the positioning point can also be located in the area between one-quarter radius and three-quarter radius of the wafer 4.
[0063] At the same time, because the position coordinates of the positioning points b3, b4, b5, and b6 are related to the first set value M, the second set value N, the horizontal unit length m, and the vertical unit length n, the wafer calibration method described in this embodiment can meet the wafer positioning requirements of chips of different sizes. In this embodiment, the wafer calibration method is used for wafer calibration of a defect scanning machine, thereby realizing online process defect monitoring of chip wafers of various sizes. In other embodiments of the present invention, the wafer calibration method can be used in other semiconductor machines requiring wafer alignment and related process flows.
[0064] In summary, the present invention provides a wafer calibration method. Multiple chips are arrayed on a wafer, with characteristic patterns disposed diagonally between adjacent chips. All characteristic patterns are arranged in a grid pattern. A grid coordinate system is then established, and four square-shaped positioning points are disposed on the wafer. The wafer's alignment marks include all of these positioning points, and wafer calibration is performed using these alignment marks. This method establishes a grid coordinate system on the wafer, disposing four square-shaped positioning points to obtain the wafer's alignment marks. This method satisfies the wafer positioning requirements for chips of different sizes, ensuring the certainty and uniqueness of wafer calibration.
[0065] Furthermore, the present invention calculates the position coordinates of the positioning point based on a first set value representing the maximum number of single-row feature patterns, a second set value representing the maximum number of single-column feature patterns, and the horizontal unit length and vertical unit length of the chip on the wafer, so that a positioning point is set in each of the four sector-shaped areas into which the wafer is evenly divided, and the positioning point is located near half the radius of the wafer surface, thereby improving the accuracy of the wafer calibration results.
[0066] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.
Claims
1. A wafer calibration method, characterized in that: include: Providing a wafer, wherein a plurality of chips are arranged in an array on the wafer, feature patterns are provided between diagonal portions of adjacent chips, and all feature patterns are arranged in a grid pattern; Establishing a grid coordinate system, setting four positioning points distributed in a square on the wafer, wherein the alignment mark of the wafer includes all the positioning points; as well as, performing wafer calibration using the alignment marks; The method for setting the positioning point includes: The maximum number of characteristic patterns in a single row is set to a first set value, and the maximum number of characteristic patterns in a single column is set to a second set value; Four different position coordinates are calculated according to the first set value and the second set value, and the characteristic patterns corresponding to the four position coordinates are the positioning points.
2. The wafer calibration method according to claim 1, wherein: In the four sector-shaped areas into which the wafer is equally divided, one positioning point is provided in each sector-shaped area, and the positioning point is located in the area between a quarter radius and a three-quarter radius of the wafer.
3. The wafer calibration method according to claim 1, wherein: A ratio of the first set value to the second set value is greater than or equal to one.
4. The wafer calibration method according to claim 1, wherein: After establishing the grid coordinate system and before setting the first set value and the second set value, the method further includes: Setting two characteristic patterns located at the diagonal of the same chip as starting points, and obtaining the coordinates of the two starting points; The horizontal unit length and the vertical unit length of the chip are calculated according to the coordinates of the two starting points.
5. The wafer calibration method according to claim 4, wherein: The four different position coordinates are (P1, Q1), (P1, Q2), (P2, Q1) and (P2, Q2), and the method for calculating the position coordinates includes: Q1=M / 4; Q2=M-Q1+m; P1=N / 4; P2=N-P1+n; Wherein, M is a first set value, N is a second set value, m is a transverse unit length of the chip, n is a longitudinal unit length of the chip, and the rounding method is used to take integers for P1 and Q1.
6. The wafer calibration method according to claim 4, wherein: After setting the starting point and before setting the first set value and the second set value, the method further includes: Get the position coordinates corresponding to all feature graphics.
7. The wafer calibration method according to claim 1, wherein: All feature graphics have the same shape and size.
8. The wafer calibration method according to claim 1 or 7, wherein: The shape of the characteristic pattern includes a cross.
9. The wafer calibration method according to claim 1, wherein: The wafer calibration method is used for wafer calibration of a defect scanning machine.
Citation Information
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