A field-effect transistor based on two-dimensional tellurene and its preparation method

Abstract

The present invention discloses a field-effect transistor based on two-dimensional tellurene and a preparation method thereof. The field-effect transistor based on two-dimensional tellurene comprises: a dielectric layer, a two-dimensional tellurene layer located on the dielectric layer, a platinum layer located at both ends of the two-dimensional tellurene layer, and a gold layer located on the platinum layers at both ends. The present invention reduces the contact resistance of the field-effect transistor and improves the performance of the device by using metal platinum with a high work function as the contact metal of the two-dimensional tellurene. This is because metal platinum has a high work function of 5.65eV, which is much larger than the valence band top of two-dimensional tellurene (about 4.35eV). It can form a small Schottky barrier at the interface between the two, promote hole transport in the two-dimensional tellurene, thereby reducing the contact resistance of the device and improving the P-type performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a field-effect transistor based on two-dimensional tellurene and a preparation method thereof. Background Art

[0002] With the advancement of Moore's Law, semiconductor devices are shrinking in size. Traditional silicon-based semiconductors face significant challenges, such as severe short-channel effects and high off-state leakage current. In recent years, two-dimensional semiconductor materials have become popular candidates to replace traditional silicon semiconductors due to their excellent electrical properties, atomic-scale thickness, and lack of dangling bonds. Two-dimensional atomic crystals such as graphene and transition metal sulfides have demonstrated their potential in nanodevices, optoelectronics, and other fields, becoming a research hotspot in the semiconductor device field.

[0003] Among the many two-dimensional semiconductors, two-dimensional tellurene of the sixth main group has become another emerging two-dimensional semiconductor material in addition to single-element materials such as graphene, phosphorene and stanene due to its unique structure and properties. Two-dimensional tellurene has a structure composed of spiral chains and hexagonal frameworks, in which each spiral chain is composed of tellurium atoms linked by covalent bonds. These spiral chains are further stacked through van der Waals forces to form two-dimensional tellurene. Crystalline tellurium is a P-type narrow bandgap semiconductor with a bandgap of about 0.31eV. As the thickness decreases, the bandgap of two-dimensional tellurene will gradually increase to about 1.17eV. In theory, the carrier mobility of two-dimensional tellurene can reach 10 4 -10 6 cm 2 V -1 s -1 These excellent electrical properties and good chemical stability make the application of two-dimensional tellurene in the field of semiconductor devices promising. In particular, field-effect transistors based on two-dimensional tellurene exhibit excellent on-off ratio and hole mobility, providing a foundation for the preparation of high-performance integrated circuits.

[0004] Contact metals are a key factor in achieving high-performance field-effect transistors. Suitable contact metals can reduce contact resistance and improve device performance. However, research on the contact resistance of two-dimensional tellurene-based field-effect transistors has been relatively lacking. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a field-effect transistor based on two-dimensional tellurene and a preparation method thereof, aiming to solve the problem that the contact resistance of the existing field-effect transistor is large, resulting in low device performance.

[0006] The technical solutions of the present invention are as follows:

[0007] In a first aspect of the present invention, a field effect transistor based on two-dimensional tellurene is provided, which comprises: a dielectric layer, a two-dimensional tellurene layer located on the dielectric layer, platinum layers located at both ends of the two-dimensional tellurene layer, and gold layers located on the platinum layers at both ends.

[0008] Optionally, the two-dimensional tellurene layer has a thickness of 10-30 nm.

[0009] Optionally, the platinum layer has a thickness of 10-15 nm.

[0010] Optionally, the thickness of the gold layer is 30-50 nm.

[0011] Optionally, the dielectric layer is a silicon oxide layer or an aluminum oxide layer.

[0012] Optionally, the dielectric layer has a thickness of 100-300 nm.

[0013] Optionally, the contact resistance of the field effect transistor is 400Ω·μm.

[0014] A second aspect of the present invention provides a method for preparing a two-dimensional tellurene-based field-effect transistor according to the present invention, comprising the steps of:

[0015] providing a dielectric layer and a two-dimensional tellurene layer;

[0016] transferring the two-dimensional tellurene layer onto the dielectric layer;

[0017] Platinum layers are prepared at both ends of the two-dimensional tellurene layer, and gold layers are prepared on the platinum layers at both ends to obtain the field effect transistor.

[0018] Optionally, the position range of the platinum layer is determined by using a photolithography technique, and the platinum layer is prepared in the determined position range by using an electron beam thermal evaporation technique.

[0019] Optionally, the position range of the gold layer is determined by using a photolithography technique, and the gold layer is prepared in the determined position range by using an electron beam thermal evaporation technique.

[0020] Beneficial Effects: By using high-work-function platinum as the contact metal for two-dimensional tellurene, the present invention reduces the contact resistance of field-effect transistors and improves device performance. This is because platinum has a high work function of 5.65 eV, which is much higher than the valence band top of two-dimensional tellurene (around 4.35 eV). This allows for a smaller Schottky barrier to form at the interface between the two, promoting hole transport in the two-dimensional tellurene, thereby reducing the device's contact resistance and improving its P-type performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of the field-effect transistor based on two-dimensional tellurene in Example 1.

[0022] Figure 2 for Figure 1 Energy band structure diagram at the interface between platinum and two-dimensional tellurene.

[0023] Figure 3 This is an optical photograph of the two-dimensional tellurene-based field-effect transistor in Example 1.

[0024] Figure 4 1 is the transfer curve of the field-effect transistor based on two-dimensional tellurene in Example 1.

[0025] Figure 5 This is the output curve of the field-effect transistor based on two-dimensional tellurene in Example 1.

[0026] Figure 6 1 is the transfer curve of the field effect transistor with different channel lengths in Example 1.

[0027] Figure 7 For Figure 6 The relationship between total resistance and channel length at different gate voltages is obtained from the transfer curve.

[0028] Figure 8 The transfer curves of the field-effect transistor based on two-dimensional tellurene at different temperatures (100-300K) in Example 1.

[0029] Figure 9 For Figure 8 The barrier heights at various gate voltages are obtained based on thermionic emission theory. DETAILED DESCRIPTION

[0030] The present invention provides a two-dimensional tellurene-based field-effect transistor and a method for preparing the same. To clarify the objectives, technical solutions, and effects of the present invention, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention.

[0031] Contact metals have always been a key factor in achieving high-performance field-effect transistors. A suitable contact metal can reduce contact resistance and improve device performance. The inventors have discovered that using platinum, a metal with a high work function, as the contact metal for two-dimensional tellurene can reduce contact resistance and improve device performance.

[0032] Based on this, an embodiment of the present invention provides a field-effect transistor based on two-dimensional tellurene, comprising: a dielectric layer, a two-dimensional tellurene layer located on the dielectric layer, platinum layers located at both ends of the two-dimensional tellurene layer, and gold layers located on the platinum layers at both ends. The two-dimensional tellurene is used as the channel material, and platinum is used as the contact metal.

[0033] This embodiment uses high work function metal platinum as the contact metal of two-dimensional tellurene to reduce the contact resistance of the field effect transistor and improve the performance of the device. Figure 2 As shown, this is because metallic platinum has a high work function of 5.65eV, which is much larger than the valence band top of two-dimensional tellurene (around 4.35eV). It can form a small Schottky barrier (65meV) at the interface between the two, promoting hole transport in the two-dimensional tellurene, thereby reducing the contact resistance of the device and improving the device's P-type performance. This embodiment can reduce the contact resistance of the two-dimensional tellurene-based field-effect transistor to 400Ω·μm, which is much lower than that of two-dimensional tellurene field-effect transistors using other contact metals.

[0034] In one embodiment, the dielectric layer is a silicon oxide layer or an aluminum oxide layer.

[0035] In one embodiment, the thickness of the dielectric layer is 100-300 nm.

[0036] In one embodiment, the length of the two-dimensional tellurene layer is 0.6-5 μm. Devices fabricated from two-dimensional tellurene in this length range have a larger on / off ratio and a higher current density.

[0037] In one embodiment, the thickness of the two-dimensional tellurene layer is 10-30 nm. Interface scattering has little effect on two-dimensional tellurene of this thickness, and the device performance can better reflect the excellent electrical properties of two-dimensional tellurene.

[0038] In one embodiment, the platinum layer has a thickness of 10-15 nm.

[0039] In one embodiment, the thickness of the gold layer is 30-50 nm. Metal electrodes in this thickness range are easy to prepare and are compatible with common transistor preparation processes.

[0040] In one embodiment, the two-dimensional tellurene layer has a thickness of 10-30 nm, the platinum layer has a thickness of 10-15 nm, the gold layer has a thickness of 30-50 nm, and the dielectric layer is a 300 nm thick silicon oxide wafer. This embodiment uses two-dimensional tellurene of appropriate thickness as the channel material, platinum and gold of appropriate thickness as contact metals, and a suitable dielectric layer, which further improves the performance of the back-gate field-effect transistor.

[0041] An embodiment of the present invention further provides a method for preparing a field-effect transistor based on two-dimensional tellurene, which comprises the steps of:

[0042] providing a dielectric layer and a two-dimensional tellurene layer;

[0043] transferring the two-dimensional tellurene layer onto the dielectric layer;

[0044] Platinum layers are prepared at both ends of the two-dimensional tellurene layer, and gold layers are prepared on the platinum layers at both ends to obtain the field effect transistor.

[0045] In this example, a two-dimensional tellurene layer is transferred onto a dielectric layer. Platinum layers are then formed at both ends of the two-dimensional tellurene layer, and gold layers are then formed on top of the two platinum layers. This results in a back-gate field-effect transistor (FET) with platinum and gold as source and drain electrodes, platinum as the contact metal, two-dimensional tellurene as the channel, and a silicon oxide wafer as the dielectric layer. It should be noted that gold has low chemical reactivity and is suitable for metal electrodes, while other active metals are not suitable for the top layer of the electrode.

[0046] This embodiment achieves low contact resistance in a two-dimensional tellurene-based field-effect transistor by using platinum as the contact metal. Compared to two-dimensional tellurene-based field-effect transistors using other contact metals, this embodiment has the following characteristics:

[0047] (1) The method adopted in this embodiment has low requirements on operating equipment, simple operation process and high feasibility of implementation.

[0048] (2) This embodiment can reduce the contact resistance of the two-dimensional tellurene-based field-effect transistor to 400Ω·μm, which is much lower than that of the two-dimensional tellurene-based field-effect transistor using other contact metals.

[0049] (3) The platinum contact metal used in this embodiment can form a smaller Schottky barrier of 65 meV with the two-dimensional tellurene channel, which facilitates the hole transport in the two-dimensional tellurene and improves the P-type performance of the field-effect transistor.

[0050] In this embodiment, the two-dimensional tellurene can be prepared by a hydrothermal reaction. In one embodiment, the thickness of the two-dimensional tellurene layer is 10-30 nm.

[0051] In one embodiment, the thickness of the dielectric layer is 100-300 nm.

[0052] In one embodiment, the dielectric layer may be a common dielectric layer such as a silicon oxide wafer or an aluminum oxide layer.

[0053] In one embodiment, the platinum layer has a thickness of 10-15 nm.

[0054] In one embodiment, the thickness of the gold layer is 30-50 nm.

[0055] In one embodiment, the position range of the platinum layer is determined by photolithography, and the platinum layer is formed in the determined position range by electron beam thermal evaporation. Furthermore, the metal evaporation rate is 0.1-0.5 nm / s.

[0056] In one embodiment, the gold layer is formed within a certain range by photolithography, and the gold layer is formed within the determined range by electron beam thermal evaporation. Furthermore, the metal evaporation rate is 0.1-0.5 nm / s.

[0057] The present invention will be further described below with reference to specific examples.

[0058] Example 1

[0059] Combine Figure 1 As shown, a 300nm thick silicon oxide substrate (i.e., silicon oxide wafer) is used as a dielectric layer, and a 15nm thick two-dimensional tellurene layer is transferred onto the dielectric layer. Traditional photolithography technology is used to determine the position range of the platinum layer and the gold layer, and electron beam thermal evaporation technology is used to sequentially prepare a 15nm thick platinum layer and a 40nm thick gold layer at both ends of the two-dimensional tellurene layer to obtain a field effect transistor, wherein the evaporation rates of platinum and gold are both 0.1nm / s.

[0060] Figure 2 for Figure 1 Energy band structure diagram at the interface between platinum and two-dimensional tellurene.

[0061] Figure 3 This is an optical photograph of the two-dimensional tellurene-based field-effect transistor in Example 1.

[0062] Figure 4 is the transfer curve of the field effect transistor based on two-dimensional tellurene in Example 1, where V gs is the gate voltage, V ds is the source-drain voltage, I ds is the source-drain current, the thickness of the two-dimensional tellurene is 15nm, and the channel length L is 600nm. The hole mobility is 420cm from the transfer curve. 2 V -1 s -1 The transfer curve is obtained by collaborative testing using a probe station and a semiconductor analysis tester.

[0063] Figure 5 is the output curve of the field effect transistor based on two-dimensional tellurene in Example 1, and its current density reaches 170μA / μm. gs is the gate voltage, V ds is the source-drain voltage, I ds The output curve is obtained by the collaborative testing of the probe station and semiconductor analysis tester.

[0064] Figure 6 is the transfer curve of the field effect transistor with different channel lengths in Example 1, which is used to calculate the contact resistance, transfer length and contact resistivity using the transfer length method, where V gs is the gate voltage, V dsis the source-drain voltage, I ds is the source-drain current, and t is the thickness of the two-dimensional tellurene. Field-effect transistors with different channel lengths are transistors that are identical except for the channel length of the two-dimensional tellurene. The channel lengths are 1.2μm, 1.9μm, 2.9μm, and 4.0μm, respectively.

[0065] Figure 7 For Figure 6 The transfer curves are obtained at different gate voltages (gate voltage V gs The relationship between the total resistance and the channel length at -80V, -40V, and 0V respectively. The contact resistance can be calculated by the transmission length method to be 400Ω·μm; the transmission length is 80nm; and the contact resistivity is 3.2×10 -7 Ω·cm 2 The transfer length method uses the linear relationship between the total resistance and the transistor channel length, calculated from the transistor transfer curve. The intercept of this linear relationship with the vertical axis (i.e., the resistance value) is the contact resistance.

[0066] Figure 8 The transfer curves of the field effect transistor based on two-dimensional tellurene at different temperatures (100-300K) in Example 1, where V gs is the gate voltage, V ds is the source-drain voltage, I ds is the source-drain current, the 2D tellurene thickness t is 20 nm, and the channel length L is 2.3 μm. The temperature-dependent transfer curve can be used to calculate the Schottky barrier between platinum and 2D tellurene.

[0067] Figure 9 For Figure 8 According to the barrier heights at various gate voltages obtained from the thermal electron emission theory, it can be concluded that the Schottky barrier between platinum and two-dimensional tellurene is 65 meV.

[0068] In summary, the present invention provides a field-effect transistor based on two-dimensional tellurene and a method for preparing the same. By using high-work-function platinum as the contact metal for two-dimensional tellurene, the present invention reduces the contact resistance of the field-effect transistor and improves the performance of the device. This is because platinum has a high work function of 5.65 eV, which is much larger than the valence band top of two-dimensional tellurene (around 4.35 eV). This allows for the formation of a small Schottky barrier at the interface between the two, promoting hole transport in the two-dimensional tellurene, thereby reducing the contact resistance of the device and improving the device's P-type performance.

[0069] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A field-effect transistor based on two-dimensional tellurene, characterized in that: include: A dielectric layer, a two-dimensional tellurene layer on the dielectric layer, platinum layers at both ends of the two-dimensional tellurene layer, and gold layers on the platinum layers at both ends; The thickness of the platinum layer is 10-15 nm.

2. The two-dimensional tellurene-based field-effect transistor according to claim 1, characterized in that: The thickness of the two-dimensional tellurene layer is 10-30 nm.

3. The two-dimensional tellurene-based field-effect transistor according to claim 1, characterized in that: The thickness of the gold layer is 30-50 nm.

4. The two-dimensional tellurene-based field-effect transistor according to claim 1, characterized in that: The dielectric layer is a silicon oxide layer or an aluminum oxide layer.

5. The two-dimensional tellurene-based field-effect transistor according to claim 1, characterized in that: The thickness of the dielectric layer is 100-300 nm.

6. The two-dimensional tellurene-based field-effect transistor according to claim 1, characterized in that: The contact resistance of the field effect transistor is 400Ω·μm.

7. A method for preparing a two-dimensional tellurene-based field-effect transistor according to any one of claims 1 to 6, characterized in that: Including steps: providing a dielectric layer and a two-dimensional tellurene layer; transferring the two-dimensional tellurene layer onto the dielectric layer; Platinum layers are prepared at both ends of the two-dimensional tellurene layer, and gold layers are prepared on the platinum layers at both ends to obtain the field effect transistor.

8. The method for preparing a two-dimensional tellurene-based field-effect transistor according to claim 7, wherein: The position range of the platinum layer is determined by using a photolithography technique, and the platinum layer is prepared in the determined position range by using an electron beam thermal evaporation technique.

9. The method for preparing a two-dimensional tellurene-based field-effect transistor according to claim 7, wherein: The position range of the gold layer is determined by using a photolithography technique, and the gold layer is prepared in the determined position range by using an electron beam thermal evaporation technique.

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