Analog-to-Digital Converter

Abstract

The present disclosure provides an analog-to-digital converter, comprising: a first capacitor array and a second capacitor array, the first capacitor array and the second capacitor array being a positive capacitor array and a negative capacitor array respectively, and comprising capacitors and switches connected to the capacitors, the capacitors being connected to different voltages by switching the switches, the first capacitor array comprising first low-order segment capacitors and first high-order segment capacitors, the second capacitor array comprising second low-order segment capacitors and second high-order segment capacitors, a loop filter, the loop filter comprising a first path and a second path, the first path and the second path being connected to the first capacitor array and the second capacitor array respectively, and the first path being used for first-order term shaping filtering, while the second path being used for second-order term shaping filtering.

Description

Technical Field

[0001] The present disclosure relates to a low-power successive approximation analog-to-digital converter. Background Art

[0002] The accuracy of a successive approximation analog-to-digital converter is usually limited by capacitor mismatch and circuit thermal noise. In recent years, various solutions have been proposed to enhance the dynamic performance of successive approximation analog-to-digital converters. For example, in the patent application CN112134565A of the applicant, a low-power successive approximation analog-to-digital converter is provided, in which redundant capacitors are used, and the first-order term noise is filtered. On this basis, in order to better reduce power consumption and provide better performance, a higher-precision low-power analog-to-digital converter is further proposed. Summary of the Invention

[0003] To solve one of the above technical problems, especially to reduce power consumption and improve accuracy, the present disclosure provides an analog-to-digital converter.

[0004] According to one aspect of the present disclosure, an analog-to-digital converter includes:

[0005] A first capacitor array and a second capacitor array, the first capacitor array and the second capacitor array are a positive electrode capacitor array and a negative electrode capacitor array respectively, and include capacitors and switches connected to the capacitors, and the capacitors are connected to different voltages by switching the switches. The first capacitor array includes a first low-order segment capacitor and a first high-order segment capacitor, and the second capacitor array includes a second low-order segment capacitor and a second high-order segment capacitor;

[0006] A loop filter, the loop filter includes a first path and a second path, the first path and the second path are respectively connected to the first capacitor array and the second capacitor array, and the first path is used for first-order term shaping filtering, and the second path is used for second-order term shaping filtering;

[0007] A comparator, the comparator includes a first set of input terminals and a second set of input terminals, the first set of input terminals is used to connect the first capacitor array and the second capacitor array, and the second set of input terminals is used to connect the output of the ring filter;

[0008] A logic controller, the logic controller controls the switches of the first capacitor array and the second capacitor array according to the output signal of the comparator to perform successive approximation analog-to-digital conversion; and

[0009] A dynamic element matching circuit, the dynamic element matching circuit is used to control the switches of the high three-bit capacitors of the first high-order segment capacitor and the high three-bit capacitors of the second high-order segment capacitor according to the output of the logic controller.

[0010] According to at least one embodiment of the present disclosure, the comparator is composed of a preamplifier circuit and a latch circuit.

[0011] According to at least one embodiment of the present disclosure, the first low-order segment capacitors of the first capacitor array include three-bit capacitors, and the first high-order segment capacitors include seven-bit capacitors. The second low-order segment capacitors of the second capacitor array include three-bit capacitors, and the second high-order segment capacitors include seven-bit capacitors. The first low-order segment capacitors and the second low-order segment capacitors are controlled according to the output signal of the logic controller. Among the first high-order segment capacitors and the second high-order segment capacitors, the remaining capacitors except for the three high-order bits are controlled according to the output signal of the logic controller.

[0012] According to at least one embodiment of the present disclosure, the first path of the loop filter includes a switch, a capacitor, and a second operational amplifier. By turning on and off the switch, the residual voltages after conversion of the first capacitor array and the second capacitor array of the analog-to-digital converter are collected on the capacitor, and the second operational amplifier is used to perform active integration on the residual voltage and output the voltage after active integration to the comparator.

[0013] According to at least one embodiment of the present disclosure, the voltage of the first capacitor array is connected to the first input terminal of the second operational amplifier through two series switches, and the voltage of the second capacitor array is connected to the second input terminal of the second operational amplifier through two series switches. A capacitor is connected between the connection point of the two series switches at the first input terminal and the connection point of the two series switches at the second input terminal.

[0014] According to at least one embodiment of the present disclosure, the second path of the loop filter includes a switch, a first capacitor, a first operational amplifier, a second capacitor, and a second operational amplifier. By turning on and off the switch, the residual voltages after conversion of the first capacitor array and the second capacitor array of the analog-to-digital converter are collected on the first capacitor, and the voltage of the first capacitor is converted to the second capacitor through the processing of the first operational amplifier. The second operational amplifier is used to perform active integration on the residual voltage and output the voltage after active integration to the comparator.

[0015] According to at least one embodiment of the present disclosure, the voltage of the first capacitor array is connected to the first input terminal of the first operational amplifier through two first series switches, the voltage of the second capacitor array is connected to the second input terminal of the first operational amplifier through two second series switches, a first capacitor is connected between the connection point of the two first series switches and the connection point of the two second series switches, and the first output terminal of the first operational amplifier is connected to the first input terminal of the second operational amplifier through two third series switches, the second output terminal of the first operational amplifier is connected to the second input terminal of the second operational amplifier through two fourth series switches, and a second capacitor is connected between the connection point of the two third series switches and the connection point of the two fourth series switches.

[0016] According to at least one embodiment of the present disclosure, the first operational amplifier and the second operational amplifier share a substrate.

[0017] According to at least one embodiment of the present disclosure, in the first operational amplifier and the second operational amplifier, the gate of the first NMOS transistor serves as the second input terminal, the gate of the second NMOS transistor serves as the first input terminal, the drain of the first NMOS transistor is connected to the source of the third NMOS transistor, the drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor, the gates of the third NMOS transistor and the fourth NMOS transistor N4 are connected, the sources of the first NMOS transistor and the second NMOS transistor are connected to the drains of the fifth NMOS transistor and the sixth NMOS transistor, and the sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded, wherein the gate of the fifth NMOS transistor is connected to the common-mode feedback voltage, the gate of the sixth NMOS transistor is connected to the bias voltage, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor and serves as the first output terminal of the operational amplifier, the drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor and serves as the second output terminal of the operational amplifier, the gates of the first PMOS transistor and the second PMOS transistor are connected, the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are connected. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the input voltage.

[0018] According to at least one embodiment of the present disclosure, the preamplifier circuit includes two sets of input terminals, wherein the first set of input terminals receives the voltage signals of the first capacitor array and the second capacitor array, and the second set of input terminals can receive the output signal of the loop filter. Description of the Drawings

[0019] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are included in this specification and form a part of this specification.

[0020] Figure 1 A block diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0022] Figure 3 A schematic diagram of a loop filter according to an embodiment of the present disclosure is shown.

[0023] Figure 4 A schematic diagram of an operational amplifier according to an embodiment of the present disclosure is shown.

[0024] Figure 5 A schematic diagram of a comparator according to an embodiment of the present disclosure is shown.

[0025] Figure 6 A diagram showing the test results of a comparator according to an embodiment of the present disclosure is shown.

[0026] Figure 7 A schematic diagram of timing control according to an embodiment of the present disclosure is shown.

[0027] Figure 8 A schematic diagram of the power consumption of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0028] Figures 9-11 A schematic diagram of the performance of an analog-to-digital converter according to an embodiment of the present disclosure is shown. Detailed Embodiments

[0029] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the sake of convenience of description, only parts related to the present disclosure are shown in the drawings.

[0030] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

[0031] Unless otherwise specified, the illustrated exemplary embodiments will be understood to provide exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Accordingly, unless otherwise specified, the features of the various embodiments can be additionally combined, separated, interchanged, and / or rearranged without departing from the technical concept of the present disclosure.

[0032] In the drawings, cross-hatching and / or shading are generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for the specific materials, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be exaggerated. When the exemplary embodiments can be implemented differently, the specific process orders may be performed in an order different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. Further, the same reference numerals denote the same components.

[0033] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on, directly connected to, or directly coupled to the other component, or there may be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. To this end, the term "connected" can refer to a physical connection, an electrical connection, etc., and can have or not have intervening components.

[0034] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "underneath", "above", "on", "over", "upper", and "side (e.g., as in "sidewall")" to describe the relationship of one component to another (other) component as shown in the drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both "above" and "under" orientations. Additionally, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0035] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when the terms "comprises" and / or "comprising" and their variants are used in this specification, it is stated that the stated features, integers, steps, operations, components, assemblies, and / or groups thereof exist, but do not preclude the existence or addition of one or more other features, integers, steps, operations, components, assemblies, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and thus they are used to explain the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0036] According to one embodiment of the present disclosure, a low-power successive approximation analog-to-digital converter (SAR ADC) is provided.

[0037] Figure 1 An analog-to-digital converter according to one embodiment of the present disclosure is shown. As Figure 1 shown, the analog-to-digital converter may include a first capacitor array 100, a second capacitor array 200, a loop filter 300, a comparator 400, a logic controller 500, and a dynamic element matching circuit 600.

[0038] The first capacitor array 100 may be a positive capacitor array. The second capacitor array 200 may be a negative capacitor array. For the specific forms of the two capacitor arrays, reference may be made to the following description regarding Figure 2 this. Additionally, each capacitor may include a plurality of capacitors, and each switch connected to the capacitor is included. By turning on or off the switch, the capacitor is connected to the corresponding voltage. The input end of the loop filter 200 may be respectively connected to the first capacitor array and the second capacitor array, and the output end is connected to the comparator 400. The comparator 400 may have two sets of inputs. One set of inputs is used to receive the voltage signals of the first capacitor array and the second capacitor array, and the other set of inputs may be connected to the output end of the loop filter to perform a subtraction operation. The logic controller 500 compares the output result of the comparator to control the switches of the first capacitor array 100 and the second capacitor array 200 to perform successive approximation analog-to-digital conversion.

[0039] The first capacitor array 100 may include first low-order segment capacitors and first high-order segment capacitors. In the present disclosure, the first low-order segment capacitors may include three capacitors, while the first high-order segment capacitors may include seven capacitors. The high-order capacitors in the first high-order segment capacitors may be controlled using a thermometer code. In the present disclosure, a dynamic element matching circuit 600 may be utilized to average the high-order capacitor errors. The second capacitor array 200 may include second low-order segment capacitors and second high-order segment capacitors. In the present disclosure, the second low-order segment capacitors may include three capacitors, while the second high-order segment capacitors may include seven capacitors. The high-order capacitors in the second high-order segment capacitors may be controlled using a thermometer code. In the present disclosure, a dynamic element matching circuit 600 may be utilized to average the high-order capacitor errors. As an embodiment, the dynamic element matching circuit 600 may be a data weighted averaging (DWA) module, and the data weighted averaging module is connected to the output of the logic controller and controls the high-order capacitors using a thermometer code encoding method.

[0040] Figure 2 Specific implementation manners according to embodiments of the present disclosure are shown. The embodiments of the present disclosure will be described in detail below with reference to Figure 2 to describe the embodiments of the present disclosure in detail.

[0041] The first capacitor array 100 is a positive electrode capacitor array and may include first high-order segment capacitors B1 - B7 (MSB) and first low-order segment capacitors B8 - B10 (LSB). Among them, the three high-order capacitors B1 - B3 in the first high-order segment capacitors B1 - B7 may be controlled using a thermometer code. The second capacitor array 200 is a negative electrode capacitor array and may include second high-order segment capacitors B1 - B7 (MSB) and second low-order segment capacitors B8 - B10 (LSB). Among them, the three high-order capacitors B1 - B3 in the second high-order segment capacitors B1 - B7 may be controlled using a thermometer code.

[0042] The capacitors B4 - B10 of the first capacitor array 100 and the capacitors B4 - B10 of the second capacitor array 200 are connected to corresponding switches, and by controlling the conduction and disconnection of each switch, switching is performed between the voltages VRN and VRP. The capacitors B1 - B3 of the first capacitor array 100 and the capacitors B1 - B3 of the second capacitor array 200 are connected to corresponding switches, and switching is performed between the voltages VRN, VRP, and Vi.

[0043] First

[0044] Comparator 400 includes a first input terminal and a second input terminal. The first input terminal and the second input terminal respectively receive the voltages of the first capacitor array 100 and the second capacitor array 200, compare the magnitudes of the voltages between the first capacitor array 100 and the second capacitor array 300, and provide the comparison result to the logic controller 500. In addition, the comparator 400 further includes a third input terminal and a fourth input terminal. The third input terminal is connected to the first output terminal of the loop filter 300, and the fourth input terminal is connected to the second output terminal of the loop filter 300.

[0045] The first input terminal of the loop filter 300 is connected to the first capacitor array 100, and the second input terminal is connected to the second capacitor array 200. The loop filter 300 performs noise shaping on the residual voltage of the capacitor array. In the present disclosure, the loop filter 300 is used to implement the functions of first-order term shaping filtering and second-order term shaping filtering.

[0046] Figure 3 A specific implementation manner of the loop filter 300 according to the present disclosure is provided. As Figure 3 shown, the loop filter 300 may be provided with two paths, where the first path is the path from the upper-side VIP / VIN to VOUTN / VOUTP, and the second path is the path from the lower-side VIP / VIN to VOUTN / VOUTP.

[0047] In the first path, the VIP terminal is connected to the first capacitor array 100, and the VIN terminal is connected to the second capacitor array 200. The voltages of the VIP terminal and the VIN terminal are converted to the two input terminals of the second operational amplifier OTA2 through switches and capacitors. The second operational amplifier performs active integration on the residual voltage and outputs the integrated voltage to the comparator. First-order term shaping filtering can be achieved in the first path. In the first path, the VIP terminal is connected to one input terminal of the second operational amplifier through two series switches, and the VIN terminal is connected to the other input terminal of the second operational amplifier through two series switches. A capacitor 2C is connected between the connection points of the two series switches.

[0048] In the second path, the VIP terminal is connected to the first capacitor array 100, and the VIN terminal is connected to the second capacitor array 200. The voltages of the VIP terminal and the VIN terminal are converted to the two input terminals of the first operational amplifier OTA1 through switches and capacitors. The first operational amplifier is used to collect the residual voltages converted by the first capacitor array and the second capacitor array onto the capacitor C (one end of the two capacitors C is grounded to VSS). And the voltage of the capacitor C is converted to the two input terminals of the second operational amplifier through a switch. The second operational amplifier is used to perform active integration on the residual voltage and output the voltage after active integration to the comparator. The voltage of the first capacitor array is connected to the first input terminal of the first operational amplifier through two first series switches, and the voltage of the second capacitor array is connected to the second input terminal of the first operational amplifier through two second series switches. A first capacitor is connected between the connection point of the two first series switches and the connection point of the two second series switches. And the first output terminal of the first operational amplifier is connected to one input terminal of the second operational amplifier through two third series switches, and the second output terminal of the first operational amplifier is connected to the second input terminal of the second operational amplifier through two fourth series switches. A second capacitor is connected between the connection point of the two third series switches and the connection point of the two fourth series switches

[0049] In the present disclosure, the operational amplifier adopts a cascode structure (common-source common-gate amplifier) to improve the gain of the operational amplifier. Additionally, the first operational amplifier and the second operational amplifier can adopt the same substrate (Cell).

[0050] Figure 4 The circuit diagram of the operational amplifier according to the structure of the present disclosure is shown. Among them, taking the second operational amplifier as an example for illustration, the structure of the first operational amplifier can be the same.

[0051] The operational amplifier may include NMOS transistors and PMOS transistors. The gate of the first NMOS transistor N1 may serve as the negative input terminal VINN, and the gate of the second NMOS transistor N2 may serve as the positive input terminal VINP. The drain of the first NMOS transistor N1 may be connected to the source of the third NMOS transistor N3, and the drain of the second NMOS transistor N2 may be connected to the source of the fourth NMOS transistor N4. The gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 may be connected. The sources of the first NMOS transistor N1 and the second NMOS transistor N2 may be connected to the drains of the fifth NMOS transistor N5 and the sixth NMOS transistor N6, and the sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 may be grounded to VSS. Among them, the gate of the fifth NMOS transistor N5 may be connected to the common-mode feedback voltage VCMFB, and the gate of the sixth NMOS transistor N6 may be connected to the bias voltage VB1. The drain of the third NMOS transistor N3 is connected to the drain of the first PMOS transistor P1 and serves as the first output terminal (positive output terminal) of the operational amplifier. The drain of the fourth NMOS transistor N4 is connected to the drain of the second PMOS transistor P2 and serves as the second output terminal (negative output terminal) of the operational amplifier. The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected. The source of the first PMOS transistor P1 is connected to the drain of the third PMOS transistor P3, and the source of the second PMOS transistor P2 is connected to the drain of the fourth PMOS transistor P4. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected. The sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the voltage VDD.

[0052] In the present disclosure, the comparator 400 may adopt the structure of a preamplifier circuit + a latch circuit. This can achieve no static current consumption.

[0053] As Figure 5 shown, the preamplifier circuit 410 may include two sets of input terminals. As Figure 2 shown, one set of inputs may receive the voltage signal of the capacitive top plate of the capacitor array, and the other set of inputs may receive the output signal of the loop filter 300.

[0054] The preamplifier circuit 410 may include a first N-type field effect transistor N11 and a second N-type field effect transistor N12. The gates of the first N-type field effect transistor N11 and the second N-type field effect transistor N12 serve as the input terminals of the first group of inputs, and are respectively used to receive the voltage signals IP and IN of the capacitor top plates of the first capacitor array and the second capacitor array. The sources of the first N-type field effect transistor N11 and the second N-type field effect transistor N12 are connected and connected to the drain of a third N-type field effect transistor N13. The source of the third N-type field effect transistor N13 is grounded, and the gate is connected to the clock signal CLKD. The drains of the first N-type field effect transistor N11 and the second N-type field effect transistor N12 are respectively connected to the latch circuit 420.

[0055] The second path of input may include a fourth N-type field effect transistor N14 and a fifth N-type field effect transistor N15. The gates of the fourth N-type field effect transistor N14 and the fifth N-type field effect transistor N15 serve as the input terminals of the second group of inputs, and are respectively used to receive the two output signals IP1 and IN1 of the loop filter 300. The sources of the fourth N-type field effect transistor N14 and the fifth N-type field effect transistor N15 are connected and connected to the drain of a sixth N-type field effect transistor N16. The source of the sixth N-type field effect transistor N16 is grounded, and the gate is connected to the clock signal CLKD. The drains of the fourth N-type field effect transistor N14 and the fifth N-type field effect transistor N12 are respectively connected to the latch circuit 420.

[0056] In addition, the drain of the first P-type field effect transistor P11 is connected to the drains of the second N-type field effect transistor N12 and the fifth N-type field effect transistor N15. The source of the first P-type field effect transistor P11 is connected to the voltage VDD, and the gate of the first P-type field effect transistor P11 is connected to the clock signal CLKD. The drain of the second P-type field effect transistor P12 is connected to the drains of the second N-type field effect transistor N12 and the fifth N-type field effect transistor N15. The source of the second P-type field effect transistor P12 is connected to the voltage VDD, and the gate of the second P-type field effect transistor P12 is connected to the clock signal CLKD.

[0057] The latch circuit 420 is respectively connected to the drains of the first N-type field effect transistor N11 and the second N-type field effect transistor N12 as the input of the first group of signals, and is respectively connected to the drains of the fourth N-type field effect transistor N14 and the fifth N-type field effect transistor N15 as the input of the second group of signals.

[0058] The latch circuit 420 may include a seventh N-type field effect transistor N17, an eighth N-type field effect transistor N18, a ninth N-type field effect transistor N19, and a tenth N-type field effect transistor N20. The sources of the seventh N-type field effect transistor N17, the eighth N-type field effect transistor N18, the ninth N-type field effect transistor N19, and the tenth N-type field effect transistor N20 are grounded. The gate of the seventh N-type field effect transistor N17 may be connected to the drain of the first P-type field effect transistor P11, and the gate of the tenth N-type field effect transistor N20 may be connected to the second P-type field effect transistor P12.

[0059] The drain of the seventh N-type field effect transistor N17 is connected to the drain of the eighth N-type field effect transistor N18. The drains of the ninth N-type field effect transistor N19 and the tenth N-type field effect transistor N20 are connected. The drain of the seventh N-type field effect transistor N17 and the drain of the eighth N-type field effect transistor N18 are connected to the drain of the third P-type field effect transistor P13. The gate of the eighth N-type field effect transistor N18 is connected to the gate of the third P-type field effect transistor P13 and is connected to the drain of the ninth N-type field effect transistor N19. The gate of the ninth N-type field effect transistor N19 is connected to the gate of the fourth P-type field effect transistor P14 and is connected to the drain of the eighth N-type field effect transistor N18. The sources of the third P-type field effect transistor P13 and the fourth P-type field effect transistor P14 are connected to the drain of the fifth P-type field effect transistor P15, and the gate of the fifth P-type field effect transistor P15 is connected to the clock signal CLKN. The source of the fifth P-type field effect transistor P15 is connected to the voltage VDD.

[0060] In addition, the drain of the ninth N-type field effect transistor N19 may also be connected to a series circuit of a sixth P-type field effect transistor P16 and an eleventh N-type field effect transistor N21. Specifically, the drain of the ninth N-type field effect transistor N19 is connected to the gates of the sixth P-type field effect transistor P16 and the eleventh N-type field effect transistor N21, the drains of the sixth P-type field effect transistor P16 and the eleventh N-type field effect transistor N21 are connected, the source of the sixth P-type field effect transistor P16 is connected to the voltage VDD, and the source of the eleventh N-type field effect transistor N21 is grounded to VSS.

[0061] The drain of the eighth N-type field effect transistor N18 is connected to the gates of a seventh P-type field effect transistor P17 and a twelfth N-type field effect transistor N22. The source of the seventh P-type field effect transistor P17 is connected to the voltage VDD. The drains of the seventh P-type field effect transistor P17 and the twelfth N-type field effect transistor N22 are connected. The source of the twelfth N-type field effect transistor N22 is grounded to VSS.

[0062] The drains of the seventh P-type field effect transistor P17 and the twelfth N-type field effect transistor N22 are also connected to the gates of the eighth P-type field effect transistor P18 and the thirteenth N-type field effect transistor N23. The source of the eighth P-type field effect transistor P18 is connected to the voltage VDD, the drains of the eighth P-type field effect transistor P187 and the thirteenth N-type field effect transistor N23 are connected, and the source of the thirteenth N-type field effect transistor N23 is grounded to VSS. In addition, the drains of the eighth P-type field effect transistor P187 and the thirteenth N-type field effect transistor N23 serve as the signal output terminal OP.

[0063] Figure 6 shows the OFFSET situation of the comparator circuit according to Figure 5 the circuit design. It can be seen from the figure that the standard deviation of its OFFSET is 1.3 mV.

[0064] In addition, for Figure 5 the generation of the clock signals CLKN and CLKN in, the clock signal CLKN can be used for generation, and the generation circuit is shown in the lower left corner of Figure 5 .

[0065] In Figure 7 , the timing diagram of the analog-to-digital conversion is shown. As Figure 7 shown, one conversion requires 16 synchronous clock cycles. Among them, the input signal is sampled (F-sample) within 1 - 2 cycles; 10 SAR logic conversions (SARCONVERSION) are performed in cycles 3 - 12; before the conversion is completed, F_AMP is used to control the access of the residual voltage signal of the capacitor to the loop filter; F_EF is used for the establishment of the operational amplifier in the filter; F_EF2 is used for one charge transfer to achieve the second-order filtering effect. The positions of the circuits corresponding to F_AMP, F_EF, and F_EF2 are as Figure 3 shown.

[0066] In the present disclosure, the applicant measured the proposed analog-to-digital converter. Among them, the analog power supply AVDD is 5V, which is mainly used for the filter and comparator circuits, while the digital voltage DVDD is 5V, mainly used for logic circuits, clock circuits, etc. According to the measurement results, it can be known that the total power consumption of the analog-to-digital converter is 1.458 mW, as Figure 8 shown. Therefore, the overall power consumption of the analog-to-digital converter can be effectively reduced, achieving the purpose of low power consumption.

[0067] In addition, in order to test the analog-to-digital converter of the present disclosure, after adding 1% random mismatch to the capacitor, the test results with the dynamic element matching circuit turned on and off can be as Figure 9 and Figure 10As shown. As shown in the figure, when the dynamic element matching circuit is turned on, the effective number of bits of the analog-to-digital converter can be 13 bits, and when the dynamic element matching circuit is not turned on, the effective number of bits of the analog-to-digital converter can be 11.6 bits. In addition, when the input signal is a sine wave of 0.8Verf (reference voltage), the spectrum of the analog-to-digital converter is as Figure 11 shown, and the effective number of bits is about 16 bits. According to the test results, it can be seen that according to the capacitor array, loop filter, comparator, etc. of the present disclosure, the purpose of low power consumption can be achieved and the purpose of analog-to-digital conversion can be well achieved.

[0068] In the description of this specification, the description of reference terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0069] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, "a plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0070] Those skilled in the art should understand that the above embodiments are only for clearly explaining the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. An analog-to-digital converter, characterized in that, Comprising: A first capacitor array and a second capacitor array, the first capacitor array and the second capacitor array being a positive electrode capacitor array and a negative electrode capacitor array respectively, and including capacitors and switches connected to the capacitors, and connecting the capacitors to different voltages by switching the switches. The first capacitor array includes first low-order segment capacitors and first high-order segment capacitors, and the second capacitor array includes second low-order segment capacitors and second high-order segment capacitors; A loop filter, the loop filter including a first path and a second path, the first path and the second path being connected to the first capacitor array and the second capacitor array respectively, and the first path being used for first-order term shaping filtering, while the second path being used for second-order term shaping filtering; A comparator, the comparator including a first set of input terminals and a second set of input terminals, the first set of input terminals being used for connecting the first capacitor array and the second capacitor array, and the second set of input terminals being used for connecting the output of the loop filter; A logic controller, the logic controller controlling the switches of the first capacitor array and the second capacitor array for successive approximation analog-to-digital conversion according to the output signal of the comparator; And A dynamic element matching circuit, the dynamic element matching circuit being used for controlling the switches of the three high-order capacitors of the first high-order segment capacitor and the switches of the three high-order capacitors of the second high-order segment capacitor according to the output of the logic controller; The comparator is composed of a preamplifier circuit and a latch circuit; The second path of the loop filter includes a switch, a first capacitor, a first operational amplifier, a second capacitor and a second operational amplifier. By turning on and off the switch, the residual voltage after conversion of the first capacitor array and the second capacitor array of the analog-to-digital converter is collected on the first capacitor, and the voltage of the first capacitor is converted to the second capacitor through the processing of the first operational amplifier, and the second operational amplifier is used for actively integrating the residual voltage and outputting the voltage after active integration to the comparator; The voltage of the first capacitor array is connected to the first input terminal of the first operational amplifier through two first series switches, the voltage of the second capacitor array is connected to the second input terminal of the first operational amplifier through two second series switches, a first capacitor is connected between the connection point of the two first series switches and the connection point of the two second series switches, and the first output terminal of the first operational amplifier is connected to the first input terminal of the second operational amplifier through two third series switches, the second output terminal of the first operational amplifier is connected to the second input terminal of the second operational amplifier through two fourth series switches, and a second capacitor is connected between the connection point of the two third series switches and the connection point of the two fourth series switches.

2. The analog-to-digital converter according to claim 1, wherein, The first low-order segment capacitors of the first capacitor array include three-bit capacitors, while the first high-order segment capacitors include seven-bit capacitors. The second low-order segment capacitors of the second capacitor array include three-bit capacitors, while the second high-order segment capacitors include seven-bit capacitors. The first low-order segment capacitors and the second low-order segment capacitors are controlled according to the output signal of the logic controller. The capacitors of the remaining bits in the first high-order segment capacitors and the second high-order segment capacitors, except for the three high-order bits, are controlled according to the output signal of the logic controller.

3. The analog-to-digital converter according to claim 1, characterized in that, The first path of the loop filter includes a switch, a capacitor, and a second operational amplifier. By turning the switch on and off, the residual voltages after conversion of the first capacitor array and the second capacitor array of the analog-to-digital converter are collected on the capacitor, and the second operational amplifier is used to perform active integration on the residual voltages and output the voltage after active integration to the comparator.

4. The analog-to-digital converter according to claim 3, wherein The voltage of the first capacitor array is connected to the first input terminal of the second operational amplifier through two series switches, and the voltage of the second capacitor array is connected to the second input terminal of the second operational amplifier through two series switches. A capacitor is connected between the connection point of the two series switches at the first input terminal and the connection point of the two series switches at the second input terminal.

5. The analog-to-digital converter according to claim 1, characterized in that, The first operational amplifier and the second operational amplifier share a substrate.

6. The analog-to-digital converter according to claim 1, wherein In the first operational amplifier and the second operational amplifier, the gate of the first NMOS transistor serves as the second input terminal, the gate of the second NMOS transistor serves as the first input terminal. The drain of the first NMOS transistor is connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor N4. The sources of the first NMOS transistor and the second NMOS transistor are connected to the drains of the fifth NMOS transistor and the sixth NMOS transistor, and the sources of the fifth NMOS transistor and the sixth NMOS transistor are grounded. The gate of the fifth NMOS transistor is connected to the common-mode feedback voltage, and the gate of the sixth NMOS transistor is connected to the bias voltage. The drain of the third NMOS transistor is connected to the drain of the first PMOS transistor and serves as the first output terminal of the operational amplifier. The drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor and serves as the second output terminal of the operational amplifier. The gates of the first PMOS transistor and the second PMOS transistor are connected. The source of the first PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are connected. The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the input voltage.

7. The analog-to-digital converter according to claim 1, characterized in that, The preamplification circuit includes two sets of input terminals. The first set of input terminals receives the voltage signals of the first capacitor array and the second capacitor array, and the second set of input terminals can receive the output signal of the loop filter.

Images