Electro-optical devices processed using deep ultraviolet radiation

Abstract

An optical device is described. At least a portion of the optical device comprises one or more ferroelectric nonlinear optical materials and is processed using ultraviolet lithography. In some aspects, the at least a portion of the optical device is processed using deep ultraviolet lithography. In some aspects, a short-range root mean square surface roughness of a sidewall of the at least a portion of the optical device is less than ten nanometers. In some aspects, the at least a portion of the optical device has a loss of no more than 2 dB / cm.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation-in-part of co-pending U.S. Patent Application No. 16 / 785,206, filed on February 7, 2020, entitled “LITHIUM NIOBATE DEVICES FABRICATED USING DEEP ULTRAVIOLET RADIATION,” which is incorporated herein by reference for all purposes. Background Art

[0003] Optical devices, such as waveguides, are used in a variety of applications. It may be desirable to use lithium niobate devices in waveguides, resonators, and other optical and electro-optical devices. However, lithium niobate is notoriously difficult to process into devices with desirable performance characteristics. Therefore, a mechanism for providing optical devices using lithium niobate with adequate performance characteristics is desirable. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

[0005] Figures 1A-1B An embodiment of an optical device including lithium niobate processed using ultraviolet photolithography is depicted.

[0006] Figure 2 Depicted are examples indicating measurements of transmission in an optical device comprising lithium niobate and processed using ultraviolet lithography.

[0007] Figure 3 is a flow chart depicting an embodiment of a method for forming an optical device including lithium niobate using ultraviolet photolithography.

[0008] Figure 4-8 An embodiment of an optical device including lithium niobate formed using ultraviolet photolithography during processing is depicted.

[0009] Figure 9 is a flow chart depicting an embodiment of a method for forming an optical device including lithium niobate using deep ultraviolet lithography.

[0010] Figure 10-15 Another embodiment of an optical device including lithium niobate formed using ultraviolet photolithography during processing is depicted.

[0011] Figure 16-21 Another embodiment of an optical device including lithium niobate formed using ultraviolet photolithography during processing is depicted. DETAILED DESCRIPTION

[0012] The present invention can be implemented in many ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor configured to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of the disclosed processes may be changed within the scope of the invention.

[0013] The following provides a detailed description of one or more embodiments of the present invention and accompanying drawings that illustrate the principles of the present invention. The present invention is described in conjunction with such embodiments, but the present invention is not limited to any embodiment. The scope of the present invention is limited only by the claims, and the present invention includes many alternatives, variations and equivalents. In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. These details are provided for illustrative purposes, and the present invention can be implemented according to the claims without some or all of these specific details. For the purpose of clarity, technical materials known in the technical field related to the present invention are not described in detail to avoid unnecessarily obscuring the present invention.

[0014] Lithium niobate (LN) is expected to be used in optical devices, particularly electro-optical devices. As used herein, optical devices can include both optical and electro-optical devices. The desirability of LN is due, at least in part, to its change in refractive index with an applied external electric field. However, processing LN optical devices with desired performance characteristics is challenging. For example, LN optical devices can exhibit higher than desired loss. Recently, electron beams have been used to process LN optical devices to pattern the mask layer (e.g., via electron beam lithography). The underlying hard mask and LN layer can be etched using other techniques. The resulting LN optical devices can have improved performance. However, electron beam lithography is time-consuming, can be non-uniform, and can have limited reproducibility. Electron beams use a scanning process to pattern the mask, which is inherently slow. Furthermore, electron beams are subject to drift during use. Because beam deflection is limited in range, electron beam lithography can only pattern relatively small areas (e.g., approximately one square millimeter or less). To pattern larger areas, the electron beam stage is moved and electron beam lithography is repeated. Besides slowing down production throughput, this aspect of electron beam lithography can also cause misalignments at the joints between these areas. These misalignments adversely affect the performance of the device being processed. Therefore, an improved method for processing LN optical devices is desired.

[0015] Other nonlinear optical materials may suffer from similar disadvantages as LN. For example, lithium tantalate (e.g., LiTaO3) has similar optical properties to LN. Processing lithium tantalate (LT) can also be challenging. Furthermore, LT can be susceptible to damage during high-temperature processing methods. It may also be desirable to use other ferroelectric nonlinear (e.g., second-order) optical materials in optical devices. Such ferroelectric nonlinear optical materials may include, but are not limited to, potassium niobate (e.g., KNbO3), gallium arsenide (GaAs), potassium titanyl phosphate (KTP), lead zirconate titanate (PZT), and barium titanate (BaTiO3). The described techniques may also be applied to other nonlinear ferroelectric optical materials, particularly those whose processing may otherwise be challenging. For example, such nonlinear ferroelectric optical materials may exhibit inert chemical etching reactions using conventional etching chemistries, such as fluorine, chlorine, or bromine compounds. Therefore, an improved method for processing devices using ferroelectric nonlinear optical materials, such as LT, is desirable.

[0016] Methods for fabricating an optical device and the optical device thus formed are described. At least a portion of the optical device includes LN and is fabricated using photolithography, such as deep ultraviolet (DUV) lithography. Fabricating the optical device may include providing a hard mask layer on the LN layer and fabricating a mask on the hard mask layer. This mask is formed using DUV photolithography. More specifically, the mask layer is provided, for example, by spin coating on a DUV photoresist. The mask layer may be thermally treated. Portions of the mask layer may be selectively exposed to electromagnetic radiation in the DUV wavelength range. In some embodiments, the mask layer is thermally treated again after exposure. The mask layer is developed. Portions of the mask layer are thereby removed to form a pattern of apertures that expose the underlying hard mask layer. A hard mask is formed from the hard mask layer by transferring the pattern of the mask to the hard mask layer. For example, portions of the hard mask layer exposed by the apertures in the mask may be selectively etched. The hard mask may have recesses or apertures in the etched areas of the hard mask layer. The pattern of the hard mask can be transferred to the LN layer, for example, using physical etching. Multiple exposures can be performed on at least a plurality of tiled areas across the surface of the substrate. In some cases, each of these tiled areas is at least ten millimeters by ten millimeters. In some embodiments, the tiled areas can be at least fifteen millimeters by fifteen millimeters. In some embodiments, each tiled area is at least twenty millimeters by twenty millimeters. Thus, longer and / or more optical devices comprising LN can be processed using DUV lithography within a single tiled area.

[0017] LNs in optical devices processed using DUV lithography have improved surface roughness on one or more sidewalls. For example, the short-range root mean square (RMS) surface roughness of the sidewalls of LNs in optical devices formed using DUV lithography is less than ten nanometers. In some embodiments, this RMS surface roughness is no more than five nanometers. In some cases, the short-range RMS surface roughness is no more than two nanometers. LNs in optical devices can also have improved performance. In some aspects, LNs in optical devices have a loss of no more than 2 dB / cm. In some embodiments, the LNs have a loss of less than 1.0 dB / cm. In some cases, this loss is no more than 0.5 dB / cm. Consequently, the performance of optical devices incorporating LNs can be improved.

[0018] Although described in the context of LN, the devices and methods described herein can be applied to other nonlinear (e.g., second-order) optical materials, particularly ferroelectric nonlinear optical materials that can be difficult to process using conventional techniques. Such nonlinear ferroelectric optical materials can exhibit an inert chemical etching reaction to conventional etching using chemistries such as fluorine, chlorine, or bromine compounds. For example, LT, potassium niobate, gallium arsenide, potassium titanyl phosphate, lead zirconate titanate, and / or barium titanate can be used instead of or in addition to LN. For example, methods of processing an optical device and the optical device thus formed include at least a portion of the optical device including one or more ferroelectric nonlinear optical materials (e.g., LT) and processed using photolithography (e.g., DUV lithography). Processing the optical device can include providing a hard mask layer on the ferroelectric nonlinear optical layer and processing a mask on the hard mask layer. Such a mask can be formed using DUV photolithography. More specifically, the mask layer can be provided, for example, by spin coating on a DUV photoresist. The mask layer can be thermally treated. Portions of the mask layer can be selectively exposed to electromagnetic radiation in the DUV wavelength range. In some embodiments, the mask layer is thermally treated again after exposure. The mask layer is developed. As a result, portions of the mask layer are removed to form a pattern of apertures that expose the underlying hard mask layer. A hard mask is formed from the hard mask layer by transferring the mask pattern to the hard mask layer. For example, portions of the hard mask layer exposed by the apertures in the mask can be selectively etched. The hard mask can have recesses or apertures in the etched areas of the hard mask layer. The hard mask pattern can be transferred to the ferroelectric nonlinear optical layer, for example, using physical etching. Multiple exposures can be performed on at least a plurality of tiled areas across the surface of the substrate. In some cases, each of these tiled areas is at least ten millimeters by ten millimeters. In some embodiments, the tiled areas can be at least fifteen millimeters by fifteen millimeters. In some embodiments, each tiled area is at least twenty millimeters by twenty millimeters. Thus, DUV lithography can be used to process longer and / or more optical devices including LN within a single tiled area.

[0019] Ferroelectric nonlinear optical material(s) in an optical device processed using DUV lithography have improved surface roughness on the sidewall(s). For example, the short-range root mean square (RMS) surface roughness of the sidewalls of the ferroelectric nonlinear optical material(s) (e.g., LT) in the optical device formed using DUV lithography is less than ten nanometers. In some embodiments, this RMS surface roughness is no more than five nanometers. In some cases, the short-range RMS surface roughness is no more than two nanometers. Ferroelectric nonlinear optical material(s) (e.g., LT) in the optical device can also have improved performance. In some aspects, the ferroelectric nonlinear optical material(s) in the optical device have a loss of no more than 2 dB / cm. In some embodiments, the ferroelectric nonlinear optical material(s) have a loss of less than 1.0 dB / cm. In some cases, this loss is no more than 0.5 dB / cm. Thus, the performance of an optical device including the ferroelectric nonlinear optical material(s) can be improved.

[0020] Figure 1A and 1B Depicted are embodiments of devices 100A and 100B, respectively, that include LN processing using photolithography, such as DUV lithography. Figure 1A is a diagram depicting a device 100A including an optical device 110A formed on a substrate 101A. Figure 1A Not drawn to scale. Substrate 101A may include a carrier wafer and any underlying layers between the wafer and optical device 110A. Optical device 110A includes an LN region. Although shown as only a portion of optical device 110A, the entire layer may be formed from LN. In some embodiments, optical device 110A may include other components not shown. Optical device 110A includes a flat region 111A, sidewalls 112A and 114A, and a top surface 116A. Thus, optical device 110 includes a ridge having sidewalls 112A and 114A and a top surface 116A. Therefore, in the illustrated embodiment, the LN layer is not completely etched through. In other embodiments and / or in other regions, the LN layer may be etched through to expose underlying layers (such as substrate 101A). In such embodiments, some or all of flat region 111A may be omitted.

[0021] Similarly, Figure 1BFIG1 is a micrograph of device 100B, which includes an optical device 110B formed on a substrate (not shown). The substrate may include a carrier wafer and any underlying layers between the wafer and optical device 110B. Optical device 110B includes an LN layer. In some embodiments, optical device 110B may include other components not shown. Optical device 110B includes a ridge and a flat region 111B, the ridge having sidewalls 112B and 114A and a top surface 116B.

[0022] The LN regions of optical devices 110A and 110B are formed using DUV lithography. As a result, sidewalls 112A, 114A, 112B, and 114B of optical devices 110A and 110B have improved surface roughness. Short-range root mean square (RMS) surface roughness is the RMS surface roughness over a length (e.g., along direction l) of no more than two hundred nanometers. The short-range RMS surface roughness of sidewalls 112A and 114A of the LN regions in optical device 110A and the short-range RMS surface roughness of LN optical device 110B are both less than ten nanometers. In some embodiments, the short-range RMS surface roughness of the LN regions of both optical devices 110A and LN optical device 110B is no more than five nanometers. In some embodiments, the short-range RMS surface roughness of the LN regions of both optical devices 110A and LN optical device 110B is no more than two nanometers. Additionally, in some embodiments, the short-range RMS roughness of each of top surfaces 116A and 116B does not exceed one nanometer. In some embodiments, the long-range (greater than 200 nanometers to 200 microns in length) RMS surface roughness of sidewalls 112A, 114A, 112B, and / or 114B can be different from the short-range RMS surface roughness.

[0023] Because of the improved smoothness, the optical device may have improved performance. Figure 2 You can see this, Figure 2Depicted is an embodiment 200 showing transmission measurements in an optical device comprising lithium niobate and fabricated using ultraviolet lithography. Graph 200 indicates transmission through a LN optical device (such as optical device(s) 110A and / or 110B) operating as a resonator. Dips in graph 200 indicate resonances. In some embodiments, the peaks are approximately picometer wide and indicate the efficiency of the corresponding optical devices. In some embodiments, the LN regions of optical device 110A and LN optical device 110B have a signal loss of no more than 5 dB / cm. In some embodiments, the LN regions of optical device 110A and LN optical device 110B each have a loss of no more than 2 dB / cm. In some such embodiments, the loss of each LN region of optical device 110A and LN optical device 110B is less than 1.0 dB / cm. For example, in some embodiments, such loss may be no more than 0.5 dB / cm.

[0024] Thus, optical devices 110A and 110B processed using DUV lithography can have reduced surface roughness and improved efficiency. Furthermore, because patterning is performed using DUV lithography, optical devices 110A and 110B can be processed with higher reproducibility, better uniformity, higher throughput, and over a larger area of ​​substrates 101A and 101B. Thus, methods for processing optical devices including LN and the optical devices formed thereby can be improved.

[0025] Figure 3 This is a flow chart depicting an embodiment of a method 300 for forming an optical device including LN using ultraviolet lithography (such as DUV lithography). Method 300 is described in the context of a process that may have subprocesses. Although described in a specific order, another order inconsistent with the description herein may be used. Method 300 begins after an LN layer has been provided on a substrate. In some embodiments, the LN layer may be thin, for example, not exceeding ten microns in thickness. In some embodiments, the LN layer may not exceed one micron in thickness. In some embodiments, the LN layer may not exceed seven hundred nanometers in thickness. In some such embodiments, the thickness may not exceed four hundred nanometers. Other thicknesses are possible. A bottom layer (such as silicon dioxide) may be present between the LN layer and a carrier wafer. In some embodiments, the carrier wafer may comprise silicon, quartz, silica, LN, sapphire, and / or another material. For example, the LN layer may be located on a silicon dioxide bottom layer having a nominal thickness of at least two microns and not exceeding five microns. Other thicknesses, additional layers, and / or other layers may be present.

[0026] At 302, a hard mask layer is provided. In some embodiments, the hard mask layer may include one or more of amorphous silicon, silicon dioxide, silicon nitride, ceramic, metal (e.g., Ti), or other hard mask materials. In some embodiments, at 302, chemical vapor deposition (CVD) or other deposition methods may be used.

[0027] At 304, a mask is formed on the hard mask layer using UV lithography. In some embodiments, 304 includes providing a mask layer. For example, the mask layer can be a photoresist layer spin-coated onto the hard mask layer. Using UV lithography, portions of the mask layer are selectively exposed. In some embodiments, the wavelength of electromagnetic radiation used for UV photolithography does not exceed 450 nanometers. In some embodiments, DUV lithography is used. For example, the wavelength of electromagnetic radiation used can be less than 250 nanometers. In some embodiments, other wavelengths of electromagnetic radiation can be used to expose the mask layer. Furthermore, as part of 304, the mask layer can be thermally treated (e.g., baked) before and / or after exposure. The exposed mask is also developed. In some embodiments, a post-development bake is not performed. As a result, portions of the mask layer are removed to form apertures in the mask layer. Thus, a mask having a pattern is formed.

[0028] At 306, a hard mask is provided from the hard mask layer. To achieve this, a mask formed by DUV lithography is used. Thus, the pattern from the mask can be transferred to the hard mask layer, thereby forming a hard mask. In some embodiments, 306 includes chemically and / or physically removing portions of the hard mask layer exposed by the pattern in the mask. In some embodiments, the removal at 306 forms apertures in the hard mask layer to provide the hard mask. In some embodiments, the removal at 306 forms recesses in the hard mask layer to provide the hard mask. A hard mask may be used in method 300 because a mask patterned using DUV lithography may be more easily removed by the etching process used to pattern the LN layer at 308, described below. This removal of the mask may result in sidewalls of the optical device having a higher surface roughness than desired. However, in other embodiments, for example, if a higher surface roughness can be tolerated, steps 302 and 304 may be omitted.

[0029] At 308, the LN layer is etched using a hard mask. Thus, the pattern in the hard mask can be transferred to the LN layer at 308. In some embodiments, physical etching is used at 308. For example, dry etching, reactive ion etching (RIE), plasma etching, and / or other physical etching mechanisms can be used at 308. In some embodiments, chemical etching or other etching methods can be used at 308. In embodiments where the hard mask includes recesses rather than apertures, the pattern transfer at 308 also removes at least some of the thinned portions of the hard mask. In some embodiments, the LN layer is not completely etched through at 308. Thus, the resulting optical device may be a raised portion or ridge remaining after 308. In some embodiments, portions of the LN layer may be etched through at 308. Furthermore, at 308, any remaining mask and / or hard mask may be removed.

[0030] At 310, some or all of method 300 may be optionally repeated. For example, at 304, a mask layer may be provided and baked. After one area is exposed, the stage may be moved to expose additional area(s) of the mask layer. Thus, this portion of 304 may be repeated. Once all desired areas have been exposed, the mask layer may be developed to provide a mask for the entire substrate. The pattern may then be transferred to underlying layers at 306 and 308. Thus, in some embodiments, at least a portion of 304 may be repeated one or more times. In other embodiments, 302, 304, 306, and 308 may be repeated for different areas of the substrate. Thus, multiple areas of a device may be processed. For example, a larger optical device and / or an optical device that extends across the edge of a patterned area may be formed.

[0031] For example, Figure 4-8 An embodiment of a device 400 comprising LN and formed using the method 300 during processing is depicted. Figure 4-8 The drawing is not to scale, and only a portion of the device 400 is shown. In addition, the device 400 is used for illustrative purposes and may not represent a specific device. For example, the sidewalls are generally shown as vertical and flat, while the top surface is generally shown as horizontal and flat. However, some variations are common.

[0032] Figure 4 Device 400 is depicted after a mask layer has been provided as part of step 304. Thus, substrate 401, which may include a carrier wafer, bottom layer 402, LN layer 410, hard mask layer 420, and DUV mask layer 430 are shown. Bottom layer 402 may be an insulator, such as silicon dioxide. In this embodiment, bottom layer 402 is depicted as separate from substrate 401. In some embodiments, other layers may be present and / or one or more of the layers shown may be omitted. For example, in some embodiments, bottom layer 402 may be omitted.

[0033] Figure 5 The device 400 is depicted after 304 has been completed. The DUV mask layer 430 has been selectively exposed to DUV light and developed. Thus, a DUV mask 430A has been formed. Portions of the hard mask layer 420 are exposed by the DUV mask 430A.

[0034] Figure 6 Device 400 is depicted after 306 has been completed. Thus, hard mask 420A has been formed. In the embodiment shown, the pattern of DUV mask 430A has been transferred to hard mask 420A. In the embodiment shown, hard mask 420A has recesses 422 in the areas where hard mask layer 430 was etched. Thus, the pattern of DUV mask 430A has been transferred to hard mask 420A.

[0035] Figure 7-8 Device 400 is depicted after 308 has been completed. DUV mask 430A and hard mask 420A have also been removed. Figure 7 is a cross-sectional view of the device 400 . Figure 8 is a plan view of the device 400 indicating the splicing (shown by the dashed lines). Thus, the LN optical device 410A is shown in Figure 7 and 8 In addition, Figure 8 LN optical device 410B is shown in FIG. In some embodiments, LN optical device 410A and / or LN optical device 410B include other components. However, for simplicity, only a portion of LN optical device 410A and a portion of LN optical device 410B are shown. LN optical devices 410A and 410B can be considered to be ridges formed in LN layer 410 by removing portions of the LN layer exposed by hard mask 420A. Therefore, the sidewalls of optical devices 410A and 410B (such as sidewalls 412 and 414) are the sidewalls of the ridges. In some embodiments, LN layer 410 can be etched through at 308. In such embodiments, underlying layers (such as bottom layer(s) 402) can be exposed after 308 is completed.

[0036] LN optics 410A and 410B are located in different stitching regions that are exposed at different times. Figure 8 As indicated in FIG, LN optical devices 410A and 410B may be misaligned. Therefore, LN optical devices 410A and 410B are slightly widened in the stitched area to reduce the effects of this misalignment. Therefore, in the illustrated embodiment, LN optical devices 410A and 410B can be considered as part of a single optical device spanning multiple stitched areas. DUV lithography is also used to form LN optical devices 410A and 410B. Therefore, each has sidewalls. Sidewalls 412 and 414 of LN optical device 410A are Figure 7 and 8 Due to the use of DUV lithography, sidewalls 412 and 414 have improved surface roughness. The short-range RMS surface roughness of sidewalls 412 and 414 of LN optical device 410A is each less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each of sidewalls 412 and 414 of LN optical device 410A is no more than five nanometers. In some embodiments, the short-range RMS surface roughness of each of sidewalls 412 and 414 of LN optical device 410A is no more than two nanometers. LN optical device 410B has similar short-range RMS surface roughness(ies) as LN optical device 410A.

[0037] Optical devices 410A and 410B can have improved performance. In some embodiments, each of LN optical devices 410A and 410B has a signal loss of no more than 5 dB / cm. In some embodiments, each of LN optical devices 410A and 410B has a signal loss of no more than 2 dB / cm. In some such embodiments, each of LN optical devices 410A and 410B has a signal loss of less than 1.0 dB / cm. For example, in some embodiments, such a signal loss may be no more than 0.5 dB / cm.

[0038] Thus, the LN optical devices 410A and 410B can have improved manufacturability, performance, and reduced sidewall surface roughness. Because DUV lithography is used, throughput can be increased and the time spent processing the device 400 is reduced, uniformity can be improved, and reproducibility can be enhanced. DUV lithography also has a large stitching area. For example, in some embodiments, a stitching area of ​​at least ten millimeters by ten millimeters can be subjected to DUV lithography in a single shot. In some embodiments, the stitching area can be at least fifteen millimeters by fifteen millimeters. For example, the stitching area can be nominally twenty millimeters by twenty millimeters or larger. Thus, a stitching area such as Figure 8 This not only increases throughput and reproducibility, but also reduces misalignment in the optical setup (e.g., as shown between LN optical setups 410A and 410B).

[0039] Figure 9This is a flow chart depicting an embodiment of a method 900 for forming an optical device including LN using DUV lithography. Method 900 is described in the context of a process that may have subprocesses. Although described in a specific order, another order inconsistent with the description herein may be used. Method 900 begins after an LN layer has been provided on a substrate (such as a carrier wafer). In some embodiments, the LN layer may be thin, for example, not exceeding ten microns in thickness. In some embodiments, the LN layer may be no thicker than one micron. In some embodiments, the LN layer may be no thicker than seven hundred nanometers. In some such embodiments, the thickness may be no more than four hundred nanometers. Other thicknesses are possible. One or more insulating underlayers (such as silicon dioxide) may be present between the LN layer and the underlying wafer. For example, the LN layer may be located on a silicon dioxide underlayer having a nominal thickness of at least two microns and no more than approximately five microns. Other thicknesses, additional layers, and / or other layers may be present.

[0040] At 902, a stop layer may be provided. The stop layer is insensitive to the etch that may be used to form the hardmask. For example, if a chemical etch is used to selectively remove portions of the hardmask layer, as discussed below, the stop layer provided at 902 is insensitive to the chemistry used for such an etch. If multiple etches are used to form the hardmask, it is desirable that the stop layer provided at 902 is insensitive to at least the final etch (or etches) used to pattern the hardmask. The etch stop layer provided at 902 may also be removed without excessive damage to the underlying LN layer. In some embodiments, 902 may be omitted.

[0041] At 904, a hard mask layer is provided. In some embodiments, the hard mask can include one or more of amorphous silicon, silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, ceramic, another semiconductor, and / or other hard mask materials. In some embodiments, a metal hard mask can be used. In some embodiments, CVD, plasma-enhanced CVD, or other deposition methods can be used at 904.

[0042] At 906, an antireflective coating (ARC) layer is provided on the hard mask layer. In some embodiments, the ARC layer is spin-coated on the hard mask layer. The ARC layer is configured to reduce reflection of DUV electromagnetic radiation from underlying layers during DUV lithography for the DUV mask. In some embodiments, 906 can be omitted.

[0043] At 908, a DUV mask layer is provided over the ARC layer. In some embodiments, the DUV mask layer is a polymer, such as a DUV photoresist. For example, a DUV photoresist such as UV™ 210 Positive DUV Photoresist can be used. In some embodiments, 908 includes spin coating the DUV mask layer. However, other deposition methods are possible.

[0044] At 910, the DUV mask layer is heat treated prior to exposure. Thus, 910 can be considered a pre-exposure bake or pre-exposure heat treatment. In some embodiments, the heat treatment at 910 is performed at a temperature(s) greater than 140 degrees Celsius. In some embodiments, the heat treatment is at a temperature(s) greater than 145 degrees Celsius. For example, a temperature at or near 150 degrees Celsius can be used for the heat treatment at 910. In some embodiments, the heat treatment lasts for more than one minute. In some embodiments, at least 70 seconds are used for the heat treatment. In some embodiments, the heat treatment at 910 lasts for at least 80 seconds. For example, the device can be heat treated at a temperature(s) at or near 150 degrees Celsius for a nominal period of 90 seconds or more.

[0045] In some embodiments, 910 includes gradually increasing the temperature to which the apparatus is exposed for the pre-exposure thermal treatment. In some embodiments, the temperature (e.g., the temperature of the mask layer, the temperature of other parts of the apparatus, or the temperature as measured in an oven or on a hot plate) is increased at a rate of no more than 140 degrees Celsius per minute. In some embodiments, the temperature is increased at a rate of no more than 125 degrees Celsius per minute. In some embodiments, the temperature is increased at a rate of no more than 100 degrees Celsius per minute.

[0046] At 912, the DUV mask layer is selectively exposed to DUV radiation. For example, a wavelength of no more than 250 nanometers may be used at 912. In some embodiments, 912 includes exposing multiple tiled regions. For example, a tiled region may be exposed, the stage moved, and another region exposed using the same or a different reticle. Thus, the DUV mask layer is selectively exposed to DUV radiation.

[0047] At 914, the DUV mask layer is thermally treated after exposure. Thus, 914 can be considered a post-exposure bake or post-exposure thermal treatment. In some embodiments, the thermal treatment at 914 is performed at a temperature(s) greater than 140 degrees Celsius. In some embodiments, the thermal treatment is at a temperature(s) greater than 145 degrees Celsius. For example, a temperature at or near 150 degrees Celsius can be used for the thermal treatment at 914. In some embodiments, the thermal treatment lasts for more than one minute. In some embodiments, at least 70 seconds are used for the thermal treatment. In some embodiments, the thermal treatment at 914 lasts for at least 80 seconds. For example, the device can be thermally treated at a temperature(s) at or near 150 degrees Celsius for a nominal period of 90 seconds or more.

[0048] In some embodiments, 914 includes gradually increasing the temperature to which the apparatus is exposed for the post-exposure thermal treatment. In some embodiments, the temperature (e.g., the temperature of the mask layer, the temperature of other parts of the apparatus, or the temperature as measured in an oven or on a hot plate) is increased at a rate of no more than 140 degrees Celsius per minute. In some embodiments, the temperature is increased at a rate of no more than 125 degrees Celsius per minute. In some embodiments, the temperature is increased at a rate of no more than 100 degrees Celsius per minute.

[0049] At 916, the exposed DUV mask layer is further developed. In some embodiments, a post-development bake is not performed. As a result, portions of the DUV mask layer are removed to form (one or more) apertures in the DUV mask layer. Thus, a DUV mask having a pattern is formed.

[0050] At 918, the portion of the ARC layer exposed by the aperture in the DUV mask is removed. For example, the ARC layer can be etched at 918. In some embodiments, 918 can be omitted. In such embodiments, the ARC layer can be removed in the same process used at 920.

[0051] At 920, the pattern of the DUV mask is transferred to the hard mask layer. In some embodiments, the pattern in the DUV mask is also transferred to the ARC layer. Thus, a hard mask is formed. In some embodiments, 920 includes chemically and / or physically removing the portion of the hard mask layer exposed by the pattern in the mask. For example, if the hard mask layer is a silicon dioxide layer, fluorine-based chemicals can be used at 920. In other embodiments, dry etching, RIE, or other etching mechanisms can be used. In some embodiments, the removal at 920 forms apertures in the hard mask layer to provide a hard mask. In such embodiments, the stop layer formed at 902 can prevent damage to the underlying LN layer. In some embodiments, the removal at 920 forms a recess in the hard mask layer to provide a hard mask. Therefore, damage to the LN layer can still be avoided.

[0052] At 922, the pattern of the hard mask can be transferred to the stop layer. This can occur via chemical or physical etching. The etch used to remove the stop layer at 922 is different from one or more of the etches used to pattern the hard mask at 920. In some embodiments, 922 can be omitted.

[0053] At 924, the pattern in the hard mask is transferred to the LN layer. In some embodiments, physical etching is used at 924. For example, dry etching, reactive ion etching (RIE), plasma etching, and / or other physical etching mechanisms may be used. In some embodiments, chemical etching or other removal mechanisms may be used at 924. In some embodiments, the LN layer is not etched through at 924. Thus, the LN optical device may be formed from or include ridges remaining after the partial removal of portions of the LN layer. In some embodiments, the LN layer may be completely etched through in some areas. In embodiments where the hard mask includes recesses rather than apertures, the pattern transfer at 924 also removes at least some of the thinned portions of the hard mask. In some embodiments, the pattern transfer at 924 may also remove some or all of the etch stop layer exposed by the hard mask. The etch used to form the hard mask at 920 can be separate from the etch used to remove portions of the LN layer at 924. Therefore, these etches can be optimized separately. This can result in smoother sidewalls of the optical device(s) being processed.

[0054] At 926, any remaining DUV mask, ARC layer, and / or hard mask may be removed. Device processing may be completed. For example, the formed LN optical device(s) may be singulated and / or additional components may be processed.

[0055] For example, Figure 10-15 An embodiment of a device 1000 comprising LN and formed using method 900 during processing is depicted. Figure 10-15The drawing is not to scale, and only a portion of device 1000 is shown. Additionally, device 1000 is for illustrative purposes and may not represent a specific device. For example, the sidewalls are shown as vertical and flat, while the top surface is shown as horizontal and flat. However, some variations are common.

[0056] Figure 10 Device 1000 is depicted after steps 904, 906, and 908 have been completed. Thus, substrate 1001, which may include a carrier wafer, bottom layer 1002, LN layer 1010, hard mask layer 1030, ARC layer 1040, and DUV mask layer 1050, is shown. Bottom layer 1002 may be an insulator, such as silicon dioxide. In this embodiment, bottom layer 1002 is depicted as separate from substrate 1001. In some embodiments, other layers may be present and / or one or more of the layers shown may be omitted. For example, in some embodiments, bottom layer(s) 1002 may be omitted. In the illustrated embodiment, an etch stop layer is not used. Therefore, steps 902 and 922 are omitted.

[0057] Figure 11 Device 1000 is depicted after steps 910, 912, 914, and 916 have been completed. DUV mask layer 1050 has been pre-exposure baked, selectively exposed to DUV radiation, post-exposure baked, and developed. Thus, DUV mask 1050A has been formed. Portions of ARC layer 1040 are exposed by DUV mask 1050A.

[0058] Figure 12 The device 1000 is depicted after 918 has been completed or the portion of the ARC layer 1040 exposed by the DUV mask 1050A has been otherwise removed (eg, as part of 920). Thus, a portion of the hard mask layer 1030 is exposed.

[0059] Figure 13 The device 1000 is depicted after 920 has been completed. Thus, the pattern of the DUV mask 1050A has been transferred to the hard mask 1030A. In the embodiment shown, the hard mask 1030A has recesses 1030B in the areas where the hard mask layer 1030 is etched. Thus, the pattern of the DUV mask 1050A has been transferred to the hard mask 1030A.

[0060] Figure 14 Device 1000 is depicted after 924 has been completed. Thus, LN optical devices 1010A and 1010B have been formed. LN device 1010A has sidewalls 1012A and 1014A. LN optical device 1010B has sidewalls 1012B and 1014B.

[0061] Figure 15Device 1000 is depicted after 926 has been completed and the layers over LN optical devices 1010A and 1010B have been removed. Device 1000 may undergo further processing to complete optical and / or other devices that utilize LN optical devices 1010A and / or 1010B.

[0062] LN optical devices 1010A and 1010B are formed using DUV lithography of method 900. Consequently, sidewalls 1012A, 1014A, 1012B, and 1014B of LN optical devices 1010A and 1010B have improved surface roughness. The short-range RMS surface roughness of sidewalls 1012A, 1014A, 1012B, and 1014B is each less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 1012A, 1014A, 1012B, and 1014B is no more than five nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 1012A, 1014A, 1012B, and 1014B is no more than two nanometers.

[0063] Optical devices 1010A and 1010B can have improved performance. In some embodiments, each of LN optical devices 1010A and 1010B has a signal loss of no more than 5 dB / cm. In some embodiments, each of LN optical devices 1010A and 1010B has a signal loss of no more than 2 dB / cm. In some such embodiments, each of LN optical devices 1010A and 1010B has a loss of less than 1.0 dB / cm. For example, in some embodiments, such a loss may be no more than 0.5 dB / cm.

[0064] Figure 16-21 An embodiment of a device 1600 comprising LN and formed using method 900 during processing is depicted. Figure 16-21 The drawing is not to scale, and only a portion of device 1600 is shown. Additionally, device 1600 is for illustrative purposes and may not represent a specific device. For example, the sidewalls are shown as vertical and flat, while the top surface is shown as horizontal and flat. However, some variations are common.

[0065] Figure 16Device 1600 is depicted after steps 902, 904, 906, and 908 have been completed. Thus, substrate 1601, which may include a carrier wafer, bottom layer 1602, LN layer 1610, etch stop layer 1620, hard mask layer 1630, ARC layer 1640, and DUV mask layer 1650 are shown. Bottom layer 1602 may be an insulator, such as silicon dioxide. In this embodiment, bottom layer 1602 is depicted as being separate from substrate 1601. Etch stop layer 1620 may include amorphous silicon and / or other materials that are insensitive to one or more of the etching(s) used for hard mask layer 1630. In some embodiments, etch stop layer 1620 may be at least ten nanometers thick and no more than fifty nanometers thick. In some embodiments, etch stop layer 1620 may also be removed without excessive damage to the underlying LN layer 1610. In some embodiments, other layers may be present and / or one or more of the layers shown may be omitted. For example, in some embodiments, bottom layer(s) 1602 may be omitted.

[0066] Figure 17 Device 1600 is depicted after steps 910, 912, 914, 916, and 918 have been completed. DUV mask layer 1650 has been subjected to a pre-exposure bake, selectively exposed to DUV radiation, subjected to a post-exposure bake, and developed. Thus, DUV mask 1650A has been formed. The portion of ARC layer 1640 exposed by DUV mask 1650A has been removed. Thus, ARC layer portion 1640A remains. Portions of hardmask layer 1630 are exposed.

[0067] Figure 18 Device 1600 is depicted after 920 has been completed. Thus, the pattern of DUV mask 1650A has been transferred to hard mask 1630A. In the embodiment shown, hard mask 1630A has apertures 1630B in the areas where hard mask layer 1630 is etched. Thus, portions of etch stop layer 1620 are exposed. Thus, the pattern of DUV mask 1650A has been transferred to hard mask 1630A.

[0068] Figure 19 Device 1600 is depicted after etch stop layer 1620 has been selectively etched, either at 922, or as part of transferring a pattern to LN layer 1610. Thus, the exposed area of ​​etch stop layer 1620 has been removed, leaving behind a portion 1620A of the etch stop layer. In some embodiments, etch stop layer 1620 need not be completely removed at 922. In such embodiments, LN layer 1610 may be covered by a portion of the etch stop layer. This portion is subsequently removed by pattern transfer at 924.

[0069] Figure 20Device 1600 is depicted after 924 has been completed. Thus, LN optical devices 1610A and 1610B have been formed. LN device 1610A has sidewalls 1612A and 1614A. LN optical device 1610B has sidewalls 1612B and 1614B.

[0070] Figure 21 Device 1600 is depicted after 926 has been completed and the layers over LN optical devices 1610A and 1610B have been removed. Device 1600 may undergo further processing to complete optical and / or other devices that utilize LN optical devices 1610A and / or 1610B.

[0071] LN optical devices 1610A and 1610B are formed using DUV lithography of method 900. Consequently, sidewalls 1612A, 1614A, 1612B, and 1614B of LN optical devices 1610A and 1610B have improved surface roughness. The short-range RMS surface roughness of sidewalls 1612A, 1614A, 1612B, and 1614B is each less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 1612A, 1614A, 1612B, and 1614B is no more than five nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 1612A, 1614A, 1612B, and 1614B is no more than two nanometers.

[0072] Optical devices 1610A and 1610B can have improved performance. In some embodiments, each of LN optical devices 1610A and 1610B has a signal loss of no more than 5 dB / cm. In some embodiments, each of LN optical devices 1610A and 1610B has a signal loss of no more than 2 dB / cm. In some such embodiments, each of LN optical devices 1610A and 1610B has a loss of less than 1.0 dB / cm. For example, in some embodiments, such a loss may be no more than 0.5 dB / cm.

[0073] Thus, method 900 provides LN optical devices 1010A, 1010B, 1610A, and / or 1610B that may have improved manufacturability, performance, and reduced sidewall surface roughness. Because DUV lithography is used, throughput can be increased, the time required to process devices 1000 and 1600 can be reduced, uniformity can be improved, and reproducibility can be enhanced. Furthermore, the use of DUV lithography can be more easily scaled for processing large numbers of devices in manufacturing. DUV lithography also allows for a larger stitching area. For example, in some embodiments, a stitching area of ​​at least ten millimeters by ten millimeters can be subjected to DUV lithography in a single shot. In some embodiments, the stitching area can be at least fifteen millimeters by fifteen millimeters. For example, the stitching area can be nominally twenty millimeters by twenty millimeters or larger. Consequently, the number of stitches (not shown) is reduced. This not only increases throughput and reproducibility, but also reduces misalignment in the optical device. Consequently, the processing and performance of optical devices including LN can be enhanced.

[0074] As discussed above, the processing techniques and devices described herein are applicable to other nonlinear optical materials, such as ferroelectric nonlinear optical materials, including but not limited to LT. For example, LT, potassium niobate, gallium arsenide, potassium titanyl phosphate, lead zirconate titanate, and / or barium titanate may be used instead of or in addition to LN. As a result, the performance and processing of optical devices including ferroelectric nonlinear optical materials may be improved.

[0075] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.

Claims

1. A device comprising: an optical device, at least a portion of the optical device comprising at least one ferroelectric nonlinear optical material, the at least a portion of the optical device being processed using ultraviolet (UV) photolithography and comprising sidewalls of the ferroelectric nonlinear optical material, the sidewalls having a short-range root mean square roughness of less than ten nanometers, the short-range root mean square roughness being a root mean square roughness along a side surface having a length not exceeding two hundred nanometers, wherein the at least a portion of the optical device is widened in an area to be spliced; The sidewall is processed using UV photolithography, a first etch and a second etch, wherein the UV photolithography is used to form a mask for processing a hard mask from a hard mask layer, the first etch is used to remove a portion of the hard mask layer to form the hard mask, the second etch is used to remove a portion of the ferroelectric nonlinear optical material to form the sidewall, the second etch is selected from dry etching, reactive ion etching RIE, plasma etching and chemical etching, and the second etch is different from the first etch, so that the sidewall has the short-distance root mean square roughness of less than ten nanometers.

2. The device of claim 1, wherein the at least one ferroelectric nonlinear optical material comprises at least one of lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanyl phosphate, lead zirconate titanate, and barium titanate.

3. The device of claim 2, wherein the at least one ferroelectric nonlinear optical material is selected from lithium tantalate and lithium niobate.

4. The device of claim 1, wherein the sidewalls have a height of at least four hundred nanometers.

5. The apparatus of claim 1 , wherein the sidewall is included in at least one tiled area, each of the at least one tiled area having an area of ​​at least ten millimeters by ten millimeters; Different stitching areas of the at least one stitching area are exposed at different times.

6. The apparatus of claim 1, wherein the short-range root mean square surface roughness does not exceed five nanometers.

7. The device of claim 1, wherein the at least a portion of the optical device has a loss of no more than 2 dB / cm.

8. The apparatus of claim 7, wherein the loss is less than 1.0 dB / cm.

9. The apparatus of claim 8, wherein the loss is less than 0.5 dB / cm.

10. The apparatus of claim 9, wherein the loss does not exceed 0.1 dB / cm.

11. A method of providing an optical device, comprising: providing a hard mask layer on a ferroelectric nonlinear optical layer, the ferroelectric nonlinear optical layer comprising at least one ferroelectric nonlinear optical material; providing a mask on the hard mask layer, the mask having a pattern formed using ultraviolet (UV) lithography; forming a hard mask from the hard mask layer by transferring the pattern to the hard mask layer; and The pattern is transferred from the hard mask to the ferroelectric nonlinear optical layer to form at least a portion of the optical device including sidewalls of the ferroelectric nonlinear optical layer, the sidewalls having a short-range root mean square roughness of less than ten nanometers, the short-range root mean square roughness being a root mean square roughness along a side surface having a length of no more than two hundred nanometers, and wherein the at least a portion of the optical device is widened in the area to be spliced.

12. The method of claim 11, wherein providing the mask further comprises: providing a mask layer; thermally treating the mask layer at a baking temperature greater than 140 degrees Celsius; exposing portions of the mask layer after the heat treatment using electromagnetic radiation in the UV wavelength range; and The mask layer is developed after the exposure to form at least one aperture in the mask layer corresponding to the pattern and to form the mask.

13. The method of claim 12, wherein providing the mask further comprises: A further heat treatment is performed after the exposing and before the developing, the further heat treatment being at a further temperature greater than one hundred forty degrees Celsius.

14. The method of claim 11, wherein the forming further comprises performing a first etch for removing a portion of the hard mask layer to form the hard mask; and Wherein, transferring the pattern from the hard mask to the ferroelectric nonlinear optical layer also includes performing a second etch for removing a portion of the ferroelectric nonlinear optical material to form the sidewall, the second etch being selected from dry etching, reactive ion etching (RIE), plasma etching, and chemical etching, and the second etch being different from the first etch, so that the sidewall has the short-distance root mean square roughness of less than ten nanometers.

15. The method of claim 11, wherein the forming of at least one of the hard masks comprises forming a recess in the hard mask layer corresponding to the pattern, and the method further comprises providing a stop layer below the hard mask layer and removing a portion of the stop layer after the forming of the hard mask.

16. The method of claim 11, wherein the pattern comprises a plurality of tiled areas, each of the tiled areas having an area of ​​at least ten millimeters by ten millimeters, the plurality of tiled areas being exposed at different times.

17. The method of claim 11, wherein the hard mask layer comprises at least one of silicon oxide, amorphous silicon, and silicon nitride.

18. The method of claim 11, wherein the ferroelectric nonlinear optical layer comprises at least one of lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanyl phosphate, lead zirconate titanate, and barium titanate, and wherein the sidewalls have a height of at least four hundred nanometers.

19. A method for providing an optical device, comprising: providing a hard mask layer on a ferroelectric nonlinear optical layer, the nonlinear optical layer comprising at least one ferroelectric nonlinear optical material; providing a mask on the hard mask layer, the mask having a pattern formed using deep ultraviolet (DUV) lithography, the providing the mask further comprising: providing a mask layer; thermally treating the mask layer at a first temperature greater than 140 degrees Celsius, the thermally treating comprising increasing the temperature of the mask layer at a rate not exceeding 140 degrees Celsius per minute; exposing portions of the mask layer using electromagnetic radiation in the DUV wavelength range; performing an additional thermal treatment after the second temperature exposure of greater than one hundred forty degrees Celsius, the additional thermal treatment comprising increasing the additional temperature for the mask layer at an additional rate not exceeding 140 degrees Celsius per minute; developing the mask layer after the further thermal treatment to form at least one aperture in the mask layer corresponding to the pattern and forming the mask; forming a hard mask from the hard mask layer by transferring the pattern to the hard mask layer; and Etching the ferroelectric nonlinear optical layer to transfer the pattern from the hard mask to the ferroelectric nonlinear optical layer, thereby forming at least a portion of the optical device including sidewalls of the ferroelectric nonlinear optical layer, the sidewalls having a short-range root mean square roughness of less than ten nanometers, the etching being different from other etches used to form the hard mask by transferring the pattern to the hard mask layer, the short-range root mean square roughness being a root mean square roughness along a side surface having a length of no more than two hundred nanometers, wherein the at least a portion of the optical device is widened in the area to be spliced.

20. The method of claim 19, wherein the ferroelectric nonlinear optical layer comprises at least one of lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanyl phosphate, lead zirconate titanate, and barium titanate.

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