A method, apparatus, computer storage medium, and terminal for implementing data processing

Abstract

The present disclosure provides a method, apparatus, computer storage medium, and terminal for implementing data processing, including: determining a first offset address of a position where data to be read in a memory is stored relative to a first base address; generating a first data read instruction including the first base address and the determined first offset address; generating a kernel interrupt and determining whether the instruction triggering the kernel interrupt is the first data read instruction; when it is determined that the instruction triggering the kernel interrupt is the first data read instruction, reading the data to be read according to the first data read instruction; wherein the first base address includes: a base address of the memory determined according to an address of a space that cannot be directly accessed by a user. In an embodiment of the present invention, by determining the first offset address of the position where data is stored relative to the first base address and directly reading the data in the memory based on the first base address and the first offset address, the data reading steps are simplified, the data reading efficiency is improved, and technical support is provided for improving application development.

Description

Technical Field

[0001] This application relates to, but is not limited to, embedded chip technology, and particularly to a method, apparatus, computer storage medium, and terminal for implementing data processing. Background Art

[0002] With the development of embedded chip technology, the requirements of application design for embedded chips are constantly increasing. To facilitate product development, it is necessary for embedded chips to adapt to the operations of the memory in the original application system. Due to different design levels of embedded chip manufacturers, or due to cost and lack of chip application design, for an embedded chip with hardware design completed, when accessing any address in the memory to read data through the direct address method, the application to be developed needs to read the memory address data through the drive of the storage area.

[0003] Currently, for an embedded chip that does not support reading the memory through a general address, when reading data from the memory, it generally needs to perform a whole-page read according to the data read address in the data read instruction, and then read the data to be read from the read page according to the base address of the page based on the data read address; Figure 1 For the flowchart of data reading in the related art, as Figure 1 shown, it includes: Step 101, read all the data in the page where the data to be read is located according to the set drive and the base address of the page; Step 102, determine whether all the data in the page where the data to be read is located has been completed; Step 103, when it is determined that all the data in the page where the data to be read is located has been completed, extract the data to be read according to the offset address of the page. The above data reading steps are cumbersome and affect the development efficiency of the application.

[0004] In summary, how to simplify the data reading steps of embedded chips and improve the application development efficiency has become a problem to be solved. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0006] Embodiments of the present invention provide a method, apparatus, computer storage medium, and terminal for implementing data processing, which can simplify the data reading steps of embedded chips.

[0007] Embodiments of the present invention provide a method for implementing data processing, including:

[0008] Determine a first offset address of the position where the data to be read in the memory is stored relative to a first base address;

[0009] Generate a first data read instruction including the first base address and the determined first offset address;

[0010] When a kernel interrupt occurs, determine whether the instruction that triggers the kernel interrupt is a first data reading instruction;

[0011] When it is determined that the instruction that triggers the kernel interrupt is a first data reading instruction, read the data to be read according to the first data reading instruction;

[0012] Wherein, the first base address includes: the base address of a memory determined according to the address of a space that cannot be directly accessed by a user.

[0013] On the other hand, an embodiment of the present invention further provides a computer storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method for implementing data processing as described above is realized.

[0014] On yet another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor, wherein a computer program is stored in the memory; wherein,

[0015] The processor is configured to execute the computer program in the memory;

[0016] When the computer program is executed by the processor, the method for implementing data processing as described above is realized.

[0017] On still another aspect, an embodiment of the present invention further provides a device for implementing data processing, including: an address determination unit, a read instruction generation unit, a judgment unit, and a read unit; wherein,

[0018] The address determination unit is configured to: determine a first offset address of the position where the data to be read in the memory is stored relative to the first base address;

[0019] The read instruction generation unit is configured to: generate a first data reading instruction including the first base address and the determined first offset address;

[0020] The judgment unit is configured to: when a kernel interrupt occurs, determine whether the instruction that triggers the kernel interrupt is a first data reading instruction;

[0021] The read unit is configured to: when it is determined that the instruction that triggers the kernel interrupt is a first data reading instruction, read the data to be read according to the first data reading instruction;

[0022] Wherein, the first base address includes: the base address of a memory determined according to the address of a space that cannot be directly accessed by a user.

[0023] The technical solution of this application includes: determining a first offset address of the position where the data to be read in the memory is stored relative to a first base address; generating a first data read instruction including the first base address and the determined first offset address; when a kernel interrupt occurs, determining whether the instruction triggering the kernel interrupt is the first data read instruction; when it is determined that the instruction triggering the kernel interrupt is the first data read instruction, reading the data to be read according to the first data read instruction; wherein, the first base address includes: the base address of the memory determined according to the address of the space that cannot be directly accessed by the user. Through determining the first offset address of the data storage position relative to the first base address, and directly reading the data in the memory based on the first base address and the first offset address, the embodiments of the present invention simplify the data reading steps, improve the data reading efficiency, and provide technical support for improving application development.

[0024] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained by the structures specifically pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are used to provide a further understanding of the technical solution of the present invention, and constitute a part of the specification. Together with the embodiments of this application, they are used to explain the technical solution of the present invention, and do not constitute a limitation to the technical solution of the present invention.

[0026] Figure 1 It is a flowchart of data reading in the related art;

[0027] Figure 2 It is a flowchart of the method for implementing data processing in the embodiments of the present invention;

[0028] Figure 3 It is a structural block diagram of the device for implementing data processing in the embodiments of the present invention;

[0029] Figure 4 It is a method flowchart of the application example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily.

[0031] The steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer executable instructions. And, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0032] Figure 2 The flowchart of the method for the embodiment of the present invention to implement data processing is as Figure 2 shown, including:

[0033] Step 201, determine the first offset address of the position where the data to be read in the memory is stored relative to the first base address;

[0034] Step 202, generate a first data read instruction including the first base address and the determined first offset address; here, the first data read instruction can be constructed and generated with reference to the related art as long as it meets the relevant protocols of the chip.

[0035] Step 203, when a kernel interrupt occurs, determine whether the instruction that triggers the kernel interrupt is the first data read instruction;

[0036] When the embodiment of the present invention executes data reading through the first data read instruction, since the first data read instruction is not the instruction specified to run by the system, according to the operation rules of the chip system in the related art, a kernel interrupt will be triggered.

[0037] Step 204, when it is determined that the instruction that triggers the kernel interrupt is the first data read instruction, read the data to be read according to the first data read instruction;

[0038] Among them, the first base address includes: the base address of the memory determined according to the address of the space that cannot be directly accessed by the user.

[0039] In an exemplary instance, when the embodiment of the present invention determines that the instruction that triggers the kernel interrupt is the first data read instruction, it can read the data to be read with reference to the related art according to the first base address and the first offset address included in the first data read instruction.

[0040] In an exemplary instance, the address of the space that cannot be directly accessed by the user in the embodiment of the present invention can be determined according to the information of the memory recorded in the chip manual; in an exemplary instance, the embodiment of the present invention can determine the address of the space that cannot be directly accessed by the user of the chip according to the space range of the memory recorded in the chip manual with reference to the related art.

[0041] The embodiment of the present invention simplifies the data reading steps and improves the data reading efficiency by determining the first offset address of the position where the data is stored relative to the first base address and directly reading the data in the memory based on the first base address and the first offset address included in the first data read instruction, providing technical support for improving application development.

[0042] In an exemplary instance, the steps of the above data reading are implemented by a chip that configures the memory in the embodiment of the present invention.

[0043] In an exemplary instance, the embodiment of the present invention determines a first offset address of the position where data is stored relative to a first base address, including:

[0044] Obtain a data read address from the received second data read instruction;

[0045] Calculate a first offset address for reading the data to be read with the first base address as the reference address according to the page where the data to be read is located, the second base address of the page, and the second offset address of the page included in the obtained data read address.

[0046] In an exemplary instance, the second data read instruction in the embodiment of the present invention is an instruction for data reading generated with reference to the related art. When using the second data read instruction for data reading, according to the related art, it is necessary to first read the page where the data to be read is located, and then extract the data to be read from the read page, which is cumbersome and inefficient.

[0047] In an exemplary instance, before determining the first offset address of the position where the data to be read in the memory is stored relative to the first base address, the method of the embodiment of the present invention further includes obtaining the first base address through the following processing:

[0048] Select one from the addresses of more than two spaces in the memory that cannot be directly accessed by users;

[0049] Determine the starting position of the selected address of the space that cannot be directly accessed by users as the first base address.

[0050] In an exemplary instance, the embodiment of the present invention can divide addresses according to the size, quantity of storage units included in the memory, and the actual space of the chip, and select one from the addresses of more than two spaces in the chip that cannot be directly accessed by users to determine the first base address of the memory; through the selection of the address of the space that cannot be directly accessed by users, the unified reading of memory data in a directly accessible manner is realized, providing support for data reading using the kernel interrupt method.

[0051] In an exemplary instance, the embodiment of the present invention determines whether the instruction triggering the kernel interrupt is a first data read instruction, including:

[0052] When it is determined that the instruction triggering the kernel interrupt contains the first base address, determine that the instruction triggering the kernel interrupt is a first data read instruction.

[0053] In an exemplary instance, embodiments of the present invention can determine the type of the instruction that triggers the kernel terminal according to the chip instruction set command. The chip instruction set command is a general term for the set of instructions executed by the chip CPU. Generally, each manufacturer will set the corresponding CPU instruction set, and different instruction parsing methods can be set according to different CPUs for instruction parsing.

[0054] In an exemplary instance, when reading the data to be read according to the first data reading instruction, the method of the embodiments of the present invention further includes:

[0055] Reading and caching the data of the first preset length before the data to be read; and / or,

[0056] Reading and caching the data of the second preset length after the data to be read.

[0057] In an exemplary instance, the first preset length and the second preset length in the embodiments of the present invention can be set by those skilled in the art according to experience; through the pre-reading of the data, the embodiments of the present invention improve the reading efficiency of the data related to the data to be read subsequently.

[0058] In an exemplary instance, the method of the embodiments of the present invention further includes:

[0059] Writing data to the memory based on the first base address and recording the first offset address when writing data according to the first base address, so as to execute the reading of the data to be read according to the first base address and the first offset address after the data is written.

[0060] When the embodiments of the present invention execute data writing based on the first base address, the first offset address can be determined according to the position of the data writing; after determining the first offset address, the data reading can be executed with reference to the above steps.

[0061] The embodiments of the present invention also provide a computer storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method for implementing data processing as described above is realized.

[0062] The embodiments of the present invention also provide a terminal, including: a memory and a processor, and a computer program is stored in the memory; wherein,

[0063] The processor is configured to execute the computer program in the memory;

[0064] When the computer program is executed by the processor, the method for implementing data processing as described above is realized.

[0065] Figure 3 It is the structural block diagram of the device for implementing data processing in the embodiments of the present invention, as Figure 3As shown, it includes: an address determination unit, a read instruction generation unit, a judgment unit, and a read unit; among them,

[0066] The address determination unit is set to: determine the first offset address of the position where the data to be read in the memory is stored relative to the first base address;

[0067] The read instruction generation unit is set to: generate a first data read instruction including the first base address and the determined first offset address;

[0068] The judgment unit is set to: when a kernel interrupt occurs, determine whether the instruction triggering the kernel interrupt is the first data read instruction;

[0069] The read unit is set to: when it is determined that the instruction triggering the kernel interrupt is the first data read instruction, read the data to be read according to the first data read instruction;

[0070] Among them, the first base address includes: the base address of the memory determined according to the address of the space that cannot be directly accessed by the user.

[0071] In an exemplary instance, the address determination unit of the embodiment of the present invention is set to:

[0072] Obtain the data read address from the received second data read instruction;

[0073] According to the page where the data to be read is located, the second base address of the page, and the second offset address of the page included in the obtained data read address, calculate the first offset address for reading the data to be read with the first base address as the reference address.

[0074] In an exemplary instance, the address determination unit of the embodiment of the present invention is further set to:

[0075] Select one from the addresses of two or more spaces that cannot be directly accessed by the user in the memory;

[0076] Determine the starting position of the selected address of the space that cannot be directly accessed by the user as the first base address.

[0077] In an exemplary instance, the judgment unit of the embodiment of the present invention is set to:

[0078] When it is determined that the instruction triggering the kernel interrupt contains the first base address, determine that the instruction triggering the kernel interrupt is the first data read instruction.

[0079] In an exemplary instance, the read unit of the embodiment of the present invention is further set to:

[0080] Read and cache the data of the first preset length before the data to be read; and / or,

[0081] Read and cache data of a second preset length after the data to be read.

[0082] In the embodiments of the present invention, through pre-reading of data, the reading efficiency of related data of the data to be read subsequently is improved.

[0083] In an exemplary instance, the device in the embodiments of the present invention further includes a writing unit, which is configured to:

[0084] Perform data writing to the memory based on a first base address, and record a first offset address when performing data writing according to the first base address, so as to perform reading of the data to be read according to the first base address and the first offset address after the data is written. It should be noted that when performing data writing according to the first base address, the first offset address can be determined according to the position where the data is written.

[0085] The following briefly describes the embodiments of the present invention through application examples. The application examples are only used to state the embodiments of the present invention and do not limit the protection scope of the embodiments of the present invention.

[0086] Application Example

[0087] In this application example, through an embedded chip and an embedded device platform, in a software manner, directly read the memory data based on the determined address, making up for the problem of cumbersome data reading caused by the chip hardware design reason, realizing the function of the chip to read the memory data through address parsing, ensuring that the upper-layer application can directly read the memory data by accessing the address; in addition, the method of this application example eliminates the difference in the function of directly reading the memory due to the lack of hardware address design inside the chip, and realizes the reading of data at any memory address through the first base address and the first offset address of the memory, improving the versatility of the embedded chip. The method of this application example can be applied to the design of embedded systems in related technologies.

[0088] In this application example, first, according to the address of the space that cannot be directly accessed by the user of the embedded chip recorded in the chip manual, determine the first base address of the memory, denoted as Base1, and according to the data reading address in the second data reading instruction, determine the first offset address of the position where the data to be read is stored relative to the first base address, denoted as offset1. Then, the reading address of the data to be read determined according to the first base address and the first offset address is B1 = Base + offset, and generate a first data reading instruction according to B1; Figure 4 This is the flowchart of the method of the application example of the present invention. As Figure 4 shown, when generating the first data reading instruction, the data reading process performed includes:

[0089] Step 401: When a kernel interrupt occurs, parse the instruction that triggers the kernel interrupt to determine the type of the instruction that triggers the kernel interrupt. In this application example, since B1 is an illegal address for the chip, a system error occurs in the chip at this time, triggering a kernel interrupt.

[0090] Step 402: Determine whether the instruction that triggers the kernel interrupt is a first data read instruction. When it is determined that the instruction that triggers the kernel interrupt is a first data read instruction, execute Step 403; when it is determined that the instruction that triggers the kernel interrupt is an instruction other than the first data read instruction, execute Step 404.

[0091] Step 403: Read data according to the first base address and the first offset address in the first data read instruction. In this application example, after parsing the first data read instruction, obtain the base address BasePage1 of the page address of B1 according to the storage page size PageSize of the memory, i.e., BasePage1 = B1 / PageSize; read the data corresponding to the first offset address according to the calculated page address and then return. In an exemplary instance, relevant information such as the data type of the data to be read, word read, half-word read, or byte read can also be added to the first data read instruction in this application example with reference to related technologies.

[0092] Step 404: Execute system exception handling. The system exception handling in this application example can be executed with reference to related technologies.

[0093] In an exemplary instance, after parsing the first data read instruction in the embodiment of the present invention, data can be read by calling an interface function according to the obtained first base address and first offset address.

[0094] In an exemplary instance, the method in the embodiment of the present invention further includes: when reading data, pre-read data with a preset length before and after the data to be read; in an exemplary instance, the preset length in the embodiment of the present invention can be dynamically adjusted according to the random access memory (RAM) space of the chip to balance its space and data processing speed.

[0095] The above method in this application example has good versatility and simple process control; it is implemented in software without the participation of hardware; and the stored data can be directly obtained through the address access method. In this application example, the chip can directly read the data in the chip memory through the address method by software; it eliminates the differences in the functions of directly reading the memory due to the lack of hardware addresses designed inside the chip, enabling the software to read the data of any memory address through the address, improving the versatility of the embedded chip.

[0096] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be executed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

Claims

1. A method for implementing data processing, comprising: Determining a first offset address of the position where the data to be read in the memory is stored relative to a first base address; Generating a first data read instruction including the first base address and the determined first offset address; When a kernel interrupt occurs, determining whether the instruction triggering the kernel interrupt is the first data read instruction; When it is determined that the instruction triggering the kernel interrupt is the first data read instruction, reading the data to be read according to the first data read instruction; Wherein, the first base address includes: a base address of the memory determined according to the address of a space that cannot be directly accessed by the user; the first base address is obtained through the following processing: selecting one from the addresses of two or more spaces that cannot be directly accessed by the user in the memory; determining the starting position of the selected address of the space that cannot be directly accessed by the user as the first base address; the determining the first offset address of the position where the data to be read in the memory is stored relative to the first base address includes: obtaining a data read address from the received second data read instruction; calculating the first offset address for reading the data to be read with the first base address as the reference address according to the page where the data to be read is located, the second base address of the page, and the second offset address of the page.

2. The method according to claim 1, wherein The determining whether the instruction triggering the kernel interrupt is the first data read instruction includes: When it is determined that the instruction triggering the kernel interrupt includes the first base address, determining that the instruction triggering the kernel interrupt is the first data read instruction.

3. The method according to claim 1, characterized in that, When reading the data to be read according to the first data read instruction, the method further includes: Reading and caching data of a first preset length before the data to be read; and / or, Reading and caching data of a second preset length after the data to be read.

4. The method according to claim 1, characterized in that, The method further includes: Performing data writing to the memory based on the first base address, and recording a first offset address when performing data writing according to the first base address, so as to execute the reading of the data to be read according to the first base address and the first offset address after data writing.

5. A computer storage medium, in which a computer program is stored, and when the computer program is executed by a processor, it implements the method for implementing data processing according to any one of claims 1 to 4.

6. A terminal, comprising: A memory and a processor, wherein a computer program is stored in the memory; wherein, The processor is configured to execute the computer program in the memory; When the computer program is executed by the processor, it implements the method for implementing data processing according to any one of claims 1 to 4.

7. An apparatus for implementing data processing, comprising: An address determination unit, a read instruction generation unit, a judgment unit, and a read unit; wherein, The address determination unit is configured to: determine a first offset address of the position where the data to be read in the memory is stored relative to a first base address; The read instruction generation unit is configured to: generate a first data read instruction including the first base address and the determined first offset address; The judgment unit is configured to: when a kernel interrupt occurs, determine whether the instruction triggering the kernel interrupt is the first data read instruction; The reading unit is set to: when determining that the instruction triggering the kernel interrupt is the first data reading instruction, read the data to be read according to the first data reading instruction; Among them, the first base address includes: the base address of the memory determined according to the address of the space that cannot be directly accessed by the user, and the first base address is obtained through the following processing: select one from the addresses of two or more spaces that cannot be directly accessed by the user in the memory; determine the starting position of the selected address of the space that cannot be directly accessed by the user as the first base address; the determining address unit is set to: obtain the data reading address from the received second data reading instruction; calculate the first offset address for reading the data to be read with the first base address as the reference address according to the page where the data to be read is located, the second base address of the page, and the second offset address of the page included in the obtained data reading address.

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