Apparatus and method for improving data input / output speed of memory device

Abstract

The present invention relates to an apparatus and method for improving data input / output speed of a memory device. The present disclosure relates to a voltage generation circuit. The voltage generation circuit includes a noise attenuation circuit configured to attenuate noise of a second supply voltage, a level of which is at least twice higher than a level of a first supply voltage, and a multi-stage voltage pump configured to receive the noise-attenuated second supply voltage from the noise attenuation circuit and generate at least one of a plurality of target voltages, each having a different level. The first and second supply voltages are input from an external device via different pins or pads, respectively.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2021-0035489, filed on March 18, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure described herein relate to an apparatus and method for improving the data input / output speed of a non-volatile memory device. Background Technology

[0004] While technologies for fast and secure data processing are gaining attention, the development of storage-class memory (SCM) and related technologies, which offer the advantages of traditional dynamic random-access memory (DRAM) and flash memory, is actively underway. SCM offers data processing speeds similar to DRAM, but data is not lost even during power outages or shutdowns. SCM can increase system speed by many times. Using this type of storage-class memory, as artificial intelligence (AI), big data, and the Internet of Things (IoT) become commercialized, technologies are being developed to handle ever-increasing data traffic more quickly and efficiently. Summary of the Invention

[0005] Embodiments of this disclosure can provide a data processing system and method for improving data input / output speed.

[0006] Embodiments of this disclosure can provide an apparatus and method for accelerating the data input / output speed of non-volatile memory devices such as flash memory. To accelerate data input / output speed, the non-volatile memory device can reduce the time spent generating high voltages for read or write operations, thereby reducing the operating margin of the read or write operations.

[0007] Non-volatile memory devices may include voltage generation circuitry. This voltage generation circuitry may include: a rectifier or filter circuit configured to avoid or reduce noise included in high voltages input from an external device via pins or pads; and a multi-stage pump configured to generate high voltages having different levels used in read or write operations. Further, the voltage generation circuitry may include diodes configured to prevent failures caused by high voltages applied to each unit voltage pump in the multi-stage pump.

[0008] In embodiments of the disclosure, a non-volatile memory device can include a plurality of data buses for speeding up data input / output speed. When the number of data buses used to transfer data items from or to a page buffer increases and each page buffer is individually connected to another component via each data bus, the data input / output speed can be improved.

[0009] In embodiments, the voltage generation circuit can include a noise attenuation circuit configured to attenuate noise of a second supply voltage having a level at least twice higher than a level of a first supply voltage, wherein the first and second supply voltages are input from an external device via different pins or pads, respectively, and a multi-stage voltage pump configured to receive the noise-attenuated second supply voltage from the noise attenuation circuit and generate at least one of a plurality of target voltages each having a different level.

[0010] The multi-stage voltage pump can include a plurality of unit voltage pumps connected in series to each other and configured to receive the second supply voltage, and at least one diode including a cathode coupled between output terminals of adjacent unit voltage pumps among the plurality of unit voltage pumps and input terminals and an anode coupled to the second supply voltage.

[0011] The at least one diode can be configured to maintain voltage levels on the output terminals and the input terminals of the adjacent unit voltage pumps to avoid applying a breakdown voltage of transistors included in the adjacent unit voltage pumps.

[0012] The noise attenuation circuit can always be coupled to the pins or pads when the voltage generation circuit generates at least one of the plurality of target voltages.

[0013] The noise attenuation circuit can include a rectifier including a diode arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

[0014] The noise attenuation circuit can include a low-pass filter including a resistor arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

[0015] The plurality of target voltages can include a program voltage for programming a data item into a non-volatile memory cell, an erase voltage for erasing the data item in the non-volatile memory cell, and a read voltage for reading the data item in the non-volatile memory cell.

[0016] In another embodiment, a memory device can include a memory bank including a plurality of non-volatile memory cells; a voltage generation circuit configured to generate at least one of a plurality of target voltages for inputting a data item to or outputting a data item from the memory bank; and a plurality of buffers configured to temporarily store the data item output from the memory bank or the data item to be input to the memory bank. The voltage generation circuit can include a noise attenuation circuit configured to attenuate a noise of a second supply voltage having a level at least two times higher than a level of a first supply voltage, wherein the first supply voltage and the second supply voltage are input from an external device via different pins or pads, respectively; and a multi-stage voltage pump configured to receive the noise-attenuated second supply voltage from the noise attenuation circuit and generate at least one of the plurality of target voltages, each target voltage having a different level.

[0017] The multi-stage voltage pump can include a plurality of cell voltage pumps connected in series to each other and configured to receive the second supply voltage; and at least one diode including a cathode coupled between output terminals and input terminals of adjacent cell voltage pumps among the plurality of cell voltage pumps and an anode coupled to the second supply voltage.

[0018] The at least one diode can be configured to maintain voltage levels on the output terminals and the input terminals of the adjacent cell voltage pumps to avoid breakdown voltage of transistors included in the adjacent cell voltage pumps.

[0019] The noise attenuation circuit can always be coupled to the pin or the pad when the voltage generation circuit generates at least one of the plurality of target voltages.

[0020] The noise attenuation circuit can include a rectifier including a diode arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

[0021] The noise attenuation circuit can include a low-pass filter including a resistor arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

[0022] The plurality of target voltages can include a program voltage for programming a data item into the non-volatile memory cells; an erase voltage for erasing the data item in the non-volatile memory cells; and a read voltage for reading the data item in the non-volatile memory cells.

[0023] The plurality of buffers can be coupled to the first supply voltage and a first ground voltage corresponding to the first supply voltage, and the multi-stage voltage pump is coupled to the second supply voltage and a second ground voltage corresponding to the second supply voltage. A node of the first ground voltage can be electrically isolated from a node of the second ground voltage.

[0024] A plurality of buffers can be coupled to individual bit lines of a memory bank. The plurality of buffers can be coupled to individual buses to transfer data items output from the memory bank.

[0025] The plurality of buffers can be coupled to a data serializer via the individual buses, and the plurality of buffers transfer data items via the individual buses without any latency.

[0026] In another embodiment, a semiconductor device can include a first pin or pad configured to receive a first supply voltage input from an external device, a second pin or pad configured to receive a second supply voltage input from the external device, wherein a level of the second supply voltage is at least twice higher than a level of the first supply voltage, a multi-stage voltage pump configured to receive the second supply voltage and generate at least one of a plurality of target voltages each having a different level, and a noise attenuation circuit disposed between the second pin or pad and the multi-stage voltage pump and configured to attenuate a noise of the second supply voltage.

[0027] The multi-stage voltage pump can include a plurality of unit voltage pumps connected in series to each other and configured to receive the noise-attenuated second supply voltage, and at least one diode including a cathode coupled between output terminals of adjacent unit voltage pumps of the plurality of unit voltage pumps and an input terminal and an anode coupled to the second supply voltage.

[0028] The at least one diode can be configured to maintain voltage levels on the output terminals and the input terminal of the adjacent unit voltage pumps to avoid applying a breakdown voltage of transistors included in the adjacent unit voltage pumps.

[0029] In another embodiment, a memory device can include a voltage generation circuit configured to receive a first supply voltage and a second supply voltage to generate a first operating voltage and a second operating voltage, respectively, the second supply voltage having a level that is two or more times higher than a level of the first supply voltage, and a memory core configured to perform operations using the first operating voltage and the second operating voltage, respectively, wherein the voltage generation circuit includes a noise attenuation circuit configured to attenuate a noise of the second supply voltage, two or more unit voltage pumps coupled in series and configured to receive the noise-attenuated second supply voltage to generate the second operating voltage, and at least one diode having an anode coupled to a node of the noise-attenuated second supply voltage and a cathode coupled to a connection of adjacent ones of the unit voltage pumps. BRIEF DESCRIPTION OF DRAWINGS

[0030] The description herein makes reference to the accompanying drawings, where like reference numerals may

[0031] Figure 1A memory device is shown in accordance with an embodiment of the present disclosure.

[0032] Figure 2 A data processing system is shown in accordance with an embodiment of the present disclosure.

[0033] Figure 3 A data processing system is shown in accordance with an embodiment of the present disclosure. Figure 1 A read operation in the memory device is shown.

[0034] Figure 4 A first example of a voltage generation circuit is shown in accordance with an embodiment of the present disclosure.

[0035] Figure 5 A second example of a voltage generation circuit is shown in accordance with another embodiment of the present disclosure.

[0036] Figure 6 A third example of a voltage generation circuit is shown in accordance with another embodiment of the present disclosure.

[0037] Figure 7A A first example of a noise attenuation circuit is shown in accordance with an embodiment of the present disclosure. Figure 7B

[0038] A first example of a multi-stage voltage pump is shown in accordance with an embodiment of the present disclosure. Figure 8

[0039] A first example of a page buffer and bus is shown in accordance with an embodiment of the present disclosure. Figure 9

[0040] A second example of a page buffer and bus is shown in accordance with another embodiment of the present disclosure. Figure 10 DETAILED DESCRIPTION

[0041] Various embodiments of the present disclosure are described below with reference to the drawings. However, elements and features of the present disclosure can be variously configured or arranged to form other embodiments, and the other embodiments can be variations of any disclosed embodiment.

[0042] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment”, “an example embodiment”, “an embodiment”, “another embodiment”, “some embodiments”, “various embodiments”, “other embodiments”, “optional embodiments”, etc. are intended to mean that any such features are included in at least one embodiment of the present disclosure, but can or can not be included in the same embodiment.

[0043] ​In the present disclosure, the terms “comprise” “comprising”, “include”, and “including” are open-ended. As used in the appended claims, these terms specify the presence of stated elements but do not preclude the presence or addition of one or more other elements. The term in the claims does not exclude that the device includes additional components (e.g., interface units, circuitry, etc.).

[0044] In the present disclosure, various units, circuits, or other components can be described or claimed as “configured to” perform one or more tasks. In this context, “configured to” is used to connote structure by indicating that a block / circuit / component includes structure (e.g., circuitry) that is capable of performing the task or tasks during operation. As used in this context, “configured to” can connote various orientations of a block / circuit / component including: (i) a structural configuration by virtue of being

[0045] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and / or digital circuitry) and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s) / software (including digital signal processors), software, and memory that work together to cause an apparatus, such as a mobile phone or server, to perform various functions described herein, and (c) circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware for operation, even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the terms “circuit” or “logic” also cover an implementation that is solely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and / or firmware. The term “circuit” or “logic” also encompasses an integrated circuit, for example, a storage device, if applicable to a particular claim element.

[0046] As used herein, the terms "first," "second," "third," etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" are not necessarily used to denote a first value written before a second value. Further, although these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another otherwise having the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0047] Further, the term "based on" is used to describe one or more factors to which determination of some element is based. This term is not exclusive, meaning that determination of some element can be based on additional factors not listed. That is, determination of some element can be based on those factors alone, or based on those factors at least in part. Consider the phrase "determine A based on B." While B is a factor that affects the determination of A in this case, this phrase does not exclude determinations of A based on C. In other cases, A can be determined based on B alone.

[0048] Herein, a term of data, data item, data entry, or entry of data can be an order of bits. For example, a data item can include content of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented in an order of bits. According to an embodiment, a data item can include a discrete object. According to another embodiment, a data item can include a unit of information within a transmission packet between two different components.

[0049] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.

[0050] Figure 1 A memory system 110 according to an embodiment of the present disclosure is illustrated. Specifically, Figure 1 An array circuit of memory cells in a memory die included in a memory device according to an embodiment of the present disclosure is schematically illustrated.

[0051] Referring to Figure 1The memory chip 200 can include a memory group 330 including a plurality of nonvolatile memory cells. The memory group 330 can include a plurality of cell strings 340. The cell string 340 includes a plurality of nonvolatile memory cells connected to each of a plurality of bit lines BL0 to BLm-1. The cell string 340 disposed in each column of the memory group 330 can include at least one drain select transistor DST and at least one source select transistor SST. A plurality of nonvolatile memory cells or memory cell transistors MC0 to MCn-1 can be connected in series between the drain select transistor DST and the source select transistor SST. For example, each of the nonvolatile memory cells MC0 to MCn-1 can be configured as a multi-layer cell (MLC) that stores a data item having a plurality of bits per cell. The cell string 340 can be electrically connected to the corresponding bit lines BL0 to BLm-1, respectively.

[0052] Figure 1 The memory group 330 including NAND type flash memory cells is illustrated as an example. However, the memory group 330 included in the memory device 150 according to an embodiment of the disclosure can not be limited to the NAND type flash memory. In another embodiment, the memory group 330 can also be implemented as a NOR type flash memory, a hybrid type flash memory that mixes or combines at least two different types of memory cells, or a one-chip NAND flash memory in which a controller is embedded in a single memory chip. In addition, the memory group 330 according to an embodiment of the disclosure can include a flash memory cell including a charge-trapping flash (CTF) layer having a conductive floating gate or an insulating layer.

[0053] According to an embodiment of the disclosure, Figure 1 The illustrated memory group 330 can include Figure 2 The memory chip 200 can include at least one memory block 152, 154, 156 included in the memory device 150 illustrated. According to an embodiment, the memory chip 200 can include a memory device having a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 can be implemented as a 3D structure (or a vertical structure). Each of the memory blocks 152, 154, 156 can have a three-dimensional structure extending in first to third directions (for example, an x-axis direction, a y-axis direction, and a z-axis direction).

[0054] The memory banks 330 of the plurality of memory blocks 152, 154, 156 that constitute the memory device 150 can be coupled to a plurality of bit lines BL, a plurality of string select lines SSL, and a plurality of drain select lines DSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL. The memory bank 300 can include a plurality of NAND strings NS, each including a plurality of memory cells MC. In the memory bank 330, each of the NAND strings NS can be connected to each of the bit lines BL. Also, a string select transistor SST of each of the NAND strings NS can be connected to the common source line CSL, and a drain select transistor DST of each of the NAND strings NS can be connected to the corresponding bit line BL. Here, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST of each of the NAND strings NS.

[0055] The voltage supply circuit 170 in the memory die 200 can supply a word line voltage (e.g., a subject voltage such as a program voltage, a read voltage, and a pass voltage) according to an operation mode via each word line, or supply a voltage to a bulk (e.g., a well region) in which each memory block including the memory cells MC is formed. In this case, a voltage generation operation of the voltage supply circuit 170 can be performed under the control of a control circuit (not shown). Also, the voltage supply circuit 170 can generate a plurality of different read voltages to distinguish a plurality of data items from each other. In response to the control of the control circuit, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. The word line voltage can be supplied to the selected word line and the unselected word line, respectively. The voltage supply circuit 170 can include a voltage generation circuit for generating a target voltage having various levels (refer to FIG. 2). Figures 4-8 ) The voltage supply circuit 170 can be coupled to a first pin or pad that receives a first power supply voltage VCC applied from the outside (e.g., an external device), and a second pin or pad that receives a second power supply voltage VPP applied from the external device. Here, the voltage level of the second power supply voltage VPP can be two times or more higher than the voltage level of the first power supply voltage VCC. For example, the first power supply voltage VCC can have a voltage level of 2.0 V to 5.5 V, and the second power supply voltage can have a voltage level of 9 V to 13 V. The voltage supply circuit 170 according to an embodiment of the disclosure can include a voltage generation circuit for generating a target voltage having various levels used in the memory bank 330 more quickly. The voltage generation circuit can use the second power supply voltage VPP to generate a target voltage having a voltage level higher than the second power supply voltage VPP.

[0056] Read / write circuitry 320, controlled by control circuitry of memory die 200, can operate as a sense amplifier or a write driver depending on the mode of operation. Read / write circuitry 320 is coupled to a first supply voltage VCC and a first ground voltage corresponding to the first supply voltage VCC. For example, in verify and read operations, read / write circuitry 320 can operate as a sense amplifier for reading data items from the memory cell array. Also, in program operations, read / write circuitry 320 can operate as a write driver that controls the potential of bit lines according to data items to be stored in the memory cell array. Read / write circuitry 320 can receive data items to be programmed to the cell array from a page buffer (not shown) during program operations. Read / write circuitry 320 can drive bit lines based on the input data items. To this end, read / write circuitry 320 includes a plurality of page buffers (PB) 322, 324, 326, each corresponding to each column (or each bit line) or each pair of columns (or each pair of bit lines). According to embodiments, a plurality of latches (not shown) can be included in each of page buffers 322, 324, 326.

[0057] Although not shown, page buffers 322, 324, 326 can be coupled to a data input / output device (e.g., serialization circuitry or serializer) through a plurality of buses BUS. When each of page buffers 322, 324, 326 is coupled to the data input / output device through a different bus, latency that can occur in data transfer from page buffers 322, 324, 326 can be reduced. For example, each page buffer 322, 324, 326 can perform data transfer without waiting time.

[0058] Figure 2 A data processing system according to embodiments of the disclosure is shown.

[0059] Referring to Figure 2 Data processing system 100 can include a host 102 interfaced or coupled with a memory system, such as memory system 110. For example, host 102 and memory system 110 can be coupled to each other via a data bus, a host cable, or the like to perform data communication.

[0060] Memory system 110 can include a memory device 150 and a controller 130. Memory device 150 and controller 130 in memory system 110 can be considered as components or elements that are physically separate from each other. Memory device 150 and controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a way.

[0061] According to embodiments, the memory device 150 and the controller 130 may be functionally divided components or elements. Further, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0062] like Figure 2 As shown, memory device 150 may include a plurality of memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells that have their data removed together in a single erase operation. Although not shown, memory blocks 152, 154, and 156 may include pages, which are a group of non-volatile memory cells that have their data stored together during a single programming operation or have their data output together during a single read operation. For example, a memory block may include multiple pages.

[0063] According to an embodiment, the memory device 150 may include Figure 1 The memory die 200 is shown. For example, the memory device 150 may include multiple memory planes or multiple memory dies. According to an embodiment, a memory plane may be considered as a logical or physical partition, which includes at least one memory block, drive circuitry capable of controlling an array including multiple non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0064] Additionally, according to an embodiment, a memory die may include at least one memory plane. A memory die can be understood as a set of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 via a data path. Each memory die may include an interface for exchanging data items and signals with the controller 130.

[0065] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. Figure 1 The internal configuration of the illustrated memory device 150 may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to those described herein. Figure 2 The internal configuration shown.

[0066] Reference Figure 2The memory device 150 may include a voltage supply circuit 170 capable of supplying at least some voltage to the memory blocks 152, 154, and 156. (See reference...) Figures 4-8 The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages used in memory blocks 152, 154, and 156. The voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation to read data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the read voltage Vrd to the selected non-volatile memory cell. During a programming operation to store data in the non-volatile memory cells included in memory blocks 152, 154, and 156, the voltage supply circuit 170 may supply the programming voltage Vprog to the selected non-volatile memory cell. Furthermore, during a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 may supply the pass voltage Vpass to an unselected non-volatile memory cell. During the erase operation that erases the data stored in the non-volatile memory cells included in memory blocks 152, 154, and 156, voltage supply circuit 170 can supply erase voltage Vers to the memory blocks.

[0067] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on the performed operation. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, it may be necessary to use the levels of multiple read voltages Vrd to identify or read multiple data items. Memory device 150 may include a table containing information corresponding to the levels of multiple read voltages Vrd corresponding to multiple data items. For example, the table may include bias values ​​stored in a register, each bias value corresponding to the level of a specific read voltage Vrd. The number of bias values ​​for the read voltage Vrd used for a read operation may be limited to a preset range. Moreover, the bias values ​​may be quantized.

[0068] Host 102 may include portable electronic devices (e.g., mobile phones, MP3 players, laptops, etc.) or non-portable electronic devices (e.g., desktop computers, game consoles, televisions, projectors, etc.). According to an embodiment, host 102 may include a central processing unit (CPU) included in both portable and non-portable electronic devices.

[0069] The host 102 can further include at least one operating system (OS) that can control functions and operations performed in the host 102. The OS can provide interoperability between the host 102 operatively engaged with the memory system 110 and a user intending to store data in the memory system 110. The OS can support functions and operations corresponding to a request of the user. As an example and not by way of limitation, the OS can be classified as a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified as a personal operating system and an enterprise operating system according to system requirements or a user environment. The enterprise operating system can be specialized to secure and support high-performance computing compared to the personal operating system.

[0070] The mobile operating system can be subject to support services or functions for mobility (e.g., power saving functions). The host 102 can include a plurality of operating systems. The host 102 can execute a plurality of operating systems interlocked with the memory system 110 corresponding to a request of the user. The host 102 can transmit a plurality of commands corresponding to a request of the user to the memory system 110, thereby performing operations corresponding to the plurality of commands within the memory system 110.

[0071] The controller 130 in the memory system 110 can control the memory device 150 in response to a request or a command input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102, and can perform a write operation (or a program operation) to store data input from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control and manage internal operations of reading data, programming data, erasing data, and the like.

[0072] According to an embodiment, the controller 130 can include a host interface 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. As Figure 2 Components included in the controller 130 as shown can vary according to the structure, functions, operational performance, and the like of the memory system 110.

[0073] For example, the memory system 110 can be implemented with any of various types of storage devices that can be electrically coupled with the host 102 according to a protocol of the host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like. Components can be added to or omitted from the controller 130 according to embodiments of the memory system 110.

[0074] The host 102 and the memory system 110 can each include a controller or an interface to transmit and receive signals, data, and the like according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device capable of transmitting and receiving signals, data, and the like to and from the host 102.

[0075] The host interface 132 included in the controller 130 can receive signals, commands (or requests), and / or data input from the host 102. For example, the host 102 and the memory system 110 can use a predetermined communication standard to transmit and receive data between each other. Examples of communication standards or interfaces supported by the host 102 and the memory system 110 for transmitting and receiving data include a universal serial bus (USB), a multimedia card (MMC), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCIe), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a mobile industry processor interface (MIPI), and the like. According to an embodiment, the host interface 132 is a layer for exchanging data with the host 102, and is implemented or driven with firmware referred to as a host interface layer (HIL).

[0076] An electronic integrated drive electronics (IDE) or an advanced technology attachment (ATA) can be used as one of the interfaces for transmitting and receiving data, and, for example, a cable including 40 parallel connections of wires can be used to support data transmission and reception between the host 102 and the memory system 110. When a plurality of memory systems 110 are connected to a single host 102, the plurality of memory systems 110 can be divided into a master and a slave by using a location or a dip switch to which the plurality of memory systems 110 are connected. The memory system 110 set as the master can be used as a master memory device. The IDE (ATA) can include, for example, a fast ATA, an ATAPI, or an enhanced IDE (EIDE).

[0077] A serial advanced technology attachment (SATA) interface is a serial data communication interface compatible with various ATA standards of a parallel data communication interface used by an electronic integrated drive electronics (IDE) device. The 40 wires in the IDE interface can be reduced to 6 wires in the SATA interface. For example, the 40 parallel signals of the IDE can be converted into 6 serial signals of the SATA interface. The SATA interface has been widely used due to its faster data transmission and reception rate and its less resource consumption for data transmission and reception in the host 102. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. In addition, the SATA interface can support hot plugging, which allows an external device to be attached to or detached from the host 102 even when data communication between the host 102 and another device is running. Accordingly, the memory system 110 can be connected or disconnected as an additional device like a device supported by a universal serial bus (USB) even when the host 102 is powered on. For example, in a host 102 having an eSATA port, the memory system 110 can be freely attached to or detached from the host 102 like an external hard disk.

[0078] A small computer system interface (SCSI) is a serial data communication interface for connecting a computer or a server with other peripheral devices. The SCSI can provide a higher transmission speed compared to other interfaces such as IDE and SATA. In the SCSI, the host 102 and at least one peripheral device (e.g., the memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In the SCSI, it is easy to connect or disconnect a device such as the memory system 110 to or from the host 102. The SCSI can support connecting 15 other devices to a single transceiver included in the host 102.

[0079] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and a plurality of peripheral devices are connected in series, and data transmission and reception between the host 102 and each of the peripheral devices can be performed in a serial data communication scheme. SAS can support connection between the host 102 and the peripheral devices through a serial cable instead of a parallel cable to easily manage devices using SAS and enhance or improve operational reliability and communication performance. SAS can support connection of eight external devices to a single transceiver included in the host 102.

[0080] A high-speed non-volatile memory (NVMe) is an interface based on at least a Peripheral Component Interconnect Express (PCIe) designed to improve performance and design flexibility of a host 102, a server, a computing device, etc. equipped with a non-volatile memory system 110. The PCIe can use a slot or a specific cable to connect a computing device (e.g., the host 102) and a peripheral device (e.g., the memory system 110). For example, the PCIe can use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to implement high-speed data communication of more than a few hundred MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). According to an embodiment, the PCIe scheme can implement a bandwidth of tens to hundreds of Giga bits per second. The NVMe can support faster operation speed of the non-volatile memory system 110, such as an SSD, than a hard disk.

[0081] According to an embodiment, the host 102 and the memory system 110 can be connected through a Universal Serial Bus (USB). The Universal Serial Bus (USB) is an extensible, hot-pluggable, plug-and-play serial interface that can provide an economical and efficient standard connection between the host 102 and peripheral devices such as a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, etc. A plurality of peripheral devices such as the memory system 110 can be coupled to a single transceiver included in the host 102.

[0082] Referring to Figure 2The error correction circuit 138 can correct error bits of data read from the memory device 150 and can include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed into the memory device 150 to generate encoded data in which parity bits are added, and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder can detect and correct error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on data read from the memory device 150, the error correction circuit 138 determines whether the error correction decoding has been successful, and outputs an instruction signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. The error correction circuit 138 can use parity bits that have been generated during the ECC encoding process for data stored in the memory device 150 in order to correct error bits of the read data. When the number of error bits is greater than or equal to the number of correctable error bits, the error correction circuit 138 can not correct the error bits, but can output a correction failure signal indicating that the correction of the error bits has failed.

[0083] According to an embodiment, the error correction circuit 138 can perform an error correction operation based on an encoding modulation such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), a block coded modulation (BCM), etc. The error correction circuit 138 can include all circuits, modules, systems, and / or devices that perform an error correction operation based on at least one of the above-described codes. Figure 2 The illustrated error correction circuit 138 can include Figure 1 At least some of the components included in the illustrated controller 130.

[0084] For example, the ECC decoder can perform hard decision decoding or soft decision decoding on data transmitted from the memory device 150. Hard decision decoding can be understood as one of two methods that are broadly classified for error correction. Hard decision decoding can include an operation of correcting error bits by reading digital data "0" or "1" from a non-volatile memory cell in the memory device 150. Since hard decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster than soft decision decoding.

[0085] Soft decision decoding can quantize threshold voltages of non-volatile memory cells in the memory device 150 by two or more quantized values (e.g., multi-bit data, approximations, analog values, etc.) in order to correct error bits based on the two or more quantized values. The controller 130 can receive two or more alphabets or quantized values from a plurality of non-volatile memory cells in the memory device 150, and then perform decoding based on information generated by characterizing the quantized values as a combination of information such as conditional probabilities or likelihoods.

[0086] According to embodiments, among methods designed for soft decision decoding, the ECC decoder can use a low-density parity-check and generator matrix (LDPC-GM) code. A low-density parity-check (LDPC) code uses an algorithm that can read a value of data from the memory device 150 according to reliability of several bits, rather than simply reading data 1 or 0 as in hard decision decoding, and iteratively repeats reading by message passing in order to improve reliability of the value. Then, the value is finally determined as data 1 or 0. For example, a decoding algorithm using the LDPC code can be understood as a probabilistic decoding. In hard decision decoding, a value output from a non-volatile memory cell is encoded as 0 or 1. In comparison with hard decision decoding, soft decision decoding can determine a value stored in a non-volatile memory cell based on stochastic information. With respect to bit flips, which can be regarded as errors likely to occur in the memory device 150, soft decision decoding can provide an improved probability of correcting errors and recovering data, and provide reliability and stability of the corrected data. The LDPC-GM code can have a scheme in which the inner LDPC-GM code can be connected in series with a high-speed LDPC code.

[0087] According to embodiments, the ECC decoder can use, for example, a low-density parity-check convolutional code (LDPC-CC) for soft decision decoding. The LDPC-CC can have a scheme using linear-time encoding and pipelined decoding based on a variable block length and a shift register.

[0088] According to embodiments, the ECC decoder can use, for example, a log-likelihood ratio turbo code (LLR-TC) for soft decision decoding. A log-likelihood ratio (LLR) can be calculated as a non-linear function of a distance between a sampled value and an ideal value. In addition, a turbo code (TC) can include a simple code in two or three dimensions (e.g., a Hamming code), and repeatedly decodes in a row direction and a column direction to improve reliability of a value.

[0089] A power management unit (PMU) 140 can control power supplied to the controller 130. The PMU 140 can monitor power supplied to the memory system 110 (e.g., a voltage supplied to the controller 130) and provide power to components included in the controller 130. The PMU 140 can not only detect power-on or power-off, but also generate a trigger signal to enable the memory system 110 to back up a current state in an emergency when power supplied to the memory system 110 is unstable. According to an embodiment, the PMU 140 can include a device or component capable of accumulating power that can be used in an emergency.

[0090] The memory interface 142 can serve as an interface for handling commands and data transferred between the controller 130 and the memory device 150, thereby allowing the controller 130 to control the memory device 150 in response to a command or request input from the host 102. In the case where the memory device 150 is a flash memory, the memory interface 142 can generate a control signal for the memory device 150 under the control of the processor 134 and can process data input to or output from the memory device 150.

[0091] For example, when the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented by or driven by firmware called a flash interface layer (FIL) to exchange data with the memory device 150.

[0092] According to an embodiment, the memory interface 142 can support an open NAND flash interface (ONFi), a toggle mode, or the like, to perform data input / output with the memory device 150. For example, the ONFi can use a data path (e.g., a lane, a channel, or the like) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between the controller 130 and the memory device 150 can be achieved through at least one interface regarding an asynchronous single data rate (SDR), a synchronous double data rate (DDR), a toggle double data rate (DDR), or the like.

[0093] The memory 144 can serve as a working memory of the memory system 110 or the controller 130 while temporarily storing transaction data of operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data output from the memory device 150 in response to a read request from the host 102 before the read data is output to the host 102. Also, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before programming the write data into the memory device 150. When the controller 130 controls operations of the memory device 150 such as data read operations, data write or programming operations, data erase operations, etc., data transmitted between the controller 130 and the memory device 150 of the memory system 110 can be temporarily stored in the memory 144.

[0094] In addition to read data or write data, the memory 144 can store information (e.g., mapping data, read requests, programming requests, etc.) for inputting or outputting data between the host 102 and the memory device 150. According to an embodiment, the memory 144 can include one or more of a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc. The controller 130 can allocate some storage spaces in the memory 144 to components established to perform data input / output operations. For example, a write buffer established in the memory 144 can be used to temporarily store target data subject to a programming operation.

[0095] In an embodiment, the memory 144 can be implemented with volatile memory. For example, the memory 144 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 The memory 144 is shown, for example, disposed within the controller 130, but embodiments are not limited thereto. The memory 144 can be located inside or outside of the controller 130. For example, the memory 144 can be implemented by an external volatile memory having a memory interface that transfers data and / or signals between the memory 144 and the controller 130.

[0096] The processor 134 can control overall operations of the memory system 110. For example, the processor 134 can control a programming operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 102. According to an embodiment, the processor 134 can run firmware to control the programming operation or the read operation in the memory system 110. Herein, the firmware can be referred to as a flash translation layer (FTL). According to an embodiment, the processor 134 can be implemented with a microprocessor, a central processing unit (CPU), etc.

[0097] According to an embodiment, the memory system 110 can be implemented with at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores, which are regarded as different processing regions. For example, when the multiple cores in the multi-core processor independently drive or run multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0098] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Further, the memory system 110 can perform operations independent of the commands or requests input from the host 102. In one case, the operations performed by the controller 130 in response to the requests or commands input from the host 102 can be regarded as foreground operations, and the operations performed by the controller 130 independent of the requests or commands input from the host 102 can be regarded as background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. In addition, parameter setting operations corresponding to setting parameter commands or setting feature commands, which are setting commands transmitted from the host 102, can be regarded as foreground operations. For example, as a background operation performed without a command transmitted from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and processing bad blocks, etc.

[0099] According to an embodiment, operations substantially similar to both foreground operations and background operations can be performed. For example, when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102, the garbage collection can be regarded as a foreground operation. When the memory system 110 performs garbage collection (e.g., automatic GC) independent of the host 102, the garbage collection can be regarded as a background operation.

[0100] When the memory device 150 includes multiple dies (or multiple chips) each including multiple nonvolatile memory cells, the controller 130 can perform parallel processing with respect to multiple requests or commands input from the host 102 in order to improve the performance of the memory system 110. For example, the transmitted requests or commands can be divided into multiple groups including at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and the multiple groups of requests or commands are processed individually or in parallel in each plane, each die, or each chip.

[0101] The memory interface 142 in the controller 130 can be connected to the plurality of dies or chips in the memory device 150 through at least one lane and at least one path. When the controller 130 distributes and stores data in the plurality of dies through each lane or each path in response to a request or a command associated with a plurality of pages including non-volatile memory cells, a plurality of operations corresponding to the request or the command can be performed simultaneously or in parallel in the plurality of dies or planes. This processing method or scheme can be regarded as an interleaving method. Since the data input / output speed of the memory system 110 is accelerated by operating with the interleaving method, the data I / O performance of the memory system 110 can be improved.

[0102] By way of example and not limitation, the controller 130 can identify a status of a plurality of lanes (or paths) associated with a plurality of dies included in the memory device 150. The controller 130 can determine a status of each lane or each path as one of a busy status, a ready status, an active status, an idle status, a normal status, and an abnormal status. The controller's determination of which lane or path to pass an instruction (and / or data) through can be associated with a physical block address. The controller 130 can refer to a descriptor passed from the memory device 150. The descriptor can include a parameter block or a parameter page describing something about the memory device 150. The descriptor can have a predetermined format or structure. For example, the descriptor can include a device descriptor, a configuration descriptor, a cell descriptor, etc. The controller 130 can refer to or use the descriptor to determine which lane(s) or path(s) to exchange an instruction or data with.

[0103] Referring to Figure 2 The memory device 150 in the memory system 110 can include a plurality of memory blocks 152, 154, 156. Each of the plurality of memory blocks 152, 154, 156 includes a plurality of non-volatile memory cells. According to an embodiment, the memory blocks 152, 154, 156 can be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, 156 can include a plurality of pages that are a group of non-volatile memory cells that are read or programmed together.

[0104] In one embodiment, each memory block 152, 154, or 156 can have a three-dimensional stacked structure to achieve high integration. Further, the memory device 150 can include a plurality of dies each including a plurality of planes each including a plurality of memory blocks 152, 154, 156. The configuration of the memory device 150 can vary depending on the performance of the memory system 110.

[0105] Figure 2A memory device 150 including a plurality of memory blocks 152, 154, and 156 is shown. The plurality of memory blocks 152, 154, and 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and the like, according to a number of bits that can be stored in one memory cell. An SLC memory block includes a plurality of pages implemented by memory cells each storing one bit of data. An SLC memory block can have a higher data I / O operation performance and a higher endurance than an MLC memory block. An MLC memory block includes a plurality of pages implemented by memory cells each storing a plurality of bits of data (e.g., two or more bits of data). An MLC memory block can have a greater storage capacity than an SLC memory block for the same space. An MLC memory block can be highly integrated in view of the storage capacity.

[0106] In an embodiment, the memory device 150 can be implemented with MLC memory blocks such as a double-level cell (DLC) memory block, a triple-level cell (TLC) memory block, a quad-level cell (QLC) memory block, and combinations thereof. A DLC memory block can include a plurality of pages implemented by memory cells each capable of storing 2 bits of data. A TLC memory block can include a plurality of pages implemented by memory cells each capable of storing 3 bits of data. A QLC memory block can include a plurality of pages implemented by memory cells each capable of storing 4 bits of data. In another embodiment, the memory device 150 can be implemented with blocks including a plurality of pages implemented by memory cells each capable of storing five or more bits of data.

[0107] According to an embodiment, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block storing one bit of data in one memory cell. A data input / output speed of a multi-level cell (MLC) memory block can be slower than a data input / output speed of an SLC memory block. That is, a margin of a read operation or a program operation can decrease when an MLC memory block is used as an SLC memory block. For example, the controller 130 can perform a data input / output operation at a higher speed when an MLC memory block is used as an SLC memory block. Accordingly, since a buffer can need a higher data input / output speed to improve a performance of the memory system 110, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data.

[0108] Further, according to an embodiment, the controller 130 can program data into the MLC multiple times in a case where an erase operation is not performed on a specific MLC memory block included in the memory device 150. Generally, a non-volatile memory cell does not support data rewriting. However, the controller 130 can use a feature of the MLC capable of storing multi-bit data to program 1-bit data into the MLC multiple times. For the MLC rewriting operation, when 1-bit data is programmed into the MLC, the controller 130 can store the number of programming times as separate operation information. According to an embodiment, an operation for uniformly balancing threshold voltages of the MLC can be performed before programming additional 1-bit data into the same MLC that has already stored another bit of data.

[0109] In an embodiment, the memory device 150 is implemented as a non-volatile memory such as a flash memory, e.g., a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 can be implemented by at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0110] Figure 3 A read operation in the memory device shown is illustrated. Figure 1 Specifically, Figure 3 Attention is drawn to operations performed in the memory device 150 or the memory die 200 in response to a read command or a read request transmitted from the controller 130.

[0111] Referring to Figure 3 , to read and output a data item stored in a non-volatile memory cell of the memory device 150 or the memory die 200, the voltage supply circuit 170 can generate a read voltage for a read operation (A1 section). Here, the read voltage can be applied through a word line WL connected to the non-volatile memory cell. The level of the read voltage can be set differently in response to a structure and a design of the non-volatile memory cell, a number of data bits programmed in the non-volatile memory cell, etc.

[0112] The memory device 150 can enable a word line WL corresponding to a specific location of the memory block 152, 154, 156 or the memory bank 330 described with reference to Figures 1-2 In addition, the memory device 150 can connect the word line WL to the voltage supply circuit 170 described with reference to Figure 1The drain select line DSL of the drain select transistor DST of each of the described NAND strings is enabled. In addition, the latch in the page buffer PB can be initialized to store the data transferred through the bit line BL. The memory device 150 can disable the drain select line DSL corresponding to the unselected NAND string.

[0113] The read voltage Vread can be applied to the subjected word line corresponding to the location of the data item, and the pass voltage Vpass can be applied to the other word lines (B2 section) other than the subjected word line.

[0114] Then, the bit line BL can be pre-charged (C1 section). The channel in the NAND string can be formed differently based on the non-volatile memory cell. For example, the channel can vary according to the data stored in the non-volatile memory cell connected to the word line to which the read voltage Vread is applied. The read voltage Vread can cause a change in the potential of the pre-charged bit line BL.

[0115] Referring to Figure 1 The described read / write circuit 320 can sense or detect the change in the potential of the bit line BL (i.e., sense data), and store the sensed data in the latch of the page buffer PB (C2 section).

[0116] Thereafter, the word line WL in the memory block 152, 154, 156 or the memory group 330 is disabled (D1 and D2 sections). In this case, the sensed data stored in the latch of the page buffer PB can be transmitted to the transceiver (e.g., serialization circuit or serializer) to perform data transmission with the controller 130.

[0117] When the read operation is completed, the drain select line DSL can be disabled, and the voltage supply circuit 170 can reset the voltage used for the read operation (D3 section).

[0118] In Figure 3Some of the segments (B1, B2, C1, C2, D1 segments) of the time taken for the operations of enabling a word line, supplying a read voltage to the word line to sense data, and disabling the word line in the read operation described in the middle can be determined based on the characteristics of the non-volatile memory cells in the memory device 150 or the memory die 200. When it is difficult to reduce the operation time of the segments (B1, B2, C1, C2, D1 segments), an interleaving method of reading data from and writing data to multiple locations within the memory device 150 in parallel can be used to improve the data input / output performance. For example, a large amount of data items can be divided into 2, 4, 8, or 16 partial data items, each data item corresponding to each of 2, 4, 8, or 16 regions (e.g., dies, planes, etc.). Each region such as a die or a plane can perform a read operation or a write operation individually. However, even when the interleaving scheme is employed in the memory device 150, it can be difficult to reduce or lower the time taken for the operations (A1, D3 segments) of generating and resetting the target voltages for the data input / output operations.

[0119] To improve the speed of the data input / output operations performed within the memory device 150 or the memory die 200, the voltage generation circuit according to an embodiment is capable of reducing the time taken for the operations (A1, D3 segments) of generating and resetting the target voltages for the data input / output operations. The voltage generation circuit is described below with reference to Figures 4-8 The voltage generation circuit is described.

[0120] Figure 4 A first example of the voltage generation circuit according to an embodiment of the disclosure is shown.

[0121] Referring to Figure 4 , the voltage generation circuit can include a first multi-stage voltage pump 282 capable of receiving a first supply voltage VCC and generating first pump generated voltages VPEPMP having various levels. Referring to Figure 1 , the memory die 200 can receive the first supply voltage VCC and the second supply voltage VPP via different pins or pads. The first multi-stage voltage pump 282 can receive the first supply voltage VCC for generating the first pump generated voltages VPEPMP. However, the first multi-stage voltage pump 282 can not use the second supply voltage VPP. According to an embodiment, the first pump generated voltages VPEPMP can include a target voltage of 15.2 V to 28.8 V or 14 V, which can be used for the data input / output operations.

[0122] Additionally, the voltage generation circuit can include first and second voltage regulators 284 and 286 for maintaining the first pump generation voltage VPEPMPoutput from the first multi-stage voltage pump 282 within a preset range. For example, the first and second voltage regulators 284 and 286 can maintain a voltage level between a ground voltage node VSSI and an output node of the first multi-stage voltage pump 282.

[0123] According to an embodiment, the first voltage regulator 284 can stabilize the first pump generation voltage VPEPMPat 15.2V to 28.8V or 14V, and the second voltage regulator 286 can output a first usage voltage VPE of 7V to 23V based on the first pump generation voltage VPEPMP. Herein, the first pump generation voltage VPEPMPand the first usage voltage VPE can be selectively applied to the memory blocks 152, 154, 156 or the memory banks 330 in response to an operation performed within the memory device 150 or the memory die 200.

[0124] As described in Figure 1 , since the level of the first supply voltage VCC is lower than the level of the second supply voltage VPP, the first multi-stage voltage pump 282 can require a preparation time or a setup time (standby period) to generate the first pump generation voltage VPEPMPhaving a high level of 15.2V to 28.8V or 14V. As a difference between a voltage input to the first multi-stage voltage pump 282 and a voltage output from the first multi-stage voltage pump 282 becomes greater, the preparation time or the setup time (standby period) can increase or become longer after the enable signal CE# is activated. When the preparation time or the setup time (standby period) becomes longer, an activation period or a work section in which the voltage supply circuit 170 can perform a data input / output operation using the target voltage VPE can be delayed. This can degrade a speed of a data input / output operation performed within the memory device 150 or the memory die 200.

[0125] Figure 5 A second example of a voltage generation circuit according to another embodiment of the disclosure is illustrated.

[0126] Referring to Figure 5 , the voltage generation circuit can include a second multi-stage voltage pump 292 capable of receiving the first supply voltage VCC and generating a second pump generation voltage VPASSPMPhaving various levels. Referring to Figure 1The memory die 200 can receive a first supply voltage VCC and a second supply voltage VPP. The second multi-level voltage pump 292 can use the first supply voltage VCC to generate a second pump generated voltage VPASSPMP, and the second supply voltage VPP of 11V to 13V is coupled to an output terminal of the second multi-level voltage pump 292. According to embodiments, the second pump generated voltage VPASSPMP can have a voltage level of 8V to 13V, which is used for data input / output operations. For example, the second multi-level voltage pump 292 can output a target voltage of 8.2V, 8.7V, 9.4V, or 10.2V for a read operation, and / or a target voltage of 11.1V, 11.5V, 11.9V, or 12.4V for a write operation or an erase operation.

[0127] In addition, the voltage generation circuit can include a third voltage regulator 294 and a fourth voltage regulator 296 capable of maintaining and outputting the second pump generated voltage VPASSPMP output from the second multi-level voltage pump 292 within a preset range. For example, the third voltage regulator 294 and the fourth voltage regulator 296 can maintain a voltage level between a ground voltage node VSSI and an output node of the second multi-level voltage pump 292.

[0128] According to embodiments, the third voltage regulator 294 can stabilize or maintain the second pump generated voltage VPASSPMP to 8~13V. Further, the fourth voltage regulator 296 can select and output a second use voltage VPASS1 of 4.2V to 10.5V based on the second pump generated voltage VPASSPMP. Herein, the second pump generated voltage VPASSPMP and the second use voltage VPASS1 can be selectively applied to the memory blocks 152, 154, 156 or the memory banks 330 in response to operations performed within the memory device 150 or the memory die 200.

[0129] Further, the voltage generation circuit can include a switch 290 between the pin or pad 298 and an output terminal of the second multi-stage voltage pump 292. The second supply voltage VPP of 11V to 13V is supplied from an external device via the pin or pad 298. When the voltage generation circuit starts to operate, if the enable signal CE# is activated, the switch 290 can momentarily transfer the high level of the second supply voltage VPP to the output terminal of the second multi-stage voltage pump 292 and the input terminal of the second voltage regulator 296. In this case, due to the second supply voltage VPP, current leakage can occur through transistors included in the second multi-stage voltage pump 292, the third voltage regulator 294, or the fourth voltage regulator 296. As a result, the ground voltage node VSSI can bounce. Due to the current leakage, the amount of current consumed during a preparation time or a setup time (standby period) can increase.

[0130] To solve the above problem, when the enable signal CE# is activated, the voltage generation circuit can turn on the switch 290 after a certain time. When the switch 290 is turned on, the second supply voltage VPP input via the pin or pad 298 can be supplied to the output terminal of the second multi-stage voltage pump 292. The switch 290 can be controlled to eliminate the bounce of the ground voltage node VSSI (e.g., to avoid bouncing the ground voltage node VSSI).

[0131] As described with reference to Figure 1 Since the level of the first supply voltage VCC is lower than the level of the second supply voltage VPP, the second supply voltage VPP of 11V to 13V can be supplied to the output terminal of the second multi-stage voltage pump 292 in order to avoid a longer preparation time or setup time (standby period) to output the second pump generated voltage VPASSPMP of 8V to 13V. However, the voltage generation circuit has an operational burden of controlling the switch 290 to avoid bouncing the ground voltage node VSSI. Also, the preparation time or setup time (standby period) taken to output the second pump generated voltage VPASSPMP can increase due to a delay time taken to avoid bouncing the ground voltage node VSSI. If the preparation time or setup time (standby period) increases, the activation period of the voltage supply circuit 170 to apply the second pump generated voltage VPASSMP and the second use voltage VPASS1 to the memory blocks 152, 154, 156, or the memory bank 330 can be delayed. Accordingly, the speed of data input / output operations performed in the memory device 150 or the memory die 200 can decrease.

[0132] Figure 6 A third example of a voltage generation circuit according to another embodiment of the disclosure is illustrated.

[0133] Referring to Figure 6, the voltage generation circuit can include a third multi-stage voltage pump 250 capable of generating a first pump generation voltage VPEPMPand a fourth multi-stage voltage pump 240 capable of generating a second pump generation voltage VPASSPMP. Although not shown, the second pump generation voltage VPASSPMPmay have a voltage level of 25 V to 30 V. Unlike the first multi-stage voltage pump 282 and the second multi-stage voltage pump 292 described in Figures 4-5 Unlike the first multi-stage voltage pump 282 and the second multi-stage voltage pump 292 described in

[0134] According to an embodiment, the voltage generation circuit can include a first voltage regulator 276 and a second voltage regulator 278 configured to maintain and output the first pump generation voltage VPEPMPoutput from the third multi-stage voltage pump 250 within a preset range. Further, the voltage generation circuit can include a third voltage regulator 272 and a fourth voltage regulator 274 configured to maintain and output the second pump generation voltage VPASSPMPoutput from the fourth multi-stage voltage pump 240 within a preset range. Figure 6 The first to fourth voltage regulators 276, 278, 272, 274 shown can correspond to Figure 4 and Figure 5 the first to fourth voltage regulators 284, 286, 294, 296 shown.

[0135] As described with reference to Figure 1 , the voltage level of the second supply voltage VPPmay be twice or more higher than the voltage level of the first supply voltage VCC. For example, the second supply voltage VPPmay have a voltage level of 11 V to 13 V, and the first supply voltage VCCmay have a voltage level of 2.0 V to 2.5 V. As described above, as the voltage level difference between the input terminal and the output terminal of the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 increases, the preparation time or setup time (standby period) of the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 can increase. Figure 6The third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 described in the middle receive the second supply voltage VPP of which the voltage level is 11V to 13V to output the first pump generation voltage VPEPMP and the second pump generation voltage VPASSPMP, so that the voltage level difference between the input terminal and the output terminal of the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 can be greatly reduced. Accordingly, the preparation time or the setup time (standby period) can be reduced.

[0136] When the second supply voltage VPP of which the voltage level is 11V to 13V is input to the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240, noise can be large. The noise of the supply voltage increases as the voltage level of the supply voltage increases. Since the voltage level of the second supply voltage VPP is twice or more higher than the voltage level of the first supply voltage VCC, the second supply voltage VPP can have a noise greater than the first supply voltage VCC. Accordingly, the voltage generation circuit can include a noise attenuation circuit 230 between the pin or the pad 298 supplied with the second supply voltage VPP and the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240.

[0137] The voltage generation circuit can be coupled to a second ground voltage node VSSI_VPP corresponding to the second supply voltage VPP. Herein, the second ground voltage node VSSI_VPP can be electrically isolated from a first ground voltage node VSSI_PERI corresponding to the first supply voltage VCC. Accordingly, elements or components in the circuit provided in the peripheral region of the memory device 150 and the memory die 200 can be prevented from being damaged, lost, or malfunctioning due to bounce or the like. In addition, according to an embodiment, in order to reduce the electrical load of the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240, the second ground voltage node VSSI_VPP can be set to a preset positive voltage in response to the second supply voltage VPP.

[0138] According to an embodiment, when the voltage level difference between the input terminal and the output terminal of the third multi-stage voltage pump 250 or the fourth multi-stage voltage pump 240 of the voltage generation circuit becomes smaller, the number of unit voltage pumps included in the third multi-stage voltage pump 250 or the fourth multi-stage voltage pump 240 can be reduced. When the number of unit voltage pumps is reduced, the amount of current consumed in the voltage generation circuit can be reduced, and the size (e.g., the area occupied in the chip) of the voltage generation circuit can also be reduced.

[0139] Further, the third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 in the voltage generation circuit are not coupled to the first supply voltage VCC and the first ground voltage node VSSI_PERI, but are coupled to the second supply voltage VPP and the second ground voltage node VSSI_VPP, so that additional switching components (e.g., refer to FIG. 1) can not be required. Figure 5The described switch 290). Further, the voltage generation circuit can not operationally affect other circuits disposed in a peripheral region of the memory device 150 or the memory die 200. The third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 are always connected to the pin or pad 298 that supplies the second power voltage VPP. The third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 can be directly connected to the pin or pad 298 without any switching component. Thus, the preparation time or setup time (standby period) can be advanced without skew or delayed latency due to the enable signal CE#. The third multi-stage voltage pump 250 and the fourth multi-stage voltage pump 240 can prepare the first pump generated voltage VPEPMP and the second pump generated voltage VPASSPMP in advance. In this case, the time required to generate the target voltage for the data input / output operation can be significantly reduced (i.e., refer to Figure 3 The described A1 segment).

[0140] Figure 7A And Figure 7B An example of a noise attenuation circuit according to an embodiment of the disclosure is shown.

[0141] Referring to Figure 7A And Figure 7B The noise attenuation circuit can be implemented in various circuits. For example, the noise attenuation circuit can include a low-pass filter 230A described in Figure 7A and a rectifier 230B described in Figure 7B Herein, the noise can include a drop or fluctuation of the second power voltage VPP. The low-pass filter 230A can include a resistor R and a capacitor C, and the rectifier 230B can include a diode and a capacitor C. The low-pass filter 230A and the rectifier 230B can remove or attenuate the noise in the input signal or input voltage Vin to generate the output signal or output voltage Vout.

[0142] Both the low-pass filter 230A and the rectifier 230B can attenuate the noise such as a drop of the second power voltage VPP. However, there is a difference between the low-pass filter 230A and the rectifier 230B when a ripple occurs in the input voltage. For example, the resistor R in the low-pass filter 230A can not block the current flowing in the opposite direction, but the diode in the rectifier 230B can block the current flowing in the opposite direction. Thus, according to an embodiment, in order to effectively cope with the ripple in the input voltage, Figure 6 The noise attenuation circuit 230 shown can include the rectifier 230B.

[0143] Figure 8 An example of a multi-stage voltage pump according to an embodiment of the disclosure is shown. Specifically, Figure 8 An example of a multi-stage voltage pump according to an embodiment of the disclosure is shown. Specifically,Figure 6 An internal configuration of the third multi-level voltage pump 250 is described. Referring to Figure 8 The multi-level voltage pump described can also be applied to the fourth multi-level voltage pump 240.

[0144] Referring to Figure 8 The third multi-level voltage pump 250 can include a plurality of unit voltage pumps 252, 254, 256. The plurality of unit voltage pumps 252, 254, 256 included in the third multi-level voltage pump 250 can be connected in series to each other to generate a target voltage having various voltage levels.

[0145] The second power supply voltage VPP can be applied to the noise attenuation circuit 230. The noise attenuation circuit 230 can attenuate noise of the second power supply voltage VPP to generate a second internal power supply voltage VPP_INT. Referring to Figure 6 and Figure 8 The second internal power supply voltage VPP_INT output from the noise attenuation circuit 230 is input to input terminals of the plurality of unit voltage pumps 252, 254, 256 included in the third multi-level voltage pump 250.

[0146] Referring to Figures 4-5 The first multi-level voltage pump 282 and the second multi-level voltage pump 292 described can receive the first power supply voltage VCC and output a target voltage having a level higher than that of the first power supply voltage VCC. However, when the second internal power supply voltage VPP_INT is applied to the input terminals of the plurality of unit voltage pumps 252, 254, 256 included in the third multi-level voltage pump 250, the input terminals and the output terminals of at least some of the unit voltage pumps included in the third multi-level voltage pump 250 can be floated or become 0 V. For example, when the target voltage output from the first multi-level voltage pump 282 and the second multi-level voltage pump 292 does not have a voltage level higher than the second power supply voltage VPP, the input terminals and the output terminals between at least some of the plurality of unit voltage pumps 252, 254, 256 can be floated or become 0 V.

[0147] To reduce current consumption and increase operation speed during operation, each of the cell voltage pumps 252, 254, 256 can include a low-voltage pass transistor. However, when the second power supply voltage VPP INT and the zero voltage 0V are applied to the input terminal and the output terminal of each of the cell voltage pumps 252, 254, 256, respectively, a voltage exceeding a breakdown voltage range of the low-voltage pass transistor included therein can be applied to the low-voltage pass transistor. The zero voltage 0V is an example of a voltage that can be applied to or maintained at the output terminal of the cell voltage pumps 252, 254, 256. Due to an operational skew of the transistor, the voltage on the output terminal of the cell voltage pumps 252, 254, 256 can leak into another component electrically coupled to the output terminal of the cell voltage pumps 252, 254, 256. Or, a voltage level on the output terminal can fluctuate to the output terminal of the cell voltage pumps 252, 254, 256. For example, the breakdown voltage of the low-voltage pass transistor can be about 3V to 5V. When a voltage exceeding the breakdown voltage range of the low-voltage pass transistor is applied, the low-voltage pass transistor can be damaged or destroyed. Thus, to ensure relaxation (e.g., to avoid a voltage interval or difference between the internal node of each cell voltage pump 252, 254, 256 and the input terminal or the output terminal (which is determined by the voltage applied to the input terminal or the output terminal of each cell voltage pump 252, 254, 256) exceeding the breakdown voltage range of the low-voltage pass transistor included in each of the cell voltage pumps 252, 254, 256), each diode 262, 264, 266 can be arranged in or coupled to the output terminal of each cell voltage pump 252, 254, 256. As shown in Figure 8 FIG. 6, an anode of each diode 262, 264, 266 can be coupled to the node of the second internal power supply voltage VPP INT, and a cathode of each diode 262, 264, 266 can be coupled between adjacent voltage pumps among the cell voltage pumps 252, 254, 256. To avoid a voltage difference caused by the voltage applied between the input terminal or the output terminal of each cell voltage pump 252, 254, 256 exceeding the breakdown voltage range of the low-voltage pass transistor, each diode 262, 264, 266 can maintain the voltage level of the input terminal and the output terminal of each of the cell voltage pumps 252, 254, 256 at a certain level.

[0148] Figure 9 A first example of a page buffer and a bus according to an embodiment of the disclosure is illustrated.

[0149] Referring to Figure 9 , referring to Figure 1The plurality of page buffers 322, 324, 326 comprised in the read / write circuit 320 in the memory die 200 described can be connected to a single data bus BUS. The read / write circuit 320 can be configured to detect data transferred through each bit line BL and store the sensed data in each of the page buffers 322, 324, 326. The data stored in the plurality of page buffers 322, 324, 326 can be transmitted to a data input / output device or a transmission device such as a serialization circuit or serializer through the single data bus BUS. Since the plurality of page buffers 322, 324, 326 are connected to the single data bus BUS, the plurality of page buffers 322, 324, 326 not only have to transmit data sequentially but also have an operating margin for data transmission, respectively. The operating margin of each page buffer 322, 324, 326 should not overlap to avoid a conflict between data transmitted from the plurality of page buffers 322, 324, 326. According to an embodiment, there is a time interval between the operating margins of adjacent page buffers. Thus, a page buffer transmission signal TRANPB applied to the plurality of page buffers 322, 324, 326 can have a plurality of enable sections for enabling each of the page buffers 322, 324, 326 and a disable section between the plurality of enable sections.

[0150] Figure 10 A second example of a page buffer and a bus according to another embodiment of the disclosure is illustrated.

[0151] Referring to Figure 9 and Figure 10 , Figure 10The plurality of page buffers 322, 324, 326 described above can be transmitted to a data input / output device through a plurality of buses BUS0 to BUS7, or a transmission device such as a serialization circuit or a serializer. In order for the plurality of page buffers 322, 324, 326 to sequentially transmit data, the page buffer transmission signal TRANPB can be sufficient to have a plurality of enable sections for sequentially enabling the plurality of page buffers 322, 324, 326, without a disable section. That is, the page buffer transmission signal TRANPB does not have any disable section between adjacent enable sections. Since data is transmitted individually through different data buses BUS0 to BUS7, each of which is connected to each of the plurality of page buffers 322, 324, 326, data does not overlap or collapse due to the different data buses BUS0 to BUS7. Therefore, a delay time (i.e., a disable section) is not necessary. As the number of buses increases, there can be a burden of arranging more wires in the memory die 200, but the time required for data transmission performed by the plurality of page buffers 322, 324, 326 can be reduced. Thus, the time taken for the operation (D1, D2 section) of transmitting data temporarily stored in the page buffer PB can be reduced, with reference to Figure 3 This is described.

[0152] As described above, the memory device according to the embodiment of the disclosure can improve a data input / output speed.

[0153] In addition, the embodiment of the disclosure can improve a data input / output speed of a nonvolatile memory device such as a flash memory, thereby replacing a storage class memory (SCM) requiring a faster operation speed, or providing a nonvolatile memory device suitable for a storage class memory (SCM) structure.

[0154] While the present teachings have been illustrated and described with respect to particular embodiments, it is not intended that the disclosure be limited to the details shown, since various modifications and changes can be made without departing from the spirit and scope of the disclosure as defined by the claims. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A voltage generation circuit comprising: a noise attenuation circuit that attenuates noise of a second supply voltage, a level of which is at least twice higher than a level of a first supply voltage, wherein the first supply voltage and the second supply voltage are input from an external device via different pins or pads, respectively; and a multi-stage voltage pump that receives the noise-attenuated second supply voltage from the noise attenuation circuit and generates at least one of a plurality of target voltages each having a different level, wherein the multi-stage voltage pump includes: a plurality of unit voltage pumps connected in series to each other and receiving the second supply voltage; and at least one diode including a cathode coupled between output terminals of adjacent unit voltage pumps among the plurality of unit voltage pumps and an input terminal, and an anode coupled to the second supply voltage, wherein the at least one diode maintains voltage levels on the output terminals and the input terminal of the adjacent unit voltage pumps to avoid applying a breakdown voltage of transistors included in the adjacent unit voltage pumps.

2. The voltage generation circuit of claim 1, wherein the noise attenuation circuit is always coupled to the pins or pads when the voltage generation circuit generates at least one of the plurality of target voltages.

3. The voltage generation circuit of claim 1, wherein the noise attenuation circuit includes a rectifier including a diode arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

4. The voltage generation circuit of claim 1, wherein the noise attenuation circuit includes a low-pass filter including a resistor arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

5. The voltage generation circuit of claim 1, wherein the plurality of target voltages include: a program voltage that programs a data item into a non-volatile memory cell; an erase voltage that erases the data item in the non-volatile memory cell; and a read voltage that reads the data item in the non-volatile memory cell.

6. A memory device comprising: a memory bank including a plurality of non-volatile memory cells; a voltage generation circuit that generates at least one of a plurality of target voltages used for inputting a data item to or outputting a data item from the memory bank; and a plurality of buffers that temporarily store the data item output from the memory bank or the data item to be input to the memory bank, wherein the voltage generation circuit includes: a noise attenuation circuit that attenuates noise of a second supply voltage, a level of which is at least twice higher than a level of a first supply voltage, wherein the first supply voltage and the second supply voltage are input from an external device via different pins or pads, respectively; and a multi-stage voltage pump that receives the noise-attenuated second supply voltage from the noise attenuation circuit and generates at least one of the plurality of target voltages each having a different level, wherein the multi-stage voltage pump includes: a plurality of unit voltage pumps connected in series to each other and receiving the second supply voltage; and at least one diode including a cathode coupled between output terminals of adjacent unit voltage pumps among the plurality of unit voltage pumps and an input terminal, and an anode coupled to the second supply voltage, wherein the at least one diode maintains voltage levels on the output terminals and the input terminal of the adjacent unit voltage pumps to avoid applying a breakdown voltage of transistors included in the adjacent unit voltage pumps. at least one diode including a cathode coupled between output terminals and input terminals of adjacent cell voltage pumps of the plurality of cell voltage pumps, and an anode coupled to the second supply voltage, wherein the at least one diode maintains voltage levels on the output terminals and input terminals of the adjacent cell voltage pumps to avoid breakdown voltage of transistors included in the adjacent cell voltage pumps.

7. The memory device of claim 6, wherein the noise attenuation circuit is always coupled to the pin or pad when the voltage generation circuit generates at least one of the plurality of target voltages.

8. The memory device of claim 6, wherein the noise attenuation circuit includes a rectifier including a diode arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

9. The memory device of claim 6, wherein the noise attenuation circuit includes a low pass filter including a resistor arranged between an input terminal and an output terminal and a capacitor coupled to the output terminal.

10. The memory device of claim 6, wherein the plurality of target voltages include: a program voltage to program a data item into a non-volatile memory cell; an erase voltage to erase a data item in the non-volatile memory cell; and a read voltage to read a data item in the non-volatile memory cell.

11. The memory device of claim 6, wherein the plurality of buffers are coupled to the first supply voltage and a first ground voltage corresponding to the first supply voltage, the multi-stage voltage pump is coupled to the second supply voltage and a second ground voltage corresponding to the second supply voltage, and wherein a node of the first ground voltage is electrically isolated from a node of the second ground voltage.

12. The memory device of claim 6, wherein the plurality of buffers are coupled to respective bit lines of the memory bank, and wherein the plurality of buffers are coupled to respective buses to transfer data items output from the memory bank.

13. The memory device of claim 12, wherein the plurality of buffers are coupled to a data serializer via the respective buses, and the plurality of buffers transfer the data items via the respective buses without any latency.

14. A semiconductor device, comprising: a first pin or pad to receive a first supply voltage input from an external device; a second pin or pad to receive a second supply voltage input from an external device, wherein a level of the second supply voltage is at least two times higher than a level of the first supply voltage; a multi-stage voltage pump to receive the second supply voltage and to generate at least one of a plurality of target voltages, each target voltage having a different level; and a noise attenuation circuit arranged between the second pin or pad and the multi-stage voltage pump and to attenuate noise of the second supply voltage, wherein the multi-stage voltage pump includes: a plurality of cell voltage pumps connected in series to each other and to receive the noise-attenuated second supply voltage; ​ and at least one diode comprising a cathode coupled between output and input terminals of adjacent ones of the plurality of cell voltage pumps and an anode coupled to the second supply voltage, wherein the at least one diode maintains voltage levels on the output and input terminals of the adjacent ones of the plurality of cell voltage pumps to avoid breakdown voltage of transistors comprised in the adjacent ones of the plurality of cell voltage pumps.

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