Memory device repair method and system

Abstract

The present invention relates to a method and system for repairing a storage device. Among them, the method for repairing a storage device includes: performing error detection on the storage units of the storage device; temporarily storing the cell addresses of the detected error cells in a register until the number of detected error cells reaches a first preset number, where the error cells are damaged storage cells, one error cell occupies one register, and the cell address includes a row address; sequentially selecting a target register from each register; determining whether the row address in the target register exists in a reference storage module, where the reference storage module stores row addresses that have been repaired or row addresses that have not been repaired; and repairing the error cells that have not undergone row address repair according to the determination result. The present application can effectively prevent repair failure caused by different error cells simultaneously appearing on the same word line in the same storage area.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method and system for repairing a storage device. Background Art

[0002] In the repair of a storage device, in order to improve the detection efficiency, after storing the cell addresses of several error cells, the several error cells stored are usually repaired uniformly. In this way, when repairing, several error cells can be repaired at one time, thereby improving the repair efficiency.

[0003] However, in the actual repair process, there will be a phenomenon of repair failure when using this repair method. Summary of the Invention

[0004] Based on this, it is necessary to provide a method and device for repairing a storage device for the problem of repair failure in the repair of a storage device.

[0005] A method for repairing a storage device includes:

[0006] Performing error detection on the storage cells of the storage device;

[0007] Temporarily storing the cell addresses of the detected error cells in a register until the number of detected error cells reaches a first preset number. The error cells are damaged storage cells, and one error cell occupies one register. The cell address includes a row address;

[0008] Sequentially selecting a target register from each of the registers;

[0009] Determining whether the row address in the target register exists in a reference storage module, where the reference storage module stores row addresses that have been repaired or row addresses that have not been repaired;

[0010] Repairing the error cells that have not undergone row address repair according to the judgment result.

[0011] In one embodiment, the reference storage module stores row addresses that have been repaired. The repairing the error cells that have not undergone row address repair according to the judgment result includes:

[0012] If the row address in the target register exists in the reference storage module, skipping the repair of the error cell corresponding to the target register.

[0013] In one embodiment, the repairing the error cells that have not undergone row address repair according to the judgment result further includes:

[0014] If the row address in the target register does not exist in the reference storage module, repair the error cell corresponding to the target register.

[0015] In one embodiment,

[0016] The storage device includes a row repair unit, which includes a second preset number of row repair fuses, and one row repair fuse corresponds to one redundant row address;

[0017] The step of, if the row address in the target register does not exist in the reference storage module, repairing the error cell corresponding to the target register includes:

[0018] Store the row address in the target register into a blank row repair fuse of the row repair unit.

[0019] In one embodiment, the reference storage module includes the row repair unit.

[0020] In one embodiment, after repairing the error cells that have not undergone row address repair according to the judgment result, it further includes:

[0021] Empty the target register.

[0022] In one embodiment, after repairing the error cells that have not undergone row address repair according to the judgment result, it further includes:

[0023] When the row addresses in all registers are all repaired, empty all registers.

[0024] In one embodiment, the storage device repair method is applied to repair a storage device in which at least two of the error cells appear on the same word line.

[0025] A storage device repair system includes:

[0026] A detection module, configured to perform error detection on the storage cells of the storage device and output the cell address of the error cell, where the error cell is a damaged storage cell;

[0027] A register module, electrically connected to the detection module, includes a number of registers not less than a first preset number. Each register is configured to receive the cell address of the error cell and output the row address of the error cell. One error cell occupies one register, and the cell address includes a row address;

[0028] A control module, electrically connected to each of the registers, is configured to sequentially select a target register from each of the registers when the number of error cells detected by the detection module reaches a first preset number;

[0029] A reference storage module is configured to store and output repaired row addresses or unrepaired row addresses;

[0030] A first judgment module, electrically connected to the reference storage module and the register module, is configured to receive the row address output by the target register and the row address output by the reference storage module, and judge whether the row address in the target register exists in the reference storage module, and output a judgment result;

[0031] A repair module, electrically connected to the first judgment module, is configured to repair the error cells that have not undergone row address repair according to the judgment result.

[0032] In one embodiment, the control module includes a first control unit and n switch units, each switch unit corresponding to a register, and n is a positive integer greater than 1;

[0033] The first control unit inputs control signals S1 to Sn to the n switch units respectively. Among them, the control signal input by the first control unit to the kth switch unit is Sk, 1≤k≤n, and when any one of S1 to Sn is a high-level signal, the remaining control signals are low-level signals;

[0034] When the number of error cells detected by the detection module reaches the first preset number, the first control unit controls S1 to Sn to sequentially become high-level signals, thereby sequentially turning on the first switch unit to the nth switch unit, so that the registers corresponding to the first switch unit to the nth switch unit sequentially become target registers, and then are connected to the first judgment module.

[0035] In one embodiment, the reference storage module is configured to store repaired row addresses, and the repair module is further configured to skip repairing the error cells corresponding to the target register when the row address in the target register exists in the reference storage module.

[0036] In one embodiment, the first judgment module includes a comparator, and the comparator is configured to receive the row address output by the target register and the row address output by the reference storage module, compare the row address output by the target register and the row address output by the reference storage module, and when the row address output by the target register and the row address output by the reference storage module are inconsistent, output a preset level signal to the repair module to activate the repair module.

[0037] In one embodiment, the preset level signal is a high level signal.

[0038] In one embodiment,

[0039] The repair module includes a row repair unit and a second control unit. The row repair unit is electrically connected to each of the registers and is used to perform row address repair on the error unit corresponding to the target register.

[0040] The second control unit is electrically connected to the comparator and the row repair unit, and is used to switch the row repair unit according to the high level signal or the low level signal output by the comparator.

[0041] In one embodiment, the row repair unit includes a second preset number of row repair fuses. One row repair fuse corresponds to one redundant row address, and the row repair unit is used to store the row address in the target register to a blank row repair fuse in the row repair unit.

[0042] In one embodiment, the reference storage module includes the row repair unit.

[0043] In one embodiment, the storage device repair system is applied to repair a storage device in which at least two error units appear on the same word line.

[0044] In the above storage device repair method and system, when repairing the unit addresses of multiple error units uniformly, first store the unit addresses of each error unit in different registers, and then determine whether the addresses in each register are stored in the reference storage module, so as to further determine whether the error units corresponding to each register have undergone row address repair, so that only the error units that have not undergone row address repair can be repaired.

[0045] Therefore, even if different error units in each error unit in the same repair process appear on the same word line of the same storage bank, the word line will not be repaired repeatedly, thus effectively preventing repair failure. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1Flow chart of a storage device repair method provided in an embodiment;

[0048] Figure 2 Flow chart of a storage device repair method provided in another embodiment;

[0049] Figure 3 Flow chart of a storage device repair method provided in yet another embodiment;

[0050] Figure 4 Schematic diagram of the module structure of a storage device repair system provided in an embodiment. Detailed implementation manners

[0051] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be referred to as the second element, component, region, layer or part; for example, the first judgment module can be referred to as the second judgment module, and similarly, the second judgment module can be referred to as the first judgment module; the first judgment module and the second judgment module are different judgment modules.

[0054] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from being present or added. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0055] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, for the "connection" in the following embodiments, if there is a transfer of electrical signals or data between the connected objects, it should be understood as "electrically connected", "communicatively connected", etc.

[0056] As described in the background art, in the repair of storage devices, in order to improve the detection efficiency, several error cells stored are often repaired uniformly after the cell addresses of several error cells are stored. In this way, when repairing, several error cells can be repaired at one time, thereby improving the repair efficiency. However, in the actual repair process, there will be a phenomenon of repair failure when using this repair method.

[0057] The inventors have found through research that one of the reasons for the repair failure phenomenon is that when different error cells appear on the same word line in the same memory bank at the same time, this word line will be repaired several times repeatedly, resulting in the failure of the entire repair. For example, if two error cells are detected to appear on the same word line, and if we do not identify them, the row address A of this word line will be stored in two row repair fuses, corresponding to two redundant word lines. Then when we read and write, if the read and write address is A, two redundant word lines will be opened at the same time, and then the read and write will be incorrect.

[0058] For the above reasons, the present application provides a storage device repair method and system. The storage device repair method and storage device repair system provided by the present application can be applied to repair a storage device in which at least two error cells appear on the same word line.

[0059] In one embodiment, please refer to Figure 1 , a storage device repair method is provided, including the following steps:

[0060] Step S100, performing error detection on the storage units of the storage device;

[0061] Step S200, temporarily store the cell address of the detected error cell into a register until the number of detected error cells reaches a first preset number. The error cell is a damaged storage cell, and one error cell occupies one register. The cell address includes a row address;

[0062] Step S300, sequentially select a target register from each register;

[0063] Step S400, determine whether the row address in the target register exists in the reference storage module. The reference storage module stores either the row addresses that have been repaired or the row addresses that have not been repaired;

[0064] Step S500, according to the judgment result, repair the error cells that have not undergone row address repair.

[0065] In step S100, the storage device includes a plurality of storage cells arranged in multiple rows and columns. At the same time, the storage device includes multiple word lines. Each word line provides a gate voltage for multiple storage cells located in the same row to control the reading and writing of data to the storage cells.

[0066] Each storage cell can store data 0 or 1. When the storage cell is damaged, it cannot perform normal reading and writing.

[0067] Perform error detection on the storage cells of the storage device, that is, detect whether each storage cell of the storage device is damaged.

[0068] In step S200, every time an error cell is detected, temporarily store the cell address of this error cell into a register. The cell address of one error cell occupies one register, and the cell addresses of different error cells are temporarily stored into different registers. When the number of detected error cells reaches the first preset number, suspend the detection.

[0069] The first preset number can be set according to actual needs, and it can be set to be the same as the number of registers in the repair system used for repair.

[0070] In step S300, select a target register among each register. The target register is the register that stores the cell address of the storage cell to be repaired currently. The row address in the target register is the row address to be repaired currently.

[0071] In step S400, the reference storage module stores either the row addresses that have been repaired or the row addresses that have not been repaired.

[0072] The row addresses that have been repaired are the row addresses of the storage cells that have undergone row address repair. The row addresses that have not been repaired are the row addresses of the storage cells that have not undergone row address repair.

[0073] By determining whether the row address in the target register exists in the reference storage module, it is possible to obtain whether the row address repair has been performed on the error cell corresponding to the target register.

[0074] In step S500, if the reference storage module stores a row address that has been repaired, when the judgment result is that the row address in the target register exists in the reference storage module, the error cell corresponding to the target register is not repaired; when the judgment result is that the row address in the target register does not exist in the reference storage module, the error cell corresponding to the target register is repaired.

[0075] If the reference storage module stores a row address that has not been repaired, when the judgment result is that the row address in the target register exists in the reference storage module, the error cell corresponding to the target register is repaired; when the judgment result is that the row address in the target register does not exist in the reference storage module, the error cell corresponding to the target register is not repaired.

[0076] In this embodiment, when the cell addresses of multiple error cells are repaired uniformly, first, the cell addresses of each error cell are stored in different registers, and then it is determined whether the addresses in each register are stored in the reference storage module, so as to determine whether the row address repair has been performed on the error cell corresponding to each register, and thus only the error cells that have not undergone row address repair can be repaired.

[0077] Therefore, even if different error cells in the same repair process appear on the same word line of the same storage area (bank) at the same time, the word line will not be repaired repeatedly, thus effectively preventing repair failure.

[0078] It can be understood that the row addresses stored in the reference storage module change gradually during the repair process. If the reference storage module stores a row address that has been repaired, after a row address repair is performed on an error cell, its row address is stored in the reference storage module. If the reference storage module stores a row address that has not been repaired, after a row address repair is performed on an error cell, its row address is removed from the reference storage module.

[0079] In one embodiment, the reference storage module stores a row address that has been repaired. At this time, before the repair, the reference storage module may not store anything. During the repair process, the stored row addresses in the reference storage module gradually increase, thereby effectively reducing the system memory and improving the repair efficiency.

[0080] At this time, step S500 includes:

[0081] Step S510, if the row address in the target register exists in the reference storage module, skip the repair of the faulty cell corresponding to the target register.

[0082] Skipping the repair of the faulty cell corresponding to the target register means skipping the current target register and automatically selecting and judging the next target register, etc.

[0083] Further, step S500 further includes:

[0084] Step S520, if the row address in the target register does not exist in the reference storage module, repair the faulty cell corresponding to the target register.

[0085] In one embodiment, the storage device includes a row repair unit. The row repair unit, that is, the circuit unit for repairing the row address of the faulty cell, includes a second preset number of row repair fuses. The second preset number can be set according to actual requirements.

[0086] The row repair fuses are used to receive and store the row addresses of the faulty cells. One row repair fuse corresponds to one redundant row address. One redundant row address corresponds to one redundant word line.

[0087] After the row address A1 of a faulty cell C1 is stored in a row repair fuse F1, the word line W1 corresponding to the faulty cell C1 will be replaced by the redundant word line WF1 corresponding to this row repair fuse F1, thereby completing the row address repair of the faulty cell C1.

[0088] Thereafter, when reading and writing the storage device, if the row address of the storage cell being read and written is A1, turn on the redundant word line WF1 and turn off the word line W1.

[0089] At this time, step S520 includes: step S522, storing the row address in the target register into a blank row repair fuse of the row repair unit.

[0090] The row address in the target register is the row address of the faulty cell corresponding to this register. Storing it into a blank row repair fuse of the row repair unit can complete the row address repair of the faulty cell corresponding to this register.

[0091] It can be understood that a "blank row repair fuse" is a row repair fuse that has not stored the row address of a storage cell.

[0092] In one embodiment, the reference storage module includes a row repair unit. Since the row address of the error cell is stored during the repair process by the row repair unit, the reference storage module includes a row repair unit, such that the row repair unit is used, on the one hand, to repair the row address of the error cell, and on the other hand, to determine whether the row address of the error cell to be repaired has been repaired, thereby effectively utilizing the row repair unit and saving system storage space.

[0093] Moreover, at this time, there is no need to separately store the row address of the error cell, thereby effectively improving the repair efficiency.

[0094] In addition, in some embodiments, before step S522, it further includes:

[0095] Step S521, determining whether there is a blank row repair fuse in the row repair unit.

[0096] If there is a blank row repair fuse in the row repair unit, then step S522 is performed to store the row address in the target register into a blank row repair fuse of the row repair unit.

[0097] In addition, the cell address stored in the register may further include a column address.

[0098] At this time, if there is no blank row repair fuse in the row repair unit, then step S523 can be performed to repair the column address of the error cell corresponding to the target register.

[0099] The column address repair can be implemented through a column repair fuse, similar to that the row address repair can be implemented through a row repair fuse in the foregoing (step S522).

[0100] In one embodiment, after step S500, it further includes:

[0101] Step S600, clearing the target register.

[0102] That is, after the relevant processing of one target register is completed, the target register is cleared. When all registers are successively selected as target registers and relevant processing is performed, all registers are cleared. Therefore, when one repair is completed, all registers are cleared, so that they can be used again for the next repair.

[0103] Therefore, this embodiment can effectively improve the utilization rate of the registers.

[0104] In this embodiment, after applying one register, the register is cleared. Of course, the present application is not limited thereto.

[0105] In another embodiment, after step S500, it further includes:

[0106] Step S700: After the row addresses in all registers are repaired, clear all registers.

[0107] Specifically, when the row address in a register has not been repaired, repair the row address to complete the repair of the row address in the register.

[0108] When the row address in a register has been repaired, the repair of the row address in the register has been completed, and it will not be repaired again.

[0109] In this embodiment, during a repair process, after all registers are used, clear all registers uniformly. At this time, each register can be used again for the next repair, thereby effectively improving the utilization rate of the registers.

[0110] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0111] In one embodiment, a storage device repair system is further provided, including a detection module 100, a register module 200, a control module 300, a reference storage module 400, a first judgment module 500, and a repair module 600.

[0112] The detection module 100 is used to detect errors in the storage units of the storage device and output the unit addresses of the error units. The error units are damaged storage units.

[0113] The register module 200 is electrically connected to the detection module 100 and includes no less than a first preset number of registers 210. Specifically, the number of registers 210 can be the same as the first preset number, thereby improving the register utilization rate.

[0114] Each register 210 is used to receive and temporarily store the unit addresses of the error units and output the row addresses in the unit addresses of the error units. One error unit occupies one register, and the unit address includes a row address.

[0115] The control module 300 is electrically connected to each register 210 and is configured to sequentially select a target register from each register when the number of error cells detected by the detection module 100 reaches a first preset number.

[0116] The reference storage module 400 is configured to store and output the row addresses that have been repaired or the row addresses that have not been repaired.

[0117] The first judgment module 500 is electrically connected to the reference storage module 400 and the register module 200, and is configured to receive the row address output by the target register 210 and the row address output by the reference storage module 400, and judge whether the row address in the target register exists in the reference storage module, and output a judgment result.

[0118] As an example, the control module 300 may include switch units 310 that are equal in number to the registers 210 in the register module 200. The first judgment module 500 may be electrically connected to each register 210 through the respective switch units 310 of the control module 300. When the corresponding switch unit in the control module 300 is turned on, the first judgment module 500 is connected to the target register.

[0119] Specifically, please refer to Figure 4 , the control module 300 may include a first control unit 320 and n switch units 310, each switch unit 310 corresponding to a register 210, and n being a positive integer greater than 1.

[0120] The first control unit 320 inputs control signals S1 to Sn to the n switch units 310 respectively. Among them, the control signal input by the first control unit 320 to the kth switch unit 310 is Sk, where 1 ≤ k ≤ n. And when any one of S1 to Sn is a high-level signal, the remaining control signals are low-level signals.

[0121] When the number of error cells detected by the detection module 100 reaches the first preset number, the first control unit 320 controls S1 to Sn to sequentially become high-level signals, thereby sequentially turning on the first switch unit to the nth switch unit, and further making the registers corresponding to the first switch unit to the nth switch unit sequentially become the target registers and connected to the first judgment module 500.

[0122] More specifically, as an example, the switch unit 310 may include a transmission gate 311 and an inverter 312. The transmission gate 311 may be composed of a PMOS transistor and an NMOS transistor connected in parallel. The gate terminal of the NMOS transistor and the input terminal of the inverter 312 may receive the control signal of the first control unit 320. At the same time, the output terminal of the inverter 312 may be connected to the gate terminal of the PMOS transistor.

[0123] The way for the first control unit 320 to control the k-th switch unit 310 to turn on can be as follows:

[0124] The control signal Sk input by the first control unit 320 to the k-th switch unit 310 is a high-level signal, and the NMOS transistor receives this high-level signal. At the same time, the inverter 312 receives the high-level signal and converts the high-level signal into a low-level signal and outputs it to the PMOS transistor. Therefore, at least one of the NMOS transistor and the PMOS transistor will conduct at this time, so that the switch unit 310 is turned on.

[0125] When the control signal Sk input by the first control unit 320 to the k-th switch unit 310 is a low-level signal, the NMOS transistor receives this low-level signal. At the same time, the inverter 312 receives the low-level signal and converts the low-level signal into a high-level signal and outputs it to the PMOS transistor. Therefore, at this time, both the NMOS transistor and the PMOS transistor are turned off, so that the switch unit 310 is turned off.

[0126] The repair module 600 is electrically connected to the first judgment module 500 and is used to repair the error cells that have not undergone row address repair according to the judgment result.

[0127] In this embodiment, under the control of the control module 300, the first judgment module 500 sequentially judges whether the row addresses of the error cells to be repaired stored in each register 210 are stored in the reference storage module 400, and then can judge whether the error cells corresponding to each register have undergone row address repair, so that only the error cells that have not undergone row address repair can be repaired.

[0128] Therefore, even if different error cells among the error cells in the same repair process appear on the same word line of the same storage area (bank) at the same time, the word line will not be repaired repeatedly, so that repair failure can be effectively prevented.

[0129] In one embodiment, the reference storage module 400 is used to store the row addresses that have been repaired. The repair module 600 is further used to skip the repair of the error cells corresponding to the target register when the row address in the target register exists in the reference storage module 400.

[0130] In one embodiment, on the basis of the above embodiment, the first judgment module 500 includes a comparator 510. The comparator 510 is used to receive the row address output by the target register 210 and the row address output by the reference storage module 400, compare the row address output by the target register 210 and the row address output by the reference storage module 400, and when the row address output by the target register and the row address output by the reference storage module are inconsistent, output a preset level signal to the repair module 600 to turn on the repair module 600.

[0131] As an example, the preset level signal may be a high level signal.

[0132] If the row address output by the target register is inconsistent with the row address output by the reference memory module 400, it indicates that the error cell corresponding to the target register 210 has not been repaired for the row address. At this time, the comparator 510 outputs a high level signal to turn on the repair module 600, and the error cell corresponding to the target register can be repaired.

[0133] When they are consistent, it indicates that the error cell corresponding to the target register 210 has been repaired for the row address. At this time, the comparator 510 can output a low level signal, and thus the repair module 600 is not turned on.

[0134] It can be understood that when there are multiple row addresses stored in the reference memory module 400, the comparator 510 sequentially compares whether the row address output by the target register 210 is consistent with each row address stored in the reference memory module 400.

[0135] In one embodiment, the repair module 600 includes a row repair unit 610 and a second control unit 620. The row repair unit 610 is electrically connected to each register 210 and is used to repair the row address of the error cell corresponding to the target register. The second control unit 620 is electrically connected to the comparator 510 and the row repair unit 610, and is used to switch the row repair unit according to the high level signal or low level signal output by the comparator 510.

[0136] As an example, the second control unit 620 may include switching devices such as switching transistors. When receiving the high level signal output by the comparator 510, the switching devices such as switching transistors are turned on to turn on the row repair unit 610, so as to repair the row address of the error cell corresponding to the target register. When receiving the low level signal output by the comparator 510, the switching devices such as switching transistors are turned off to turn off the row repair unit, skipping the repair of the error cell corresponding to the target register or terminating the current repair.

[0137] Specifically, the repair module 600 can be electrically connected to each register 210 through the respective switching units 310 of the control module 300 together with the first determination module 500.

[0138] As an example, as described above, the control module 300 may include a first control unit 320 and n switching units 310, each switching unit 310 corresponding to a register 210, and n is a positive integer greater than 1.

[0139] The first control unit 320 inputs control signals S1 to Sn to the n switch units 310 respectively. Among them, the control signal input by the first control unit 320 to the k-th switch unit 310 is Sk, where 1 ≤ k ≤ n. And when any one of S1 to Sn is a high-level signal, the remaining control signals are low-level signals.

[0140] When the number of error units detected by the detection module 100 reaches the first preset number, the first control unit 320 controls S1 to Sn to become high-level signals in sequence, and then sequentially opens the first switch unit to the n-th switch unit, so that the registers corresponding to the first switch unit to the n-th switch unit become target registers in sequence.

[0141] For the target register, when it becomes the target register, the corresponding switch unit 310 is open. Therefore, the row address in the target register can be transmitted to the first judgment module 500 and the repair module 600.

[0142] At this time, the comparator 510 of the first judgment module 500 can directly obtain the row address in the target register, compare it with the row address output by the reference storage module 400, and output a level signal according to the comparison result.

[0143] When the level signal output by the comparator 510 is a preset level signal to open the second control unit 620, the row repair unit 610 receives and stores the row address in the target register, so that the row address in the target register can be stored in the row repair unit 610 for repair.

[0144] In one embodiment, the row repair unit 610 includes a second preset number of row repair fuses, and one row repair fuse corresponds to one redundant row address. The row repair unit 610 is used to store the row address in the target register in a blank row repair fuse of the row repair unit.

[0145] Further, at this time, the reference storage module 400 includes the row repair unit 610.

[0146] In addition, in some embodiments, the storage device repair system may further include a second judgment module (not shown), and the second judgment module is used to judge whether there is a blank row repair fuse in the row repair unit 610.

[0147] At this time, the second control unit 620 can turn on the row repair unit when the row address in the target register does not exist in the reference storage module 400 and there is a blank row repair fuse in the row repair unit 610.

[0148] Meanwhile, the cell address may further include a column address. The repair module 600 further includes a column repair unit (not shown), and the column repair unit is configured to perform column address repair on the error cells corresponding to the target register.

[0149] The second control unit may activate the column repair unit when the row address in the target register does not exist in the reference storage module, but there is no blank row repair fuse in the row repair unit.

[0150] For the specific limitations of the storage device repair system, reference may be made to the limitations on the storage device repair method described above, which will not be elaborated here. Each module in the above storage device repair system can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0151] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0152] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for repairing a storage device, characterized in that, Including: Performing error detection on the memory cells of the memory device; Temporarily storing the cell addresses of the detected error cells in a register until the number of the detected error cells reaches a first preset number, where the error cells are damaged memory cells, one error cell occupies one register, and each register corresponds to a switch unit, and the cell address includes a row address; Selecting target registers in sequence among the registers in the following manner: when the number of the detected error cells reaches the first preset number, controlling the first preset number of switch units to be turned on in sequence so that the corresponding registers become target registers in sequence; Judging whether the row address in the target register exists in a reference memory module, where the reference memory module stores row addresses that have been repaired or row addresses that have not been repaired; Repairing the error cells that have not undergone row address repair according to the judgment result.

2. The storage device repair method according to claim 1, wherein The reference memory module stores row addresses that have been repaired, and the repairing the error cells that have not undergone row address repair according to the judgment result includes: If the row address in the target register exists in the reference memory module, skipping the repair of the error cell corresponding to the target register.

3. The storage device repair method according to claim 2, wherein The repairing the error cells that have not undergone row address repair according to the judgment result further includes: If the row address in the target register does not exist in the reference memory module, repairing the error cell corresponding to the target register.

4. The memory device repair method according to claim 3, wherein The memory device includes a row repair unit, and the row repair unit includes a second preset number of row repair fuses, and one row repair fuse corresponds to one redundant row address; The if the row address in the target register does not exist in the reference memory module, repairing the error cell corresponding to the target register includes: Storing the row address in the target register in a blank row repair fuse of the row repair unit.

5. The storage device repair method according to claim 4, wherein, The reference memory module includes the row repair unit.

6. The storage device repair method according to claim 1, wherein After the repairing the error cells that have not undergone row address repair according to the judgment result, it further includes: Clearing the target register.

7. The storage device repair method according to claim 1, wherein, After the repairing the error cells that have not undergone row address repair according to the judgment result, it further includes: When the row addresses in all registers have been repaired, clearing all registers.

8. The storage device repair method according to claim 1, wherein The memory device repair method is applied to repair a memory device in which at least two error cells appear on the same word line.

9. A storage device repair system, characterized in that, Including: A detection module, configured to perform error detection on the memory cells of the memory device and output the cell addresses of the error cells, where the error cells are damaged memory cells; A register module, electrically connected to the detection module, includes a number of registers not less than the first preset number, and each register is configured to receive the cell addresses of the error cells and output the row addresses of the error cells, one error cell occupies one register, and the cell address includes a row address; A control module, electrically connected to each of the registers, is configured to sequentially select a target register from each of the registers when the number of error cells detected by the detection module reaches a first preset number; A reference storage module is configured to store and output repaired row addresses or unrepaired row addresses; A first judgment module, electrically connected to the reference storage module and the register module, is configured to receive the row address output by the target register and the row address output by the reference storage module, and judge whether the row address in the target register exists in the reference storage module, and output a judgment result; A repair module, electrically connected to the first judgment module, is configured to repair the error cells that have not undergone row address repair according to the judgment result; The control module includes a first control unit and n switch units, each switch unit corresponding to one of the registers, where n is a positive integer greater than 1; The first control unit inputs control signals S1 to Sn to the n switch units respectively. Among them, the control signal input by the first control unit to the k-th switch unit is Sk, 1≤k≤n, and when any one of S1 to Sn is a high-level signal, the remaining control signals are low-level signals; When the number of error cells detected by the detection module reaches the first preset number, the first control unit controls S1 to Sn to sequentially become high-level signals, thereby sequentially turning on the first switch unit to the n-th switch unit, so that the registers corresponding to the first switch unit to the n-th switch unit sequentially become target registers and are then connected to the first judgment module.

10. The storage device repair system according to claim 9, wherein The reference storage module is configured to store repaired row addresses, and the repair module is further configured to skip repairing the error cells corresponding to the target register when the row address in the target register exists in the reference storage module.

11. The storage device repair system according to claim 10, wherein The first judgment module includes a comparator, which is configured to receive the row address output by the target register and the row address output by the reference storage module, compare the row address output by the target register and the row address output by the reference storage module, and when the row address output by the target register is inconsistent with the row address output by the reference storage module, output a preset level signal to the repair module to turn on the repair module.

12. The storage device repair system according to claim 11, characterized in that, The preset level signal is a high-level signal.

13. The storage device repair system according to claim 11, wherein The repair module includes a row repair unit and a second control unit. The row repair unit is electrically connected to each of the registers and is configured to perform row address repair on the error cells corresponding to the target register; The second control unit is electrically connected to the comparator and the row repair unit and is configured to switch the row repair unit according to the high-level signal or low-level signal output by the comparator.

14. The storage device repair system according to claim 13, wherein The row repair unit includes a second preset number of row repair fuses, and one row repair fuse corresponds to one redundant row address. The row repair unit is configured to store the row address in the target register into a blank row repair fuse of the row repair unit.

15. The storage device repair system according to claim 14, characterized in that, The reference storage module includes the row repair unit.

16. The storage device repair system according to claim 9, characterized in that, The storage device repair system is applied to repair a storage device in which at least two of the error cells appear on the same word line.

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