A MOSFET device and method of fabrication thereof

Abstract

The application provides a MOSFET device and a manufacturing method thereof, which comprises the following steps: etching a silicon substrate by using a first etching condition to obtain a first groove; etching the silicon substrate by using a second etching condition to obtain a second groove; the angle between the sidewall of the first groove and the normal line of the silicon substrate is smaller than the angle between the sidewall of the second groove and the normal line of the silicon substrate; etching the silicon substrate by using a third etching condition to obtain an isolation groove; the isolation groove divides the silicon substrate to obtain an active region under a hard mask layer; the active region comprises a main body part and a cap layer above the main body part; the width of the cap layer is smaller than the width of the main body part; the top corner of the main body part is a rounded corner; a subsequent gate medium layer is obtained by oxidizing the cap layer; and in the process, the top corner of the main body part of the active region is protected by the isolation medium layer and cannot be consumed, which is beneficial to reduce the parasitic effect on the MOSFET device, avoid the double-peak effect, and finally improve the electrical performance of the MOSFET device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuits, and relates to a MOSFET device and a manufacturing method thereof. BACKGROUND

[0002] The morphology at the active area corner (AA corner) is very important for the electrical performance of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Since the polysilicon is closely attached to the active area corner, too sharp a corner will cause the gate to turn on too early, resulting in a double-hump phenomenon in the Id-Vg curve (drain current-gate voltage curve) and poor electrical performance of the device. In order to improve the electrical performance of the device, a more rounded corner is pursued in process development, i.e. the active area corner rounding technology

[0003] The existing technology ignores the consumption of silicon in subsequent processes and does not protect the active area corner after the active area etching step completes the active area corner rounding effect, which greatly reduces the effect of the active area corner rounding after the gate oxide layer is formed, and even completely invalidates the effect.

[0004] Therefore, how to improve the active area corner rounding process so that the active area corner can remain in a rounded state in subsequent processes has become an important technical problem to be solved by those skilled in the art. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a MOSFET device and a manufacturing method thereof, which are used to solve the problem that the gate turns on too early due to the insufficient rounding of the top corner of the active area, resulting in a double-hump phenomenon in the Id-Vg curve.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a MOSFET device, comprising the following steps:

[0007] A silicon substrate is provided, a pad oxide layer, a hard mask layer and a photoresist layer are formed on the silicon substrate in sequence, and the photoresist layer is patterned;

[0008] The hard mask layer and the pad oxide layer are etched based on the patterned photoresist layer to expose the silicon substrate;

[0009] The silicon substrate is etched using the hard mask layer as a mask and a first etching condition to obtain a first trench, the first trench extending from the top surface of the silicon substrate to a first depth;

[0010] etching the silicon substrate using a second etching condition different from the first etching condition to obtain a second trench, the second trench extending from a bottom surface of the first trench to a second depth, an angle between a sidewall of the first trench close to the hard mask layer and a normal of the silicon substrate being smaller than an angle between a sidewall of the second trench close to the hard mask layer and the normal of the silicon substrate;

[0011] etching the silicon substrate using a third etching condition to obtain an isolation trench, the isolation trench dividing the active region located under the hard mask layer into a main body and a cap layer located above the main body, a width of the cap layer being smaller than a width of the main body, a top corner of the main body being a rounded corner;

[0012] forming an isolation dielectric layer to fill the isolation trench, and thinning the isolation dielectric layer to expose the hard mask layer;

[0013] removing the hard mask layer and the liner oxide layer to expose the cap layer, the top corner of the main body still being covered by the isolation dielectric layer;

[0014] oxidizing the cap layer to obtain a gate dielectric layer.

[0015] Optionally, the angle between the sidewall of the first trench close to the hard mask layer and the normal of the silicon substrate ranges from 0 to 10 degrees.

[0016] Optionally, the method of etching the silicon substrate using the first etching condition to obtain the first trench comprises dry etching, and the method of etching the silicon substrate using the second etching condition different from the first etching condition to obtain the second trench comprises dry etching.

[0017] Optionally, a dry etching by-product generation rate under the first etching condition is smaller than a dry etching by-product generation rate under the second etching condition.

[0018] Optionally, the dry etching gas used in the first etching condition and the dry etching gas used in the second etching condition both comprise Cl2 and O2, and a proportion of Cl2 in the first etching condition is higher than a proportion of Cl2 in the second etching condition.

[0019] Optionally, the hard mask layer comprises a silicon nitride layer.

[0020] Optionally, the etching the hard mask layer based on the patterned photoresist layer comprises a main etching stage and an over-etching stage; the etching method adopted in the main etching stage comprises dry etching, and the etching gas comprises He, O2, HBr and CF4; the etching method adopted in the over-etching stage comprises dry etching, and the etching gas comprises CF4 and CH2F2.

[0021] Optionally, the thickness of the gate dielectric layer ranges from 110 angstroms to 120 angstroms.

[0022] Optionally, the isolation dielectric layer comprises a liner oxide layer formed by thermal oxidation and a bulk oxide layer formed by high-density plasma-enhanced chemical vapor deposition.

[0023] The application further provides a MOSFET device manufactured by the method.

[0024] As described above, the method for manufacturing a MOSFET device of the application first etches the silicon substrate by using a first etching condition to obtain a first trench, then etches the silicon substrate by using a second etching condition different from the first etching condition to obtain a second trench, the angle between the sidewall of the side of the first trench close to the hard mask layer and the normal line of the silicon substrate is smaller than the angle between the sidewall of the side of the second trench close to the hard mask layer and the normal line of the silicon substrate, and then etches the silicon substrate by using a third etching condition to obtain an isolation trench, which divides the active region located below the hard mask layer in the silicon substrate, the active region comprises a bulk part and a cap layer located above the bulk part, the width of the cap layer is smaller than the width of the bulk part, and the top corner of the bulk part is a rounded corner. In the subsequent process, the gate dielectric layer is obtained by oxidizing the cap layer above the bulk part of the active region. In the process of forming the gate dielectric layer, the top corner of the bulk part of the active region is protected by the isolation dielectric layer and will not be consumed, which is beneficial to reduce the parasitic effect on the MOSFET device, avoid the occurrence of double-peak effect, and finally improve the electrical performance of the MOSFET device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic view showing the sequential formation of a liner oxide layer, a silicon nitride hard mask layer and a photoresist layer on a silicon substrate in the manufacturing process of a MOSFET device, and the patterning of the photoresist layer.

[0026] Figure 2 A schematic view showing the etching of a silicon nitride hard mask layer and a liner oxide layer based on a patterned photoresist layer to expose a silicon substrate in the manufacturing process of a MOSFET device, and the formation of a trapezoidal silicon shoulder on the top of an active region.

[0027] Figure 3A schematic view showing etching of a silicon substrate to form an isolation trench in the silicon substrate during fabrication of a MOSFET device.

[0028] Figure 4 A schematic view showing deposition of an isolation dielectric layer to fill the isolation trench and planarization of the isolation dielectric layer during fabrication of a MOSFET device.

[0029] Figure 5 A schematic view showing removal of a silicon nitride hard mask layer and excess oxide layer to expose a top surface of an active region during fabrication of a MOSFET device.

[0030] Figure 6 A schematic view showing oxidation of a surface of the active region to form a gate oxide layer during fabrication of a MOSFET device.

[0031] Figure 7 A schematic view showing formation of a pad oxide layer, a hard mask layer and a photoresist layer on a silicon substrate and patterning of the photoresist layer during fabrication of a MOSFET device according to the present application.

[0032] Figure 8 A schematic view showing etching of the hard mask layer and the pad oxide layer to expose the silicon substrate during fabrication of a MOSFET device according to the present application.

[0033] Figure 9 A schematic view showing etching of the silicon substrate using a first etching condition to obtain a first trench during fabrication of a MOSFET device according to the present application.

[0034] Figure 10 A schematic view showing etching of the silicon substrate using a second etching condition to obtain a second trench during fabrication of a MOSFET device according to the present application.

[0035] Figure 11 A schematic view showing etching of the silicon substrate using a third etching condition to obtain an isolation trench during fabrication of a MOSFET device according to the present application.

[0036] Figure 12 A schematic view showing formation of an isolation dielectric layer to fill the isolation trench during fabrication of a MOSFET device according to the present application.

[0037] Figure 13 A schematic view showing removal of the hard mask layer and the pad oxide layer to expose a cap layer during fabrication of a MOSFET device according to the present application.

[0038] Figure 14 A schematic view showing oxidation of the cap layer to obtain a gate dielectric layer during fabrication of a MOSFET device according to the present application.

[0039] Element Number Description

[0040] 101 silicon substrate

[0041] 102 liner oxide layer

[0042] 103 silicon nitride hard mask layer

[0043] 104 photoresist layer

[0044] 105 trapezoidal silicon shoulder

[0045] 106 isolation trench

[0046] 107 isolation dielectric layer

[0047] 108 gate oxide layer

[0048] 201 silicon substrate

[0049] 202 liner oxide layer

[0050] 203 hard mask layer

[0051] 204 photoresist layer

[0052] 205 first trench

[0053] 206 second trench

[0054] 207 isolation trench

[0055] 208 body portion

[0056] 209 cap layer

[0057] 210 isolation dielectric layer

[0058] 211 gate dielectric layer

[0059] A first depth

[0060] B second depth DETAILED DESCRIPTION

[0061] The present application is herein described, by way of example only, with the

[0062] Reference will now be made to the drawings, wherein Figures 1 to 14It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] The fabrication process of a MOSFET device includes the following steps:

[0064] like Figure 1 As shown, a silicon substrate 101 is provided, and a pad oxide layer 102, a silicon nitride hard mask layer 103 and a photoresist layer 104 are sequentially formed on the silicon substrate 101. The photoresist layer 104 is patterned by photolithography processes such as exposure and development, and the patterned photoresist layer 104 covers the active area.

[0065] like Figure 2 As shown, the silicon nitride hard mask layer 103 and the pad oxide layer 102 are etched based on the patterned photoresist layer 104 to expose the silicon substrate 101, and a trapezoidal silicon shoulder 105 is formed on top of the active region.

[0066] like Figure 3 As shown, the silicon substrate 101 is etched based on the etched silicon nitride hard mask layer 103 to form an isolation trench 106 in the silicon substrate 101, wherein the trapezoidal silicon shoulder 105 is transformed into a rounded trapezoidal silicon shoulder 106 during the etching process.

[0067] like Figure 4 As shown, an isolation medium layer 107 is deposited to fill the isolation trench 106, and the isolation medium layer 107 is planarized by chemical mechanical polishing. The isolation medium layer 107 may include a pad oxide layer formed by thermal oxidation and a host oxide layer deposited by high-density plasma-enhanced chemical vapor deposition (HDP-CVD).

[0068] like Figure 5 As shown, the silicon nitride hard mask layer 103 and excess oxide layer are removed until the upper surface of the active region is exposed, and pre-cleaning is performed, wherein the silicon exposed in the active region serves as a precursor for the gate oxide layer.

[0069] like Figure 6 As shown, a gate oxide layer 108 is generated on the surface of the active region by oxidation.

[0070] In the above process, once the silicon in the active region is exposed, subsequent processes will consume silicon, primarily for the growth of the gate oxide layer. Due to this silicon consumption, the rounding effect of the active region corners deteriorates, causing the corners to gradually approach right angles, which can easily lead to device failure. This invention improves the fabrication method of MOSFET devices, compensating for the silicon consumption in the processes following active region etching, while fully preserving the rounding effect of the active region corners formed by the active region etching step. The following specific embodiments illustrate the improvement of this invention.

[0071] Example 1

[0072] This embodiment provides a method for fabricating a MOSFET device, including the following steps:

[0073] S1: A silicon substrate is provided, and a pad oxide layer, a hard mask layer and a photoresist layer are sequentially formed on the silicon substrate, and the photoresist layer is patterned.

[0074] S2: Based on the patterned photoresist layer, the hard mask layer and the pad oxide layer are etched to expose the silicon substrate;

[0075] S3: Using the hard mask layer as a mask and employing the first etching conditions, the silicon substrate is etched to obtain a first trench, the first trench extending downward from the top surface of the silicon substrate to a first depth;

[0076] S4: Using the hard mask layer as a mask and employing a second etching condition different from the first etching condition, the silicon substrate is etched to obtain a second trench. The second trench extends downward from the bottom surface of the first trench to a second depth. The angle between the sidewall of the first trench near the hard mask layer and the normal of the silicon substrate is smaller than the angle between the sidewall of the second trench near the hard mask layer and the normal of the silicon substrate.

[0077] S5: Using the hard mask layer as a mask and etching the silicon substrate under the third etching condition to obtain an isolation trench, the isolation trench divides the silicon substrate into an active region located below the hard mask layer. The active region includes a main body and a cap layer located above the main body. The width of the cap layer is smaller than the width of the main body, and the top corner of the main body is a rounded corner.

[0078] S6: Form an isolation dielectric layer to fill the isolation trench, and thin the isolation dielectric layer to expose the hard mask layer;

[0079] S7: Remove the hard mask layer and the pad oxide layer to expose the cap layer, while the top corner of the main body is still covered by the insulating medium layer;

[0080] S8: Oxidize the cap layer to obtain the gate dielectric layer.

[0081] Please refer to the following first. Figure 7 Perform step S1: Provide a silicon substrate 201, and sequentially form a pad oxide layer 202, a hard mask layer 203 and a photoresist layer 204 on the silicon substrate 201, and pattern the photoresist layer 204.

[0082] As an example, the pad oxide layer 202 can be formed on the surface of the silicon substrate 201 by thermal oxidation or other suitable methods. The hard mask layer 203 may include a silicon nitride layer or other suitable material layer, which may be deposited by chemical vapor deposition or other suitable methods. The method of patterning the photoresist layer 204 includes photolithography processes such as photolithography and development.

[0083] Please see again Figure 8 Step S2 is performed: the hard mask layer 203 and the pad oxide layer 202 are etched based on the patterned photoresist layer 204 to expose the silicon substrate 201.

[0084] As an example, the etching of the hard mask layer 203 based on the patterned photoresist layer 204 includes a main etching stage and an over-etching stage. The etching method used in the main etching stage includes dry etching, and the etching method used in the over-etching stage also includes dry etching. The main etching stage is used to etch the hard mask layer 203 until the etching endpoint signal is detected, and the over-etching stage is used to ensure that the hard mask layer 203 not blocked by the photoresist layer 204 is completely etched.

[0085] As an example, when silicon nitride is selected for the hard mask layer 203, the etching gases used in the main etching stage include He, O2, HBr and CF4, and the etching gases used in the over-etching stage include CF4 and CH2F2.

[0086] Please see again Figure 9 Step S3 is performed: using the hard mask layer 203 as a mask and etching the silicon substrate 201 under the first etching conditions to obtain a first trench 205, wherein the first trench 205 extends downward from the top surface of the silicon substrate 201 to a first depth A.

[0087] As an example, the angle between the sidewall of the first trench 205 near the hard mask layer 203 and the normal of the silicon substrate 201 is in the range of 0-10 degrees, that is, the sidewall of the first trench 205 near the hard mask layer 203 is perpendicular or substantially perpendicular to the plane where the silicon substrate 201 is located.

[0088] As an example, the method of etching the silicon substrate 201 to obtain the first trench 205 using the first etching conditions includes dry etching, and the dry etching gas includes Cl2 and O2.

[0089] It should be noted that the inclination of the sidewall of the first trench 205 can be achieved by adjusting the etching gas ratio, as follows:

[0090] (1) A large number of byproducts (organic polymers) are generated during the dry etching process. The byproducts need to be removed while etching. The net deposition rate of byproducts at the edge of the active area is greater than that in the open area (when the net deposition rate is greater than 0, the net deposition rate = deposition rate - removal rate).

[0091] (2) During the dry etching process, the etching rate can be reduced by adjusting the gas ratio to increase the amount of byproducts generated, and the etching rate can be increased by adjusting the gas ratio to reduce the amount of byproducts generated.

[0092] (3) When it is necessary to form a sidewall that is inclined relative to the plane of the silicon substrate (the active region has a trapezoidal profile), the generation rate of by-products can be controlled to reach a certain range, so that the deposition rate of by-products at the edge of the active region is higher than that of by-products in the open area, resulting in a slower etching rate at the corner of AA than in the open area; when it is necessary to form a sidewall that is perpendicular to the plane of the silicon substrate (the active region has a rectangular profile), it is necessary to reduce the generation rate of by-products and remove the by-products at the edge of the active region in a timely manner.

[0093] In this step, by adjusting the etching gas ratio to reduce the generation rate of byproducts and by timely removing byproducts from the edge of the active region, the cross-section of the active region defined by the first trench can be rectangular, i.e., the sidewalls are vertical or nearly vertical.

[0094] Please see again Figure 10 Step S4 is performed: using the hard mask layer 203 as a mask and employing a second etching condition different from the first etching condition to etch the silicon substrate 201 to obtain a second trench 206, the second trench 206 extending downward from the bottom surface of the first trench 205 to a second depth B.

[0095] Specifically, the angle between the sidewall of the second trench 206 near the hard mask layer 203 and the normal of the silicon substrate 201 is greater than the angle between the sidewall of the first trench 205 near the hard mask layer 203 and the normal of the silicon substrate 201. That is, when the cross-section of the active region portion defined by the first trench 205 is rectangular or quasi-rectangular, the cross-section of the active region portion defined by the second trench 206 is trapezoidal.

[0096] As an example, the method of etching the silicon substrate 201 under the second etching conditions to obtain the second trench 206 includes dry etching, and the dry etching by-product generation rate under the second etching conditions is greater than the dry etching by-product generation rate under the first etching conditions.

[0097] As an example, the dry etching gas used in the second etching condition also includes Cl2 and O2, and the proportion of Cl2 in the second etching condition is lower than the proportion of Cl2 in the first etching condition.

[0098] Please see again Figure 11 Step S5 is executed: using the hard mask layer as a mask and etching the silicon substrate 201 under the third etching condition to obtain an isolation trench 207. The isolation trench 207 divides the silicon substrate 201 to form an active region located below the hard mask layer 203. The active region includes a main body 208 and a cap layer 209 located above the main body 208. The width of the cap layer 209 is smaller than the width of the main body 208, and the top corner of the main body 208 is a rounded corner.

[0099] Specifically, the aforementioned steps involve etching the silicon substrate 201 under the first etching condition to obtain the first trench 205 and etching the silicon substrate 201 under the second etching condition to obtain the second trench 206 as pre-etching stages. This step involves etching the silicon substrate 201 under the third etching condition to obtain the isolation trench 207 as the main etching stage. The main etching stage can use a conventional process for forming shallow trench isolation trenches. During this process, the side of the active region portion with a trapezoidal cross-section defined by the second trench 206 is rounded, ultimately making the top corner of the main body portion 208 a rounded corner.

[0100] Please see again Figure 12 Then, perform step S6: form an isolation medium layer 210 to fill the isolation trench 207, and thin the isolation medium layer 210 to expose the hard mask layer 203.

[0101] As an example, the isolation medium layer 210 includes a pad oxide layer formed by thermal oxidation and a host oxide layer formed by high-density plasma-enhanced chemical vapor deposition.

[0102] As an example, a method for thinning the insulating dielectric layer 210 includes chemical mechanical polishing.

[0103] Please see again Figure 13 Then, perform step S7: remove the hard mask layer 203 and the pad oxide layer 202 to expose the cap layer 209, while the top corner of the main body 208 is still covered by the isolation medium layer 210.

[0104] Please see again Figure 14 Step S8 is performed: the cap layer 209 is oxidized to obtain the gate dielectric layer 211.

[0105] As an example, the thickness of the gate dielectric layer is in the range of 110 angstroms to 120 angstroms or other desired thickness.

[0106] In this embodiment, the MOSFET device fabrication method involves forming an isolation trench after etching the hard mask layer. The etching of the silicon substrate is divided into a pre-etching stage and a main etching stage. In the pre-etching stage, a first etching condition and a second etching condition are used sequentially. Under the first etching condition, a gas combination with low by-product generation is used to etch for a period of time to obtain a rectangular or near-rectangular active region. Under the second etching condition, a gas combination with high by-product generation is used to etch for a certain period of time to obtain a trapezoidal active region. Ultimately, this method can protect the rounding effect of the active region corners in subsequent processes, reduce parasitic effects on the MOSFET device, thereby solving the double-peak effect of MOSFET electrical performance and improving the electrical performance of the MOSFET device.

[0107] Example 2

[0108] This embodiment provides a MOSFET device, wherein the top corner of the active region of the MOSFET device is a rounded corner, and the MOSFET device is fabricated using the MOSFET device fabrication method described in Embodiment 1.

[0109] In summary, the MOSFET device fabrication method of the present invention first uses a first etching condition to etch the silicon substrate to obtain a first trench, and then uses a second etching condition different from the first etching condition to etch the silicon substrate to obtain a second trench. The angle between the sidewall of the first trench near the hard mask layer and the normal of the silicon substrate is smaller than the angle between the sidewall of the second trench near the hard mask layer and the normal of the silicon substrate. Then, a third etching condition is used to etch the silicon substrate to obtain an isolation trench. The isolation trench divides the silicon substrate into an active region located below the hard mask layer. The active region includes a main body and a cap layer located above the main body. The width of the cap layer is smaller than the width of the main body. The top corner of the main body is a rounded corner. In subsequent processes, the gate dielectric layer is obtained by oxidizing the cap layer above the main body of the active region. During the formation of the gate dielectric layer, the top corner of the main body of the active region is protected by the isolation dielectric layer and is not consumed, which helps to reduce parasitic effects on the MOSFET device, avoid double-peak effects, and ultimately improve the electrical performance of the MOSFET device. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a MOSFET device, characterized in that, Includes the following steps: A silicon substrate is provided, and a pad oxide layer, a hard mask layer and a photoresist layer are sequentially formed on the silicon substrate, and the photoresist layer is patterned. Based on the patterned photoresist layer, the hard mask layer and the pad oxide layer are etched to expose the silicon substrate; Using the hard mask layer as a mask and employing the first etching conditions, the silicon substrate is etched to obtain a first trench, the first trench extending downward from the top surface of the silicon substrate to a first depth; Using the hard mask layer as a mask and employing a second etching condition different from the first etching condition, the silicon substrate is etched to obtain a second trench. The second trench extends downward from the bottom surface of the first trench to a second depth. The angle between the sidewall of the first trench near the hard mask layer and the normal of the silicon substrate is smaller than the angle between the sidewall of the second trench near the hard mask layer and the normal of the silicon substrate. Using the hard mask layer as a mask and etching the silicon substrate under a third etching condition to obtain an isolation trench, the isolation trench divides the silicon substrate into an active region located below the hard mask layer. The active region includes a main body and a cap layer located above the main body. The width of the cap layer is smaller than the width of the main body, and the top corner of the main body is a rounded corner. An isolation dielectric layer is formed to fill the isolation trench, and the isolation dielectric layer is thinned to expose the hard mask layer; Remove the hard mask layer and the pad oxide layer to expose the cap layer, while the top corner of the main body is still covered by the insulating medium layer; Oxidize the cap layer to obtain the gate dielectric layer; The method of etching the silicon substrate to obtain the first trench using the first etching condition includes dry etching, and the method of etching the silicon substrate to obtain the second trench using the second etching condition different from the first etching condition includes dry etching, wherein the dry etching by-product generation rate under the first etching condition is lower than the dry etching by-product generation rate under the second etching condition.

2. The method for fabricating a MOSFET device according to claim 1, characterized in that: The angle between the sidewall of the first trench near the hard mask layer and the normal of the silicon substrate is in the range of 0-10 degrees.

3. The method for fabricating a MOSFET device according to claim 1, characterized in that: Both the dry etching gas used in the first etching condition and the dry etching gas used in the second etching condition include Cl2 and O2, and the proportion of Cl2 in the first etching condition is higher than that in the second etching condition.

4. The method for fabricating a MOSFET device according to claim 1, characterized in that: The hard mask layer includes a silicon nitride layer.

5. The method for fabricating a MOSFET device according to claim 4, characterized in that: The etching of the hard mask layer based on the patterned photoresist layer includes a main etching stage and an over-etching stage; the etching method used in the main etching stage includes dry etching, and the etching gas includes He, O2, HBr and CF4; the etching method used in the over-etching stage includes dry etching, and the etching gas includes CF4 and CH2F2.

6. The method for fabricating a MOSFET device according to claim 1, characterized in that: The thickness of the gate dielectric layer ranges from 110 angstroms to 120 angstroms.

7. The method for fabricating a MOSFET device according to claim 1, characterized in that: The isolation medium layer comprises a pad oxide layer formed by thermal oxidation and a main oxide layer formed by high-density plasma-enhanced chemical vapor deposition.

8. A MOSFET device, characterized in that: The MOSFET device is manufactured using the method for manufacturing a MOSFET device as described in any one of claims 1-7.

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