Testing the circuit structure of TSV in 3D integrated circuits

Abstract

The present invention proposes a circuit structure for testing silicon vias in a three-dimensional integrated circuit, comprising a silicon via region in which a plurality of silicon vias are formed, and a switch circuit having a plurality of row lines and a plurality of column lines to form an addressable test array, wherein two ends of each silicon via are respectively connected to a row line and a column line, the switch circuit sends a test voltage signal to the silicon vias in the same column through a column line, and receives a current signal passing through the silicon vias in the column through the row lines, or the switch circuit sends a test voltage signal to the silicon vias in the same row through a row line, and receives a current signal passing through the silicon vias in the row through the column lines.

Description

Technical Field

[0001] The present invention relates to a circuit structure for testing through silicon via (TSV), and more specifically, to a circuit structure for testing the electrical continuity of a through silicon via in a three-dimensional integrated circuit. Background Art

[0002] With the evolution of semiconductor manufacturing technology, multiple chips can now be integrated into a single package structure. In this type of package structure, the connection between chips is achieved through a through silicon via (TSV) structure. TSV is a conductive through-hole structure that can pass through the entire silicon wafer or chip to provide electrical continuity. For example Figure 1 As shown, three chips 10, 12, and 14 are stacked and electrically connected to each other through silicon vias 16 to transmit circuit signals. Silicon vias allow two or more integrated circuit components to be stacked vertically into a three-dimensional chip. For example, the silicon via of the IC component at the top of the stack will be connected to the silicon via of the IC component below it. By electrically connecting the IC components in the three-dimensional stack, the silicon via can allow the IC components in the stack to operate as a single component. Silicon via technology allows three-dimensional stacked chips to have higher connectivity, bandwidth, and efficiency, and only occupy a small part of the layout area.

[0003] TSVs are generally formed by deep etching deep holes in a wafer or substrate. These holes are filled with liner and conductive layers, and then the wafer is thinned from the back until the filled conductive layer is exposed. The back metal layer and bumps are deposited on the thinned back as electrical contacts. There may be a large number of TSV structures in a three-dimensional stacked chip. As long as one TSV fails, such as an open circuit or poor contact, it may cause the yield of the entire chip to decrease. Therefore, the testing of TSVs in three-dimensional stacked chips is very important. In today's general traditional TSV testing, most TSVs are connected in series into chains, such as 1,000 TSVs in a daisy chain, and the electrical properties of the entire chain are measured at once. The disadvantage of this approach is that if the resistance of a few TSVs in the chain is abnormal or outliers, the test results cannot reflect the abnormal performance of those few TSVs. For example, some silicon vias only have structural or material defects due to manufacturing process variations or imperfect manufacturing processes. They are not completely open-circuited or short-circuited, and the test results cannot diagnose their abnormalities. Furthermore, the method of measuring the silicon vias on the entire chain at one time cannot know the exact location of the abnormal silicon vias, so it is impossible to perform electrical fault tests or physical fault tests on the problem points based on the obtained measurement results to solve the manufacturing process problems. In addition, there may be a large number of silicon via structures in today's three-dimensional stacked integrated circuits, and the number may reach more than tens of thousands, and because they are used to connect different IC components, their layout is also relatively complex. When measuring in the above traditional way, not only does the test circuit (such as test pads, etc.) occupy a large layout area, but it also takes a lot of time to measure all silicon via chains.

[0004] Therefore, it can be seen that the current TSV testing method is not only time-consuming, but also may not be able to detect or accurately determine the location of defective TSVs, and is even more unable to detect a small number of abnormal TSVs that are electrical outliers and incomplete failures. Summary of the invention

[0005] In view of the shortcomings of the above-mentioned existing TSV measurement methods, the present invention proposes a novel circuit structure for testing TSVs, which uses a specific switch circuit to form an addressable test array, so that row-by-row or column-by-column scanning test and accurate addressing of the position of abnormal TSVs can be achieved. The test data of individual TSVs can also be used for subsequent electrical diagnostic analysis. It is particularly suitable for working with a wafer acceptance test (WAT) machine to measure TSVs in three-dimensional integrated circuits.

[0006] One aspect of the present invention is to provide a circuit structure for testing TSVs in a three-dimensional integrated circuit, comprising a TSV region in which a plurality of TSVs are formed, and a switch circuit having a plurality of row lines and a plurality of column lines to form an addressable test array, wherein two ends of each TSV are respectively connected to a row line and a column line, and the switch circuit sends a test voltage signal to the TSVs through the column lines, and receives a current signal passing through the TSVs through the row lines.

[0007] Another aspect of the present invention is to provide a circuit structure for testing TSVs in a three-dimensional integrated circuit, comprising a TSV region in which a plurality of TSVs are formed, and a switch circuit having a plurality of row lines and a plurality of column lines to form an addressable test array, wherein two ends of each TSV are respectively connected to the row line and the column line, and the switch circuit sends test voltage signals to the TSVs through the row lines, and receives current signals passing through the TSVs through the column lines.

[0008] These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is described in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This specification contains drawings and constitutes a part of this specification, so that readers can further understand the embodiments of the present invention. These drawings depict some embodiments of the present invention and illustrate their principles together with the description herein. In these drawings:

[0010] Figure 1 is a schematic diagram of a three-dimensional stacked wafer;

[0011] Figure 2 A schematic diagram of a circuit for testing through silicon vias in a three-dimensional integrated circuit according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of an addressable test array composed of interlaced row lines and column lines in an embodiment of the present invention;

[0013] Figure 4 for Figure 3 A schematic cross-sectional view of the addressable test array structure shown;

[0014] Figure 5 is a schematic diagram of an addressable test array composed of interlaced row lines and column lines in another embodiment of the present invention;

[0015] Figure 6 Schematic diagram of an addressable test array composed of interlaced row lines and column lines in another embodiment of the present invention;

[0016] Figure 7 for Figure 6 A schematic cross-sectional view of the addressable test array structure shown; and

[0017] Figure 8 FIG. 4 is a schematic diagram of an addressable test array formed by interweaving row lines and column lines according to another embodiment of the present invention.

[0018] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0019] Explanation of symbols

[0020] 100 Switch Circuit

[0021] 102 Analog Sensing Circuit

[0022] 104 Test control circuit

[0023] 106 TSV area

[0024] 108 Silicon substrate

[0025] 110,112 Silicon wafer

[0026] 114 Silicon substrate

[0027] 116 Interconnect Metal Layer

[0028] 118 Guide hole

[0029] CLK clock pulse signal

[0030] Column1~ColumnN row lines

[0031] IPIN1, IPIN2 current signal

[0032] I1~I N Current

[0033] ML Floor Metal Wiring

[0034] RDL Redistribution Layer

[0035] RN

[0036] Row1~RowM

[0037] SO

[0038] TSV,TSV1,TSV2 Through Silicon Via

[0039] VDD1, VDD2 operating voltage

[0040] VPIN1, VPIN2 test voltage signal

[0041] VSS1, VSS2 Common ground voltage DETAILED DESCRIPTION

[0042] In various embodiments described herein, a switch circuit is used to perform a test, such as a wafer acceptance test (WAT), on one or more through silicon vias (TSVs) in a through silicon via (TSV) region of an integrated circuit component, each of which can be individually addressed for testing. The switch circuit includes an address decoder that selectively couples one or more TSVs to a test input circuit and / or a test sensing circuit that can be integrated into an integrated circuit component, such as a memory circuit. The embodiments described herein allow testing to be extended beyond the TSVs of a single IC component. For example, the proposed embodiments can also test one or more TSV chains in an IC stack structure, such as a three-dimensional memory stack structure. The switch circuit can share resources (such as address decoders, external test devices, test processes, etc.) with other tests (such as memory array tests). Thus, the embodiments disclosed herein provide an accurate and efficient TSV test structure that does not require too much layout space and cost. Furthermore, in embodiments, the techniques and methods described herein may be used in conjunction with Wide IO memory, hybrid memory cubes, 3D stacked memory, or other related components.

[0043] First, please refer to Figure 2 , which depicts a schematic diagram of a circuit for testing silicon vias in a three-dimensional integrated circuit according to an embodiment of the present invention. As shown in the figure, the silicon via test circuit includes a switch circuit 100 and a silicon via region 106. A plurality of silicon vias (TSVs) are formed in the silicon via region 106, and the number of the silicon vias (TSVs) may be as many as tens of thousands. The silicon vias (TSVs) are vertical interconnect structures used to connect multiple wafers or chips stacked in a three-dimensional integrated circuit, so that electronic signals can be transmitted between different chips. As shown in the figure, the silicon vias (TSVs) may be arranged in an array in the silicon via region 106, or may be connected in series in a daisy chain, but is not limited thereto.

[0044] Re-reference Figure 2The switch circuit 100 includes an analog sensing circuit 102 and a test control circuit 104. The test control circuit 104 may include a row decoder and a column decoder, which are respectively connected to a plurality of row lines Column1-ColumnN and a plurality of column lines Row1-RowM. In an embodiment of the present invention, the row lines Column1-ColumnN and the column lines Row1-RowM are interwoven to form an addressable test array, which corresponds to and is connected to the through silicon vias TSV in the through silicon via region 106, so that each through silicon via TSV can be individually addressed for testing. It should be noted that in an embodiment of the present invention, the switch circuit 100 is integrated into an IC component, such as integrated into various types of volatile or non-volatile three-dimensional stacked memory circuits or a controller component, and the row decoder and column decoder of the test control circuit 104 may also be shared with the IC component and may adopt the same addressing method. For example, the row decoder and the column decoder may also be used to address a storage cell or storage element in a memory device, which helps to reduce the layout space and cost required for the entire test structure.

[0045] On the other hand, the test control circuit 104 is coupled to another external test circuit or device, such as the analog sensing circuit 102 shown in the figure, which may be a source measure unit (SMU) in a wafer acceptance tester. The analog sensing circuit 102 can provide test stimulus factors (such as charge, alternating current, pulse bias, test data or other information) to test the silicon via TSV, which will be provided to the addressed silicon via TSV through the row lines Column1 to ColumnN or the column lines Row1 to RowM of the test control circuit 104. After that, these test stimulus factors can be received by the test control circuit 104 to analyze and diagnose the electrical properties of the silicon via TSV, such as providing a test voltage and receiving the current passing through the silicon via TSV to analyze and diagnose whether the electrical continuity of the silicon via TSV is normal or outlier, or comparing the differences between two or more test results. In actual testing, the WAT machine can electrically contact the pads or bumps on the device under test through the probe card, so as to send the test stimulus signal to the switch circuit and the device under test and receive its test results.

[0046] In one embodiment, the switch circuit 100 is connected with various signal outputs and inputs, including the working voltage VDD1, the common ground voltage VSS1, the Norton equivalent circuit signal RN, the clock pulse signal CLK, the switch signal SO, etc. connected to the test control circuit 104, and the working voltage VDD2 and the common ground voltage VSS2 connected to the TSV region 106, and the test voltage signals VPIN1, VPIN2 and the received current signals IPIN1, IPIN2, etc. sent by the analog sensing circuit 102. The test program can perform various tests on the selected TSV to obtain the quality of the selected TSV, such as testing to determine whether it is short-circuited or open-circuited, diagnosing whether the electrical continuity of the TSV is normal or outlier, testing whether it is leaking according to the capacitance value, using pulse signal propagation for testing, data compression testing, comparing the difference between two or more test results, etc., and using the obtained data for electrical fault analysis or physical fault analysis. In an embodiment, such tests can be performed before the die is packaged, or when the IC device is subjected to other pre-assembly tests. The test program can be executed using any suitable processor, which provides instructions for the processor to perform the functions described above. Furthermore, the test program can be stored in any suitable storage location or computer-readable storage medium (such as a storage device associated with an IC component test system or analyzer, etc.).

[0047] Please refer to the following Figure 3 , which depicts a schematic diagram of an addressable test array composed of interlaced row lines and column lines according to an embodiment of the present invention. Figure 3As shown, the addressable test array of the present invention is composed of a plurality of row lines Column1 to ColumnN and a plurality of column lines Row1 to RowM in two different directions. The intersection of each row line and column line is used as a fixed address point, which may correspond to a through silicon via TSV to be tested, wherein the two ends of each through silicon via TSV are respectively connected to the row line and column line corresponding to it. In one embodiment of the present invention, part or the whole of the switch circuit 100 may be manufactured on a silicon carrier using a CMOS compatible manufacturing process, the row lines Column1 to ColumnN may be grounded metal wirings ML formed in the silicon wafer 110, and the column lines Row1 to RowM may be or may be included in a redistribution layer RDL formed on the surface of the IC stacking structure, for example, the column lines and the row lines are metal wirings formed on different silicon wafers, or metal wirings formed on the same silicon wafer and different layers. In one embodiment of the present invention, the through silicon vias located in the same row are connected to each other through a redistribution layer RDL, and may be connected to the corresponding column line through a through silicon via TSV on the outermost side of the array. The silicon vias located in the same row are directly connected to the corresponding row lines. In the actual test operation, the test control circuit 104 can select the TSV column to be tested, which can be achieved through the switch in the test control circuit 104. For example, as shown in the figure, it only selects to open the channel of the column line Row1, and the analog sensing circuit 102 sends a test stimulus, such as a test voltage, to one end of each silicon via TSV on the column Row1 through the redistribution layer RDL. After passing through the silicon vias TSV, the test voltage will obtain currents I1~I N , these currents I1~I N The current can be transmitted to the test control circuit 104 through the corresponding row lines Column1 to ColumnN, and then a dedicated analysis platform can be used to generate analysis results. For example, if the current value obtained from a row line is abnormal or outlier, it means that the TSV at the corresponding position where the row line and the row line intersect is defective, such as electrical abnormality or failure caused by a tiny pinhole defect or a complete short circuit or open circuit.

[0048] Please refer to the following Figure 4 , which is Figure 3The cross-sectional schematic diagram of the addressable test array structure shown in the figure. The embodiment shown in the figure is an IC stacking structure formed by bonding two silicon wafers 110, 112, and the outer sides of the silicon wafers 110, 112 are respectively connected to a silicon carrier 108, 114. In this embodiment, the silicon wafers 110, 112 are provided with metal wirings required for the TSV test structure of the present invention, such as the aforementioned landing metal wiring ML for row lines, column lines, and interconnection metal layers 116 required for other logic circuits, which can be formed by general semiconductor back-end manufacturing processes. The switch circuit 100 includes switches and circuit elements composed of gates and source / drain electrodes, which can be formed on the silicon carrier 108 by CMOS compatible manufacturing processes. The through silicon via TSV will be formed from one side of the silicon carrier 114, for example, it can be formed by deep etching and hole filling and other manufacturing processes, and it will pass through the silicon wafer 112 and electrically contact the landing metal wiring ML (i.e., the row line in the present invention) of the silicon wafer 110. The other end of the through silicon via TSV is electrically connected to a redistribution layer (connected to the column line in the present invention) RDL or a bump structure to transmit signals to or from an external circuit, such as the test control circuit 104 and the WAT test machine.

[0049] In practice, a three-dimensional integrated circuit may be formed by stacking and connecting two or more layers of wafers or chips, each of which may have TSVs formed therein, and these TSVs may be connected to each other to achieve circuit integration. For the sake of simplicity of illustration and description, the figure only shows a design of two stacked silicon wafers and a single TSV. The reader should understand that the embodiments and scope of the present invention are not limited to Figure 4 The design and concept of the IC stacking structure shown can be applied to multi-layer IC stacking structures and various TSV types, including various TSV methods such as via first, via middle, via last, and via after bonding.

[0050] Please refer to the following Figure 5 , which depicts a schematic diagram of an addressable test array composed of interlaced row lines and column lines according to another embodiment of the present invention. Figure 5 The embodiment shown and Figure 3The difference is that the test voltage signal is sent by the row lines Column1~ColumnN. In the actual test operation, the test control circuit 104 can select the TSV row to be tested, which can be achieved by the switch in the test control circuit 104. As shown in the figure, it only selects to open the channel of the row line Column1, and the analog sensing circuit 102 sends a test stimulus, such as a test voltage, through the ground metal wire (i.e., the row line) ML to one end of each silicon via TSV on the row Column1. After the test voltage passes through these silicon vias TSV, currents I1~I N , these currents I1~I N The data may be transmitted to the test control circuit 104 via the corresponding column lines Row1 -RowM, and the analysis results may be generated by a subsequent dedicated analysis platform.

[0051] Please refer to the following Figure 6 , which depicts a schematic diagram of an addressable test array composed of interlaced row lines and column lines according to another embodiment of the present invention. Figure 5 The embodiment shown and Figure 3 Similar, the difference is that each address bit corresponds to a pair of through silicon vias TSV1, TSV2. Among them, one end of a through silicon via TSV2 in the pair of through silicon vias is connected to a corresponding column line through the guide hole 118, and the other end is connected to one end of another through silicon via TSV1 through the redistribution layer RDL, and the other end of the other through silicon via TSV1 is connected to a corresponding row line. In the actual test operation, the test control circuit 104 can select the TSV column to be tested, which can be achieved through the switch in the test control circuit 104. As shown in the figure, it only selects to open the channel of the column line Row1, and the analog sensing circuit 102 sends a test stimulus factor, such as a test voltage, which is transmitted to the through silicon via TSV2 through the column line Row1, and then transmitted to its paired through silicon via TSV1 through the redistribution layer RDL. After passing through the through silicon vias TSV1, TSV2, the test voltage will obtain currents I1~I N , these currents I1~I N The data may be transmitted to the test control circuit 104 via the corresponding row lines Column1 ˜ColumnN, and the analysis results may be generated by a subsequent dedicated analysis platform.

[0052] Please refer to the following Figure 7 , which is Figure 6The cross-sectional schematic diagram of the addressable test array structure is shown. The embodiment shown in the figure is an IC stacking structure formed by bonding two silicon wafers 110, 112, and the outer sides of the silicon wafers 110, 112 are respectively connected to the silicon carriers 108, 114. In this embodiment, the silicon wafers 110, 112 are provided with metal wiring required for the TSV test structure of the present invention, such as the aforementioned landing metal wiring ML for row lines, guide holes 118, column lines and interconnection metal layers 116 required for other logic circuits, which can be formed by general semiconductor back-end manufacturing processes. The switch circuit 100 includes switches and circuit elements composed of gates and source / drains, which can be formed on the silicon carrier 108 by a CMOS compatible manufacturing process. The through silicon vias TSV1 and TSV2 are formed from one side of the silicon substrate 114, for example, by deep etching and hole filling processes, and pass through the silicon wafer 112 to electrically contact the ground metal wiring ML (i.e., the row line in the present invention) of the silicon wafer 110. The through silicon vias TSV1 and TSV2 at the other end are connected to each other through the redistribution layer RDL. In this embodiment, the through silicon via TSV2 is further connected to the column line Row on a different layer from the row line ML through the guide hole 118.

[0053] Please refer to the following Figure 8 , which depicts a schematic diagram of an addressable test array composed of interlaced row lines and column lines according to another embodiment of the present invention. Figure 8 The embodiment shown and Figure 6 Similar, the difference is that the test voltage signal is sent by the row lines Column1~ColumnN. In the actual test operation, the test control circuit 104 can select the TSV row to be tested, which can be achieved through the switch in the test control circuit 104. As shown in the figure, it only selects to open the channel of the row line Column1, and the analog sensing circuit 102 sends a test stimulus, such as a test voltage, which is transmitted to one end of each silicon via TSV1 on the row Column1 through the ground metal wiring (i.e., the row line) ML. After the test voltage passes through the silicon vias TSV1, the redistribution layer RDL and the silicon vias TSV2 in sequence, the current I1~I N , these currents I1~I N The data may be transmitted to the test control circuit 104 via the corresponding column lines Row1 -RowM, and the analysis results may be generated by a subsequent dedicated analysis platform.

[0054] According to the above-mentioned embodiments, it can be understood that the advantage of the silicon via test circuit structure proposed by the present invention is that an addressable test array is formed through a specific switch circuit to achieve the selection function, so that the WAT machine or other test machines can achieve row-by-row or column-by-column scanning test, without the need for the probe card to frequently change the needle position like the traditional measurement method, which greatly reduces the time required for testing and the required test pad layout area. The addressable test array method can also accurately address the location of abnormal silicon vias, and the test data of individual silicon vias obtained can also be used for subsequent electrical analysis to obtain more accurate diagnostic results, and to clarify and solve the manufacturing process problems for the problem points.

[0055] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A circuit structure for testing through silicon vias in a three-dimensional integrated circuit, characterized in that: Include: a TSV region in which a plurality of TSVs are formed; and The switch circuit has a plurality of row lines and a plurality of column lines to form an addressable test array, wherein two ends of each silicon via are respectively connected to a row line and a column line, and the switch circuit sends a test voltage signal to the silicon vias in the same column through a column line, and receives a current signal passing through the silicon vias in the column through the row lines, or the switch circuit sends a test voltage signal to the silicon vias in the same row through a row line, and receives a current signal passing through the silicon vias in the row through the column lines.

2. The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 1, wherein one ends of the TSVs in the same row in the TSV region are connected to each other through a redistribution layer, and the redistribution layer is further connected to a corresponding row line. 3 . The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 2 , wherein the redistribution layer is connected to the corresponding column line through the TSV located at the outermost side in the TSV region. 4 . The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 1 , wherein one end of the TSVs in the same row in the TSV region is directly connected to a corresponding row line.

5. The circuit structure for testing TSVs in a three-dimensional integrated circuit as described in claim 1, wherein the switch circuit is disposed on a silicon carrier, two or more stacked silicon wafers are bonded to the silicon carrier, and the TSVs, the row lines, and the column lines are formed in the silicon wafers.

6. The circuit structure for testing TSVs in a three-dimensional integrated circuit as described in claim 1, wherein the switch circuit comprises a test control circuit and an analog sensing circuit, the plurality of row lines and the plurality of column lines are connected to the test control circuit, and the column line or the row line to which the test voltage signal is to be sent is selected by the test control circuit.

7. The circuit structure for testing TSVs in a three-dimensional integrated circuit as described in claim 6, wherein the analog sensing circuit is connected to or included in a wafer acceptance test machine, the analog sensing circuit is connected to the test control circuit and sends the test voltage signal, and the test control circuit receives the current signal passing through the TSVs.

8. A circuit structure for testing through silicon vias in a three-dimensional integrated circuit, characterized in that: Include: a TSV region in which a plurality of TSVs are formed; and A switch circuit has a plurality of row lines and a plurality of column lines forming an addressable test array, wherein an address where a row line intersects with a column line corresponds to a pair of TSVs, two ends of one of the TSVs in the pair of TSVs are respectively connected to the corresponding column line and a redistribution layer, and two ends of the other TSV are respectively connected to the redistribution layer and the corresponding row line, the switch circuit sends a test voltage signal to the TSVs in the same row through one of the row lines, and receives a current signal passing through the TSVs in the row through the column lines, or the switch circuit sends a test voltage signal to the TSVs in the same row through one of the column lines, and receives a current signal passing through the TSVs in the row through the row lines.

9. The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 8, wherein one of the TSVs in each pair of TSVs is directly connected to the corresponding row line, and the other TSV is connected to the corresponding column line through a guide via. 10 . The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 8 , wherein the row lines and the column lines respectively comprise metal wirings formed in different silicon wafers. 11 . The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 8 , wherein the row lines and the column lines respectively comprise metal wirings formed in the same silicon wafer and at different layers.

12. The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 8, wherein the switch circuit is disposed on a silicon carrier, two or more stacked silicon wafers are bonded to the silicon carrier, and the TSVs, the row lines and the column lines are formed in the silicon wafers.

13. The circuit structure for testing TSVs in a three-dimensional integrated circuit as described in claim 8, wherein the switch circuit comprises a test control circuit and an analog sensing circuit, the plurality of row lines and the plurality of column lines are connected to the test control circuit, and the row line or the column line to which the test voltage signal is to be sent is selected by the test control circuit.

14. The circuit structure for testing TSVs in a three-dimensional integrated circuit as claimed in claim 13, wherein the analog sensing circuit is connected to or included in a wafer acceptance test machine, the analog sensing circuit is connected to the test control circuit and sends the test voltage signal, and the test control circuit receives the current signal passing through the TSVs.

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